Storage system

Abstract

A storage system of one embodiment of the present application includes a substrate including a core portion, a plurality of first and second pad electrodes provided over a first surface, and a plurality of third and fourth pad electrodes provided over a second surface opposite to the first surface; a memory controller provided on the first surface side; a nonvolatile memory provided on the first surface side; a first member provided on the second surface side; a second member provided on the second surface side; a plurality of first electrodes respectively connected between the memory controller and each of the plurality of first pad electrodes; a plurality of second electrodes respectively connected between the nonvolatile memory and each of the plurality of second pad electrodes; a plurality of third electrodes respectively connected between the first member and each of the plurality of third pad electrodes; and a plurality of fourth electrodes respectively connected between the second member and each of the plurality of fourth pad electrodes. Each of the plurality of first pad electrodes and each of the plurality of third pad electrodes are provided at positions symmetrical with respect to an imaginary surface passing through a center line in a thickness direction of the substrate. The plurality of second pad electrodes and the plurality of fourth pad electrodes are provided at positions symmetrical with respect to the imaginary surface.

Description

[0001] Related applications

[0002] This application claims priority to Japanese Patent Application No. 2021-48940 (filed on March 23, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] The implementation method mainly relates to a storage system. Background Technology

[0004] A memory system is known to include a non-volatile memory and a memory controller. The non-volatile memory stores data non-volatilely, and the memory controller controls the non-volatile memory. The non-volatile memory and memory controller are mounted on a printed circuit board. The non-volatile memory and memory controller are electrically connected to a host device via the printed circuit board. Summary of the Invention

[0005] The implementation provides a storage system capable of suppressing defects caused by shock and heat.

[0006] The storage system of the embodiment includes: a substrate having a first surface and a second surface located opposite to the first surface, and comprising a core, a plurality of first pad electrodes and a plurality of second pad electrodes respectively disposed on the first surface, and a plurality of third pad electrodes and a plurality of fourth pad electrodes respectively disposed on the second surface; a memory controller disposed on the first surface side; a non-volatile memory disposed on the first surface side; a first component disposed on the second surface side; a second component disposed on the second surface side; a plurality of first electrodes connected between the memory controller and each of the plurality of first pad electrodes; a plurality of second electrodes connected between the non-volatile memory and each of the plurality of second pad electrodes; a plurality of third electrodes connected between the first component and each of the plurality of third pad electrodes; and a plurality of fourth electrodes connected between the second component and each of the plurality of fourth pad electrodes. Each of the plurality of first pad electrodes and each of the plurality of third pad electrodes are disposed symmetrically with respect to an imaginary plane with respect to a centerline passing through the thickness direction of the substrate. Each of the plurality of second pad electrodes is positioned symmetrically with respect to the plurality of fourth pad electrodes relative to the hypothetical plane. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating an example of the configuration of an information processing system implemented in this way.

[0008] Figure 2 This is a top view showing an example of the layout of the chips constituting the storage system of the embodiment.

[0009] Figure 3 This is a cross-sectional view of an example of the storage system of the embodiment along line III-III.

[0010] Figure 4 This is a top view showing an example of the layout of the pad electrodes on the substrate in an embodiment.

[0011] Figure 5 This is a top view showing an example of the layout of the chips that constitute a variation of the memory system.

[0012] Figure 6 This is a cross-sectional view of an example of a storage system along line VI-VI, representing a variation.

[0013] Figure 7 This is a top view showing an example of the layout of the pad electrodes on the substrate in a variation example. Detailed Implementation

[0014] Hereinafter, embodiments will be described with reference to the accompanying drawings. In the description, constituent elements having substantially the same function and structure will be labeled with the same symbols. Furthermore, the embodiments shown below illustrate the technical concept. The embodiments are not limited to the material, shape, structure, or arrangement of the constituent components. Various modifications can be made to the embodiments.

[0015] 1. Implementation Method

[0016] 1.1 Composition

[0017] 1.1.1 Information Processing System

[0018] The configuration of the information processing system of the first embodiment will be described.

[0019] Figure 1 This is a block diagram illustrating the configuration of the information processing system according to the first embodiment. The information processing system 1 includes a storage system 100 and a host device 200.

[0020] Storage system 100 is a storage device. Storage system 100 may be, for example, an SSD (Solid State Drive) that functions as a storage area of ​​host device 200. Storage system 100 performs data write and read operations according to requests from host device 200.

[0021] Host device 200 is an external information processing device of storage system 100. Host device 200 is, for example, a server or personal computer in a data center.

[0022] 1.1.2 Internal Structure of the Storage System

[0023] Next use Figure 1 The internal structure of the storage system 100 will be described.

[0024] The storage system 100 includes a memory controller 10, a non-volatile memory 20, a volatile memory 30, and a power control circuit 40. The storage system 100 may also include two or more non-volatile memories 20. Hereinafter, the memory controller 10, the non-volatile memory 20, the volatile memory 30, and the power control circuit 40 are sometimes collectively referred to as component MP.

[0025] The memory controller 10 is an IC (Integrated Circuit) chip such as a System-on-a-Chip (SoC). The memory controller 10 controls the non-volatile memory 20 based on received requests. Specifically, for example, the memory controller 10 writes the requested data to the non-volatile memory 20. Additionally, the memory controller 10 reads the requested data from the non-volatile memory 20.

[0026] The non-volatile memory 20 is, for example, a NAND (NOT AND) type flash memory. Alternatively, the non-volatile memory 20 can also be an EEPROM. TM Non-volatile memory other than NAND flash memory, such as electrically erasable programmable read-only memory. Non-volatile memory 20 non-volatilely stores data.

[0027] The volatile memory 30 is, for example, DRAM (Dynamic Random Access Memory). The volatile memory 30 temporarily stores data.

[0028] The power control circuit 40 is an IC chip. The power control circuit 40 supplies power to the memory controller 10 based on externally supplied power. The power control circuit 40 supplies power to the non-volatile memory 20 and the volatile memory 30 via the memory controller 10.

[0029] 1.1.3 Layout of components constituting the storage system

[0030] Next, the layout of the storage system 100 in the implementation method will be described. Figure 2 This is a top view showing an example of the layout of the components constituting the storage system of the embodiment. Figure 2In the diagram, two non-volatile memories, 20-1 and 20-2, are shown as non-volatile memories 20. Furthermore, the storage system 100 further includes a substrate 5 and components 10c, 20c, 30c, and 40c. Next, the substrate 5 and components 10c, 20c, 30c, and 40c will be described.

[0031] Substrate 5 is a printed substrate. Substrate 5 has a cuboid shape, comprising a rectangular first face and a second face located opposite the first face. Hereinafter, the long sides of the first and second faces of substrate 5 are defined as the X-direction. The short sides of the first and second faces of substrate 5 are defined as the Y-direction. The alignment of the first and second faces of substrate 5 is defined as the Z-direction. Figure 2 The upper part (A) shows a top view of the first surface of substrate 5 viewed in the Z direction. Figure 2 The lower part (B) shows a top view of the second surface of substrate 5 viewed in the Z direction. The shape of substrate 5 is, for example, according to the M.2 standard. Specifically, the combination (W, L) of the short side length W and the long side length L of substrate 5 in the top view includes, for example, various cases such as (22 mm, 42 mm), (22 mm, 60 mm), (22 mm, 80 mm), and (22 mm, 110 mm).

[0032] In the following description, "the second and third elements are symmetrical with respect to the first element" means that the second and third elements are symmetrical with respect to an imaginary surface within the first element. An imaginary surface within the first element is, for example, the XY plane that bisects the first element in the Z direction or the thickness direction of the first element. "The second and third elements are symmetrical about the first element" is synonymous with "the second and third elements are symmetrical with respect to the first element." "Multiple second elements and multiple third elements are symmetrical with respect to the first element" means that one element arbitrarily selected from multiple second elements is symmetrical with respect to one corresponding element from multiple third elements with respect to the first element. Furthermore, "symmetry" includes substantial symmetry. That is, the positional relationship between the second and third elements that are symmetrical with respect to the first element allows for manufacturing errors. Manufacturing errors include, for example, pattern misalignment.

[0033] Component 10c serves as a counterweight for the memory controller 10. That is, component 10c has the same weight and shape as the memory controller 10. For example, the weight of component 10c may be equal to that of the memory controller 10, but design errors may also be included. Similarly, the shape of component 10c may be identical to that of the memory controller 10, but design errors may also be included. Component 10c is positioned symmetrically with respect to the substrate 5 and the memory controller 10. The center of gravity of component 10c is located symmetrically with respect to the substrate 5 and the center of gravity of the memory controller 10.

[0034] Components 20c-1 and 20c-2 serve as balancing weights for non-volatile memories 20-1 and 20-2, respectively. That is, components 20c-1 and 20c-2 have the same weight and shape as non-volatile memories 20-1 and 20-2, respectively. For example, the weight of each component 20c-1 and 20c-2 may be equal to the weight of each non-volatile memory 20-1 and 20-2, but may also include design-permissible errors or manufacturing errors. Similarly, the shape of each component 20c-1 and 20c-2 may be identical to the shape of each non-volatile memory 20-1 and 20-2, but may also include design-permissible errors or manufacturing errors. Components 20c-1 and 20c-2 are positioned symmetrically to non-volatile memories 20-1 and 20-2 relative to the substrate 5, respectively. The center of gravity of component 20c-1 and the center of gravity of component 20c-2 are located at positions symmetrical to the center of gravity of non-volatile memory 20-1 and the center of gravity of non-volatile memory 20-2, respectively, relative to substrate 5.

[0035] Component 30c serves as a balancing weight for the volatile memory 30. That is, component 30c has the same weight and shape as the volatile memory 30. For example, the weight of component 30c is equal to the weight of the volatile memory 30, but it may also include design-permissible errors or manufacturing errors. For example, the shape of component 30c is the same as the shape of the volatile memory 30, but it may also include design-permissible errors or manufacturing errors. Component 30c is positioned symmetrically with respect to the substrate 5 and the volatile memory 30. The center of gravity of component 30c is located symmetrically with respect to the substrate 5 and the center of gravity of the volatile memory 30.

[0036] Component 40c serves as a balancing weight for the power control circuit 40. That is, component 40c has the same weight and shape as the power control circuit 40. For example, the weight of component 40c is equal to the weight of the power control circuit 40, but may include design-permissible errors or manufacturing errors. For example, the shape of component 40c is the same as the shape of the power control circuit 40, but may also include design-permissible errors or manufacturing errors. Component 40c is positioned symmetrically with respect to the substrate 5 and the power control circuit 40. The center of gravity of component 40c is located symmetrically with respect to the substrate 5 and the center of gravity of the power control circuit 40.

[0037] A connector portion 6 is provided at the first end of the substrate 5 along the X direction. The connector portion 6 is configured to physically and electrically connect the storage system 100 and the host device 200. A slit 7 is provided at an off-center position in the Y direction of the connector portion 6. The position of the slit 7 corresponds to the standard upon which communication between the storage system 100 and the host device 200 is based (e.g., PCIe). TM(Peripheral Component Interconnect express).

[0038] A component MP is disposed on the first surface of the substrate 5. Components 10c, 20c, 30c, and 40c are disposed on the second surface of the substrate 5. Components MP, 10c, 20c, 30c, and 40c can also be mounted on the substrate 5 in the form of a BGA (Ball Grid Array).

[0039] The memory controller 10, one of the components MP, is disposed near the center along the X direction relative to the non-volatile memories 20-1 and 20-2, the volatile memory 30, and the power control circuit 40.

[0040] Components 10c, 20c, 30c, and 40c can also be functional components. Functional components are those containing electronic circuitry. For example, components 10c, 20c, 30c, and 40c can also be IC chips. Components 10c, 20c, 30c, and 40c can also be non-functional components. Non-functional components are those without electronic circuitry. Components 10c, 20c, 30c, and 40c can also be plate-shaped parts. Components 10c, 20c, 30c, and 40c can also be made of iron.

[0041] 1.1.4 Cross-sectional structure of the storage system

[0042] Next, the cross-sectional structure of the storage system 100 of the embodiment will be described. Figure 3 This is a cross-sectional view of an example of the storage system according to the embodiment, along line III-III. The substrate 5 is a multilayer substrate. The substrate 5 includes a core 50, a plurality of pad electrodes 51, 52-1, 52-2, 53, 54, 51c, 52c-1, 52c-2, 53c, and 54c, and wiring layers 55, 56, 57, and 58.

[0043] The core 50 is an insulator. The core 50 covers a portion of each of the multiple pad electrodes 51, 52-1, 52-2, 53, 54, 51c, 52c-1, 52c-2, 53c, and 54c, as well as a portion or all of the wiring layers 55, 56, 57, and 58.

[0044] Multiple pad electrodes 51, 52-1, 52-2, 53, and 54 are solder pads. Multiple pad electrodes 51, 52-1, 52-2, 53, and 54 are disposed on the first surface of the substrate 5. Multiple pad electrodes 51, 52-1, 52-2, 53, and 54 are exposed from the core 50 on the first surface of the substrate 5.

[0045] Multiple pad electrodes 51c, 52c-1, 52c-2, 53c, and 54c are bonding pads. These pad electrodes 51c, 52c-1, 52c-2, 53c, and 54c are disposed on the second surface of the substrate 5. The pad electrodes 51c, 52c-1, 52c-2, 53c, and 54c are exposed from the core 50 on the second surface of the substrate 5.

[0046] Wiring layers 55, 56, 57, and 58 are conductive. Wiring layers 55, 56, 57, and 58 are disposed in different layers within the core 50. Wiring layers 55, 56, 57, and 58 are electrically connected to multiple solder pad electrodes 51, 52-1, 52-2, 53, and 54, and the connector portion 6, via through-holes (not shown). Wiring layers 55, 56, 57, and 58 may also be electrically connected to multiple solder pad electrodes 51c, 52c-1, 52c-2, 53c, and 54c via through-holes (not shown), or they may not be electrically connected. Wiring layers 55 and 58 each include, for example, a single wire extending throughout the layer to which it is disposed. A ground voltage or a power supply voltage can be applied to the wire contained in wiring layers 55 and 58. Therefore, the wire contained in wiring layers 55 and 58 is responsible for stabilizing the ground voltage and the power supply voltage. The ground voltage is a reference potential for any of the components MP (memory controller 10, non-volatile memory 20, volatile memory 30, and power control circuit 40) to operate. The reference potential is determined by the connection between the storage system 100 and the host device 200. The power supply voltage is a power supply potential for any of the components MP to operate. That is, each of wiring layers 55 and 58 can be grounded. Wiring layers 56 and 57 each contain, for example, multiple wirings distributed within the layer where they are configured. The multiple wirings contained in wiring layers 56 and 57 are responsible for communication between the storage system 100 and the host device 200.

[0047] Next, the connection relationship between components MP, 10c, 20c, 30c, and 40c and substrate 5 will be explained.

[0048] The memory controller 10 is connected to a plurality of ball electrodes 11. Each ball electrode 11 is a solder ball. The ball electrodes 11 are disposed on one surface of the memory controller 10. Each ball electrode 11 is connected to a plurality of pad electrodes 51. Thus, the memory controller 10 is electrically connected to the substrate 5.

[0049] Non-volatile memory devices 20-1 and 20-2 are respectively connected to a plurality of ball electrodes 21-1 and a plurality of ball electrodes 21-2. The ball electrodes 21-1 and 21-2 are solder balls. The ball electrodes 21-1 and 21-2 are disposed on one surface of each of the non-volatile memory devices 20-1 and 20-2. The ball electrodes 21-1 and 21-2 are respectively connected to a plurality of pad electrodes 52-1 and 52-2. Thus, the non-volatile memory devices 20-1 and 20-2 are electrically connected to the substrate 5.

[0050] The volatile memory 30 is connected to a plurality of ball electrodes 31. Each ball electrode 31 is a solder ball. The ball electrodes 31 are disposed on one surface of the volatile memory 30. Each ball electrode 31 is connected to a plurality of pad electrodes 53. Thus, the volatile memory 30 is electrically connected to the substrate 5.

[0051] A power control circuit 40 is connected to a plurality of ball electrodes 41. Each ball electrode 41 is a solder ball. The ball electrodes 41 are disposed on one side of the power control circuit 40. Each ball electrode 41 is connected to a plurality of pad electrodes 54. Thus, the power control circuit 40 is electrically connected to the substrate 5.

[0052] Component 10c is connected to a plurality of ball electrodes 11c. The plurality of ball electrodes 11c are solder balls. The plurality of ball electrodes 11c are disposed on one surface of component 10c. The plurality of ball electrodes 11c are respectively connected to a plurality of pad electrodes 51c. Thus, component 10c is electrically connected to substrate 5.

[0053] Components 20c-1 and 20c-2 are respectively connected to a plurality of ball electrodes 21c-1 and a plurality of ball electrodes 21c-2. The ball electrodes 21c-1 and 21c-2 are solder balls. The ball electrodes 21c-1 and 21c-2 are disposed on one surface of each of components 20c-1 and 20c-2. The ball electrodes 21c-1 and 21c-2 are respectively connected to a plurality of pad electrodes 52c-1 and 52c-2. Thus, components 20c-1 and 20c-2 are electrically connected to the substrate 5.

[0054] Component 30c is connected to a plurality of ball electrodes 31c. The plurality of ball electrodes 31c are solder balls. The plurality of ball electrodes 31c are disposed on one surface of component 30c. The plurality of ball electrodes 31c are respectively connected to a plurality of pad electrodes 53c. Thus, component 30c is electrically connected to substrate 5.

[0055] Component 40c is connected to a plurality of ball electrodes 41c. The plurality of ball electrodes 41c are solder balls. The plurality of ball electrodes 41c are disposed on one surface of component 40c. The plurality of ball electrodes 41c are respectively connected to a plurality of pad electrodes 54c. Thus, component 40c is electrically connected to substrate 5.

[0056] When components 10c, 20c, 30c, and 40c function as electronic circuits, they can communicate with component MP through electrical connections to wiring layers 55, 56, 57, and 58. When components 10c, 20c, 30c, and 40c do not function as electronic circuits, they can help stabilize grounding voltage and power supply voltage through electrical connections to wiring layers 55 and 58.

[0057] 1.1.5 Layout of pad electrodes on the substrate

[0058] Next, the layout of the pad electrodes 51, 52, 53, 54, 51c, 52c, 53, and 54c on the substrate 5 of the embodiment will be described. Figure 4 This is a top view illustrating an example of the layout of the pad electrodes on the substrate according to an embodiment. Specifically, in Figure 4 The upper part (A) shows a top view of the plurality of pad electrodes 51, 52, 53, and 54 disposed on the first surface of the substrate 5, viewed in the Z direction. Figure 4 The upper part (A) uses dotted lines to indicate the arrangement of component MP. Additionally, in... Figure 4 The lower part (B) shows a top view taken in the Z direction of multiple pad electrodes 51c, 52c, 53, and 54c disposed on the second surface of substrate 5. Figure 4 The lower part (B) uses dotted lines to represent the configuration of component MP.

[0059] Multiple pad electrodes 51 are arranged across the entire area of ​​the first surface of the substrate 5 that overlaps with the memory controller 10 when viewed in the Z direction. Conversely, multiple pad electrodes 51c are arranged across the entire area of ​​the second surface of the substrate 5 that overlaps with the component 10c when viewed in the Z direction. The multiple pad electrodes 51c are respectively positioned symmetrically with respect to the core 50 or the substrate 5 to the multiple pad electrodes 51. The center of gravity of the multiple pad electrodes 51c is located symmetrically with respect to the center of gravity of the multiple pad electrodes 51 with respect to the core 50 or the substrate 5. The number of multiple pad electrodes 51c is equal to the number of multiple pad electrodes 51.

[0060] Multiple pad electrodes 52-1 and 52-2 are respectively arranged across the entire region of the portion of the first surface of the substrate 5 that overlaps with the non-volatile memory 20-1 and 20-2 when viewed in the Z direction. Conversely, multiple pad electrodes 52c-1 and 52c-2 are respectively arranged across the entire region of the second surface of the substrate 5 that overlaps with the components 20c-1 and 20c-2 when viewed in the Z direction. The multiple pad electrodes 52c-1 are respectively arranged in positions symmetrical to the multiple pad electrodes 52-1 with respect to the core 50 or the substrate 5. The centroids of the multiple pad electrodes 52c-1 are located in positions symmetrical to the centroids of the multiple pad electrodes 52-1 with respect to the core 50 or the substrate 5. The multiple pad electrodes 52c-2 are respectively arranged in positions symmetrical to the multiple pad electrodes 52-2 with respect to the core 50. The centroids of the multiple pad electrodes 52c-2 are located in positions symmetrical to the centroids of the multiple pad electrodes 52-2 with respect to the core 50 or the substrate 5. The number of multiple pad electrodes 52c-1 and 52c-2 is equal to the number of multiple pad electrodes 52-1 and 52-2, respectively.

[0061] Multiple pad electrodes 53 are arranged across the entire region of the first surface of the substrate 5, overlapping with the volatile memory 30 when viewed in the Z direction. Conversely, multiple pad electrodes 53c are arranged across the entire region of the second surface of the substrate 5, overlapping with the component 30c when viewed in the Z direction. The multiple pad electrodes 53c are respectively positioned symmetrically with respect to the core 50 or the substrate 5 to the multiple pad electrodes 53. The center of gravity of the multiple pad electrodes 53c is located symmetrically with respect to the center of gravity of the multiple pad electrodes 53 with respect to the core 50 or the substrate 5. The number of multiple pad electrodes 53c is equal to the number of multiple pad electrodes 53.

[0062] Multiple pad electrodes 54 are arranged across the entire area of ​​the first surface of the substrate 5 that overlaps with the power control circuit 40 when viewed in the Z direction. Conversely, multiple pad electrodes 54c are arranged across the entire area of ​​the second surface of the substrate 5 that overlaps with the component 40c when viewed in the Z direction. The multiple pad electrodes 54c are respectively positioned symmetrically with respect to the core 50 or the substrate 5 to the multiple pad electrodes 54. The center of gravity of the multiple pad electrodes 54c is located symmetrically with respect to the center of gravity of the multiple pad electrodes 54 to the core 50 or the substrate 5. The number of multiple pad electrodes 54c is equal to the number of multiple pad electrodes 54.

[0063] 1.3 Effects of the Implementation Method

[0064] According to the embodiment, a plurality of pad electrodes 51, 52, 53, and 54 disposed on the first surface and a plurality of pad electrodes 51c, 52c, 53c, and 54c disposed on the second surface are positioned symmetrically with respect to the substrate 5. Therefore, stress concentration on either the first or second surface can be suppressed. Furthermore, defects caused by impact and heat can be suppressed.

[0065] According to the implementation method, it is possible to suppress the breakage of ball electrodes 11, 21-1, 21-2, 31 and 41, as well as wiring layers 55, 56, 57 and 58.

[0066] The memory controller 10 is a component that is prone to overheating due to heat generation. According to the embodiment, the memory controller 10 is disposed near the center along the long side of the substrate 5. Therefore, deviations in thermal stress along the long side can be suppressed. Thus, warping in the substrate 5 can be reduced.

[0067] Furthermore, according to the embodiment, the heat transferred from the component MP to the substrate 5 can be efficiently released to the second surface side.

[0068] 2. Variation Examples

[0069] Various variations can be made to the implementation. Hereinafter, examples of variations will be described. In one variation, a component is provided on the second surface, corresponding to the component MP on the first surface.

[0070] Figure 5 This is a top view showing an example of the layout of the components constituting a modified storage system. The modified storage system 100 includes, in addition to the substrate 5 and the component MP, component 60c.

[0071] Component 60c is the balancing weight of component MP. That is, component 60c has the same weight as component MP. For example, the weight of component 60c is equal to the total weight of component MP, but it may also include design-permissible errors or manufacturing errors. The center of gravity of component 60c is located symmetrically to the center of gravity of component MP relative to substrate 5. The center of gravity of component MP is the combined center of gravity of memory controller 10, non-volatile memory 20, volatile memory 30, and power control circuit 40. Component 60c can also be an electronic circuit. Component 60c can also be an IC chip. Component 60c can also be a plate-shaped component. Component 60c can also be iron. Component 60c is mounted on substrate 5 in BGA form. Component 60c has a shape that overlaps with component MP when viewed from above.

[0072] Figure 6 This is a cross-sectional view along line VI-VI of the storage system shown in the variation example. The substrate 5 is constructed in the same manner as in the embodiment.

[0073] Component 60c is electrically connected to substrate 5. Component 60c is electrically connected to wiring layers 55, 56, 57, and 58, thereby enabling communication with component MP. Component 60c is connected to multiple ball electrodes 61c, 62c-1, 62c-2, 63c, and 64c.

[0074] Multiple ball electrodes 61c, 62c-1, 62c-2, 63c, and 64c are solder balls. Multiple ball electrodes 61c, 62c-1, 62c-2, 63c, and 64c are disposed on one face of component 60c. Multiple ball electrodes 61c are connected to multiple pad electrodes 51c. Multiple ball electrodes 62c-1 are connected to multiple pad electrodes 52c-1. Multiple ball electrodes 62c-2 are connected to multiple pad electrodes 52c-2. Multiple ball electrodes 63c are connected to multiple pad electrodes 53c. Multiple ball electrodes 64c are connected to multiple pad electrodes 54c.

[0075] Figure 7This is a top view showing an example of the layout of the pad electrodes on the substrate in a variation example. The arrangement of the plurality of pad electrodes 51, 52, 53, 54, 51c, 52c, 53, and 54c is the same as in the embodiment. That is, the component 60c is connected to the substrate 5 via the plurality of pad electrodes 51c, 52c, 53c, and 54c, which are arranged in positions symmetrical with respect to the substrate 5 and to the plurality of pad electrodes 51, 52, 53, and 54.

[0076] According to the variation example, the connection points between substrate 5 and component MP and between substrate 5 and component 60c can be positioned symmetrically with respect to substrate 5. Therefore, stress concentration on specific solder balls can be suppressed.

[0077] Furthermore, according to the variation example, warping generated in the substrate 5 can be reduced. Therefore, breakage of the ball electrodes 11, 21-1, 21-2, 31 and 41, as well as the wiring layers 55, 56, 57 and 58, can be suppressed.

[0078] Furthermore, according to the variation example, the heat transferred from the component MP to the substrate 5 can be efficiently released to the second surface side.

[0079] 3. Other

[0080] A portion of the component MP can also be disposed on the second surface of the substrate 5. In this case, warping in the substrate 5 can also be reduced by disposing components 10c, 20c, 30c, and 40c at positions symmetrical to the substrate 5 for the component MP.

[0081] The embodiments described are illustrative, and the scope of the invention is not limited to the embodiments described.

Claims

1. A storage system, characterized in that... have: The substrate has a first surface and a second surface located on the opposite side of the first surface, and includes a core, a plurality of first pad electrodes and a plurality of second pad electrodes respectively disposed on the first surface, and a plurality of third pad electrodes and a plurality of fourth pad electrodes respectively disposed on the second surface. A memory controller is disposed on the first surface side; A non-volatile memory is disposed on the first surface side; The first component is disposed on the second surface side; The second component is disposed on the second surface side; A plurality of first electrodes are connected between the memory controller and each of the plurality of first pad electrodes; A plurality of second electrodes are connected between the non-volatile memory and each of the plurality of second pad electrodes; A plurality of third electrodes are connected between the first component and each of the plurality of third pad electrodes; and A plurality of fourth electrodes are connected between the second component and each of the plurality of fourth pad electrodes; and Each of the plurality of first pad electrodes and each of the plurality of third pad electrodes are positioned symmetrically with respect to an imaginary plane with respect to the centerline through the thickness direction of the substrate. Each of the plurality of second pad electrodes and each of the plurality of fourth pad electrodes are positioned symmetrically with respect to the imaginary plane. The center of gravity of the memory controller is symmetrical to the center of gravity of the first component relative to the imaginary plane, and the center of gravity of the non-volatile memory is symmetrical to the center of gravity of the second component relative to the imaginary plane, or The total weight of the memory controller and the plurality of first electrodes is equal to the total weight of the first component and the plurality of third electrodes, and the total weight of the non-volatile memory and the plurality of second electrodes is equal to the total weight of the second component and the plurality of fourth electrodes.

2. The storage system according to claim 1, characterized in that: The number of the plurality of first pad electrodes is equal to the number of the plurality of third pad electrodes. The number of the plurality of second pad electrodes is equal to the number of the plurality of fourth pad electrodes.

3. The storage system according to claim 1 or 2, characterized in that: The weight of the memory controller is equal to the weight of the first component. The weight of the non-volatile memory is equal to the weight of the second component.

4. The storage system according to claim 3, characterized in that: The shape of the memory controller is the same as the shape of the first component. The shape of the non-volatile memory is the same as the shape of the second component.

5. The storage system according to claim 1, characterized in that: The plurality of first electrodes, the plurality of second electrodes, the plurality of third electrodes, and the plurality of fourth electrodes comprise solder.

6. The storage system according to claim 1, characterized in that: The first component and the second component are plate-shaped parts containing iron.

7. The storage system according to claim 6, characterized in that: The substrate further includes a grounded wiring layer. The first component and the second component are electrically connected to the wiring layer.

8. A storage system, characterized in that... have: The substrate has a first surface and a second surface located on the opposite side of the first surface, and includes a core, a plurality of first pad electrodes and a plurality of second pad electrodes respectively disposed on the first surface, and a plurality of third pad electrodes and a plurality of fourth pad electrodes respectively disposed on the second surface. A memory controller is disposed on the first surface side; A non-volatile memory is disposed on the first surface side; The first component is disposed on the second surface side; The second component is disposed on the second surface side; A plurality of first electrodes are connected between the memory controller and each of the plurality of first pad electrodes; A plurality of second electrodes are connected between the non-volatile memory and each of the plurality of second pad electrodes; A plurality of third electrodes are connected between the first component and each of the plurality of third pad electrodes; and A plurality of fourth electrodes are connected between the second component and each of the plurality of fourth pad electrodes; and Each of the plurality of first pad electrodes and each of the plurality of third pad electrodes are positioned symmetrically with respect to an imaginary plane with respect to the centerline through the thickness direction of the substrate. Each of the plurality of second pad electrodes and each of the plurality of fourth pad electrodes are positioned symmetrically with respect to the imaginary plane. The substrate further includes a plurality of fifth pad electrodes disposed on the first surface and a plurality of sixth pad electrodes disposed on the second surface. The storage system further comprises: Volatile memory; The third component; A plurality of fifth electrodes are respectively connected between the volatile memory and the plurality of fifth pad electrodes; and A plurality of sixth electrodes are respectively connected between the third component and the plurality of sixth pad electrodes; and The plurality of fifth pad electrodes and the plurality of sixth pad electrodes are positioned symmetrically relative to the hypothetical face.

9. The storage system according to claim 8, characterized in that: The substrate further includes a plurality of seventh pad electrodes disposed on the first surface and a plurality of eighth pad electrodes disposed on the second surface. The storage system further comprises: Power control circuit; Component 4; A plurality of seventh electrodes are respectively connected between the power control circuit and the plurality of seventh pad electrodes; and A plurality of eighth electrodes are respectively connected between the fourth component and the plurality of eighth pad electrodes; and The plurality of seventh pad electrodes and the plurality of eighth pad electrodes are positioned symmetrically relative to the core.

10. The storage system according to claim 9, characterized in that: The substrate further includes a connector portion based on PCIe.

11. The storage system according to claim 10, characterized in that: The shape of the substrate conforms to the M.2 standard.

12. The storage system according to claim 8, characterized in that: The plurality of first electrodes, the plurality of second electrodes, the plurality of third electrodes, and the plurality of fourth electrodes comprise solder.

13. The storage system according to claim 8, characterized in that: The first component and the second component are plate-shaped parts containing iron.

14. A storage system, characterized in that... have: The substrate has a first surface and a second surface located on the opposite side of the first surface, and includes a core, a plurality of first pad electrodes and a plurality of second pad electrodes respectively disposed on the first surface, and a plurality of third pad electrodes and a plurality of fourth pad electrodes respectively disposed on the second surface. A memory controller is disposed on the first surface side; A non-volatile memory is disposed on the first surface side; The component is disposed on the second surface side; A plurality of first electrodes are connected between the memory controller and each of the plurality of first pad electrodes; A plurality of second electrodes are connected between the non-volatile memory and each of the plurality of second pad electrodes; A plurality of third electrodes are connected between the component and each of the plurality of third pad electrodes; and A plurality of fourth electrodes are connected between the component and each of the plurality of fourth pad electrodes; and Each of the plurality of first pad electrodes and each of the plurality of third pad electrodes are positioned symmetrically with respect to an imaginary plane with respect to the centerline through the thickness direction of the substrate. Each of the plurality of second pad electrodes and each of the plurality of fourth pad electrodes are positioned symmetrically with respect to the imaginary plane. The substrate further includes a plurality of fifth pad electrodes disposed on the first surface and a plurality of sixth pad electrodes disposed on the second surface. The storage system further comprises: Volatile memory; A plurality of fifth electrodes are respectively connected between the volatile memory and the plurality of fifth pad electrodes; and A plurality of sixth electrodes, between the component and the plurality of sixth pad electrodes; and The plurality of fifth pad electrodes and the plurality of sixth pad electrodes are positioned symmetrically relative to the hypothetical face.

15. The storage system according to claim 14, characterized in that: The substrate further includes a plurality of seventh pad electrodes disposed on the first surface and a plurality of eighth pad electrodes disposed on the second surface. The storage system further comprises: Power control circuit; A plurality of seventh electrodes are respectively connected between the power control circuit and the plurality of seventh pad electrodes; and A plurality of eighth electrodes are respectively connected between the component and the plurality of eighth pad electrodes; and The plurality of seventh pad electrodes and the plurality of eighth pad electrodes are positioned symmetrically with respect to the hypothetical face.

16. The storage system according to claim 15, characterized in that: The total weight of the memory controller, the non-volatile memory, the volatile memory, and the power control circuit is equal to the weight of the component.

17. The storage system according to claim 16, characterized in that: The combined center of gravity of the memory controller, the non-volatile memory, the volatile memory, and the power control circuit is located symmetrically with respect to the imaginary plane with respect to the center of gravity of the component.

18. The storage system according to claim 16, characterized in that: The total weight of the memory controller, the non-volatile memory, the volatile memory, the power control circuit, the plurality of first electrodes, the plurality of second electrodes, the plurality of fifth electrodes, and the plurality of seventh electrodes is equal to the total weight of the component, the plurality of third electrodes, the plurality of fourth electrodes, the plurality of sixth electrodes, and the plurality of eighth electrodes.

19. The storage system according to claim 15, characterized in that: The substrate further includes a connector portion based on PCIe.

20. The storage system according to claim 19, characterized in that: The shape of the substrate conforms to the M.2 standard.

21. The storage system according to claim 14, characterized in that: The plurality of first electrodes, the plurality of second electrodes, the plurality of third electrodes, and the plurality of fourth electrodes comprise solder.

22. The storage system according to claim 14, characterized in that: The component is a plate-shaped part containing iron.

23. The storage system according to claim 22, characterized in that: The substrate further includes a grounded wiring layer. The component is electrically connected to the wiring layer.

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