semiconductor devices

Abstract

The present invention aims to facilitate thermal design for a semiconductor device having a MOSFET and an SBD connected in anti-parallel. The semiconductor device (101) comprises: a MOSFET chip (5) arranged on a pattern (31), wherein its drain electrode and source electrode are electrically connected to the pattern (31) and the pattern (32), respectively; an SBD chip (6) arranged on a pattern (33), wherein its cathode electrode and anode electrode are electrically connected to the pattern (33) and the pattern (34), respectively; a drain main terminal (7) connected to the pattern (31); a source main terminal (8) connected to the pattern (32); a cathode main terminal (9) connected to the pattern (33); and an anode main terminal (10) connected to the pattern (34). At least one of the drain main terminal (7) and the cathode main terminal (9) and the source main terminal (8) and the anode main terminal (10) is not electrically connected.

Description

Technical Field

[0001] The present invention relates to semiconductor devices. Background Art

[0002] Patent Document 1 discloses a semiconductor device comprising a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and a Schottky barrier diode (SBD) connected in antiparallel with the MOSFET, with the GND between the MOSFET and the SBD separated. This semiconductor device structure allows for separate measurement of the forward voltage Vf of the MOSFET and the SBD, and for the thermal resistance of the MOSFET and the SBD to be measured independently based on the temperature dependence of their respective forward voltages Vf.

[0003] Patent Document 1: Japanese Patent Application Laid-Open No. 2005-310907

[0004] In the semiconductor device of Patent Document 1, the MOSFET chip and SBD chip are mounted on the same die pad, resulting in significant thermal interference between the two chips. Consequently, differences in thermal resistance values occur during actual use under various heat-generating conditions, as well as when thermal resistance measurements are taken of the individual chips, making thermal design difficult. Summary of the Invention

[0005] The present invention has been made to solve the above-mentioned problem, and an object of the present invention is to facilitate thermal design of a semiconductor device including a MOSFET and an SBD.

[0006] The semiconductor device of the present invention comprises: a base plate; at least one insulating substrate provided on the base plate; a first pattern, a second pattern, a third pattern, and a fourth pattern as conductive patterns, which are separately provided on the at least one insulating substrate; a MOSFET chip provided on the first pattern, the drain electrode and the source electrode of the MOSFET chip being electrically connected to the first pattern and the second pattern, respectively; an SBD chip provided on the third pattern, the cathode electrode and the anode electrode of the SBD chip being electrically connected to the third pattern and the fourth pattern, respectively; a drain terminal connected to the first pattern; a source terminal connected to the second pattern; a cathode terminal connected to the third pattern; and an anode terminal connected to the fourth pattern. The drain terminal is not electrically connected to at least one of the cathode terminal and the source terminal is not electrically connected to the anode terminal.

[0007] Effects of the Invention

[0008] In the semiconductor device of the present invention, since the MOSFET chip and the SBD chip are disposed on separate conductive patterns, thermal interference between the MOSFET chip and the SBD chip is suppressed. As a result, the thermal resistance of the two chips during actual use can be brought close to the thermal resistance measured for each chip alone, facilitating thermal design. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 This is a top view of the semiconductor device according to the first embodiment.

[0010] Figure 2 It is an equivalent circuit diagram of a semiconductor device.

[0011] Figure 3 This is a top view of a semiconductor device according to a first modification of the first embodiment.

[0012] Figure 4 It is an equivalent circuit diagram of a semiconductor device.

[0013] Figure 5 This is a top view of a semiconductor device according to a second modification of the first embodiment.

[0014] Figure 6 It is an equivalent circuit diagram of a semiconductor device.

[0015] Figure 7 This is a top view of a semiconductor device according to a second embodiment.

[0016] Figure 8 This is a top view of a semiconductor device according to a first modification of the second embodiment.

[0017] Figure 9 This is a top view of a semiconductor device according to a second variation of the second embodiment.

[0018] Figure 10 This is a top view of a semiconductor device according to a third embodiment.

[0019] Figure 11 This is a top view of a semiconductor device according to a first variation of the third embodiment.

[0020] Figure 12 This is a top view of a semiconductor device according to a second variation of the third embodiment.

[0021] Figure 13 This is a top view of a semiconductor device according to a third modification of the third embodiment.

[0022] Figure 14 This is a top view of a semiconductor device according to a fourth embodiment.

[0023] Figure 15This is a top view of a semiconductor device according to a first variation of the fourth embodiment.

[0024] Figure 16 This is a top view of a semiconductor device according to a second variation of the fourth embodiment.

[0025] Figure 17 This is a top view of a semiconductor device according to a third variation of the fourth embodiment. DETAILED DESCRIPTION

[0026] <A. Implementation Method 1>

[0027] A-1. Structure

[0028] Figure 1 This is a top view of a semiconductor device 101 according to Embodiment 1. The semiconductor device 101 includes a base plate 1, an insulating substrate 2, conductive patterns 31, 32, 33, 34, and 35, a plurality of MOSFET chips 5, a plurality of SBD chips 6, a drain main terminal 7, a source main terminal 8, a cathode main terminal 9, an anode main terminal 10, a drain auxiliary terminal 11, a gate auxiliary terminal 12, a source auxiliary terminal 13, a cathode auxiliary terminal 14, and an anode auxiliary terminal 15.

[0029] An insulating substrate 2 is mounted on a base plate 1. Patterns 31, 32, 33, 34, and 35 are formed on the insulating substrate 2.

[0030] A plurality of MOSFET chips 5 are mounted on the pattern 31. A drain electrode is present on the lower surface of each MOSFET chip 5, and a source electrode and a gate electrode are present on the upper surface. Therefore, by mounting each MOSFET chip 5 on the pattern 31, the drain electrode of each MOSFET chip 5 is electrically connected to the pattern 31. In other words, the pattern 31 is a drain conductive pattern having the same potential as the drain electrode. The pattern 31 is also referred to as the first pattern. The pattern 31 is connected to the drain main terminal 7 and the drain auxiliary terminal 11. The drain main terminal 7 is an external connection terminal for connecting the drain electrode of each MOSFET chip 5 to the outside of the semiconductor device 101.

[0031] The source electrodes on the top surfaces of the MOSFET chips 5 are connected to each other via wires 41 and are also connected to pattern 32. Specifically, pattern 32 is a source conductive pattern at the same potential as the source electrodes. Pattern 32 is also referred to as a second pattern. Pattern 32 is connected to source main terminal 8 and source auxiliary terminal 13. Source main terminal 8 is an external connection terminal for connecting the source electrodes of each MOSFET chip 5 to the outside of semiconductor device 101.

[0032] The gate electrodes on the upper surfaces of the MOSFET chips 5 are connected to each other via wires 42 and are also connected to the pattern 35. That is, the pattern 35 is a gate conductive pattern having the same potential as the gate electrode. The pattern 35 is connected to the gate auxiliary terminal 12.

[0033] A plurality of SBD chips 6 are mounted on the pattern 33. A cathode electrode is present on the lower surface of each SBD chip 6, and an anode electrode is present on the upper surface. Therefore, by mounting each SBD chip 6 on the pattern 33, the cathode electrode of each SBD chip 6 is electrically connected to the pattern 33. That is, the pattern 33 is a cathode conductive pattern having the same potential as the cathode electrode. The pattern 33 is also referred to as the third pattern. The pattern 33 is connected to the cathode main terminal 9 and the cathode auxiliary terminal 14. The cathode main terminal 9 is an external connection terminal for connecting the cathode electrode of each SBD chip 6 to the outside of the semiconductor device 101.

[0034] The anode electrodes on the top surfaces of each SBD chip 6 are connected to each other via a wire 43 and are also connected to pattern 34. Specifically, pattern 34 is an anode conductive pattern with the same potential as the anode electrodes. Pattern 34 is also referred to as the fourth pattern. Pattern 34 is connected to the anode main terminal 10 and the anode auxiliary terminal 15. The anode main terminal 10 is an external connection terminal for connecting the anode electrodes of the SBD chip 6 to the outside of the semiconductor device 101.

[0035] The drain main terminal 7 is not directly connected to the cathode main terminal 9. Furthermore, the drain main terminal 7 is connected to a pattern 31 that is different from the pattern 33 connected to the cathode main terminal 9, and the two patterns 31 and 33 are insulated by the insulating substrate 2. Therefore, the drain main terminal 7 is not electrically connected to the cathode main terminal 9.

[0036] Similarly, the source main terminal 8 is not directly connected to the anode main terminal 10. Furthermore, the source main terminal 8 is connected to a pattern 32 that is different from the pattern 34 to which the anode main terminal 10 is connected, and the two patterns 32 and 34 are insulated from each other by the insulating substrate 2. Therefore, the source main terminal 8 is not electrically connected to the anode main terminal 10.

[0037] Figure 2 This is an equivalent circuit diagram of semiconductor device 101. The multiple MOSFET chips 5 correspond to MOSFET 51 and body diode 52 connected between the source and drain of MOSFET 51. Furthermore, the multiple SBD chips 6 correspond to SBD 61. The drain electrode of MOSFET 51 is not electrically connected to the cathode electrode of SBD 61. Furthermore, the source electrode of MOSFET 51 is not electrically connected to the anode electrode of SBD 61.

[0038] A-2. Effects

[0039] In the semiconductor device 101 of the first embodiment, the drain main terminal 7 is not electrically connected to the cathode main terminal 9, and the source main terminal 8 is not electrically connected to the anode main terminal 10. Therefore, the forward voltage Vf of the body diode 52 of the MOSFET 51 and the forward voltage Vf of the SBD 61 can be measured separately. Therefore, the temperature dependence of these forward voltages Vf can be used to accurately measure the thermal resistance of the MOSFET 51 and the SBD 61.

[0040] In particular, when the MOSFET is a SiC-MOSFET using SiC as the semiconductor material, the SiC-MOSFET has complex temperature characteristics. Therefore, accurate thermal resistance measurement can be performed simply by measuring the thermal resistance using the body diode. Therefore, the structure of the semiconductor device 101 is effective in enabling thermal resistance measurement using a practically usable element.

[0041] In semiconductor device 101, multiple MOSFET chips 5 are mounted on patterns 31 and 32, and multiple SBD chips 6 are mounted on patterns 33 and 34. By mounting the multiple MOSFET chips 5 and the multiple SBD chips 6 on different patterns, thermal interference between the multiple MOSFET chips 5 and the multiple SBD chips 6 is suppressed. Consequently, during actual use, when the multiple MOSFET chips 5 and the multiple SBD chips 6 generate heat under their respective operating conditions, and when thermal resistance measurements are performed on individual chips, the difference in thermal resistance values is minimized, facilitating thermal design.

[0042] like Figure 1 As shown, patterns 31 and 32 for mounting multiple MOSFET chips 5 and patterns 33 and 34 for mounting multiple SBD chips 6 preferably have substantially the same shape. Specifically, pattern 31 preferably has substantially the same shape as pattern 33, and pattern 32 preferably has substantially the same shape as pattern 34. This makes the heat capacity from each MOSFET chip 5 to the base plate 1 substantially equal to the heat capacity from each SBD chip 6 to the base plate 1, facilitating design using transient thermal resistance.

[0043] A-3. Modifications

[0044] In order to measure the forward voltage Vf of the body diode 52 of the MOSFET 51 and the forward voltage Vf of the SBD 61 separately, it is sufficient that at least one of the drain main terminal 7 and the cathode main terminal 9 and the source main terminal 8 and the anode main terminal 10 is not electrically connected. Figure 3In the semiconductor device 102 of the first variant of the first embodiment, shown in a top view, the drain main terminal 7 and the cathode main terminal 9 are connected to each other by a common terminal 16. Common terminal 16 is also referred to as a first common terminal. Common terminal 16 includes a first component 161 extending linearly from the drain conductive pattern, i.e., pattern 31, in a direction perpendicular to the end side of base plate 1; a second component 162 extending linearly from the cathode conductive pattern, i.e., pattern 33, in a direction perpendicular to the end side of base plate 1; and a third component 163 connecting first component 161 and second component 162. First component 161 is a current path from the external structure of the semiconductor device connected to common terminal 16 to pattern 31, and constitutes drain main terminal 7. Furthermore, second component 162 is a current path from the external structure of the semiconductor device connected to common terminal 16 to pattern 33, and constitutes cathode main terminal 9. Figure 4 is an equivalent circuit diagram of the semiconductor device 102. Figure 4 In FIG. 5 , the source terminal of the MOSFET 51 is not electrically connected to the anode terminal of the SBD 61 , but the drain terminal of the MOSFET 51 is electrically connected to the anode terminal of the SBD 61 .

[0045] In addition, you can also Figure 5 In the semiconductor device 103 of the second variant of the first embodiment, shown in a top view, the source main terminal 8 and the anode main terminal 10 are connected to each other by a common terminal 17. Common terminal 17 is also referred to as a second common terminal. Common terminal 17 includes a first member 171 extending linearly from pattern 32, a source conductive pattern, in a direction perpendicular to the end side of base plate 1; a second member 172 extending linearly from pattern 34, an anode conductive pattern, in a direction perpendicular to the end side of base plate 1; and a third member 173 connecting first member 171 and second member 172. First member 171 is a current path from the external structure of the semiconductor device connected to common terminal 17 to pattern 32, and constitutes source main terminal 8. Furthermore, second member 172 is a current path from the external structure of the semiconductor device connected to common terminal 17 to pattern 34, and constitutes anode main terminal 10. Figure 6 is an equivalent circuit diagram of the semiconductor device 103. Figure 6 In FIG. 5 , the drain terminal of the MOSFET 51 is not electrically connected to the cathode terminal of the SBD 61 , but the source terminal of the MOSFET 51 is electrically connected to the anode terminal of the SBD 61 .

[0046] exist Figure 3, an example is shown in which the drain main terminal 7 and the cathode main terminal 9 are connected by a common terminal 16. Instead of this structure, a structure in which the drain conductive pattern 31 and the cathode conductive pattern 33 are connected by a bus bar is also possible, whereby the drain main terminal 7 and the cathode main terminal 9 are electrically connected. Figure 5 , an example is shown in which the source main terminal 8 and the anode main terminal 10 are connected via a common terminal 17. Instead of this structure, a structure in which the source conductive pattern 32 and the anode conductive pattern 34 are connected via a bus bar is also possible, thereby electrically connecting the source main terminal 8 and the anode main terminal 10.

[0047] <B. Implementation Method 2>

[0048] B-1. Structure

[0049] Figure 7 This is a top view of a semiconductor device 201 according to a second embodiment. In the semiconductor device 101 according to the first embodiment, patterns 31 and 32 for mounting multiple MOSFET chips 5 and patterns 33 and 34 for mounting multiple SBD chips 6 are provided on the same insulating substrate 2. In contrast, in the semiconductor device 201 according to the second embodiment, patterns 31 and 32 for mounting multiple MOSFET chips 5 and patterns 33 and 34 for mounting multiple SBD chips 6 are provided on different insulating substrates 21 and 22. That is, in the semiconductor device 201, insulating substrates 21 and 22 are mounted on a base plate 1. Furthermore, patterns 31 and 32 are formed on insulating substrate 21, and patterns 33 and 34 are formed on insulating substrate 22. The remaining structure of the semiconductor device 201 is the same as that of the semiconductor device 101.

[0050] The equivalent circuit diagram of the semiconductor device 201 is Figure 2 The equivalent circuit diagram of the semiconductor device 101 shown is the same.

[0051] B-2. Effects

[0052] Semiconductor device 201 achieves the following advantages in addition to those of semiconductor device 101. In semiconductor device 201, patterns 31 and 32 for mounting multiple MOSFET chips 5 and patterns 32 and 4b for mounting multiple SBD chips 6 are provided on separate insulating substrates 21 and 22, respectively. This reduces thermal interference between the multiple MOSFET chips 5 and the multiple SBD chips 6, compared to the structure of Embodiment 1. Consequently, during actual use, when the multiple MOSFET chips 5 and the multiple SBD chips 6 generate heat under their respective operating conditions, and when thermal resistance measurements are performed on individual chips, the difference in thermal resistance values is further reduced, making thermal design easier.

[0053] like Figure 7 As shown, the insulating substrate 21 and the insulating substrate 22 preferably have substantially the same shape. This makes the heat capacity from each MOSFET chip 5 to the base plate 1 substantially equal to the heat capacity from each SBD chip 6 to the base plate 1, thereby facilitating design using transient thermal resistance.

[0054] B-3. Modifications

[0055] Figure 8 1 is a top view of a semiconductor device 202 according to a first variation of the second embodiment. The first variation of the second embodiment is a variation obtained by applying the first variation of the first embodiment to the second embodiment. The semiconductor device 202 is the same as the semiconductor device 201 except that the drain main terminal 7 and the cathode main terminal 9 are connected by a common terminal 16. The equivalent circuit diagram of the semiconductor device 202 is the same as that of the semiconductor device 201. Figure 4 The equivalent circuit diagram of the semiconductor device 102 shown is the same.

[0056] Figure 9 2 is a top view of a semiconductor device 203 according to a second variation of the second embodiment. The second variation of the second embodiment is a variation obtained by applying the second variation of the first embodiment to the second embodiment. The semiconductor device 203 is the same as the semiconductor device 201 except that the source main terminal 8 and the anode main terminal 10 are connected by a common terminal 17. The equivalent circuit diagram of the semiconductor device 203 is the same as that of the semiconductor device 201. Figure 6 The equivalent circuit diagram of the semiconductor device 103 shown is the same.

[0057] <C. Implementation Method 3>

[0058] <C-1. Structure>

[0059] Figure 10 : is a top view of a semiconductor device 301 according to Embodiment 3. In the first variant of Embodiment 1, the drain main terminal 7 and the cathode main terminal 9 are connected by being formed by a common terminal 16. In contrast, in the semiconductor device 301, the drain conductive pattern, i.e., pattern 31, and the cathode conductive pattern, i.e., pattern 33, are connected by a wire 44, thereby electrically connecting the drain main terminal 7 and the cathode main terminal 9. The structure of the semiconductor device 301 is otherwise the same as that of the semiconductor device 101 according to Embodiment 1. The equivalent circuit diagram of the semiconductor device 301 is the same as that of the semiconductor device 101 according to Embodiment 1. Figure 4 The equivalent circuit diagram of the semiconductor device 102 shown is the same.

[0060] C-2. Effects

[0061] In semiconductor device 301 of Embodiment 3, pattern 31 (a drain conductive pattern) and pattern 33 (a cathode conductive pattern) are connected via wire 44, thereby electrically connecting drain main terminal 7 and cathode main terminal 9. Therefore, compared to the first modified embodiment of Embodiment 1, in which drain main terminal 7 and cathode main terminal 9 are connected via common terminal 16, thermal interference between the plurality of MOSFET chips 5 and the plurality of SBD chips 6 is suppressed. As a result, compared to the first modified embodiment of Embodiment 1, the difference in thermal resistance values between the plurality of MOSFET chips 5 and the plurality of SBD chips 6 during actual use, where they generate heat under their respective operating conditions, and when thermal resistance is measured as a single chip, is reduced, facilitating thermal design.

[0062] <C-3. Modification>

[0063] Figure 11 1 is a top view of a semiconductor device 302 according to a first variant of embodiment 3. The first variant of embodiment 3 is a variant obtained by applying the second variant of embodiment 1 to embodiment 3. In the semiconductor device 302, the source conductive pattern, i.e., pattern 32, and the anode conductive pattern, i.e., pattern 34, are connected by a wire 45, thereby electrically connecting the source main terminal 8 and the anode main terminal 10. The structure of the semiconductor device 302 is otherwise the same as that of the semiconductor device 101 according to embodiment 1. The equivalent circuit diagram of the semiconductor device 302 is the same as that of the semiconductor device 101 according to embodiment 1. Figure 6 The equivalent circuit diagram of the semiconductor device 103 shown is the same.

[0064] Figure 12 : is a top view of a semiconductor device 303 of a second variant of embodiment 3. The second variant of embodiment 3 is a variant obtained by applying the first variant of embodiment 2 to embodiment 3. In the semiconductor device 303, the drain conductive pattern, i.e., pattern 31, and the cathode conductive pattern, i.e., pattern 33, are connected by a wire 44, whereby the source main terminal 8 of each MOSFET chip 5 and the anode main terminal 10 of each SBD chip 6 are electrically connected. The structure of the semiconductor device 303 is otherwise the same as that of the semiconductor device 201 of embodiment 2. The equivalent circuit diagram of the semiconductor device 303 is the same as that of the semiconductor device 201 of embodiment 2. Figure 4 The equivalent circuit diagram of the semiconductor device 102 shown is the same.

[0065] Figure 133 is a top view of a semiconductor device 304 of the third variant of the third embodiment. The third variant of the third embodiment is a variant obtained by applying the second variant of the second embodiment to the third embodiment. In the semiconductor device 304, the source conductive pattern, i.e., pattern 32, and the anode conductive pattern, i.e., pattern 34, are connected by a wire 45, whereby the source main terminal 8 of each MOSFET chip 5 and the anode main terminal 10 of each SBD chip 6 are electrically connected. The structure of the semiconductor device 304 is otherwise the same as that of the semiconductor device 201 of the second embodiment. The equivalent circuit diagram of the semiconductor device 304 is the same as that of the semiconductor device 201 of the second embodiment. Figure 6 The equivalent circuit diagram of the semiconductor device 103 shown is the same.

[0066] <D. Implementation Method 4>

[0067] <D-1. Structure>

[0068] Figure 14 This is a top view of a semiconductor device 401 according to Embodiment 4. Semiconductor device 401 differs from semiconductor device 102 according to the first variation of Embodiment 1 only in that common terminal 18 is included instead of common terminal 16. Common terminal 18, like common terminal 16, is also referred to as a first common terminal.

[0069] Common terminal 18 is constructed with a first member 181 extending linearly from pattern 33, a cathode conductive pattern, in a direction perpendicular to the edge of base plate 1, and a second member 182 connecting pattern 31, a drain conductive pattern, to first member 181. First member 181 forms the current path from the external structure of the semiconductor device connected to common terminal 18 to pattern 33, constituting cathode main terminal 9. Furthermore, the portion from the external structure of the semiconductor device connected to common terminal 18 to the connection between first member 181 and second member 182, as well as the entirety of second member 182, forms the current path from the external structure to pattern 31, constituting drain main terminal 7. In other words, common terminal 18 is connected to both pattern 31 and pattern 33, and is extended with an offset toward pattern 33, a cathode conductive pattern.

[0070] D-2. Effects

[0071] Due to the shape of the common terminal 18, the drain main terminal 7 is longer than the cathode main terminal 9. Therefore, the wiring inductance of the drain main terminal 7 is greater than the wiring inductance of the cathode main terminal 9. As a result, when the SBD chip 6 is energized, the body diode 52 of the MOSFET 51 is prevented from being turned on by the induced electromotive force generated by the wiring inductance of the cathode main terminal 9 on the SBD chip 6 side.

[0072] <D-3. Modification>

[0073] Figure 15 This is a top view of a semiconductor device 402 according to a first variation of Embodiment 4. The first variation of Embodiment 4 is a variation obtained by applying the first variation of Embodiment 2 to Embodiment 4. Semiconductor device 402 differs from semiconductor device 202 according to the first variation of Embodiment 2 only in that common terminal 16 is replaced with common terminal 18.

[0074] Figure 16 This is a top view of a semiconductor device 403 according to the second variant of embodiment 4. The second variant of embodiment 4 is a variant obtained by applying the second variant of embodiment 1 to embodiment 4. Semiconductor device 403 differs from semiconductor device 103 according to the second variant of embodiment 1 only in that common terminal 19 is replaced with common terminal 17. Common terminal 19, like common terminal 17, is also referred to as a second common terminal. Common terminal 19 is constructed to include a first component 191 extending linearly from pattern 34, an anode conductive pattern, in a direction perpendicular to the end edge of base plate 1, and a second component 192 connecting pattern 32, a source conductive pattern, to first component 191. First component 191 is a current path from the external structure of the semiconductor device connected to common terminal 19 to pattern 34, and constitutes anode main terminal 10. Furthermore, the portion from the external structure of the semiconductor device connected to the common terminal 19 to the connection between the first component 191 and the second component 192, and the entire second component 192, constitutes the current path from the external structure to the pattern 32 and forms the source main terminal 8. In other words, the common terminal 19 is connected to both the pattern 32 and the pattern 34, and the common terminal 19 is drawn out toward the anode conductive pattern, i.e., the pattern 34.

[0075] Due to the shape of the common terminal 19, the source main terminal 8 is longer than the anode main terminal 10. Therefore, the wiring inductance of the source main terminal 8 is greater than the wiring inductance of the anode main terminal 10. As a result, it is possible to prevent the body diode 52 of the MOSFET 51 from being turned on when the SBD chip 6 is energized due to the induced electromotive force generated by the wiring inductance of the anode main terminal 10 on the SBD chip 6 side.

[0076] Figure 17 This is a top view of a semiconductor device 404 according to a third variation of Embodiment 4. The third variation of Embodiment 4 is a variation obtained by applying the second variation of Embodiment 2 to Embodiment 4. Semiconductor device 404 differs from semiconductor device 203 according to the second variation of Embodiment 2 only in that common terminal 19 is included instead of common terminal 17.

[0077] The shapes of the common terminals 18 and 19 described above are merely examples. Common terminals 18 and 19 may be shaped such that the wiring inductance on the MOSFET chip 5 side is greater than the wiring inductance on the SBD chip 6 side. Specifically, common terminal 18 may be shaped such that the wiring inductance of the drain main terminal 7 is greater than the wiring inductance of the cathode main terminal 9. Furthermore, common terminal 19 may be shaped such that the wiring inductance of the source main terminal 8 is greater than the wiring inductance of the anode main terminal 10.

[0078] The structures of Embodiment 3 and Embodiment 4 may be combined. Specifically, the drain main terminal 7 and cathode main terminal 9 may be provided separately and connected to patterns 31 and 33 via wire 44. In this case, the shapes of the drain main terminal 7 and cathode main terminal 9 are designed so that the wiring inductance of the drain main terminal 7 is greater than the wiring inductance of the cathode main terminal 9. Alternatively, the source main terminal 8 and anode main terminal 10 may be provided separately and connected to patterns 32 and 34 via wire 45. In this case, the shapes of the source main terminal 8 and anode main terminal 10 are designed so that the wiring inductance of the source main terminal 8 is greater than the wiring inductance of the anode main terminal 10.

[0079] Furthermore, the various embodiments can be freely combined, or the various embodiments can be appropriately modified or omitted.

[0080] Description of the label

[0081] 1 base plate, 2, 21, 22 insulating substrate, 5 MOSFET chip, 6 SBD chip, 7 drain main terminal, 8 source main terminal, 9 cathode main terminal, 10 anode main terminal, 11 drain auxiliary terminal, 12 gate auxiliary terminal, 13 source auxiliary terminal, 14 cathode auxiliary terminal, 15 anode auxiliary terminal, 16, 18 first common terminals, 17, 19 second common terminals, 31, 32, 33, 34, 35 patterns, 41, 42, 43, 44, 45 wires, 51 MOSFET, 52 body diode, 61 SBD.

Claims

1. A semiconductor device comprising: base plate; at least one insulating substrate disposed on the base plate; a first pattern, a second pattern, a third pattern, and a fourth pattern as conductive patterns, which are separately provided on the at least one insulating substrate; a MOSFET chip disposed on the first pattern, wherein the drain electrode and the source electrode of the MOSFET chip are electrically connected to the first pattern and the second pattern respectively; an SBD chip disposed on the third pattern, wherein the cathode electrode and the anode electrode of the SBD chip are electrically connected to the third pattern and the fourth pattern respectively; a drain terminal connected to the first pattern; a source terminal connected to the second pattern; a cathode terminal connected to the third pattern; as well as an anode terminal connected to the fourth pattern, The drain terminal is not electrically connected to at least one of the cathode terminal and the source terminal is not electrically connected to the anode terminal. The drain terminal is electrically connected to the cathode terminal, The semiconductor device has a first common terminal connected to the first pattern and the third pattern. The current path from the external connection end of the first common terminal to the first pattern constitutes the drain terminal. The current path from the external connection end of the first common terminal to the third pattern constitutes the cathode terminal. The wiring inductance of the drain terminal is greater than the wiring inductance of the cathode terminal.

2. The semiconductor device according to claim 1, wherein The first pattern and the third pattern are connected by a conductive wire.

3. A semiconductor device comprising: base plate; at least one insulating substrate disposed on the base plate; a first pattern, a second pattern, a third pattern, and a fourth pattern as conductive patterns, which are separately provided on the at least one insulating substrate; a MOSFET chip disposed on the first pattern, wherein the drain electrode and the source electrode of the MOSFET chip are electrically connected to the first pattern and the second pattern respectively; an SBD chip disposed on the third pattern, wherein the cathode electrode and the anode electrode of the SBD chip are electrically connected to the third pattern and the fourth pattern respectively; a drain terminal connected to the first pattern; a source terminal connected to the second pattern; a cathode terminal connected to the third pattern; as well as an anode terminal connected to the fourth pattern, The drain terminal is not electrically connected to at least one of the cathode terminal and the source terminal is not electrically connected to the anode terminal. The source terminal is electrically connected to the anode terminal, The semiconductor device has a second common terminal connected to the second pattern and the fourth pattern. The current path from the external connection end of the second common terminal to the second pattern constitutes the source terminal. The current path from the external connection end of the second common terminal to the fourth pattern constitutes the anode terminal. The wiring inductance of the source terminal is larger than the wiring inductance of the anode terminal.

4. The semiconductor device according to claim 3, wherein The second pattern and the fourth pattern are connected by a conductive wire.

5. The semiconductor device according to any one of claims 1 to 4, wherein The first pattern and the third pattern have substantially the same shape, The second pattern and the fourth pattern have substantially the same shape.

6. The semiconductor device according to any one of claims 1 to 4, wherein The at least one insulating substrate includes a first insulating substrate and a second insulating substrate. The first pattern and the second pattern are provided on the first insulating substrate, and the third pattern and the fourth pattern are provided on the second insulating substrate.

7. The semiconductor device according to claim 6, wherein The first insulating substrate and the second insulating substrate have substantially the same shape.

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