Array substrate and display panel

Abstract

The application provides an array substrate and a display panel, comprising: a substrate and a plurality of pixel circuit groups and a plurality of signal line groups located on the substrate, the plurality of pixel circuit groups and the plurality of signal line groups are arranged at intervals along a row direction, the pixel circuit group comprises two pixel circuit subgroups arranged at intervals along the row direction; the at least part of the orthographic projection of the signal line group on the substrate is between the orthographic projections of the two pixel circuit subgroups in the same pixel circuit group on the substrate; one pixel circuit group is arranged correspondingly with one signal line group, and the two pixel circuit subgroups in the pixel circuit group are electrically connected with the signal line group. The distance between the two adjacent signal line groups is large, and the orthographic projection of at least part of the light emitting unit on the substrate is between the orthographic projections of the two adjacent signal line groups on the substrate. Therefore, the array substrate and the display panel provided by the application can improve the color deviation phenomenon of the display panel, thereby ensuring the display effect of the display panel.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to an array substrate and a display panel. BACKGROUND

[0002] Organic Light-Emitting Diode (OLED) as a kind of self-luminous device, because it has low power consumption, high color saturation, wide viewing angle, thin thickness, can realize flexible and does not need backlight source and other excellent performance, is widely used in terminal equipment and wearable device and other display devices.

[0003] The display panel can include a substrate, a metal trace layer and a light-emitting layer which are sequentially stacked on the substrate, the light-emitting layer includes a plurality of light-emitting units arranged at intervals, and a normal projection of the metal trace layer on the substrate partially overlaps a normal projection of the light-emitting units on the substrate.

[0004] However, in the related art, the color shift phenomenon of the light-emitting unit under a large viewing angle is more serious, which affects the display effect of the display panel. SUMMARY

[0005] In view of the above at least one technical problem, the embodiments of the present application provide an array substrate and a display panel, which can improve the color shift phenomenon of the display panel, thereby ensuring the display effect of the display panel.

[0006] In order to achieve the above purpose, the embodiments of the present application provide the following technical solutions:

[0007] The first aspect of the embodiments of the present application provides an array substrate, comprising: a substrate and a plurality of pixel circuit groups and a plurality of signal line groups on the substrate, the plurality of pixel circuit groups and the plurality of signal line groups are arranged at intervals along a row direction, the pixel circuit group includes two pixel circuit subgroups arranged at intervals along the row direction; at least part of the normal projection of the signal line group on the substrate is located between the normal projections of the two pixel circuit subgroups in the same pixel circuit group on the substrate; one pixel circuit group and one signal line group are correspondingly arranged, and the two pixel circuit subgroups in the pixel circuit group are electrically connected with the signal line group.

[0008] The array substrate provided by the embodiments of the present application can include a substrate and a plurality of pixel circuit groups and a plurality of signal line groups located on the substrate; one pixel circuit group is arranged correspondingly with one signal line group, and the signal line group is used to provide various signals for the pixel circuit group. The plurality of pixel circuit groups and the plurality of signal line groups are arranged at intervals along a row direction, and the pixel circuit group includes two pixel circuit subgroups arranged at intervals along the row direction; wherein each pixel circuit subgroup includes a plurality of pixel circuits arranged at intervals along a column direction. The two pixel circuit subgroups in the pixel circuit group are electrically connected with the correspondingly arranged signal line group. At least part of the orthographic projection of the signal line group on the substrate is located between the orthographic projections of the two pixel circuit subgroups in the same pixel circuit group on the substrate. The orthographic projections of the adjacent two signal line groups on the substrate are located on the opposite sides of the orthographic projections of one pixel circuit subgroup in the former column of pixel circuit groups and one pixel circuit subgroup in the latter column of pixel circuit groups on the substrate, that is, the orthographic projections of the adjacent two signal line groups on the substrate are located on the opposite sides of the orthographic projections of the two pixel circuit subgroups along the row direction on the substrate. Compared with the orthographic projections of the adjacent two signal line groups on the substrate being respectively located on the opposite sides of the orthographic projection of the same pixel circuit subgroup along the row direction on the substrate, the distance between the adjacent two signal line groups can be larger, so that at least part of the orthographic projection of the light emitting unit in the light emitting layer on the substrate is located between the orthographic projections of the adjacent two signal line groups on the substrate and does not overlap with the orthographic projections of the adjacent two signal line groups on the substrate, so as to avoid the influence of the adjacent two signal line groups on the flatness of the light emitting unit, thereby improving the color deviation phenomenon of the light emitting unit under a large viewing angle and improving the display effect of the display panel.

[0009] In a possible implementation, the signal line group includes a power line and a data line, and the power line and the data line are electrically connected with the two pixel circuit subgroups in the pixel circuit group.

[0010] In this way, the power line and the data line provide the pixel circuit group with a power signal and a data signal, respectively.

[0011] In a possible implementation, the data line in the signal line group includes two, and one data line is electrically connected with one pixel circuit subgroup;

[0012] It can be implemented that in the same signal line group, the orthographic projection of the power line on the substrate is located between the orthographic projections of the two data lines on the substrate.

[0013] In a possible implementation, the power line in the signal line group includes one, and the power line is electrically connected with the two pixel circuit subgroups in the pixel circuit group, respectively;

[0014] It can be implemented that in the same signal line group, the orthographic projections of the two data lines on the substrate are symmetrically arranged on the two sides of the orthographic projection of the power line on the substrate.

[0015] In this way, the interference between the two data lines and the power line in the same signal line group is consistent, so that the consistency of the data signals input into the corresponding pixel circuits by the two data lines is high.

[0016] In a possible implementation, the power line in the signal line group includes two, and one power line is electrically connected with one pixel circuit subgroup.

[0017] In a possible implementation, the pixel circuit subgroup includes a plurality of pixel circuits arranged at intervals in the column direction, and the two pixel circuits in the same row are symmetrically arranged in the same pixel circuit group.

[0018] In this way, the two adjacent pixel circuits are symmetrically arranged, so that the signal line group can input signals into the corresponding two pixel circuits.

[0019] In a possible implementation, the array substrate is used in a display panel with a light-emitting layer, and the array substrate further includes a pad member, the signal line group is arranged in the same layer as the pad member, and the light-emitting layer includes a pixel opening, a normal projection of the pixel opening on the substrate is located in a normal projection of the pad member on the substrate.

[0020] In this way, the pad member is electrically connected with the power line.

[0021] In this way, the single pad member is a complete integrated structure and has a relatively flat surface, so that the flatness of the light-emitting unit can be ensured, the color cast phenomenon of the light-emitting unit under a large viewing angle is improved, and the display effect of the display panel is improved.

[0022] In a possible implementation, the pad member includes a first pad member, and the first pad member is located between the two data lines in the same signal line group.

[0023] In this way, the first pad member has a relatively flat surface, so that the flatness of the light-emitting unit can be ensured, the color cast phenomenon of the light-emitting unit under a large viewing angle is improved, and the display effect of the display panel is improved.

[0024] In this way, the distance between the two data lines in the bending region is large, the interference between the two data lines can be reduced, and the first pad member can be arranged in the large accommodation space between the two data lines.

[0025] In this way, the distance between the two data lines in the bending region is large, the interference between the two data lines can be reduced, and the first pad member can be arranged in the large accommodation space between the two data lines.

[0026] In this way, the first pad member is an integrated structure with the power line.

[0027] It can be implemented that the gasket piece includes a second gasket piece, and the second gasket piece is located between two adjacent signal line groups.

[0028] In this way, the second gasket piece has a relatively flat surface, which can ensure the flatness of the light-emitting unit, thereby improving the color deviation phenomenon of the light-emitting unit under a large viewing angle, to improve the display effect of the display panel.

[0029] The second aspect of the embodiment of the present application provides a display panel, including the array substrate in the first aspect.

[0030] The display panel provided by the embodiment of the present application includes an array substrate, and the array substrate can include a substrate and a plurality of pixel circuit groups and a plurality of signal line groups located on the substrate; one pixel circuit group is arranged correspondingly with one signal line group, and the signal line group is used to provide various signals for the pixel circuit group. The plurality of pixel circuit groups and the plurality of signal line groups are arranged at intervals along a row direction, and the pixel circuit group includes two pixel circuit subgroups arranged at intervals along the row direction; wherein each pixel circuit subgroup includes a plurality of pixel circuits arranged at intervals along a column direction. The two pixel circuit subgroups in the pixel circuit group are electrically connected with the correspondingly arranged signal line group. At least part of the orthographic projection of the signal line group on the substrate is located between the orthographic projections of the two pixel circuit subgroups in the same pixel circuit group on the substrate. The orthographic projections of the two adjacent signal line groups on the substrate are located on opposite sides of the orthographic projections of one pixel circuit subgroup in a previous column of pixel circuit groups and one pixel circuit subgroup in a next column of pixel circuit groups on the substrate, that is, the orthographic projections of the two adjacent signal line groups on the substrate are located on opposite sides of the orthographic projections of the two pixel circuit subgroups on the substrate along the row direction. Compared with the orthographic projections of the two adjacent signal line groups on the substrate being located on opposite sides of the orthographic projection of the same pixel circuit subgroup on the substrate along the row direction, the distance between the two adjacent signal line groups can be larger, so that at least part of the orthographic projection of the light-emitting layer on the substrate is located between the orthographic projections of the two adjacent signal line groups on the substrate, and does not overlap with the orthographic projections of the two adjacent signal line groups on the substrate, to avoid the influence of the two adjacent signal line groups on the flatness of the light-emitting unit, thereby improving the color deviation phenomenon of the light-emitting unit under a large viewing angle, to improve the display effect of the display panel.

[0031] The configuration of the present application and its other purposes and benefits will be more apparent and understandable through the description of the preferred embodiments in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0033] Figure 1 A top view of an array substrate provided by an embodiment of the present application;

[0034] Figure 2 Another top view of an array substrate provided by an embodiment of the present application;

[0035] Figure 3 A structural schematic diagram of a semiconductor layer in a single pixel circuit provided by an embodiment of the present application;

[0036] Figure 4 A structural schematic diagram of writing a data signal in a pixel circuit provided by an embodiment of the present application;

[0037] Figure 5 A structural schematic diagram of writing a power signal in a pixel circuit provided by an embodiment of the present application.

[0038] Explanation of reference signs:

[0039] 100 - array substrate; 101 - pixel circuit group;

[0040] 102 - signal line group; 110 - pixel circuit sub-group;

[0041] 111 - first pixel circuit sub-group; 112 - second pixel circuit sub-group;

[0042] 113 - pixel circuit; 120 - power line;

[0043] 130 - data line; 131 - first data line;

[0044] 132 - second data line; 140 - spacer;

[0045] 141 - first spacer; 142 - second spacer;

[0046] 151 - first scan line; 152 - second scan line;

[0047] 153 - third scan line; 154 - light-emitting control line;

[0048] 155 - reference line; 161 - first connection structure;

[0049] 162 - second connection structure; 171 - first plate. DETAILED DESCRIPTION

[0050] The inventors have found that, in the prior art, a display panel includes a plurality of pixel circuits arranged in an array of multiple rows and multiple columns, one pixel circuit corresponding to one light emitting unit. The pixel circuit is located on a substrate, and the light emitting unit is located on a side of the pixel circuit away from the substrate. The pixel circuit provides a driving signal for the light emitting unit to drive the light emitting unit to emit light. One column of pixel circuits forms one pixel circuit group, and one pixel circuit group corresponds to electrically connected one signal line group. The signal line group provides various signals for the pixel circuit group. The orthographic projection of the corresponding signal line group on the substrate is located on one side of the orthographic projection of the corresponding pixel circuit group on the substrate along the row direction. The orthographic projections of two adjacent signal line groups on the substrate are respectively located on opposite sides of the orthographic projection of the same pixel circuit group on the substrate along the row direction.

[0051] However, since the orthographic projections of two adjacent signal line groups on the substrate are respectively located on opposite sides of the orthographic projection of the same pixel circuit group on the substrate along the row direction, the distance between the two adjacent signal line groups is small, and the size of part of the light emitting units is large. The orthographic projection of the light emitting unit on the substrate and the orthographic projections of the two adjacent signal line groups on the substrate are partially overlapped. The light emitting unit is across the two adjacent signal line groups, and the two adjacent signal line groups are arranged at intervals. The flatness between the two adjacent signal line groups is poor, which leads to poor flatness of the light emitting unit, and further causes the color shift phenomenon of the light emitting unit under a large viewing angle to be more serious, thereby affecting the display effect of the display panel.

[0052] To solve at least one of the above technical problems, an array substrate and a display panel are provided in embodiments of the present application. The array substrate can include a substrate and a plurality of pixel circuit groups and a plurality of signal line groups on the substrate. One pixel circuit group is arranged correspondingly to one signal line group, and the signal line group is configured to provide various signals for the pixel circuit group. The plurality of pixel circuit groups and the plurality of signal line groups are arranged in a row direction. Each pixel circuit group includes two pixel circuit subgroups arranged in the row direction. Each pixel circuit subgroup includes a plurality of pixel circuits arranged in a column direction. The two pixel circuit subgroups in the pixel circuit group are electrically connected to the correspondingly arranged signal line group. At least part of the orthogonal projection of the signal line group on the substrate is between the orthogonal projections of the two pixel circuit subgroups in the same pixel circuit group on the substrate. The orthogonal projections of adjacent two signal line groups on the substrate are located on opposite sides of the orthogonal projections of one pixel circuit subgroup in a previous column of pixel circuit groups and one pixel circuit subgroup in a next column of pixel circuit groups on the substrate, i.e., the orthogonal projections of the adjacent two signal line groups on the substrate are located on opposite sides of the orthogonal projections of the two pixel circuit subgroups on the substrate in the row direction. Compared with the case that the orthogonal projections of the adjacent two signal line groups on the substrate are located on opposite sides of the orthogonal projection of the same pixel circuit subgroup on the substrate in the row direction, the distance between the adjacent two signal line groups is larger, so that at least part of the orthogonal projection of the light emitting layer on the substrate is between the orthogonal projections of the adjacent two signal line groups on the substrate and does not overlap with the orthogonal projections of the adjacent two signal line groups on the substrate. This avoids the influence of the adjacent two signal line groups on the flatness of the light emitting unit, thereby improving the color shift phenomenon of the light emitting unit under a large viewing angle and improving the display effect of the display panel.

[0053] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0054] The following will be described in conjunction with Figures 1-5 The display panel provided in the embodiments of the present application will be described.

[0055] The display panel provided in the embodiments of the present application can be applied to electronic paper, mobile phones, tablet computers, televisions, displays, notebook computers, digital photo frames, smart wristbands, smart watches, super personal computers, navigation devices, and other mobile or fixed terminals.

[0056] The display panel can be an organic light-emitting diode (OLED) display panel, a micro light-emitting diode (Micro LED or μLED) display panel, or a liquid crystal (LCD) display panel.

[0057] The display panel can include an array substrate 100 and a light-emitting layer on the array substrate 100. The array substrate 100 is electrically connected to the light-emitting layer. The light-emitting layer can include an anode, a cathode, and a light-emitting material layer between the cathode and the anode. The anode can be a pixel electrode, and the cathode can be a common electrode.

[0058] The light-emitting material layer can generally include a plurality of light-emitting units arranged at intervals, and the plurality of light-emitting units can be arranged in an array. The plurality of light-emitting units can include, but are not limited to, red light-emitting units, green light-emitting units, and blue light-emitting units. In other examples, the plurality of light-emitting units can also include white light-emitting units.

[0059] The light-emitting layer can also include a pixel definition layer between the cathode and the anode, and the pixel definition layer can have a plurality of pixel openings arranged at intervals therein. The light-emitting units are arranged in the pixel openings, and the pixel definition layer can surround the outer periphery of the light-emitting units.

[0060] The array substrate 100 provided by the embodiments of the present application is described below.

[0061] In the embodiments of the present application, the array substrate 100 can include a substrate, which can provide support for the remaining structure layers arranged subsequently. In some examples, the substrate can be a rigid substrate, for example, the material of the substrate can be glass. In other examples, the substrate can be a flexible substrate, and the material of the substrate can include at least one of polyimide (PI), polyethylene terephthalate, polyethylene naphthalate, polyethylene, polyacrylate, polyetherimide, polycarbonate, polyarylate, and polyethersulfone.

[0062] As shown in FIG. 1, the array substrate 100 can include a substrate 110, a thin film transistor (TFT) layer 120, a planarization layer 130, a pixel definition layer 140, and a light-emitting layer 150. Figure 1As shown in FIG. 1, the array substrate 100 can include a first direction X, which can be a width direction of the array substrate 100; the array substrate 100 can include a second direction Y, which can be a length direction of the array substrate 100; and the array substrate 100 can include a third direction, which can be a thickness direction of the array substrate 100. The length, width and thickness in the embodiments of the present application are merely for the convenience of description, and do not mean any limitation on the size. For example, the width can be greater than, equal to or less than the length. Among them, the first direction X, the second direction Y and the third direction are all different.

[0063] The embodiments of the present application are described in the first direction X as the row direction and the second direction Y as the column direction.

[0064] As shown in FIG. 2, the array substrate 100 can include a plurality of signal line groups 102 on the substrate, and the plurality of signal line groups 102 can be arranged at intervals along the row direction, and each signal line group 102 extends along the column direction. Each signal line group 102 can include a data line 130 and a power line 120. Figure 1 As shown in FIG. 3, the array substrate 100 can further include a first scan line 151, a second scan line 152, a third scan line 153, a light-emitting control line 154 and a reference line 155. Figure 2

[0065] As shown in FIG. 4 and FIG. 5, the array substrate 100 can include a plurality of pixel circuit groups 101 on the substrate, and the plurality of pixel circuit groups 101 can be arranged at intervals along the row direction, and each pixel circuit group 101 includes two pixel circuit subgroups 110 arranged at intervals along the row direction, and the two pixel circuit subgroups 110 can include a first pixel circuit subgroup 111 and a second pixel circuit subgroup 112. Each pixel circuit subgroup 110 includes a plurality of pixel circuits 113 arranged at intervals along the column direction. Figure 1 Figure 2 Figure 2

[0066] The plurality of pixel circuits 113 can be arranged in an array of multiple rows and multiple columns. The pixel circuit 113 is electrically connected to the light-emitting layer to provide a driving signal for the light-emitting layer. The pixel circuit 113 can include a plurality of transistors (Thin Film Transistor, referred to as TFT) and a capacitor structure.

[0067] Among them, the array substrate 100 can include a semiconductor layer, a first metal layer, a second metal layer, a third metal layer and a fourth metal layer which are sequentially stacked on the substrate, and an insulating layer is arranged between any two adjacent layers of the semiconductor layer, the first metal layer, the second metal layer, the third metal layer and the fourth metal layer.

[0068] As shown in FIG. 6, the array substrate 100 can include a plurality of pixel circuit groups 101 on the substrate, and the plurality of pixel circuit groups 101 can be arranged at intervals along the row direction, and each pixel circuit group 101 includes two pixel circuit subgroups 110 arranged at intervals along the row direction, and the two pixel circuit subgroups 110 can include a first pixel circuit subgroup 111 and a second pixel circuit subgroup 112. Each pixel circuit subgroup 110 includes a plurality of pixel circuits 113 arranged at intervals along the column direction. Figure 2 ​​​​As shown, the semiconductor layer includes an active layer of a plurality of transistors, the first metal layer can include a first scan line 151, a second scan line 152, a third scan line 153, a first plate 171 of a capacitor structure, a light-emitting control line 154, and a gate of the plurality of transistors; the second metal layer can include a reference line 155 and a second plate of the capacitor structure; the third metal layer can include a source / drain of the transistor; and the fourth metal layer can include a data line 130 and a power line 120. Figure 1

[0069] The material of the semiconductor layer can include polysilicon (e.g., low-temperature polysilicon) or metal oxide. The material of any one or more of the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer can include a metal material such as silver, aluminum, copper, etc.

[0070] For example, the plurality of pixel circuits 113 can be arranged in M rows and N columns, the plurality of pixel circuits 113 in the same column form a pixel circuit sub-group 110, the pixel circuit sub-group 110 includes N columns, and two adjacent pixel circuit sub-groups 110 form a pixel circuit group 101, i.e., the array substrate 100 can include N / 2 pixel circuit groups 101, and one pixel circuit group 101 is arranged corresponding to one signal line group 102, and the one signal line group 102 and the one pixel circuit group 101 are electrically connected, i.e., the signal line group 102 can also include N / 2.

[0071] As shown in Figure 1 , the pixel circuit group 101 and the signal line group 102 are electrically connected one by one, for example, the i-th column of pixel circuit group 101 is electrically connected to the i-th column of signal line group 102, where M and N are positive integers, and i is a positive integer less than or equal to N / 2.

[0072] The array substrate 100 further includes a data driver for providing a data signal to the data line 130, a scan driver for providing a scan signal to the first scan line 151, the second scan line 152, and the third scan line 153, a light-emitting driver for providing a light-emitting control signal to the light-emitting control line 154, and a timing controller for providing a driving signal to the data driver, the scan driver, and the light-emitting driver.

[0073] As shown in Figure 1 , the signal line group 102 includes the power line 120 and the data line 130, and the power line 120 and the data line 130 are electrically connected to two pixel circuit sub-groups 110 in the corresponding pixel circuit group 101.

[0074] With reference to the foregoing Figure 1 ​Each column of signal line group 102 may include two data lines 130. The two data lines 130 may include a first data line 131 and a second data line 132 that are spaced apart along the row direction. The orthographic projection of the first data line 131 on the substrate is close to the orthographic projection of the first pixel circuit subgroup 111 on the substrate, and the first data line 131 is electrically connected to the first pixel circuit subgroup 111. The orthographic projection of the second data line 132 on the substrate is close to the orthographic projection of the second pixel circuit subgroup 112 on the substrate, and the second data line 132 is electrically connected to the second pixel circuit subgroup 112.

[0075] The power lines 120 in each signal line group 102 provide power signals to each pixel circuit 113 in the corresponding pixel circuit group 101. In the same signal line group 102, the orthographic projection of the power line 120 on the substrate is located between the orthographic projections of the first data line 131 and the second data line 132 on the substrate, and the orthographic projection of the power line 120 on the substrate does not overlap with the orthographic projections of the first data line 131 and the second data line 132 on the substrate, which can avoid short circuits between the power line 120 and the data line 130.

[0076] like Figure 1 As shown, data line 130 has a bend region W. In the same signal line group 102, the distance between the first data line 131 and the second data line 132 located in the bend region W is greater than the distance between the first data line 131 and the second data line 132 located in the remaining areas. At least some of the light-emitting units have their orthographic projections on the plane where the data line 130 is located between the first data line 131 and the second data line 132 in the bend region W, and do not overlap with the first data line 131 and the second data line 132. This avoids the flatness of some light-emitting units being affected by the small distance between the first data line 131 and the second data line 132.

[0077] For example, the power line 120 in the signal line group 102 may include two power lines, one of which is electrically connected to a pixel circuit subgroup 110. For instance, the power line 120 may include a first power line and a second power line, the orthographic projections of which are both located between the orthographic projections of the first data line 131 and the second data line 132 on the substrate. The first power line is closer to the first pixel circuit subgroup 111, and the second power line is closer to the second pixel circuit subgroup 112. The first power line can be electrically connected to the first pixel circuit subgroup 111, and the second power line can be electrically connected to the second pixel circuit subgroup 112.

[0078] For example, such as Figure 1As shown, the signal line group 102 can include one power line 120, which is electrically connected with two pixel circuit subgroups 110 in the pixel circuit group 101 respectively, i.e., one power line 120 is electrically connected with the first pixel circuit subgroup 111 and the second pixel circuit subgroup 112 simultaneously, and the first pixel circuit subgroup 111 and the second pixel circuit subgroup 112 share one power line 120. Without separately arranging two power lines 120 for the two pixel circuit subgroups 110, the structure of the power line 120 is relatively simple, and the manufacturing process of the array substrate 100 can be simplified. In the same signal line group 102, the orthogonal projections of the two data lines 130 on the substrate are symmetrically arranged on both sides of the orthogonal projection of the power line 120 on the substrate. The embodiment of the present application takes one power line 120 as an example for description.

[0079] The following describes the plurality of transistors provided by the embodiment of the present application.

[0080] As shown in Figure 2 , the pixel circuit 113 can include any one or more of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the driving transistor DT. The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 can be switching transistors.

[0081] The types of the transistors in the pixel circuit 113 can all be P-type transistors or N-type transistors. Alternatively, a part of the transistors can be P-type transistors, and the rest of the transistors can be N-type transistors. Different enable levels are provided according to different transistor types. The enable level refers to the level that can turn on the transistor. Exemplarily, when the transistor is a P-type transistor, the enable level is a low level. When the transistor is an N-type transistor, the enable level is a high level. The embodiment of the present application takes the case that the plurality of transistors are all P-type transistors as an example for description.

[0082] As shown in Figure 1 and Figure 3As shown, the first electrode T11 of the first transistor T1 is electrically connected with the data line 130, and the second electrode T12 of the first transistor T1 is electrically connected with the first electrode DT1 of the driving transistor DT; the second electrode DT2 of the driving transistor DT is electrically connected with the second electrode T22 of the second transistor T2, and the first electrode T21 of the second transistor T2 is electrically connected with the first plate 171 of the capacitor structure; the first electrode T31 of the third transistor T3 is electrically connected with the power supply line 120, and the second electrode T32 of the third transistor T3 is electrically connected with the first electrode DT1 of the driving transistor DT; the first electrode T41 of the fourth transistor T4 is electrically connected with the anode, and the second electrode T42 of the fourth transistor T4 is electrically connected with the second electrode DT2 of the driving transistor DT; the first electrode T51 of the fifth transistor T5 is electrically connected with the anode, and the second electrode T52 of the fifth transistor T5 is electrically connected with the reference line 155; the first electrode T61 of the sixth transistor T6 is electrically connected with the reference line 155, and the second electrode T62 of the sixth transistor T6 is electrically connected with the first plate 171 of the capacitor structure; and the second plate of the capacitor structure is connected with the power supply line 120.

[0083] In addition, the gate of the first transistor T1 is connected with the second scan line 152, the gate of the second transistor T2 is connected with the second scan line 152, the gate of the third transistor T3 is connected with the light-emitting control line 154, the gate of the fourth transistor T4 is connected with the light-emitting control line 154, the gate of the fifth transistor T5 is connected with the third scan line 153, and the gate of the sixth transistor T6 is connected with the first scan line 151; and the gate of the driving transistor DT is connected with the first plate 171 of the capacitor structure.

[0084] The working process of the pixel circuit 113 provided by the embodiment of the present application is described below.

[0085] In the first stage, the light-emitting control line 154 provides a high level, controls the third transistor T3 and the fourth transistor T4 to be cut off, and the light-emitting layer does not emit light. The first scan line 151 provides a low level, controls the sixth transistor T6 to be turned on, and the reference voltage of the reference line 155 is transmitted to the first plate 171 of the capacitor structure and resets the first plate 171; the second scan line 152 provides a high level, controls the first transistor T1 and the second transistor T2 to be cut off, and the third scan line 153 provides a low level, controls the fifth transistor T5 to be turned on, and the reference voltage of the reference line 155 is transmitted to the anode, and the anode of the light-emitting layer is reset.

[0086] In the second stage, the light-emitting control line 154 provides a high level, controls the third transistor T3 and the fourth transistor T4 to be cut off, and the light-emitting layer does not emit light. The first scan line 151 provides a high level, controls the sixth transistor T6 to be cut off, and the second scan line 152 provides a low level, controls the first transistor T1 and the second transistor T2 to be turned on. Figure 4The arrows in the diagram illustrate the data voltage transmission path, where the data voltage of data line 130 is transmitted to the first plate 171 of the capacitor structure via the first transistor T1, the driving transistor DT, and the second transistor T2, charging the capacitor structure. The third scan line 153 provides a high level, controlling the fifth transistor T5 to turn off.

[0087] In the third stage, the light-emitting control line 154 provides a low level, controlling the third transistor T3 and the fourth transistor T4 to turn on. The first scan line 151 provides a high level, controlling the sixth transistor T6 to turn off; the second scan line 152 provides a high level, controlling the first transistor T1 and the second transistor T2 to turn off; the third scan line 153 provides a high level, controlling the fifth transistor T5 to turn off; and under the potential control of the first plate 171 of the capacitor structure, the transistor DT is driven to turn on. Figure 5 The arrows in the diagram show the transmission path of the power signal, wherein the power signal of the power line 120 is transmitted to the anode through the third transistor T3, the driving transistor DT and the fourth transistor T4; the power line 120 provides driving current to the light-emitting layer to drive the light-emitting layer to emit light.

[0088] like Figure 2 As shown, the array substrate 100 may include a first connection structure 161. One end of the first connection structure 161 is electrically connected to the first electrode T21 of the second transistor T2, and the other end of the first connection structure 161 is electrically connected to the first electrode 171 of the capacitor structure, so that the data line 130 charges the first electrode 171 of the capacitor structure through the first transistor T1, the driving transistor DT, the second transistor T2, and the first connection structure 161. For example, the first connection structure 161 may be formed of a third metal layer.

[0089] like Figure 2 As shown, the array substrate 100 may include a second connection structure 162 for electrically connecting the anode and the first electrode T41 of the fourth transistor T4. Additionally, the second connection structure 162 may also be used to electrically connect the first electrode T51 of the fifth transistor T5 and the anode. For example, the second connection structure 162 may be formed of a third metal layer.

[0090] It should be noted that one of the first and second terminals of a transistor can be the source of the transistor, and the other of the first and second terminals can be the drain of the transistor.

[0091] The positional relationship between the signal line group 102 and the pixel circuit group 101 provided in the embodiments of this application will be described below.

[0092] like Figure 1As shown, at least part of the orthographic projection of the signal line group 102 on the substrate is located between the orthographic projections of the first pixel circuit subgroup 111 and the second pixel circuit subgroup 112 in the same pixel circuit group 101 on the substrate. The orthographic projection of the signal line group 102 on the substrate is referred to as a signal line group projection, the orthographic projection of the pixel circuit group 101 on the substrate is referred to as a pixel circuit group projection, the orthographic projection of the pixel circuit subgroup 110 on the substrate is referred to as a pixel circuit subgroup projection, the orthographic projection of the first pixel circuit subgroup 111 on the substrate is referred to as a first pixel circuit subgroup projection, and the orthographic projection of the second pixel circuit subgroup 112 on the substrate is referred to as a second pixel circuit subgroup projection. Part of the signal line group projection is located on one side of the first pixel circuit subgroup projection close to the second pixel circuit subgroup projection, and the other part of the signal line group projection is located on one side of the second pixel circuit subgroup projection close to the first pixel circuit subgroup projection.

[0093] Specifically, the orthographic projections of two adjacent signal line groups include a first signal line group projection and a second signal line group projection. The first signal line group projection and the second signal line group projection are located on opposite sides of the second pixel circuit subgroup projection of the pixel circuit group 101 in the previous column and the first pixel circuit subgroup projection of the pixel circuit group 101 in the next column, respectively. At this time, the first signal line group projection and the second signal line group projection are located on opposite sides of two adjacent pixel circuit subgroup projections. Compared with the case where the first signal line group projection and the second signal line group projection are located on opposite sides of the same pixel circuit subgroup projection, the distance between the first signal line group projection and the second signal line group projection is larger, so that at least part of the light emitting unit is located between the orthographic projections of the two adjacent signal line groups on the substrate, and does not overlap with the two adjacent signal line groups, that is, the light emitting unit does not cross the two adjacent signal line groups 102, thereby avoiding the influence of the two adjacent signal line groups 102 on the flatness of the light emitting unit, improving the color shift phenomenon of the light emitting unit at a large viewing angle, and improving the display effect of the display panel.

[0094] In the embodiment in which only one power line 120 is arranged in the signal line group 102, the area of the array substrate 100 occupied by one power line 120 is smaller than the area of the array substrate 100 occupied by two power lines 120, further increasing the distance between the two adjacent signal line groups 102, avoiding the influence of the adjacent signal line groups 102 on the flatness of the light emitting unit, thereby improving the color shift phenomenon of the light emitting unit at a large viewing angle, and improving the display effect of the display panel.

[0095] For example, in the same pixel circuit group 101, two pixel circuits 113 located in the same row include a first pixel circuit and a second pixel circuit, and the first pixel circuit and the second pixel circuit have a center line AA( Figure 1In the embodiment, the first pixel circuit and the second pixel circuit are symmetrically arranged relative to the center line AA, so as to facilitate the signal line group 102 to input signals into the corresponding first pixel circuit and second pixel circuit respectively.

[0096] In the same signal line group 102, the power supply line 120 can be symmetrically arranged along the center line AA relative to the first pixel circuit and the second pixel circuit. Figure 1 In the embodiment, the third transistor T3 of the first pixel circuit and the third transistor T3 of the second pixel circuit are symmetrically arranged along the center line AA, so that the power supply line 120 inputs the power supply signal to the third transistor T3 of the first pixel circuit and the third transistor T3 of the second pixel circuit with the same distance and high consistency of the power supply signal.

[0097] In addition, the transmission path of the power supply signal in the first pixel circuit and the second pixel circuit is symmetrically arranged along the center line AA, so that the transmission path of the power supply signal is consistent, and the consistency of the power supply signal is further improved.

[0098] In the same signal line group 102, the first data line 131 and the second data line 132 are symmetrically arranged along the center line AA relative to the first pixel circuit and the second pixel circuit. Figure 1 In the embodiment, the first transistor T1 of the first pixel circuit and the first transistor T1 of the second pixel circuit are symmetrically arranged along the center line AA, so that the distance between the first data line 131 and the first transistor T1 of the first pixel circuit and the distance between the second data line 132 and the first transistor T1 of the second pixel circuit are the same, and the consistency of the data signal input by the first data line 131 and the second data line 132 to the corresponding first transistor T1 is high. In addition, the transmission path of the data signal in the first pixel circuit and the second pixel circuit is symmetrically arranged along the center line AA, so that the transmission path of the data signal is consistent, and the consistency of the data signal is further improved.

[0099] It can be realized that, in the same signal line group 102, along the row direction, the orthogonal projection of the first data line 131 and the second data line 132 on the substrate is symmetrically arranged on the opposite sides of the orthogonal projection of the power supply line 120 on the substrate. The distance between the first data line 131, the second data line 132 and the power supply line 120 is consistent, so that the interference between the first data line 131, the second data line 132 and the power supply line 120 is consistent, thereby making the consistency of the data signal input by the first data line 131 and the second data line 132 to the corresponding first transistor T1 high.

[0100] In some embodiments, as shown in FIG. 1, the first data line 131 and the second data line 132 are symmetrically arranged along the center line AA relative to the first pixel circuit and the second pixel circuit. Figure 1As shown, the array substrate 100 can further include a pad member 140, and the signal line group 102 and the pad member 140 are arranged in the same layer, i.e., the pad member 140 is formed by the fourth metal layer, so that the manufacturing process of the pad member 140 can be simplified. The normal projection of the pixel opening B on the substrate is located in the normal projection of the pad member 140 on the substrate, so that the normal projection of the light emitting unit in the pixel opening B on the substrate is located in the normal projection of the pad member 140 on the substrate. The size of the pad member 140 is greater than the size of the light emitting unit, the pad member 140 is located on the side of the light emitting unit facing the substrate, and a single pad member 140 is a complete integrated structure with a relatively flat surface, which can ensure the flatness of the light emitting unit, thereby improving the color deviation phenomenon of the light emitting unit under a large viewing angle, and improving the display effect of the display panel.

[0101] For example, the pad member 140 can be electrically connected to the power line 120, so as to increase the area of the power line 120, so that the resistance of the power line 120 is low, thereby reducing the voltage drop of the power line 120 and improving the display uniformity of the display panel. For example, the pad member 140 can be electrically connected to the power line 120 through a connection structure formed by at least one of the second metal layer and the third metal layer. Of course, the pad member 140 can not be electrically connected to the power line 120.

[0102] For example, the pad member 140 can include a first pad member 141, and the first pad member 141 is located between the first data line 131 and the second data line 132 in the same signal line group 102, e.g., between the first data line 131 and the second data line 132 in the bending area W( Figure 1 For example, the first pad member 141 and the power line 120 can be an integrated structure, so as to reduce the voltage drop of the power line 120 and improve the display uniformity of the display panel. In addition, since the distance between the first data line 131 and the second data line 132 in the bending area W( Figure 1 For example, the sizes of different first pad members 141 can be the same or different.

[0103] For example, the sizes of different first pad members 141 can be the same or different. Figure 1As shown, the gasket piece 140 can further include a second gasket piece 142 located between two adjacent signal line groups 102. The distance between the two adjacent signal line groups 102 is large, and the second gasket piece 142 can be arranged at a distance from the two adjacent signal line groups 102, so as to avoid short circuit caused by contact between the second gasket piece 142 and the two adjacent signal line groups 102. For example, the sizes of different second gasket pieces 142 can be the same or different.

[0104] It can be understood that the sizes of the first gasket piece 141 and the second gasket piece 142 can be the same or different. For example, Figure 1 As shown, the size of a part of the second gasket piece 142 can be smaller than the size of another part of the second gasket piece 142, and the size of the first gasket piece 141 can be smaller than the size of the second gasket piece 142, so as to arrange light emitting units of different sizes. The gasket piece 140 with a larger size can correspond to a light emitting unit with a lower light emitting efficiency, and the gasket piece 140 with a smaller size can correspond to a light emitting unit with a higher light emitting efficiency, so as to improve the display effect of the display panel. It can be understood that each light emitting unit is arranged with a gasket piece 140.

[0105] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An array substrate, characterized by, The array substrate comprises: a substrate and a plurality of pixel circuit groups and a plurality of signal line groups on the substrate; the plurality of pixel circuit groups and the plurality of signal line groups are arranged along a row direction, and each pixel circuit group comprises two pixel circuit subgroups arranged along the row direction; at least part of the signal line group is in orthographic projection on the substrate, and the orthographic projection of the two pixel circuit subgroups in the same pixel circuit group on the substrate is between the orthographic projections of the two pixel circuit subgroups on the substrate; one pixel circuit group is arranged correspondingly to one signal line group, and the two pixel circuit subgroups in the pixel circuit group are electrically connected to the signal line group; the signal line group comprises a power line and a data line, and the power line and the data line are electrically connected to the two pixel circuit subgroups in the pixel circuit group; the pixel circuit subgroup comprises a plurality of pixel circuits arranged along a column direction, and in the same pixel circuit group, the two pixel circuits in the same row are arranged symmetrically.

2. The array substrate of claim 1, wherein, The data line in the signal line group comprises two data lines, and one data line is electrically connected to one pixel circuit subgroup.

3. The array substrate of claim 2, wherein, In the same signal line group, the orthographic projection of the power line on the substrate is between the orthographic projections of the two data lines on the substrate.

4. The array substrate of claim 3, wherein, The power line in the signal line group comprises one power line, and the power line is electrically connected to the two pixel circuit subgroups in the pixel circuit group.

5. The array substrate of claim 4, wherein, In the same signal line group, the orthographic projections of the two data lines on the substrate are symmetrically arranged on both sides of the orthographic projection of the power line on the substrate.

6. The array substrate of claim 3, wherein, The power line in the signal line group comprises two power lines, and one power line is electrically connected to one pixel circuit subgroup.

7. The array substrate according to any one of claims 2 to 6, wherein, The array substrate is used for a display panel with a light-emitting layer, and further comprises a pad member, the signal line group and the pad member are arranged in the same layer, the light-emitting layer comprises a pixel opening, and the orthographic projection of the pixel opening on the substrate is located in the orthographic projection of the pad member on the substrate.

8. The array substrate of claim 7, wherein, The pad member is electrically connected to the power line.

9. The array substrate of claim 8, wherein, The pad member comprises a first pad member, and the first pad member is located between the two data lines in the same signal line group.

10. The array substrate of claim 9, wherein, The data line has a bending region, in the same signal line group, the distance between the two data lines in the bending region is greater than the distance between the two data lines in other regions, and the first pad member is located between the two data lines in the bending region.

11. The array substrate of claim 10, wherein, The first pad member is in an integral structure with the power line.

12. The array substrate of claim 7, wherein, The pad member comprises a second pad member, and the second pad member is located between adjacent two signal line groups.

13. A display panel, characterized by The array substrate comprises any one of the array substrates in claims 1-12.

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