Resistive field plate asymmetric gate field effect device and method of making same

Abstract

The application provides a resistance field plate asymmetric gate field effect device and a preparation method thereof. Two asymmetric deep groove type resistance field plate structures are arranged in a minimum repeatable unit of the resistance field plate asymmetric gate field effect device. A top end of a first resistance field plate structure is provided with a MOSFET structure and is connected with a source electrode of the MOSFET structure. A top end of a second resistance field plate structure leads out a control electrode. When the source electrode of the MOSFET structure and the control electrode are connected at the same potential, due to the structural asymmetry and difference of the two resistance field plate structures, the electric field coupling effect generated by the two resistance field plate structures is better, which is more suitable for improving the impurity concentration of the drift region of the MOSFET, reducing the on-resistance of the drift region while maintaining the withstand voltage, optimizing the basic contradiction between the on-resistance and the withstand voltage, and reducing the repulsion and extrusion of adjacent other minimum repeatable units, so as to facilitate the structure compression of the minimum repeatable unit and be beneficial to the structure miniaturization design and high density design.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor devices and integrated circuits, and particularly relates to a resistance field plate asymmetric gate field effect device and a preparation method thereof. BACKGROUND

[0002] The known super-junction structure high-voltage MOSFET device based on PN junction charge balance has become a factually industrial standard MOSFET high-voltage power device with a withstand voltage of 350 V or above. The super-junction device based on the PN junction charge balance is quite sensitive to the PN junction charge balance. In view of the process control difficulty caused by the charge sensitivity, a second generation of new structures similar to the PN junction super-junction function have been proposed at home and abroad, one of which is to replace the P-type or N-type region in the first type of PN junction structure with a thin layer of ordinary commonly used dielectric constant medium material and semi-insulating material along the interface of the replaced P-type or N-type region, so as to realize the structure of the resistance field plate.

[0003] However, how to use this principle to realize the specific device structure is only conceptually involved by a few at home and abroad, but the related device structure design always has various deficiencies, such as: either the problems that may be encountered in the process implementation are not solved in detail enough, or it is impossible to meet the similar super-junction two-dimensional electric field coupling to obtain smaller device cells while combining the engineering implementation conditions.

[0004] Therefore, how to obtain a high-voltage MOSFET device with easy implementation, small cell volume and high integration density on the basis of the second generation of resistance field plate type super-junction is a technical problem that needs to be solved at present. SUMMARY

[0005] In view of the above-mentioned deficiencies of the prior art, the purpose of the present application is to provide a technical solution of a resistance field plate asymmetric gate field effect device for solving the above-mentioned technical problems.

[0006] To achieve the above-mentioned purposes and other related purposes, the technical solution provided by the present application is as follows.

[0007] A resistance field plate asymmetric gate field effect device comprises:

[0008] A high-doped substrate;

[0009] An epitaxial layer is arranged on the high-doped substrate, and a first deep trench and a second deep trench are formed in the epitaxial layer, and the first deep trench and the second deep trench vertically enter the high-doped substrate;

[0010] A first resistance field plate structure is arranged in the first deep trench, and the bottom of the first resistance field plate structure is electrically connected with the high-doped substrate;

[0011] a MOSFET structure disposed in the epitaxial layer and on the first resistive field plate structure, a source electrode of which is electrically connected to a top of the first resistive field plate structure;

[0012] a second resistive field plate structure disposed in the second deep trench and a bottom of which is electrically connected to the highly-doped substrate, and a top of which is electrically connected to a control electrode;

[0013] wherein, during operation of the asymmetric gate field effect device, the control electrode has a same potential as one of a source electrode of the MOSFET structure or a gate electrode of the MOSFET structure.

[0014] Optionally, the highly-doped substrate and the epitaxial layer have a same impurity conductivity type.

[0015] Optionally, the MOSFET structure comprises:

[0016] a channel diffusion region disposed in the epitaxial layer and having an opposite impurity conductivity type to the epitaxial layer;

[0017] a source diffusion region disposed in the epitaxial layer and on the channel diffusion region and having a same impurity conductivity type to the epitaxial layer;

[0018] a gate dielectric layer disposed on the epitaxial layer;

[0019] a polysilicon gate disposed on the gate dielectric layer and laterally covering at least a non-overlapping region of the channel diffusion region and the source diffusion region;

[0020] a source electrode vertically passing through the gate dielectric layer and electrically connected to the channel diffusion region, the source diffusion region and a top of the first resistive field plate structure, and the source electrode being electrically connected to the channel diffusion region and the source diffusion region at a top sidewall of the first deep trench;

[0021] a gate electrode electrically connected to the polysilicon gate;

[0022] a drain electrode electrically connected to the highly-doped substrate away from the epitaxial layer.

[0023] Optionally, the MOSFET structure comprises:

[0024] a channel diffusion region disposed in the epitaxial layer and having an opposite impurity conductivity type to the epitaxial layer;

[0025] a source diffusion region disposed in the epitaxial layer and on the channel diffusion region and having a same impurity conductivity type to the epitaxial layer;

[0026] a channel contact region disposed in the epitaxial layer and in contact with the channel diffusion region, having an impurity conductivity type opposite to that of the epitaxial layer;

[0027] a gate dielectric layer disposed on the epitaxial layer;

[0028] a polysilicon gate disposed on the gate dielectric layer and laterally covering at least a non-overlapping region of the channel diffusion region and the source diffusion region;

[0029] a source electrode vertically passing through the gate dielectric layer and electrically connected to the source diffusion region, the channel contact region and the top of the first resistive field plate structure, and the source electrode is electrically connected to the source diffusion region and the channel contact region at the top surface of the first deep trench;

[0030] a gate electrode electrically connected to the polysilicon gate;

[0031] a drain electrode electrically led out from the high-doped substrate away from the epitaxial layer.

[0032] A method for manufacturing a resistive field plate asymmetric gate field effect device, comprising the steps of:

[0033] providing a high-doped substrate and forming an epitaxial layer on the high-doped substrate;

[0034] forming a gate dielectric layer on the epitaxial layer and forming a polysilicon gate on the gate dielectric layer;

[0035] forming a channel diffusion region and a source diffusion region in a local region on the top of the epitaxial layer according to the polysilicon gate by using self-aligned implantation technology and double diffusion technology, and the source diffusion region is vertically on the top of the channel diffusion region;

[0036] forming a first deep trench and a second deep trench, the first deep trench vertically passing through the source diffusion region, the channel diffusion region and the epitaxial layer to the high-doped substrate, and the second deep trench vertically passing through the epitaxial layer to the high-doped substrate;

[0037] forming a first resistive field plate structure in the first deep trench and a second resistive field plate structure in the second deep trench, the first resistive field plate structure does not fill the first deep trench, and the top of the first resistive field plate structure is vertically within the range from the bottom of the channel diffusion region to the bottom of the source diffusion region;

[0038] forming a source electrode, a gate electrode and a control electrode, the source electrode vertically penetrating through the gate dielectric layer and electrically connecting with the top of the channel diffusion region, the source diffusion region and the first resistive field plate structure, and the source electrode electrically connecting with the channel diffusion region and the source diffusion region at the top sidewall of the first deep trench, the gate electrode electrically connecting with the polysilicon gate, and the control electrode electrically connecting with the top of the second resistive field plate structure.

[0039] Optionally, according to the polysilicon gate, the step of forming the channel diffusion region and the source diffusion region in the local region on the top of the epitaxial layer by using self-aligned implantation technology and double diffusion technology comprises:

[0040] masking with the polysilicon gate and the first photoresist, performing first ion implantation and first ion diffusion to form the channel diffusion region in the top of the epitaxial layer;

[0041] masking with the polysilicon gate and the second photoresist, performing second ion implantation to form the source diffusion region in the top of the epitaxial layer, and the source diffusion region is vertically on the top of the channel diffusion region and horizontally within the channel diffusion region.

[0042] Optionally, the step of forming the first resistive field plate structure in the first deep trench and the second resistive field plate structure in the second deep trench comprises:

[0043] forming an oxide layer in the first deep trench and the second deep trench, and removing the oxide layer at the bottom of the first deep trench and the oxide layer at the bottom of the second deep trench;

[0044] depositing semi-insulating polysilicon material to fill at least the first deep trench and the second deep trench;

[0045] etching to remove part of the semi-insulating polysilicon material filled in the first deep trench to expose the top of the first deep trench, and the exposed bottom of the first deep trench is within the range from the bottom of the channel diffusion region to the bottom of the source diffusion region in the vertical direction;

[0046] wherein the oxide layer at the sidewall of the first deep trench and the remaining semi-insulating polysilicon material constitute the first resistive field plate structure, and the oxide layer at the sidewall of the second deep trench and the filled semi-insulating polysilicon material constitute the second resistive field plate structure.

[0047] A method for manufacturing a resistive field plate asymmetric gate field effect device, comprising the steps of:

[0048] providing a highly doped substrate and forming an epitaxial layer on the highly doped substrate;

[0049] forming a gate dielectric layer on the epitaxial layer, and forming a polysilicon gate on the gate dielectric layer;

[0050] According to the polysilicon gate, a channel diffusion region, a channel contact region and a source diffusion region are formed in a local region on top of the epitaxial layer by using a self-aligned implantation technique and a double diffusion technique, and the channel contact region and the source diffusion region are on top of the channel diffusion region in a vertical direction, and the channel contact region is in contact with the channel diffusion region.

[0051] forming a first deep trench and a second deep trench, the first deep trench vertically penetrating through the channel contact region, the channel diffusion region and the epitaxial layer to the highly-doped substrate, and the second deep trench vertically penetrating through the epitaxial layer to the highly-doped substrate;

[0052] forming a first resistance field plate structure in the first deep trench and a second resistance field plate structure in the second deep trench;

[0053] forming a source electrode, a gate electrode and a control electrode, the source electrode vertically penetrating through the gate dielectric layer and electrically connected to top of the source diffusion region, the channel contact region and the first resistance field plate structure, and the source electrode is electrically connected to the source diffusion region and the channel contact region at a top surface of the first deep trench, the gate electrode is electrically connected to the polysilicon gate, and the control electrode is electrically connected to top of the second resistance field plate structure.

[0054] Optionally, according to the polysilicon gate, the step of forming the channel diffusion region, the channel contact region and the source diffusion region in a local region on top of the epitaxial layer by using a self-aligned implantation technique and a double diffusion technique comprises:

[0055] masking with the polysilicon gate and a third photoresist, performing a first ion implantation and a first ion diffusion to form the channel diffusion region in the epitaxial layer;

[0056] masking with the polysilicon gate and a fourth photoresist, performing a second ion implantation to form the channel contact region in the epitaxial layer, the channel contact region being in contact with the channel diffusion region;

[0057] masking with the polysilicon gate and a fifth photoresist, performing a third ion implantation to form the source diffusion region in the epitaxial layer, the source diffusion region being on top of the channel diffusion region in a vertical direction and within the channel diffusion region in a horizontal direction.

[0058] Optionally, the step of forming the first resistance field plate structure in the first deep trench and the second resistance field plate structure in the second deep trench comprises:

[0059] forming an oxide layer in the first deep trench and the second deep trench, and removing the oxide layer at the bottom of the first deep trench and the oxide layer at the bottom of the second deep trench;

[0060] depositing a semi-insulating polysilicon material, which at least fills the first deep trench and the second deep trench;

[0061] etching to remove the excess semi-insulating polysilicon material, and only retaining the semi-insulating polysilicon material filled in the first deep trench and the second deep trench, and part of the semi-insulating polysilicon material in the adjacent area at the top of the second deep trench;

[0062] wherein the oxide layer at the sidewall of the first deep trench and the filled semi-insulating polysilicon material constitute the first resistive field plate structure, and the oxide layer at the sidewall of the second deep trench and the filled semi-insulating polysilicon material constitute the second resistive field plate structure.

[0063] As described above, the resistive field plate asymmetric gate field effect device and the preparation method thereof have at least the following beneficial effects:

[0064] 1) In the present application, two asymmetric deep trench type resistive field plate structures are arranged in the minimum repeatable unit of the MOSFET device, the top end of the first resistive field plate structure is provided with a MOSFET structure and is connected with the source electrode of the MOSFET structure, and the top end of the second resistive field plate structure leads out a control electrode, which is different from the conventional habit of symmetric arrangement of the drift region structure of the first generation PN super-junction device and the MOSFET.

[0065] 2) When the source electrode of the MOSFET structure is connected with the control electrode at the same potential, due to the structural asymmetry and difference of the two resistive field plate structures, the electric field coupling effect generated by the two resistive field plate structures is better, which is more suitable for improving the impurity concentration of the drift region of the MOSFET, reducing the on-resistance of the drift region while maintaining the withstand voltage, optimizing the basic contradiction between the on-resistance and the withstand voltage, and the electric field coupling effect is better, so as to facilitate the structure compression of the minimum repeatable unit (cell), which is beneficial to the structure miniaturization design and high density design, and further improves the on performance.

[0066] 3) When the gate electrode of the MOSFET structure is connected with the control electrode at the same potential, the carrier concentration of the drift region of the MOSFET structure can also be adjusted and improved by the second resistive field plate, the on-resistance of the drift region is reduced, the conductivity of the device is increased, and the basic contradiction between the on-resistance and the withstand voltage is further optimized.

[0067] 4), the modern 2.5-dimensional three-dimensional processing technology based on deep trench etching is adopted in the process, which is further beneficial to the structure miniaturization design and high density design, and is more suitable for the development direction of MorethanMoore (beyond Moore) of modern integrated semiconductor devices. BRIEF DESCRIPTION OF DRAWINGS

[0068] Figure 1 A structure schematic diagram of the resistance field plate asymmetric gate field effect device in the embodiment one of the present application is shown.

[0069] Figure 2 A step schematic diagram of the preparation method of the resistance field plate asymmetric gate field effect device in the embodiment one of the present application is shown.

[0070] Figures 3-16 A process flow chart of the preparation method of the resistance field plate asymmetric gate field effect device in the embodiment one of the present application is shown.

[0071] Figure 17 A structure schematic diagram of the resistance field plate asymmetric gate field effect device in the embodiment two of the present application is shown.

[0072] Figures 18-29 A process flow chart of the preparation method of the resistance field plate asymmetric gate field effect device in the embodiment two of the present application is shown.

[0073] BRIEF DESCRIPTION OF DRAWINGS

[0074] 1-highly doped substrate, 2-epitaxial layer, 3-first resistance field plate structure, 4-MOSFET structure, 41-channel diffusion region, 42-source diffusion region, 43-gate dielectric layer, 44-poly-silicon gate, 45-source electrode, 46-gate electrode, 47-channel contact region, 5-second resistance field plate structure, 31, 51-oxide layer, 32, 52-semi-insulating poly-silicon structure, 6-control electrode, 71-first photoresist, 721-second photoresist, 73-third photoresist, 74-fourth photoresist, 75-fifth photoresist, 8-masking dielectric layer, 9-semi-insulating poly-silicon material, 10-isolation dielectric layer, T1-first deep trench, T2-second deep trench, T3-source electrode contact hole, T4-gate electrode contact hole, T5-control electrode contact hole. DETAILED DESCRIPTION

[0075] The inventor found that in the high-voltage MOSFET device based on the second generation of resistance field plate type super junction, the optimization of the contradictory relationship between the breakdown voltage and the on-resistance of the device has been trapped in a bottleneck, and it becomes more and more difficult to further reduce the on-resistance while keeping the breakdown voltage unchanged; the integrated design density of the corresponding device is low, which is not conducive to the structure miniaturization design and the further improvement of the on-state performance of the device.

[0076] Based on this, the application provides a technical scheme of a resistance field plate asymmetric gate field effect device: two asymmetric deep groove type resistance field plate structures are arranged in a minimum repeatable unit of a MOSFET device, a top end of one resistance field plate structure is provided with a MOSFET structure and is connected with a source electrode of the MOSFET structure, and a top end of the other resistance field plate structure leads out a control electrode; when the source electrode of the MOSFET structure is connected with the control electrode in the same potential, through the asymmetry and structure difference of the two resistance field plate structures, the impurity concentration of the drift region of the MOSFET is more suitable to be improved, so as to reduce the on-resistance of the drift region while maintaining the withstand voltage, and the repulsion and extrusion on the adjacent other minimum repeatable units can be reduced, so as to facilitate the structure miniaturization design and high density design; when the gate electrode of the MOSFET structure is connected with the control electrode in the same potential, the carrier concentration of the drift region of the MOSFET structure can be adjusted and improved through the resistance field plate structure, and the on-resistance of the drift region can be further reduced.

[0077] The above description is only used to explain the application, and the skilled in the art can easily understand other advantages and effects of the application from the above description. The application can also be implemented or applied by different specific embodiments, and the details in the specification can be modified or changed based on different views and applications without departing from the spirit of the application.

[0078] Please refer to Figures 1-29 It should be noted that the drawings provided in the embodiments only schematically illustrate the basic concept of the application, and only the components related to the application are shown in the drawings, not the number, shape and size of the components in actual implementation. The shape, number and proportion of each component in actual implementation can be randomly changed, and the component layout pattern can be more complex. The structure, proportion, size, etc. shown in the drawings attached to the specification are only used to illustrate the content disclosed in the specification, so that those skilled in the art can understand and read, and are not used to limit the implementation conditions of the application. Therefore, any modification of the structure, change of the proportion relationship or adjustment of the size, without affecting the effect and purpose that can be achieved by the application, should still fall within the scope of the technical content disclosed by the application.

[0079] The following describes the embodiment of the technical solution by taking an N-channel high-voltage MOSFET device as an example, and other ways to realize the content of the present application should not be considered as different from the present solution. The corresponding P-channel high-voltage MOSFET device is identical in structure to the N-channel high-voltage MOSFET device, but the doping is different. The process needs to be adjusted according to the different process characteristics of P-type and N-type impurities, which can be realized by the general technicians in the industry, and should not be considered as being restricted by the present application. The following examples describe the process as a mature existing process, and no very detailed description is made, which can be understood and understood by the general technicians in the industry.

[0080] Embodiment one

[0081] As shown in Figure 1 , the embodiment of the present application provides a resistance field plate asymmetric gate field effect device, which comprises:

[0082] highly doped substrate 1;

[0083] epitaxial layer 2, arranged on the highly doped substrate 1, and having a first deep trench and a second deep trench formed therein, and the first deep trench and the second deep trench vertically enter the highly doped substrate 1;

[0084] first resistance field plate structure 3, arranged in the first deep trench, and the bottom of which is electrically connected with the highly doped substrate 1;

[0085] MOSFET structure 4, arranged in the epitaxial layer 2 and located on the first resistance field plate structure 3, and the source electrode 45 of which is electrically connected with the top of the first resistance field plate structure 3;

[0086] second resistance field plate structure 5, arranged in the second deep trench, and the bottom of which is electrically connected with the highly doped substrate 1, and the top of which is electrically connected with the control electrode 6;

[0087] wherein, during the operation of the resistance field plate asymmetric gate field effect device, the potential of the control electrode 6 is the same as that of one of the source electrode 45 of the MOSFET structure or the gate electrode 46 of the MOSFET structure.

[0088] In detail, as shown in Figure 1 , in the embodiment of the present application, the MOSFET structure 4 comprises:

[0089] channel diffusion region 41, arranged in the epitaxial layer 2, and having an impurity conductivity type opposite to that of the epitaxial layer 2;

[0090] source diffusion region 42, arranged in the epitaxial layer 2 and located on the channel diffusion region 41, and having an impurity conductivity type same as that of the epitaxial layer 2;

[0091] gate dielectric layer 43, arranged on the epitaxial layer 2;

[0092] a polysilicon gate 44 disposed on the gate dielectric layer 43 and laterally covering at least the non-overlapping regions of the channel diffusion region 41 and the source diffusion region 42;

[0093] a source electrode 45 vertically penetrating the gate dielectric layer 43 and electrically connected to the top of the channel diffusion region 41, the source diffusion region 42 and the first resistive field plate structure 3, and the source electrode 45 is electrically connected to the channel diffusion region 41 and the source diffusion region 42 at the top sidewall of the first deep trench;

[0094] a gate electrode 46 electrically connected to the polysilicon gate 44;

[0095] a drain electrode electrically led out from the high-doped substrate 1 away from the epitaxial layer 2.

[0096] In more detail, as shown in Figure 1 the first resistive field plate structure 3 includes an oxide layer 31 located at the sidewall of the first deep trench and a semi-insulating polysilicon structure 32 filled in the first deep trench; the first resistive field plate structure 3 does not fill the first deep trench, the bottom of the semi-insulating polysilicon structure 32 (or the first resistive field plate structure 3) is electrically connected (ohmic contact) to the high-doped substrate 1, and the top of the semi-insulating polysilicon structure 32 (or the first resistive field plate structure 3) is located within the range from the bottom of the channel diffusion region 41 to the bottom of the source diffusion region 42.

[0097] In more detail, as shown in Figure 1 the second resistive field plate structure 5 includes an oxide layer 51 located at the sidewall of the second deep trench and a semi-insulating polysilicon structure 52 filled in the second deep trench, and the top of the semi-insulating polysilicon structure 52 is electrically led out as the control electrode 6.

[0098] In which, as shown in Figure 1 the distance from the bottom of the channel diffusion region 41 to the bottom of the source diffusion region 42 is h1, the distance from the top of the semi-insulating polysilicon structure 32 to the bottom of the source diffusion region 42 is h2, which must be greater than zero, the distance from the top of the oxide layer 31 at the sidewall of the first deep trench to the bottom of the channel diffusion region 41 is h3, which must also be greater than zero, and the sum of h2 and h3 must be less than h1, so as to ensure that the source electrode 45 can be reliably electrically connected to the channel diffusion region 41 without being in electrical contact with the epitaxial layer 2 to cause leakage or damage the normal function of the MOSFET structure 4; the first resistive field plate structure 3 and the second resistive field plate structure 5 are deeply inserted into the high-doped substrate 1, and the depth of the insertion into the high-doped substrate 1 is h4, which is determined by target parameters and process conditions and is not limited herein.

[0099] Meanwhile, as shown in Figures 2-16 the present application also provides a preparation method of the resistive field plate asymmetric gate field effect device, which includes the following steps:

[0100] S1, asFigure 3 As shown, a highly doped substrate 1 is provided, and an epitaxial layer 2 is formed on the highly doped substrate 1;

[0101] S2, such as Figures 4-5 As shown, a gate dielectric layer 43 is formed on the epitaxial layer 2, and a polysilicon gate 44 is formed on the gate dielectric layer 43;

[0102] S3, such as Figures 6-7 As shown, based on the polysilicon gate 44, a channel diffusion region 41 and a source diffusion region 42 are formed in a local area at the top of the epitaxial layer 2 using self-aligned implantation technology and double diffusion technology, and the source diffusion region 42 is located at the top of the channel diffusion region 41 in the vertical direction.

[0103] S4, such as Figure 9 As shown, a first deep trench T1 and a second deep trench T2 are formed. The first deep trench T1 passes vertically through the source diffusion region 42, the channel diffusion region 41 and the epitaxial layer 2 to the highly doped substrate 1. The second deep trench T2 passes vertically through the epitaxial layer 2 to the highly doped substrate 1.

[0104] S5, such as Figures 10-13 As shown, a first resistive field plate structure 3 is formed in the first deep trench T1, and a second resistive field plate structure 5 is formed in the second deep trench T2. The first resistive field plate structure 3 does not fill the first deep trench T1, and the top of the first resistive field plate structure 3 is located in the range from the bottom of the channel diffusion region 41 to the bottom of the source diffusion region 42 in the vertical direction.

[0105] S6, such as Figures 14-16 As shown, a source electrode 45, a gate electrode 46, and a control electrode 6 are formed. The source electrode 45 passes vertically through the gate dielectric layer 43 and is electrically connected to the top of the channel diffusion region 41, the source diffusion region 42, and the first resistive field plate structure 3. The source electrode 45 is electrically connected to the channel diffusion region 41 and the source diffusion region 42 at the top sidewall of the first deep trench T1. The gate electrode 46 is electrically connected to the polysilicon gate 44. The control electrode 6 is electrically connected to the top of the second resistive field plate structure 5.

[0106] In detail, such as Figure 3 As shown, in step S1, a highly doped substrate 1 is provided mainly as the drain region of the MOSFET device, which is an N-type doped semiconductor material (such as silicon, silicon carbide, gallium arsenide, etc.); an epitaxial layer 2 is formed on the substrate 1 as the drift region and part of the drain region of the MOSFET device, and the epitaxial layer 2 is also an N-type doped semiconductor material.

[0107] More specifically, the highly doped substrate 1 is heavily doped, and the epitaxial layer 2 is lightly doped, meaning the impurity concentration in the highly doped substrate 1 is higher than the medium impurity concentration in the epitaxial layer 2. It is understandable that the conductivity types of the impurities in the epitaxial layer 2 and the highly doped substrate 1 could be opposite, which will not be elaborated further here.

[0108] The thickness of the epitaxial layer 2 can be flexibly designed as appropriate, such as 20 μm for a breakdown voltage of 300 V.

[0109] In detail, between the step S1 and the step S2, the method for manufacturing the resistive field plate asymmetric gate field effect device further comprises a step of forming a photoetching alignment mark on the epitaxial layer 2 by using a common method in the industry, so as to facilitate alignment in subsequent process steps.

[0110] In detail, as shown in Figures 4-5 the step S2 further comprises:

[0111] S21, as shown in Figure 4 , a top portion of the epitaxial layer 2 is oxidized by using a common process to form a gate dielectric layer 43, such as performing a chlorine-doped dry oxidation process at 1050°C for 110 minutes to obtain a gate dielectric layer 43 with a thickness of about 80 nm-120 nm;

[0112] S22, as shown in Figure 5 , a layer of polycrystalline silicon material with a thickness of 450 nm±100 nm is formed on the gate dielectric layer 43 by using a low-pressure chemical vapor deposition process (LPCVD), and the polycrystalline silicon material layer is doped by using a common in-situ doping, ion implantation, diffusion, etc. Then, the doped polycrystalline silicon material layer is photoetched and etched to form a polycrystalline silicon gate 44.

[0113] In detail, as shown in Figures 6-7 , the step S3 of forming the channel diffusion region 41 and the source diffusion region 42 in the local area of the top portion of the epitaxial layer 2 according to the polycrystalline silicon gate 44 by using a self-aligned implantation technology and a double diffusion technology further comprises:

[0114] S31, as shown in Figure 6 , a first photoresist 71 is first formed on the gate dielectric layer 43 and the polycrystalline silicon gate 44, a specific window is photoetched by using a common photoetching process, and the first photoresist 71 is reserved, then, the polycrystalline silicon gate 44 and the remaining first photoresist 71 are used as a mask to perform a first ion implantation and a first ion diffusion to form the channel diffusion region 41 in the top portion of the epitaxial layer 2.

[0115] S32, as shown in Figure 7 , the polycrystalline silicon gate 44 and a second photoresist 72 are used as a mask to perform a second ion implantation to form the source diffusion region 42 in the top portion of the epitaxial layer 2, and the source diffusion region 42 is located on the top portion of the channel diffusion region 41 in the vertical direction and is located within the channel diffusion region 41 in the horizontal direction.

[0116] More specifically, as shown in Figure 6As shown, in step S31, the first ion implantation is performed using the polysilicon gate 44 and the remaining first photoresist 71 as a mask, such as 100 KeV, 1~5×10⁻⁶. 13 cm -2 After the first ion implantation is completed, the remaining first photoresist 71 is removed, and then the first ion diffusion is carried out under the protection of inert gas, such as ion diffusion at 1050℃ for 90 minutes, to form a P-type doped channel diffusion region 41 in the top of the epitaxial layer 2.

[0117] This process can be adjusted according to the specific performance parameters required by the MOSFET device, which is well known to most technicians in the industry and will not be limited here.

[0118] More in detail, such as Figure 7 As shown, in step S32, source region photolithography is first performed on the second photoresist 72. Then, using the polysilicon gate 44 and the remaining second photoresist 72 as a shielding mask, a second ion implantation is performed, such as at 170 keV and 5 × 10⁻⁶ ppm. 15 cm -2 Arsenic ions are implanted to form source diffusion region 42.

[0119] In detail, such as Figure 8 As shown, between step S3 and step S4, the fabrication method of the resistive field plate asymmetric gate field effect device further includes the following steps: removing the remaining second photoresist 72, and forming a masking dielectric layer 8 on the gate dielectric layer 43 and the polysilicon gate 44 using a low-pressure chemical vapor deposition (LPCVD) process or a dielectric plasma-enhanced chemical vapor deposition (PECVD) process. The masking dielectric layer 8 can be a silicon dioxide dielectric layer with a thickness of 500nm to 700nm, which can mask the subsequent etching of the first deep trench T1 and the second deep trench T2.

[0120] Specifically, in step S4, the positions of the first deep trench T1 and the second deep trench T2 are first exposed using a photolithography machine and a corresponding photomask. Then, dry etching is performed. After etching opens the masking dielectric layer 8 and the gate dielectric layer 43, etching continues. The first deep trench T1 and the second deep trench T2 are formed in the epitaxial layer 2 and the highly doped substrate 1. The etched first deep trench T1 perpendicularly passes through the source diffusion region 42, the channel diffusion region 41, and the epitaxial layer 2 to the highly doped substrate 1. The etched second deep trench T2 perpendicularly passes through the epitaxial layer 2 to the highly doped substrate 1. Figure 9 As shown.

[0121] The specific parameters (including the number, depth, width and depth into the high-doped substrate 1) of the first deep trench T1 and the second deep trench T2 need to be designed according to the working voltage of the high-voltage MOSFET device and the process implementation capability, and the size of the gate polysilicon electrode and the semi-insulating material resistive field plate in the same deep trench and the optimal area required by the MOSFET device need to be considered in the design process; in the embodiment of the present application, the specific parameters of the first deep trench T1 and the second deep trench T2 are designed as follows: the depth is 22 μm, the width is 0.8-1.2 μm, and the depth into the high-doped substrate 1 is h4=2 μm.

[0122] In detail, as shown in Figures 10-13 , the step S5 of forming the first resistive field plate structure 3 in the first deep trench T1 and the second resistive field plate structure 5 in the second deep trench T2 further comprises:

[0123] S51, as shown in Figure 10 , the bottom and sidewall of the first deep trench T1 are oxidized to form an oxide layer 31 in the first deep trench T1, and the bottom and sidewall of the second deep trench T2 are oxidized to form an oxide layer 51 in the second deep trench T2; as shown in Figure 11 , the oxide layer 31 at the bottom of the first deep trench T1 and the oxide layer 51 at the bottom of the second deep trench T2 are removed by using an anisotropic dry etching process, and the oxide layer 31 at the sidewall of the first deep trench T1 and the oxide layer 51 at the sidewall of the second deep trench T2 are reserved;

[0124] S52, as shown in Figure 12 , a low-pressure chemical vapor deposition process is adopted to deposit a semi-insulating polysilicon material 9, the deposition thickness of the semi-insulating polysilicon material 9 is 1.1 μm±0.1 μm, and the semi-insulating polysilicon material 9 at least fills the first deep trench T1 and the second deep trench T2;

[0125] S53, as shown in Figure 13 , a photolithography machine and a corresponding photomask are used to expose the required pattern, the semi-insulating polysilicon material 9 on the surface is etched in reverse, the excess semi-insulating polysilicon material 9 is etched and removed, most of the semi-insulating polysilicon material 9 on the dielectric layer 8 is etched and removed, only part of the semi-insulating polysilicon material 9 in the adjacent area of the second deep trench T2 is reserved, then the semi-insulating polysilicon material 9 filled in the first deep trench T1 is continuously and carefully etched and removed, the top of the first deep trench T1 is exposed, and the bottom of the exposed part of the first deep trench T1 is located within the range from the bottom of the channel diffusion region 41 to the bottom of the source diffusion region 42 in the vertical direction;

[0126] In detail, as shown in Figure 13As shown, the oxide layer 31 at the sidewall of the first deep trench T1 and the remaining semi-insulating polysilicon material 9 (denoted as semi-insulating polysilicon structure 32) constitute the first resistance field plate structure 3, and the oxide layer 51 at the sidewall of the second deep trench T2 and the filled semi-insulating polysilicon material 9 (denoted as semi-insulating polysilicon structure 52) constitute the second resistance field plate structure 5; it can be understood that, according to the resistance field plate theory, the oxide layer 31 and the oxide layer 51 are not necessary components, but the existence of the oxide layer 31 and the oxide layer 51 is beneficial to reduce the reverse bias leakage current of the asymmetric gate field effect device.

[0127] Meanwhile, the formation processes of the gate dielectric layer 43, the polysilicon gate 44, the channel diffusion region 41 and the source diffusion region 42 in steps S2-S3 can also be implemented in the deep trench formation process in steps S4-S5 or based on the inter-step compatible process, which is easy for the general technical personnel in the industry to understand and achieve, and will not be described in detail here.

[0128] In detail, as shown in Figures 14-16 Step S6 of forming the source electrode 45, the gate electrode 46 and the control electrode 6 further includes:

[0129] S61, as shown in Figure 14 An isolation dielectric layer 10 is formed by a low pressure chemical vapor deposition process (LPCVD), and the isolation dielectric layer 10 can be a silicon dioxide dielectric layer, which is used to close and isolate the first resistance field plate structure 3, the MOSFET structure 4 and the second resistance field plate structure 5;

[0130] S62, as shown in Figure 15 Through photolithography and etching, a source electrode contact hole T3, a gate electrode contact hole T4 and a control electrode contact hole T5 are opened, the source electrode contact hole T3 exposes the channel diffusion region 41, the source diffusion region 42 and the top of the first resistance field plate structure 3, the gate electrode contact hole T4 exposes the polysilicon gate 44, and the control electrode contact hole T5 exposes the remaining semi-insulating polysilicon material 9 which is electrically connected to the top of the second resistance field plate structure 5;

[0131] S63, as shown in Figure 16As shown, the metal layer is deposited and photoetched to form the source electrode 45 at the position of the source electrode contact hole T3, the source electrode 45 vertically penetrates through the isolation medium layer 10, the masking medium layer 8 and the gate medium layer 43 to electrically connect with the top of the channel diffusion region 41, the source diffusion region 42 and the first resistance field plate structure 3, and the source electrode 45 is electrically connected with the top of the channel diffusion region 41, the source diffusion region 42 and the first resistance field plate structure 3 at the top sidewall of the first deep trench T1, the gate electrode 46 is formed at the position of the gate electrode contact hole T4, the gate electrode 46 vertically penetrates through the isolation medium layer 10 and the masking medium layer 8 to electrically connect with the polysilicon gate 44, the control electrode 6 is formed at the position of the control electrode contact hole T5, the control electrode 6 vertically penetrates through the isolation medium layer 10 to electrically connect with the top of the second resistance field plate structure 5 through the remaining semi-insulating polysilicon material 9.

[0132] In addition, the drain region of the MOSFET structure 4 is composed of the highly doped substrate 1 and the epitaxial layer 2 close to the highly doped substrate 1, and accordingly, the drain electrode is arranged on the side of the highly doped substrate 1 away from the epitaxial layer 2, and the metal layer is first deposited on the side of the highly doped substrate 1 away from the epitaxial layer 2 to form the drain electrode.

[0133] Finally, the resistance field plate asymmetric gate field effect device as shown in Figure 1 or Figure 16 is obtained, two asymmetric deep trench type resistance field plate structures are arranged in the minimum repeatable unit of the MOSFET device, the top end of one resistance field plate structure is provided with the MOSFET structure and is connected with the source electrode of the MOSFET structure, and the top end of the other resistance field plate structure leads out the control electrode: when the source electrode of the MOSFET structure is connected with the control electrode at the same potential, based on the asymmetry and structural difference of the two resistance field plate structures, it is more suitable to improve the impurity concentration of the drift region of the MOSFET, to reduce the on-resistance of the drift region while maintaining the withstand voltage, to optimize the basic contradiction between the on-resistance and the withstand voltage, and at the same time, the electric field coupling effect is better, and the repulsion and extrusion on the adjacent other minimum repeatable units are also reduced, thereby facilitating the structure compression of the minimum repeatable unit and being beneficial to the structure miniaturization design and high-density design; when the gate electrode of the MOSFET structure is connected with the control electrode at the same potential, the carrier concentration of the drift region of the MOSFET structure can also be adjusted and improved by the second resistance field plate, the on-resistance of the drift region is reduced, the current-carrying capacity of the device is increased, and the basic contradiction between the on-resistance and the withstand voltage is further optimized; in the process, the modern 2.5-dimensional three-dimensional processing technology based on deep trench etching is adopted, which is further beneficial to the structure miniaturization design and high-density design, and is more suitable for the development direction of modern integrated semiconductor devices beyond Moore.

[0134] Furthermore, it should be noted that the steps in the above embodiments omit well-known and obvious industry-standard cleaning processes and conditions, which are common knowledge to those skilled in the art and will not be described in detail here.

[0135] Example 2

[0136] In the resistive field plate asymmetric gate field effect device of the present invention, the source electrode 45 is electrically connected to the channel diffusion region 41 and the source diffusion region 42 at the top sidewall of the first deep trench T1. The top of the first resistive field plate structure 3 formed in the first deep trench T1 must be located in the vertical direction within the range from the bottom of the channel diffusion region 41 to the bottom of the source diffusion region 42, so as to ensure that the source electrode 45 is reliably electrically connected to the channel diffusion region 41 and the source diffusion region 42 without making electrical contact with the epitaxial layer 2, thereby causing leakage or damaging the normal function of the MOSFET structure 4. This places relatively stringent requirements on the process.

[0137] Based on this, an improved solution is proposed in this embodiment of the invention: the electrical connection of the channel diffusion region 41 is led to the surface of the epitaxial layer 2 through the channel contact region that contacts the channel diffusion region 41, so that the subsequent electrical connection between the source electrode 45 and the channel diffusion region 41 and the source diffusion region 42 can be realized at the surface of the epitaxial layer 2 (i.e., at the top surface of the first deep trench T1), thereby reducing the difficulty of the process.

[0138] like Figure 17 As shown, an embodiment of the present invention provides a resistive field-plate asymmetric gate field-effect device, which includes:

[0139] Highly doped substrate 1;

[0140] Epitaxial layer 2 is disposed on highly doped substrate 1, and a first deep trench and a second deep trench are formed therein, with the first deep trench and the second deep trench perpendicularly entering the highly doped substrate 1.

[0141] The first resistive field plate structure 3 is disposed in the first deep trench, and its bottom is electrically connected to the highly doped substrate 1.

[0142] MOSFET structure 4 is disposed in epitaxial layer 2 and located on first resistive field plate structure 3, and its source electrode 45 is electrically connected to the top of first resistive field plate structure 3.

[0143] The second resistive field plate structure 5 is disposed in the second deep trench, and its bottom is electrically connected to the highly doped substrate 1, and the top is electrically led out to the control electrode 6.

[0144] When the resistive field plate asymmetric gate field effect device is working, the potential of the control electrode 6 is the same as the potential of one of the electrodes, either the source electrode 45 of the MOSFET structure or the gate electrode 46 of the MOSFET structure.

[0145] In detail, as shown in Figure 17 , in the embodiment of the present application, the MOSFET structure 4 comprises:

[0146] a channel diffusion region 41 disposed in the epitaxial layer 2 and having an impurity conductivity type opposite to that of the epitaxial layer 2;

[0147] a source diffusion region 42 disposed in the epitaxial layer 2 and located on the channel diffusion region 41, and having an impurity conductivity type same as that of the epitaxial layer 2;

[0148] a channel contact region 47 disposed in the epitaxial layer 2 and in contact with the channel diffusion region 41, and having an impurity conductivity type opposite to that of the epitaxial layer 2;

[0149] a gate dielectric layer 43 disposed on the epitaxial layer 2;

[0150] a polysilicon gate 44 disposed on the gate dielectric layer 43 and laterally covering at least non-overlapping regions of the channel diffusion region 41 and the source diffusion region 42;

[0151] a source electrode 45 vertically penetrating through the gate dielectric layer 43 and electrically connected to the source diffusion region 42, the channel contact region 47 and the top of the first resistive field plate structure 3, and the source electrode 45 is electrically connected to the source diffusion region 42 and the channel contact region 47 at the top surface of the first deep trench;

[0152] a gate electrode 46 electrically connected to the polysilicon gate 44;

[0153] a drain electrode electrically led out from the high-doped substrate 1 away from the epitaxial layer 2.

[0154] In detail, as shown in Figure 17 , the device structure in the embodiment of the present application is similar to that in the first embodiment, and the only difference is that the MOSFET structure 4 further comprises a channel contact region 47 disposed in the epitaxial layer 2 and in contact with the channel diffusion region 41, so that the subsequent electrical connection of the source electrode 45 to the channel diffusion region 41 and the source diffusion region 42 can be realized at the surface of the epitaxial layer 2; at the same time, since the channel diffusion region 41 no longer needs to be exposed to the sidewall of the first deep trench T1, the first resistive field plate structure 3 completely fills the first deep trench T1.

[0155] Wherein, other detailed structures of the resistive field plate asymmetric gate field effect device can refer to Figure 17 and the related description of the first embodiment, which will not be repeated here.

[0156] Correspondingly, as shown in Figures 3-5 , Figures 18-29 , the embodiment of the present application further provides a preparation method of a resistive field plate asymmetric gate field effect device, which comprises the following steps:

[0157] Stp1, as shown in Embodiment One, a high doped substrate 1 is provided and an epitaxial layer 2 is formed on the high doped substrate 1; Figure 3

[0158] Stp2, as shown in Embodiment One, a gate dielectric layer 43 is formed on the epitaxial layer 2 and a polysilicon gate 44 is formed on the gate dielectric layer 43; Figures 4-5

[0159] Stp3, as shown in Embodiment One, according to the polysilicon gate 44, a channel diffusion region 41, a channel contact region 47 and a source diffusion region 42 are formed in a top portion of the epitaxial layer 2 by using self-aligned implantation and double diffusion techniques, and the channel contact region 47 and the source diffusion region 42 are vertically on top of the channel diffusion region 41, and the channel contact region 47 is in contact with the channel diffusion region 41; Figures 18-20

[0160] Stp4, as shown in Embodiment One, a first deep trench T1 and a second deep trench T2 are formed, the first deep trench T1 vertically passes through the channel contact region 47, the channel diffusion region 41 and the epitaxial layer 2 to the high doped substrate 1, and the second deep trench T2 vertically passes through the epitaxial layer 2 to the high doped substrate 1; Figure 22

[0161] Stp5, as shown in Embodiment One, a first resistance field plate structure 3 is formed in the first deep trench T1 and a second resistance field plate structure 5 is formed in the second deep trench T2; Figures 23-26

[0162] Stp6, as shown in Embodiment One, a source electrode 45, a gate electrode 46 and a control electrode 6 are formed, the source electrode 45 vertically passes through the gate dielectric layer 43 and is electrically connected to the top of the source diffusion region 42, the channel contact region 47 and the first resistance field plate structure 3, the gate electrode 46 is electrically connected to the polysilicon gate 44, and the control electrode 6 is electrically connected to the top of the second resistance field plate structure 5. Figures 27-29 Wherein, steps Stp1-S tp2 are similar to steps S1-S2 in Embodiment One, and will not be described here again; the difference starts from step Stp3.

[0163] In detail, as shown in Embodiment One, according to the polysilicon gate 44, a channel diffusion region 41, a source diffusion region 42 and a channel contact region 47 are formed in a top portion of the epitaxial layer 2 by using self-aligned implantation and double diffusion techniques, and the channel contact region 47 and the source diffusion region 42 are vertically on top of the channel diffusion region 41, and the channel contact region 47 is in contact with the channel diffusion region 41;

[0164] Figures 18-20 Stp31, as shown in Embodiment One, a channel diffusion region 41 is formed in a top portion of the epitaxial layer 2 by using self-aligned implantation and double diffusion techniques;

[0165] Stp32, as shown in Embodiment One, a source diffusion region 42 is formed in a top portion of the epitaxial layer 2 by using self-aligned implantation and double diffusion techniques; Figure 18 ​​​​​​As shown, a third photoresist 73 is first formed on the gate dielectric layer 43 and the polysilicon gate 44. A specific window is etched using a general photolithography process, and the third photoresist 73 is retained. Then, the polysilicon gate 44 and the remaining third photoresist 73 are used as a mask to perform the first ion implantation and the first ion diffusion, forming a channel diffusion region 41 in the top of the epitaxial layer 2.

[0166] Stp32, such as Figure 19 As shown, a fourth photoresist 74 is first formed on the gate dielectric layer 43 and the polysilicon gate 44. A specific window is etched using a general photolithography process, and the fourth photoresist 74 is retained. Then, using the polysilicon gate 44 and the remaining fourth photoresist 74 as a mask, a second ion implantation is performed to form a channel contact region 47 in the top of the epitaxial layer 2. The channel contact region 47 contacts the channel diffusion region 41. In the horizontal direction, the channel contact region 47 is located within the source diffusion region 42.

[0167] Stp33, such as Figure 20 As shown, a fifth photoresist 75 is first formed on the gate dielectric layer 43 and the polysilicon gate 44. A specific window is etched using a general photolithography process, and the fifth photoresist 75 is retained. Then, using the polysilicon gate 44 and the remaining fifth photoresist 75 as a mask, a third ion implantation is performed to form a source diffusion region 42 in the top of the epitaxial layer 2. In the vertical direction, the source diffusion region 42 is located on top of the channel diffusion region 41, and in the horizontal direction, the source diffusion region 42 is located within the channel diffusion region 41.

[0168] More in detail, such as Figure 18 As shown, in step Stp31, the first ion implantation is performed using the polysilicon gate 44 and the remaining third photoresist 73 as a mask, such as 100 KeV, 1~5×10⁻⁶. 13 cm -2 Boron ion implantation is performed. After the first ion implantation is completed, the remaining third photoresist 73 is removed. Then, the first ion diffusion is performed under the protection of inert gas, such as ion diffusion at 1050℃ for 90 minutes, to form a P-type doped channel diffusion region 41 in the top of the epitaxial layer 2.

[0169] More in detail, such as Figure 19 As shown, in step Stp32, the channel contact area is first photolithography is performed on the fourth photoresist 74. Then, using the polysilicon gate 44 and the remaining fourth photoresist 74 as a shielding mask, a second ion implantation is performed, such as at 80 keV and 3 × 10⁻⁶ ppm. 15 cm -2 Boron ion implantation forms the channel contact region 47.

[0170] More in detail, such as Figure 20As shown, in step Stp33, source region photolithography is first performed on the fifth photoresist 75. Then, using the polysilicon gate 44 and the remaining fifth photoresist 75 as a shielding mask, a third ion implantation is performed, such as at 170 keV and 5 × 10⁻⁶ ppm. 15 cm -2 Arsenic ions are implanted to form source diffusion region 42.

[0171] In detail, such as Figure 21 As shown, similar to Embodiment 1, between step Stp3 and step Stp4, the fabrication method of the resistive field plate asymmetric gate field effect device further includes the following steps: removing the remaining fifth photoresist 75, and forming a masking dielectric layer 8 on the gate dielectric layer 43 and the polysilicon gate 44 using a low-pressure chemical vapor deposition process (LPCVD) or a dielectric plasma-enhanced chemical vapor deposition process (PECVD) to mask the subsequent etching of the first deep trench T1 and the second deep trench T2.

[0172] In detail, such as Figure 22 As shown, in step Stp4, the positions of the first deep trench T1 and the second deep trench T2 are first exposed using a photolithography machine and a corresponding photomask. Then, dry etching is performed. After etching opens the masking dielectric layer 8 and the gate dielectric layer 43, etching continues. The first deep trench T1 and the second deep trench T2 are etched in the epitaxial layer 2 and the highly doped substrate 1. The etched first deep trench T1 vertically passes through the channel contact region 47, the channel diffusion region 41, and the epitaxial layer 2 to the highly doped substrate 1. The etched second deep trench T2 vertically passes through the epitaxial layer 2 to the highly doped substrate 1, as shown. Figure 9 As shown.

[0173] In detail, such as Figures 23-26 As shown, similar to Embodiment 1, step Stp5, which involves forming a first resistive field plate structure 3 in the first deep trench T1 and a second resistive field plate structure 5 in the second deep trench T2, further includes:

[0174] Stp51, such as Figure 23 As shown, the bottom and sidewalls of the first deep trench T1 are oxidized to form an oxide layer 31 in the first deep trench T1, and the bottom and sidewalls of the second deep trench T2 are oxidized to form an oxide layer 51 in the second deep trench T2; as Figure 24 As shown, an anisotropic dry etching process is used to remove the oxide layer 31 at the bottom of the first deep trench T1 and the oxide layer 51 at the bottom of the second deep trench T2, while retaining the oxide layer 31 on the sidewall of the first deep trench T1 and the oxide layer 51 on the sidewall of the second deep trench T2.

[0175] Stp52, such as Figure 25As shown, a low pressure chemical vapor deposition process is used to deposit the semi-insulating polysilicon material 9, and the thickness of the semi-insulating polysilicon material 9 is 1.1 μm ± 0.1 μm, and the semi-insulating polysilicon material 9 at least fills the first deep trench T1 and the second deep trench T2;

[0176] Stp53, as shown in Figure 26 As shown, a photolithography machine and a corresponding photomask are used to expose the desired pattern, and a reverse etching process is used to etch the surface of the semi-insulating polysilicon material 9, and the excess semi-insulating polysilicon material 9 is etched away, and most of the semi-insulating polysilicon material 9 on the dielectric layer 8 is etched away, and only the semi-insulating polysilicon material 9 filled in the first deep trench T1 and the second deep trench T2, and the portion of the semi-insulating polysilicon material 9 in the adjacent area on the top of the second deep trench T2 are reserved;

[0177] In which, the oxide layer 31 on the sidewall of the first deep trench T1 and the semi-insulating polysilicon material 9 filled therein (denoted as semi-insulating polysilicon structure 32) constitute the first resistance field plate structure 3, and the oxide layer 51 on the sidewall of the second deep trench T2 and the semi-insulating polysilicon material 9 filled therein (denoted as semi-insulating polysilicon structure 52) constitute the second resistance field plate structure 5.

[0178] In detail, as shown in Figures 27-29 As shown, the steps Stp6 of forming the source electrode 45, the gate electrode 46 and the control electrode 6 further include:

[0179] Stp61, as shown in Figure 27 As shown, a low pressure chemical vapor deposition process (LPCVD) is used to deposit the isolation dielectric layer 10, and the isolation dielectric layer 10 can be a silicon dioxide dielectric layer, and the first resistance field plate structure 3, the MOSFET structure 4 and the second resistance field plate structure 5 are closed and isolated;

[0180] Stp62, as shown in Figure 28 As shown, through photolithography and etching, the source electrode contact hole T3, the gate electrode contact hole T4 and the control electrode contact hole T5 are opened, the source electrode contact hole T3 exposes the source diffusion region 42, the channel contact region 47 and the top of the first resistance field plate structure 3, the gate electrode contact hole T4 exposes the polysilicon gate 44, and the control electrode contact hole T5 exposes the remaining semi-insulating polysilicon material 9 which is electrically connected to the top of the second resistance field plate structure 5;

[0181] Stp63, as shown in Figure 29As shown, the metal layer is deposited and photoetched to form the source electrode 45 at the position of the source electrode contact hole T3, the source electrode 45 is electrically connected to the top of the source diffusion region 42, the channel contact region 47 and the first resistance field plate structure 3 vertically through the isolation medium layer 10, the masking medium layer 8 and the gate medium layer 43, and the source electrode 45 is electrically connected to the top of the source diffusion region 42, the channel contact region 47 and the first resistance field plate structure 3 at the top surface of the first deep trench T1, the gate electrode 46 is formed at the position of the gate electrode contact hole T4, the gate electrode 46 is electrically connected to the polysilicon gate 44 vertically through the isolation medium layer 10 and the masking medium layer 8, and the control electrode 6 is formed at the position of the control electrode contact hole T5, the control electrode 6 is electrically connected to the top of the second resistance field plate structure 5 through the remaining semi-insulating polysilicon material 9 vertically through the isolation medium layer 10.

[0182] In summary, in the asymmetric resistance field plate MOSFET device and the preparation method thereof, two asymmetric deep trench resistance field plate structures are arranged in the minimum repeatable unit of the MOSFET device, the top of the first resistance field plate structure is provided with the MOSFET structure and is electrically connected to the source electrode of the MOSFET structure, and the top of the second resistance field plate structure is provided with the control electrode. When the source electrode of the MOSFET structure is electrically connected to the control electrode, the electric field coupling effect of the two resistance field plate structures is better due to the structural asymmetry and difference, which is more suitable for improving the impurity concentration of the drift region of the MOSFET, reducing the on-resistance of the drift region while maintaining the withstand voltage, and optimizing the basic contradiction between the on-resistance and the withstand voltage. At the same time, the electric field coupling effect is better, and the repulsion and extrusion of the adjacent other minimum repeatable units are reduced, thereby facilitating the structure compression of the minimum repeatable unit and being beneficial to the structure miniaturization design and high-density design. When the gate electrode of the MOSFET structure is electrically connected to the control electrode, the carrier concentration of the drift region of the MOSFET structure can also be adjusted and improved by the second resistance field plate, the on-resistance of the drift region is reduced, the conductivity of the device is increased, and the basic contradiction between the on-resistance and the withstand voltage is further optimized. The modern 2.5-dimensional three-dimensional processing technology based on deep trench etching is adopted in the process, which is further beneficial to the structure miniaturization design and high-density design, and is more suitable for the development direction of modern integrated semiconductor devices beyond Moore.

[0183] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not intended to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.

Claims

1. A resistive field plate asymmetric gate field effect device, characterized by, The application relates to an asymmetric gate field effect device, comprising: a high-doped substrate; an epitaxial layer arranged on the high-doped substrate, a first deep trench and a second deep trench being formed in the epitaxial layer and vertically penetrating into the high-doped substrate; a first resistive field plate structure arranged in the first deep trench and electrically connected to the high-doped substrate at the bottom of the first resistive field plate structure; a MOSFET structure arranged in the epitaxial layer and on the first resistive field plate structure, a source electrode of the MOSFET structure being electrically connected to the top of the first resistive field plate structure; a second resistive field plate structure arranged in the second deep trench and electrically connected to the high-doped substrate at the bottom of the second resistive field plate structure and electrically leading out a control electrode at the top of the second resistive field plate structure; wherein, during the operation of the asymmetric gate field effect device, the potential of the control electrode is the same as the potential of one of the source electrode of the MOSFET structure or the gate electrode of the MOSFET structure. Two asymmetric deep trench type resistive field plate structures are arranged in the minimum repeatable unit of the MOSFET device, the top of the first resistive field plate structure is provided with the MOSFET structure and is connected to the source electrode of the MOSFET structure, and the top of the second resistive field plate structure leads out the control electrode.

2. The field plate resistor asymmetric gate field effect device of claim 1, wherein, The impurity conductive type of the high-doped substrate is the same as the impurity conductive type of the epitaxial layer.

3. The field plate resistor asymmetric gate field effect device of claim 1 or 2, wherein, The MOSFET structure comprises: a channel diffusion region arranged in the epitaxial layer and having an impurity conductive type opposite to the impurity conductive type of the epitaxial layer; a source diffusion region arranged in the epitaxial layer and on the channel diffusion region and having an impurity conductive type the same as the impurity conductive type of the epitaxial layer; a gate dielectric layer arranged on the epitaxial layer; a polysilicon gate arranged on the gate dielectric layer and at least laterally covering the non-overlapping regions of the channel diffusion region and the source diffusion region; a source electrode vertically penetrating through the gate dielectric layer and electrically connected to the channel diffusion region, the source diffusion region and the top of the first resistive field plate structure, and the source electrode being electrically connected to the channel diffusion region and the source diffusion region at the top sidewall of the first deep trench; a gate electrode electrically connected to the polysilicon gate; and a drain electrode electrically led out from the high-doped substrate away from the epitaxial layer.

4. The field plate resistor asymmetric gate field effect device of claim 1 or 2, wherein, The MOSFET structure comprises: a channel diffusion region arranged in the epitaxial layer and having an impurity conductive type opposite to the impurity conductive type of the epitaxial layer; a source diffusion region arranged in the epitaxial layer and on the channel diffusion region and having an impurity conductive type the same as the impurity conductive type of the epitaxial layer; a channel contact region arranged in the epitaxial layer and in contact with the channel diffusion region and having an impurity conductive type opposite to the impurity conductive type of the epitaxial layer; a gate dielectric layer arranged on the epitaxial layer; a polysilicon gate arranged on the gate dielectric layer and at least laterally covering the non-overlapping regions of the channel diffusion region and the source diffusion region. a source electrode vertically passing through the gate dielectric layer and electrically connected to the source diffusion region, the channel contact region and the top of the first resistance field plate structure, and the source electrode is electrically connected to the source diffusion region and the channel contact region at the top surface of the first deep trench; a gate electrode electrically connected to the polysilicon gate; a drain electrode electrically led out from the high doped substrate away from the epitaxial layer.

5. A method for fabricating a resistive field-plate asymmetric gate field-effect device, characterized in that, The method comprises the steps of: providing a high doped substrate and forming an epitaxial layer on the high doped substrate; forming a gate dielectric layer on the epitaxial layer and a polysilicon gate on the gate dielectric layer; forming a channel diffusion region and a source diffusion region in a local region on the top of the epitaxial layer according to the polysilicon gate by using self-aligned implantation technology and double diffusion technology, and the source diffusion region is vertically on the top of the channel diffusion region; forming a first deep trench vertically passing through the source diffusion region, the channel diffusion region and the epitaxial layer to the high doped substrate and a second deep trench vertically passing through the epitaxial layer to the high doped substrate; forming a first resistance field plate structure in the first deep trench and a second resistance field plate structure in the second deep trench, the first resistance field plate structure does not fill the first deep trench, and the top of the first resistance field plate structure is vertically within the range from the bottom of the channel diffusion region to the bottom of the source diffusion region; forming a source electrode, a gate electrode and a control electrode, the source electrode vertically passing through the gate dielectric layer and electrically connected to the channel diffusion region, the source diffusion region and the top of the first resistance field plate structure, and the source electrode is electrically connected to the channel diffusion region and the source diffusion region at the top sidewall of the first deep trench, the gate electrode is electrically connected to the polysilicon gate, and the control electrode is electrically connected to the top of the second resistance field plate structure.

6. The method of claim 5, wherein the method further comprises: The step of forming the channel diffusion region and the source diffusion region in a local region on the top of the epitaxial layer according to the polysilicon gate by using self-aligned implantation technology and double diffusion technology comprises: performing first ion implantation and first ion diffusion with the polysilicon gate and a first photoresist as a mask to form the channel diffusion region in the top of the epitaxial layer; performing second ion implantation with the polysilicon gate and a second photoresist as a mask to form the source diffusion region in the top of the epitaxial layer, and the source diffusion region is vertically on the top of the channel diffusion region and horizontally within the channel diffusion region.

7. The method of claim 6, wherein the method further comprises: forming a gate oxide layer on the substrate; forming a gate electrode on the gate oxide layer; and forming a gate pad on the gate electrode. The step of forming the first resistance field plate structure in the first deep trench and the second resistance field plate structure in the second deep trench comprises: forming an oxide layer in the first deep trench and the second deep trench, and removing the oxide layer at the bottom of the first deep trench and the oxide layer at the bottom of the second deep trench; depositing semi-insulating polysilicon material, which at least fills the first deep trench and the second deep trench; etching the filled part of the first deep trench to remove the part of the filled semi-insulating polysilicon material, to expose the top of the first deep trench, and the exposed part of the bottom of the first deep trench is within the range of the bottom of the channel diffusion region to the bottom of the source diffusion region in the vertical direction; wherein the oxide layer at the sidewall of the first deep trench and the remaining semi-insulating polysilicon material form the first resistive field plate structure, and the oxide layer at the sidewall of the second deep trench and the filled semi-insulating polysilicon material form the second resistive field plate structure.

8. A method for fabricating a resistive field-plate asymmetric gate field-effect device, characterized in that, comprising the steps of: providing a high-doped substrate, and forming an epitaxial layer on the high-doped substrate; forming a gate dielectric layer on the epitaxial layer, and forming a polysilicon gate on the gate dielectric layer; forming a channel diffusion region, a channel contact region and a source diffusion region in a local region on the top of the epitaxial layer according to the polysilicon gate by using a self-aligned implantation technique and a double diffusion technique, and the channel contact region and the source diffusion region are on the top of the channel diffusion region in the vertical direction, and the channel contact region is in contact with the channel diffusion region; forming a first deep trench and a second deep trench, the first deep trench vertically penetrating through the channel contact region, the channel diffusion region and the epitaxial layer to the high-doped substrate, and the second deep trench vertically penetrating through the epitaxial layer to the high-doped substrate; forming a first resistive field plate structure in the first deep trench, and forming a second resistive field plate structure in the second deep trench; forming a source electrode, a gate electrode and a control electrode, the source electrode vertically penetrating through the gate dielectric layer and electrically connected with the source diffusion region, the channel contact region and the top of the first resistive field plate structure, and the source electrode is electrically connected with the source diffusion region and the channel contact region at the top surface of the first deep trench, the gate electrode is electrically connected with the polysilicon gate, and the control electrode is electrically connected with the top of the second resistive field plate structure.

9. The method of claim 8, wherein the method further comprises: forming a gate oxide layer on the substrate; forming a gate electrode on the gate oxide layer; and forming a gate pad on the gate electrode. 9 the step of forming the channel diffusion region, the channel contact region and the source diffusion region in a local region on the top of the epitaxial layer according to the polysilicon gate by using a self-aligned implantation technique and a double diffusion technique comprises: performing a first ion implantation and a first ion diffusion by using the polysilicon gate and a third photoresist as a mask to form the channel diffusion region in the top of the epitaxial layer; performing a second ion implantation by using the polysilicon gate and a fourth photoresist as a mask to form the channel contact region in the top of the epitaxial layer, and the channel contact region is in contact with the channel diffusion region; performing a third ion implantation by using the polysilicon gate and a fifth photoresist as a mask to form the source diffusion region in the top of the epitaxial layer, and the source diffusion region is on the top of the channel diffusion region in the vertical direction, and the source diffusion region is within the channel diffusion region in the horizontal direction.

10. The method of claim 9, wherein the method further comprises: the step of forming the first resistive field plate structure in the first deep trench and forming the second resistive field plate structure in the second deep trench comprises: forming an oxide layer in the first deep trench and the second deep trench, and removing the oxide layer at the bottom of the first deep trench and the oxide layer at the bottom of the second deep trench; depositing a semi-insulating polysilicon material, the semi-insulating polysilicon material at least filling the first deep trench and the second deep trench; etching to remove excess semi-insulating polysilicon material, leaving only the semi-insulating polysilicon material filled in the first deep trench and the second deep trench, and a portion of the semi-insulating polysilicon material in the region adjacent to the top of the second deep trench; wherein the oxide layer at the sidewall of the first deep trench and the filled semi-insulating polysilicon material form the first resistive field plate structure, and the oxide layer at the sidewall of the second deep trench and the filled semi-insulating polysilicon material form the second resistive field plate structure.

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