Pulse dispensing apparatus and method

Abstract

The embodiment of the application discloses a pulse distribution device and method, the pulse distribution device comprises a pulse distribution module, which is used for distributing a PWM pulse signal with the same phase and period as a pulse synchronization signal and being output at the same time to a target channel in N channels when a target edge state of the pulse synchronization signal is detected; a straight-through prevention module is used for obtaining an inverse signal of the PWM pulse signal, and the PWM pulse signal output by the target channel is transmitted to a group of power tubes corresponding to the target channel, and the inverse signal of the PWM pulse signal is transmitted to the power tubes belonging to the same bridge arm as each power tube in the group of power tubes; different channels in the N channels correspond to different groups of power tubes in N groups of power tubes connected with a load in a multi-phase bridge; wherein, N is greater than 1; the PWM pulse signal and the pulse synchronization signal are output by a PWM pulse signal sending source in response to an enable signal. The reliability of PWM control is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of control, more particularly, to a pulse distribution device and method. BACKGROUND

[0002] In some control scenarios, a load (such as a motor or the like) is controlled by a multi-phase bridge through PWM (Pulse Width Modulation) control, the multi-phase bridge is composed of a plurality of bridge arms connected in parallel, each bridge arm is composed of two power tubes connected in series, and the two power tubes in each bridge arm constitute the upper tube and the lower tube of the bridge arm. In a specific application scenario, one half of the bridge arms of the multi-phase bridge are connected to the input end of the load, and the other half of the bridge arms are connected to the output end of the load, the upper power tube of one bridge arm connected to the input end of the load and the lower power tube of another bridge arm connected to the output end of the load constitute a group of power tubes, therefore, the load is connected to a plurality of groups of power tubes, and the control of the load by the multi-phase bridge is to send PWM pulse signals to each group of power tubes connected to the load in turn in time division, so that only one group of power tubes is turned on at the same time, thereby achieving control of the load.

[0003] The current bridge arm control is to send PWM pulse signals to the power tube groups corresponding to the pins of the MCU (Microcontroller Unit) through the pins of the MCU in turn to realize PWM control, because the pulse synchronization of each pin of the MCU is poor, it is impossible to ensure that the power tubes are turned on or turned off at the same time, and the reliability is poor. SUMMARY

[0004] The purpose of the present application is to provide a pulse distribution device and method to improve the reliability of PWM control. The technical solutions include the following:

[0005] A pulse distribution device, comprising:

[0006] A pulse distribution module is configured to, when a target edge state of a pulse synchronization signal is detected, distribute a PWM pulse signal having the same phase and period as the pulse synchronization signal and being output at the same time to a target channel of N channels; different channels of the N channels correspond to different groups of power tubes of N groups of power tubes connected to a load in a multi-phase bridge; wherein N is greater than 1; the PWM pulse signal and the pulse synchronization signal are output by a PWM pulse signal sending source in response to an enable signal; and the PWM pulse signal is distributed to different channels of the N channels when different times of the target edge state of the pulse synchronization signal are detected.

[0007] The anti-direct module is configured to obtain an inverted signal of the one PWM pulse signal, and transmit the PWM pulse signal output by the target channel to a group of power tubes corresponding to the target channel, and transmit the inverted signal of the one PWM pulse signal to a power tube belonging to the same bridge arm as each power tube in the group of power tubes.

[0008] Optionally, the pulse distribution module comprises:

[0009] The edge detection submodule is configured to detect a target edge state of the pulse synchronization signal.

[0010] The channel distribution submodule is configured to turn on a target channel in N channels of the controllable switch according to a preset control sequence when the edge detection submodule detects the target edge state of the pulse synchronization signal, so as to distribute the one PWM pulse signal to the target channel.

[0011] Optionally, the pulse distribution module further comprises:

[0012] The channel configuration submodule is configured to determine a target number of available channels in the controllable switch and a control sequence of the target number of available channels when the target number is obtained.

[0013] The first channel belongs to the target number of available channels.

[0014] Optionally, the channel configuration submodule comprises a dial switch and a first configuration unit, wherein:

[0015] The first configuration unit is configured to determine a binary code through a state of each key of the dial switch.

[0016] The binary code corresponds to a decimal number as the target number.

[0017] Optionally, the channel configuration submodule comprises a field programmable gate array chip and a second configuration unit, wherein:

[0018] The second configuration unit is configured to determine a binary code through a level of each target pin of the field programmable gate array chip, and the level of the target pin is related to a position of a target resistor in an external circuit of the target pin.

[0019] The binary code corresponds to a decimal number as the target number.

[0020] Optionally, the anti-direct module comprises:

[0021] The inversion submodule is configured to invert the one PWM pulse signal to obtain an inverted signal of the one PWM pulse signal.

[0022] The output sub-module is configured to determine whether the inverse signal of the PWM pulse signal is high; if the determination result is no, the PWM pulse signal output by the target channel is transmitted to a group of power tubes corresponding to the target channel, and the inverse signal of the PWM pulse signal is transmitted to power tubes belonging to the same bridge arm as each power tube in the group of power tubes.

[0023] Optionally, the device further comprises:

[0024] The interference filtering module is configured to perform low-pass filtering on the pulse synchronization signal and the PWM pulse signal, respectively.

[0025] The pulse distribution module is specifically configured to, when detecting a target edge state of the low-pass filtered pulse synchronization signal, distribute the low-pass filtered PWM pulse signal to a target channel in the N channels.

[0026] Optionally, the target edge state is a rising edge, or the target edge state is a falling edge.

[0027] Optionally, the one PWM pulse signal is distributed to only one channel in the N channels at the same time.

[0028] A pulse distribution method comprises:

[0029] When a target edge state of a pulse synchronization signal is detected, a PWM pulse signal having the same phase and period as the pulse synchronization signal and being output at the same time is distributed to a target channel in N channels; different channels in the N channels correspond to different groups of power tubes connected to a load in a multiphase bridge; wherein N is greater than 1; the PWM pulse signal and the pulse synchronization signal are output by a PWM pulse signal sending source in response to an enable signal; when different times the target edge state of the pulse synchronization signal is detected, the PWM pulse signal is distributed to different channels in the N channels.

[0030] An inverse signal of the PWM pulse signal is obtained, the PWM pulse signal output by the target channel is transmitted to a group of power tubes corresponding to the target channel, and the inverse signal of the PWM pulse signal is transmitted to power tubes belonging to the same bridge arm as each power tube in the group of power tubes.

[0031] It can be known by the above scheme that the pulse distribution device and method provided by the application, the pulse distribution device comprises a pulse distribution module, which is used for distributing a PWM pulse signal with the same phase and period as a pulse synchronization signal and simultaneously output to a target channel in N channels when a target edge state of the pulse synchronization signal is detected; a direct-through prevention module is used for obtaining an inverse signal of the PWM pulse signal, and the PWM pulse signal output by the target channel is transmitted to a group of power tubes corresponding to the target channel, and the inverse signal of the PWM pulse signal is transmitted to the power tubes belonging to the same bridge arm as each power tube in the group of power tubes; different channels in the N channels correspond to different groups of power tubes in N groups of power tubes connected with the load in the multi-phase bridge; wherein, N is greater than 1; the PWM pulse signal and the pulse synchronization signal are output by a PWM pulse signal sending source in response to an enable signal. The application no longer outputs PWM pulse signals by each pin of the MCU, but only outputs a PWM pulse signal by the PWM pulse signal sending source, and the same PWM pulse signal is distributed to different groups of power tubes through the pulse synchronization signal, which improves the pulse synchronization of the PWM pulse signals received by different groups of power tubes, and further improves the reliability of PWM control. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description only constitute some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0033] Figure 1 An example diagram of a multi-phase bridge provided by the embodiment of the present application;

[0034] Figure 2 An example structural diagram of a pulse distribution device provided by the embodiment of the present application;

[0035] Figure 3 An example diagram of a pulse synchronization signal and a PWM pulse signal with the same phase and period provided by the embodiment of the present application;

[0036] Figure 4 An example structural diagram of a pulse distribution module provided by the embodiment of the present application;

[0037] Figure 5 Another example structural diagram of a pulse distribution module provided by the embodiment of the present application;

[0038] Figure 6 An example structural diagram of a channel configuration sub-module provided by the embodiment of the present application;

[0039] Figure 7 Another structural schematic view of the channel configuration sub-module provided by the embodiment of the present application is shown in FIG. 6.

[0040] Figure 8 Another structural schematic view of the anti-through module provided by the embodiment of the present application is shown in FIG. 7.

[0041] Figure 9 Another structural schematic view of the pulse distribution device provided by the embodiment of the present application is shown in FIG. 8.

[0042] Figure 10 A timing diagram for sequentially outputting PWM pulse signals to four groups of power tubes in a multi-phase bridge provided by the embodiment of the present application is shown in FIG. 9.

[0043] Figure 11 An implementation flowchart of the pulse distribution method provided by the embodiment of the present application is shown in FIG. 10.

[0044] Figure 12 A hardware structure block diagram of the electronic device provided by the embodiment of the present application is shown in FIG. 11.

[0045] The terms "first", "second", "third", "fourth" and the like in the description and claims, and above-described drawings, if any, are used for distinguishing between similar objects, and do not necessarily have to imply a described sequence or chronology. It is to be understood that data so described can be interchanged, under appropriate circumstances, so that the embodiments of the application described herein can be practiced in a variety of sequences and / or combinations. DETAILED DESCRIPTION

[0046] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort belong to the scope of protection of the present application.

[0047] Please refer to Figure 1 An example diagram of a multi-phase bridge (also referred to as an inverter bridge, an inverter, etc.) provided by the embodiment of the present application is shown in FIG. 1. In this example,

[0048] The power tubes in the same column constitute a bridge arm. Obviously, Figure 1The multi-phase bridge shown has 6 bridge arms, for the sake of description and distinction, the bridge arms are sequentially labeled as 1-6 from left to right, for example, power tube T11 and power tube T21 constitute the 1st bridge arm, wherein the power tube T11 is the upper tube of the 1st bridge arm, and the power tube T21 is the lower tube of the 1st bridge arm, for another example, the power tube T13 and the power tube T23 constitute the 3rd bridge arm, wherein the power tube T13 is the upper tube of the 3rd bridge arm, and the power tube T23 is the lower tube of the 3rd bridge arm, and so on, so that the upper tube and the lower tube of each bridge arm can be determined.

[0049] Based on Figure 1 When the load (such as a motor) needs to be controlled, the upper tube of one bridge arm and the lower tube of another bridge arm are in an open state at the same time, and the other power tubes are in an off state. For example, the power tube T11 and the power tube T24 are simultaneously turned on, and the other power tubes are in an off state, the power tube T12 and the power tube T25 are simultaneously turned on, and the other power tubes are in an off state, the power tube T13 and the power tube T26 are simultaneously turned on, and the other power tubes are in an off state.

[0050] Please refer to Figure 2 A structure example diagram of the pulse distribution device provided by the embodiment of the application can include: a pulse distribution module 201 and an anti-through module 202; wherein,

[0051] The pulse distribution module 201 is used for, when a target edge state of a pulse synchronization signal is detected, distributing a PWM pulse signal with the same phase and period as the pulse synchronization signal and simultaneously output to a target channel of N channels; different channels of the N channels correspond to different groups of power tubes of N groups of power tubes connected to the load in the multi-phase bridge; wherein N is an integer greater than 1; the PWM pulse signal and the pulse synchronization signal are output by a PWM pulse signal sending source in response to an enable signal; different times when a target edge state of a pulse synchronization signal is detected, the PWM pulse signal is distributed to different channels of N channels.

[0052] In the embodiment of the application, the PWM pulse signal sending source not only generates the PWM pulse signal, but also generates the pulse synchronization signal with the same phase and period as the PWM pulse signal, and the PWM pulse signal sending source simultaneously outputs the PWM pulse signal and the pulse synchronization signal. Among them, the PWM pulse signal only needs to generate one, and does not need to generate multiple PWM pulse signals.

[0053] In the embodiment of the present application, the PWM pulse signal sending source can output PWM pulse signals with various duty cycles, and the specific duty cycle of the PWM pulse signal output is determined according to the actual application scenario, which will not be described here. Whether the PWM pulse signal sending source outputs the PWM pulse signal and the pulse synchronization signal can be controlled by the upper computer, that is, the upper computer can send an enable signal to the PWM pulse signal sending source to trigger the PWM pulse signal sending source to output the PWM pulse signal and the pulse synchronization signal, and further, the upper computer can also send a stop signal to the PWM pulse signal sending source to trigger the PWM pulse signal sending source to stop outputting the PWM pulse signal and the pulse synchronization signal. The upper computer can send an enable signal or a stop signal to the PWM pulse signal sending source in response to user operation.

[0054] As shown in Figure 3 Fig. 1 is an example diagram of the pulse synchronization signal and the PWM pulse signal with the same phase and period provided by the embodiment of the present application, in which the duty cycle of the PWM pulse signal output by the PWM pulse signal sending source is variable. However, no matter how the PWM pulse signal changes, the PWM pulse signal and the pulse synchronization signal have the same phase and period, and are output at the same time. Of course, the duty cycle of the PWM pulse signal output by the PWM pulse signal sending source can also be constant. The duty cycle of the PWM pulse signal can be any duty cycle in the range of 0% to 100%.

[0055] Figure 3 In the embodiment of the present application, the duty cycle of the pulse synchronization signal is 50%, and in the present application, the duty cycle of the pulse synchronization signal can also be other values, which is not limited in the present application.

[0056] In the embodiment of the present application, N channels are configured in the pulse distribution module 201, and when the pulse distribution module 201 detects the target edge state of the pulse synchronization signal output by the PWM pulse signal sending source, a PWM pulse signal with the same phase and period as the pulse synchronization signal and output at the same time is distributed to one of the N channels (for the sake of description and distinction, it is recorded as a target channel). Wherein, the pulse distribution module 201 distributes the above-mentioned PWM pulse signal to different channels of the N channels when detecting the target edge state of the pulse synchronization signal different times. Wherein, different channels of the N channels correspond to different groups of power tubes in the N groups of power tubes connected to the load in the multi-phase bridge, that is, one channel of the N channels corresponds to one group of power tubes in the N groups of power tubes. Only the above-mentioned PWM pulse signal is distributed to one of the N channels at the same time.

[0057] Each of the N groups of power transistors includes the upper transistor of the first bridge arm and the lower transistor of the second bridge arm; the first bridge arm is different from the second bridge arm, the first bridge arm is connected to the first end of the load, and the second bridge arm is connected to the second end of the load; the first end and the second end of the load are both connected to at least two bridge arms, and different groups of power transistors include different power transistors.

[0058] by Figure 1 Taking the multiphase bridge shown as an example, there can be various methods for grouping power transistors. However, regardless of the grouping method, it must be ensured that in each group of power transistors, one power transistor belongs to the bridge arm connected to the first end of the load (for ease of description and distinction, it is referred to as the first bridge arm), and the other power transistor belongs to the bridge arm connected to the second end of the load (for ease of description and distinction, it is referred to as the second bridge arm). The first bridge arm and the second bridge arm are different.

[0059] For example, power transistors T11 and T24 can be grouped together, power transistors T12 and T25 can be grouped together, and power transistors T13 and T26 can be grouped together.

[0060] For example, power transistors T11 and T25 can be grouped together, power transistors T12 and T26 can be grouped together, and power transistors T13 and T24 can be grouped together.

[0061] For example, power transistors T11 and T26 can be grouped together, power transistors T12 and T25 can be grouped together, and power transistors T13 and T24 can be grouped together.

[0062] The above grouping method only describes the grouping of half of the power transistors (referred to as the first group of power transistors for ease of description and distinction). The other half of the power transistors (referred to as the first group of power transistors for ease of description and distinction) can also be grouped according to the same principle.

[0063] For example, power transistors T14 and T21 can be grouped together, power transistors T15 and T22 can be grouped together, and power transistors T16 and T23 can be grouped together.

[0064] For example, power transistors T15 and T21 can be grouped together, power transistors T16 and T22 can be grouped together, and power transistors T14 and T23 can be grouped together.

[0065] For example, power transistors T16 and T21 can be grouped together, power transistors T15 and T22 can be grouped together, and power transistors T14 and T23 can be grouped together.

[0066] The first part of the power tube is used for controlling the current from the first end of the load to the second end of the load, and the second part of the power tube is used for controlling the current from the second end of the load to the first end of the load. Based on this, when the load current needs to flow from the first end of the load to the second end of the load, only a part of the power tube of the multi-phase bridge can be controlled, and when the load current needs to flow from the second end of the load to the first end of the load, only the second part of the power tube of the multi-phase bridge can be controlled.

[0067] As an example, the target edge state described above can be a rising edge.

[0068] As an example, the target edge state described above can be a falling edge.

[0069] The anti-pass-through module 202 is used to obtain the inverse signal of the PWM pulse signal described above, and deliver the PWM pulse signal output by the target channel to a group of power tubes corresponding to the target channel, and deliver the inverse signal of the PWM pulse signal described above to the power tubes belonging to the same bridge arm as each power tube in the group of power tubes.

[0070] In the multi-phase bridge, the phenomenon that two power tubes in the same bridge arm are turned on at the same time is called pass-through, and pass-through can burn the power tubes that cause the pass-through phenomenon, so it is necessary to avoid the simultaneous conduction of two power tubes in the same bridge arm. Based on this, the anti-pass-through module 202 is provided in the present application, and the anti-pass-through module 202 obtains the inverse signal of the PWM pulse signal described above, and delivers the PWM pulse signal output by the target channel (that is, the PWM pulse signal described above) to a group of power tubes corresponding to the target channel, while delivering the inverse signal of the PWM pulse signal described above to the power tubes belonging to the same bridge arm as each power tube in the group of power tubes, so as to ensure that the multi-phase bridge does not have the problem of pass-through.

[0071] Also Figure 1 The multi-phase bridge shown in the figure is taken as an example, and three groups of power tubes are provided in this example. It is assumed that the power tubes T11 and T24 are the first group of power tubes, the power tubes T12 and T25 are the second group of power tubes, and the power tubes T13 and T26 are the third group of power tubes. Among them, the first group of power tubes corresponds to the first channel in the pulse distribution module 201, the second group of power tubes corresponds to the second channel in the pulse distribution module 201, and the third group of power tubes corresponds to the third channel in the pulse distribution module 201.

[0072] When the multi-phase bridge is used to control the load, the three groups of power tubes are turned on in turn. For example, when the edge state of the pulse synchronization signal appears the target edge state for the first time, the pulse distribution module 201 distributes the PWM pulse signal to the first channel, so that the anti-pass-through module 202 transmits the PWM pulse signal to the power tubes T11 and T24, and transmits the inverse signal of the PWM pulse signal to the power tubes T21 and T14, so that only the first group of power tubes is turned on, and the other power tubes are not turned on. When the edge state of the pulse synchronization signal appears the target edge state for the second time, the pulse distribution module 201 no longer distributes the PWM pulse signal to the first channel (i.e., no longer distributes the PWM pulse signal to the power tubes T11 and T24), but distributes the PWM pulse signal to the second channel, so that the anti-pass-through module 202 transmits the PWM pulse signal to the power tubes T12 and T25, and transmits the inverse signal of the PWM pulse signal to the power tubes T22 and T15, so that only the second group of power tubes is turned on, and the other power tubes are not turned on. When the edge state of the pulse synchronization signal appears the target edge state for the third time, the pulse distribution module 201 no longer distributes the PWM pulse signal to the second channel (i.e., no longer distributes the PWM pulse signal to the power tubes T12 and T25), but distributes the PWM pulse signal to the third channel, so that the anti-pass-through module 202 transmits the PWM pulse signal to the power tubes T13 and T26, and transmits the inverse signal of the PWM pulse signal to the power tubes T23 and T16, so that only the third group of power tubes is turned on, and the other power tubes are not turned on. When the edge state of the pulse synchronization signal appears the target edge state for the fourth time, the pulse distribution module 201 no longer distributes the PWM pulse signal to the third channel (i.e., no longer distributes the PWM pulse signal to the power tubes T13 and T26), but distributes the PWM pulse signal to the first channel, so that the anti-pass-through module 202 transmits the PWM pulse signal to the power tubes T11 and T24, and transmits the inverse signal of the PWM pulse signal to the power tubes T21 and T14, so that only the first group of power tubes is turned on, and the other power tubes are not turned on. In this way, the PWM pulse signal is transmitted until the PWM pulse signal source no longer outputs the PWM pulse signal.

[0073] Figure 2 In the figure, the PWM pulse signal x1 represents one PWM pulse signal, and the PWM pulse signal xN represents N PWM pulse signals. Since the pulse distribution module 201 selects only one channel at a time, the pulse distribution module 201 outputs the N PWM pulse signals in turn in time, rather than simultaneously. Similarly, the anti-pass-through module 202 also outputs the N PWM pulse signals in turn in time, rather than simultaneously.

[0074] The pulse distribution device provided by the embodiment of the present application no longer outputs PWM pulse signals through each pin of the MCU, but outputs only one PWM pulse signal through a PWM pulse signal sending source, and the same PWM pulse signal is distributed to different power tube groups through a pulse synchronization signal, so that the pulse synchronization of the PWM pulse signals received by different power tube groups is improved, and the reliability of PWM control is further improved.

[0075] In an optional embodiment, a structural diagram of the pulse distribution module 201 is shown in Figure 4 as shown, which can include:

[0076] The edge detection submodule 401 and the channel distribution submodule 402; wherein,

[0077] The edge detection submodule 401 is configured to detect a target edge state of the pulse synchronization signal.

[0078] The pulse distribution device of the present application can be realized through a field programmable gate array (FPGA). The pulse width resolution of the pulse synchronization signal of the FPGA is related to the working frequency of the FPGA, specifically, the pulse width resolution of the pulse synchronization signal of the FPGA is the reciprocal of the working frequency of the FPGA, therefore, the pulse width of the pulse synchronization signal can be set as an integer multiple of the reciprocal of the working frequency of the FPGA. For example, assuming that the working frequency of the FPGA is 50MHz, the pulse width of the pulse synchronization signal can be 20ns, or 40ns, or 60ns, etc. The FPGA can realize the recognition of the pulse width through counting, and the pulse width of the pulse synchronization signal is set as an integer multiple of the reciprocal of the working frequency of the FPGA, therefore, one period of the pulse synchronization signal is an integer multiple of the reciprocal of the working frequency of the FPGA, and thus, a new target edge state of the pulse synchronization signal can be detected every time a target edge state of the pulse synchronization signal is detected, and when the number of counts reaches a preset value (the ratio of one period of the pulse synchronization signal to the working frequency of the FPGA), it is considered that a new target edge state is detected.

[0079] The channel distribution submodule 402 is configured to turn on a target channel in N channels of the controllable switch according to a preset control sequence when the edge detection submodule 401 detects a target edge state of the pulse synchronization signal, so as to distribute the one PWM pulse signal to the target channel.

[0080] In the embodiment of the present application, the channel distribution submodule 402 is provided with a controllable switch, and the controllable switch has M selectable channels, and M is an integer greater than or equal to N. The controllable switch can be a single-pole multi-throw switch, and thus only one channel can be turned on at a time.

[0081] The moving end of the controllable switch is the input end, which is the input end of the PWM pulse signal. The multiple stationary ends of the controllable switch constitute multiple output ends. The control end of each group of power transistors in the multiphase bridge is connected to one stationary end of the controllable switch. Different groups of power transistors are connected to different stationary ends. When the moving end of the controllable switch is connected to any stationary end, a conductive channel is formed.

[0082] The control terminal of each group of power transistors is the control terminal of each power transistor in that group, such as... Figure 1 In the multiphase bridge shown, the control terminal of each power transistor is its gate.

[0083] Since the channels of the power transistor group and the controllable switch are in one-to-one correspondence, the order in which the PWM pulse signal is assigned to the channel corresponds to the order in which the PWM pulse signal is assigned to the power transistor group.

[0084] In an optional embodiment, another structural schematic diagram of the pulse distribution module 201 described above is shown below. Figure 5 As shown, it may also include:

[0085] The channel configuration submodule 501 is used to determine the available channels for the target number and the control sequence of the available channels for the target number in the controllable switch when the target number is obtained; the first channel belongs to the available channels for the target number.

[0086] The target number can be input by the user through operation of the pulse distribution module 201. In other words, the pulse distribution device provided in this application can be configured with different numbers of channels, so that the pulse distribution device can be applied to the control of multiphase bridges of various sizes (corresponding to different values ​​of N), thereby improving the applicability of the pulse distribution device.

[0087] In an optional embodiment, a schematic diagram of the structure of the channel configuration submodule 501 described above is shown below. Figure 6 As shown, it may include: a DIP switch 601 and a first configuration unit 602; wherein,

[0088] The first configuration unit 602 is used to determine the binary code by the state of each key of the DIP switch 601, and the decimal number corresponding to the binary code is the target number.

[0089] Each key of the DIP switch 601 can select between binary codes 0 and 1. Assuming the DIP switch 601 has K keys, it can select between K binary codes, supporting a maximum of 2... K The configuration of each channel. For example, assuming K=4, the binary code obtained through the DIP switch 601 is 0110, and the decimal number corresponding to the binary code 0110 is 6, then the target number can be determined to be 6.

[0090] The first configuration unit 602 can also be configured to determine a target number of available channels in the controllable switch and a control sequence of the target number of available channels.

[0091] The control sequence of the target number of available channels can be pre-set, for example, assuming that each channel in the controllable switch has a number, the selection is performed in descending order of the number, or the selection is performed in ascending order of the number, etc.

[0092] In an optional embodiment, another structural schematic diagram of the channel configuration sub-module 501 is shown in FIG. 7, which can include a field programmable gate array (FPGA) chip 701 and a second configuration unit 702. Figure 7

[0093] The second configuration unit 702 is configured to determine a binary code corresponding to a decimal number of the target number of available channels through a level of each target pin of the FPGA chip 701, and the level of the target pin is related to a position of a target resistor in an external circuit of the target pin.

[0094] As an example, each target pin of the FPGA chip 701 can be connected to two parallel lines, one of the two lines (referred to as a first line for ease of description and distinction) can make the target pin connected to a preset power supply (for example, a 3.3v power supply) through a 0 ohm resistor, and the other line (referred to as a second line for ease of description and distinction) can make the target pin grounded through a 0 ohm resistor. The resistors on the two lines are pluggable to the corresponding lines. When the 0 ohm resistor is connected to the first line of the target pin A and not connected to the second line of the target pin A, the FPGA chip 701 detects a binary code 1 of the target pin A, and when the 0 ohm resistor is connected to the second line of the target pin A and not connected to the first line of the target pin A, the FPGA chip 701 detects a binary code 0 of the target pin A. Assuming that the FPGA chip 701 includes K target pins, the K target pins can realize the selection of K-bit binary codes, and at most can support the configuration of 2 K K channels. Corresponding to the K target pins, K 0 ohm resistors can be configured, that is, a 0 ohm resistor is inserted into each target pin. The user can insert a 0 ohm resistor into each target pin according to the actual resistance to be selected, for example, assuming that the user wants to configure 4 channels, and the corresponding binary code is 0100, then a 0 ohm resistor needs to be connected to the second line at the target pin corresponding to the highest bit, a 0 ohm resistor needs to be connected to the first line at the target pin corresponding to the second highest bit, a 0 ohm resistor needs to be connected to the second line at the target pin corresponding to the third highest bit, and a 0 ohm resistor needs to be connected to the second line at the target pin corresponding to the lowest bit.

[0095] ​The second configuration unit 702 can also be configured to determine a target number of available channels in the controllable switch and a control sequence of the target number of available channels.

[0096] The control sequence of the target number of available channels can be preset, for example, assuming that each channel in the controllable switch has a number, the selection is performed in descending order of the number, or the selection is performed in ascending order of the number, etc.

[0097] In an optional embodiment, a structural diagram of the anti-through module 202 is shown in Figure 8 The anti-through module 202 can include a negation sub-module 801 and an output sub-module 802.

[0098] The negation sub-module 801 is configured to negate the PWM pulse signal to obtain an inverted signal of the PWM pulse signal.

[0099] As an example, the negation sub-module 801 can be implemented by an inverter.

[0100] The output sub-module 802 is configured to determine whether the inverted signal of the PWM pulse signal is high. If the determination result is no, the PWM pulse signal output by the target channel is transmitted to a group of power tubes corresponding to the target channel, and the inverted signal of the PWM pulse signal is transmitted to power tubes belonging to the same bridge arm as each power tube in the group of power tubes.

[0101] In order to further ensure that the power tubes belonging to the same bridge arm as the power tubes in the group of power tubes are in an off state, the present application first determines whether the inverted signal of the PWM pulse signal is high, and only in the case that the inverted signal of the PWM pulse signal is not high, the inverted signal of the PWM pulse signal is output to the power tubes belonging to the same bridge arm as each power tube in the group of power tubes, thereby ensuring that the power tubes belonging to the same bridge arm are not in an on state at the same time.

[0102] Further, if the inverted signal of the PWM pulse signal is high, the control end of the power tubes belonging to the same bridge arm as each power tube in the group of power tubes is forcibly changed to low, thereby avoiding the through problem.

[0103] In an optional embodiment, another structural diagram of the pulse distribution device provided by the present application is shown in Figure 9 The pulse distribution device can further include:

[0104] The interference filtering module 901 is configured to perform low-pass filtering on the pulse synchronization signal and the PWM pulse signal.

[0105] In order to avoid false pulses, glitches and other interference signals of the PWM pulse signal generated by the PWM pulse signal sending source and the pulse synchronization signal, the PWM pulse signal generated by the PWM pulse signal sending source and the pulse synchronization signal are subjected to low-pass filtering processing to filter out the false pulses and glitches and other interference signals, so as to avoid the interference signals from causing misoperation of channel distribution and prevent the interference signals from being transmitted to the next stage.

[0106] Correspondingly, the pulse distribution module 201 is specifically configured to distribute the low-pass filtered PWM pulse signal to a target channel in the N channels when detecting the target edge state of the low-pass filtered pulse synchronization signal.

[0107] As shown in Figure 10 , a timing diagram for sequentially outputting PWM pulse signals to four groups of power tubes in a multiphase bridge is provided.

[0108] Among them, "clock synchronization" and "PWM input" represent the pulse synchronization signal and the PWM pulse signal output by the PWM pulse signal sending source. "PWM output 1" is the PWM pulse signal distributed to the first group of power tubes in the four groups of power tubes, "PWM output 2" is the PWM pulse signal distributed to the second group of power tubes in the four groups of power tubes, "PWM output 3" is the PWM pulse signal distributed to the third group of power tubes in the four groups of power tubes, and "PWM output 4" is the PWM pulse signal distributed to the fourth group of power tubes in the four groups of power tubes.

[0109] Corresponding to the device embodiment, the embodiment of the application also provides a pulse distribution method. An implementation flowchart of the pulse distribution method provided by the embodiment of the application is shown in Figure 11 , which can include:

[0110] Step S1101: When a target edge state of a pulse synchronization signal is detected, a PWM pulse signal with the same phase and period as the pulse synchronization signal and output at the same time is distributed to a target channel in N channels; different channels in the N channels correspond to different groups of power tubes in N groups of power tubes connected to the load in a multiphase bridge; wherein N is greater than 1; the PWM pulse signal and the pulse synchronization signal are output by a PWM pulse signal sending source in response to an enable signal; when a target edge state of the pulse synchronization signal is detected at different times, the PWM pulse signal is distributed to different channels in the N channels;

[0111] Step S1102: Obtain an inverse signal of the PWM pulse signal, transmit the PWM pulse signal output by the target channel to a group of power tubes corresponding to the target channel, and transmit the inverse signal of the PWM pulse signal to power tubes belonging to the same bridge arm as each power tube in the group of power tubes.

[0112] The pulse distribution method provided by the embodiment of the present application no longer outputs PWM pulse signals from each pin of the MCU, but only outputs one PWM pulse signal, and the same PWM pulse signal is distributed to different power tube groups through a pulse synchronization signal, thereby improving the pulse synchronization of the PWM pulse signals received by different groups of power tubes, and further improving the reliability of PWM control.

[0113] In an optional embodiment, the pulse distribution method can further include target edge state detection on the pulse synchronization signal.

[0114] The implementation of the above-mentioned distribution of one PWM pulse signal with the same phase and period as the pulse synchronization signal and simultaneously output to a target channel in N channels can be as follows:

[0115] When the target edge state of the pulse synchronization signal is detected, the target channel in the N channels of the controllable switch is turned on according to the preset control sequence, so as to distribute the one PWM pulse signal to the target channel.

[0116] In an optional embodiment, the pulse distribution method can further include, when the target number is obtained, determining the target number of available channels in the controllable switch, and the control sequence of the target number of available channels.

[0117] The first channel belongs to the target number of available channels.

[0118] In an optional embodiment, the implementation of the above-mentioned obtaining of the target number includes determining a binary code through the state of each key of a DIP switch.

[0119] The decimal number corresponding to the binary code is the target number.

[0120] In an optional embodiment, the implementation of the above-mentioned obtaining of the target number includes determining a binary code through the level of each target pin of a field programmable gate array (FPGA) chip; and the level of the target pin is related to the position of a target resistor in the external circuit of the target pin.

[0121] The decimal number corresponding to the binary code is the target number.

[0122] In an optional embodiment, step S1102 can specifically include:

[0123] Inverting the one PWM pulse signal to obtain an inverted signal of the one PWM pulse signal.

[0124] determining whether the inverting signal of the PWM pulse signal is high; if the determination result is no, delivering the PWM pulse signal output by the target channel to a group of power tubes corresponding to the target channel, and delivering the inverting signal of the PWM pulse signal to power tubes belonging to the same bridge arm as each power tube in the group of power tubes.

[0125] In an optional embodiment, the pulse distribution method described above can further include:

[0126] respectively performing low-pass filtering processing on the pulse synchronization signal and the PWM pulse signal;

[0127] The above-mentioned distribution of the PWM pulse signal having the same phase and period as the pulse synchronization signal and being output at the same time to the target channel of the N channels when the target edge state of the pulse synchronization signal is detected includes:

[0128] The above-mentioned distribution of the PWM pulse signal having the same phase and period as the pulse synchronization signal and being output at the same time to the target channel of the N channels when the target edge state of the pulse synchronization signal is detected includes:

[0129] The pulse distribution device and method provided by the embodiments of the present application can be applied in electronic devices. Figure 12 A hardware structure block diagram of an electronic device is shown, referring to Figure 12 The hardware structure of the electronic device can include at least one processor 1, at least one communication interface 2, at least one memory 3 and at least one communication bus 4.

[0130] In the embodiments of the present application, the number of the processor 1, the communication interface 2, the memory 3 and the communication bus 4 is at least one, and the processor 1, the communication interface 2 and the memory 3 complete communication with each other through the communication bus 4.

[0131] The processor 1 can be a central processing unit CPU, or a specific integrated circuit ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the embodiments of the present application, etc.

[0132] The memory 3 can include a high-speed RAM memory, and can also include a non-volatile memory, etc., such as at least one disk memory.

[0133] The memory stores a program, and the processor can call the program stored in the memory, and the program is used for:

[0134] When a target edge state of a pulse synchronization signal is detected, a PWM pulse signal with the same phase and period as the pulse synchronization signal and output at the same time is assigned to a target channel of N channels; different channels of the N channels correspond to different groups of power tubes of N groups of power tubes connected to a load in a multiphase bridge; wherein N is greater than 1; the PWM pulse signal and the pulse synchronization signal are output by a PWM pulse signal sending source in response to an enable signal; when a target edge state of the pulse synchronization signal is detected at different times, the PWM pulse signal is assigned to different channels of the N channels.

[0135] An inverse signal of the PWM pulse signal is obtained, the PWM pulse signal output by the target channel is transmitted to a group of power tubes corresponding to the target channel, and the inverse signal of the PWM pulse signal is transmitted to power tubes belonging to the same bridge arm as each power tube in the group of power tubes.

[0136] Optionally, the refinement function and the expansion function of the program can refer to the description above.

[0137] The embodiment of the application further provides a storage medium which can store a program suitable for processor execution, and the program is used for:

[0138] When a target edge state of a pulse synchronization signal is detected, a PWM pulse signal with the same phase and period as the pulse synchronization signal and output at the same time is assigned to a target channel of N channels; different channels of the N channels correspond to different groups of power tubes of N groups of power tubes connected to a load in a multiphase bridge; wherein N is greater than 1; the PWM pulse signal and the pulse synchronization signal are output by a PWM pulse signal sending source in response to an enable signal; when a target edge state of the pulse synchronization signal is detected at different times, the PWM pulse signal is assigned to different channels of the N channels.

[0139] An inverse signal of the PWM pulse signal is obtained, the PWM pulse signal output by the target channel is transmitted to a group of power tubes corresponding to the target channel, and the inverse signal of the PWM pulse signal is transmitted to power tubes belonging to the same bridge arm as each power tube in the group of power tubes.

[0140] Optionally, the refinement function and the expansion function of the program can refer to the description above.

[0141] Those skilled in the art can understand that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0142] In several embodiments provided by the present application, it should be understood that the disclosed system (if any), device and method can be implemented in other ways. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interface, device or unit, and can be electrical, mechanical or other form.

[0143] The units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, i.e. they can be located in one place or distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0144] In addition, each functional unit in each embodiment of the present application can be integrated into a processing unit, or each unit can exist physically, or two or more units can be integrated into one unit.

[0145] It should be understood that the features of the embodiments of the present application, the various embodiments, the features can be combined with each other, and all can achieve the purpose of solving the above technical problems.

[0146] If the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application or the parts of the technical solutions that essentially contribute to the prior art can be embodied in the form of software products. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The foregoing storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk and various program code storage media.

[0147] The foregoing description of the disclosed embodiments enables a person skilled in the art to make or use the application. Modifications of these embodiments will occur to persons of skill in the art, and, while certain modifications are discussed, it is desired to be protected in accordance with the spirit and scope of the application. Therefore, the application is not limited to the specific embodiments shown and described, but only by the scope of the appended claims, unless otherwise specified.

Claims

1. A pulse distribution device, characterized in that, include: A pulse distribution module is used to distribute a PWM pulse signal with the same phase and period as the pulse synchronization signal, which is output simultaneously, to a target channel among N channels when a target edge state of the pulse synchronization signal is detected. Different channels among the N channels correspond to different groups of power transistors in N groups of power transistors connected to the load in a multiphase bridge. Each group of power transistors includes the upper transistor of the first bridge arm and the lower transistor of the second bridge arm. The first bridge arm is different from the second bridge arm; the first bridge arm is connected to the first end of the load, and the second bridge arm is connected to the second end of the load. Wherein, N is greater than 1. The PWM pulse signal and the pulse synchronization signal are output by a PWM pulse signal transmitter in response to an enable signal. The PWM pulse signal is distributed to different channels among the N channels when the target edge state of the pulse synchronization signal is detected at different times. The anti-shoot-through module is used to obtain the inverted signal of the PWM pulse signal, send the PWM pulse signal output by the target channel to a group of power transistors corresponding to the target channel, and send the inverted signal of the PWM pulse signal to the power transistors that belong to the same bridge arm as each power transistor in the group of power transistors. The pulse distribution module includes: An edge detection submodule is used to detect the target edge state of the pulse synchronization signal; The channel allocation submodule is used to turn on the target channel among the N channels of the controllable switch according to a preset control sequence when the edge detection submodule detects the target edge state of the pulse synchronization signal, so as to allocate the PWM pulse signal to the target channel, thereby realizing the allocation of the same PWM pulse signal to different power transistor groups by triggering the pulse synchronization signal. The pulse distribution module can be configured with different numbers of channels, making it suitable for controlling multiphase bridges of various sizes.

2. The apparatus according to claim 1, characterized in that, The pulse distribution module further includes: The channel configuration submodule is used to determine the number of available channels for the target number and the control sequence of the available channels for the target number in the controllable switch when the target number is obtained.

3. The apparatus according to claim 2, characterized in that, The channel configuration submodule includes: a DIP switch and a first configuration unit; wherein... The first configuration unit is used to determine the binary code by the state of each key of the DIP switch; The decimal number corresponding to the binary code is the target number.

4. The apparatus according to claim 2, characterized in that, The channel configuration submodule includes: a field-programmable gate array (FPGA) chip and a second configuration unit; wherein... The second configuration unit is used to determine the binary code by the level of each target pin of the field-programmable gate array chip; the level of the target pin is related to the position of the target resistor in the external circuit of the target pin; The decimal number corresponding to the binary code is the target number.

5. The apparatus according to claim 1, characterized in that, The anti-straight-through module includes: The inverting submodule is used to invert one of the PWM pulse signals to obtain the inverted signal of the PWM pulse signal. The output submodule is used to determine whether the inverted signal of the PWM pulse signal is high; if the determination result is no, the PWM pulse signal output by the target channel is sent to a group of power transistors corresponding to the target channel, and the inverted signal of the PWM pulse signal is sent to the power transistors belonging to the same bridge arm as each power transistor in the group of power transistors.

6. The apparatus according to claim 1, characterized in that, Also includes: An interference filtering module is used to perform low-pass filtering on the pulse synchronization signal and the PWM pulse signal respectively. The pulse distribution module is specifically used to distribute the low-pass filtered PWM pulse signal to the target channel among the N channels when the target edge state of the low-pass filtered pulse synchronization signal is detected.

7. The apparatus according to claim 1, characterized in that, The target edge state is either a rising edge or a falling edge.

8. The apparatus according to claim 1, characterized in that, At any given time, only one PWM pulse signal is allocated to one of the N channels.

9. A pulse distribution method, characterized in that, include: When the target edge state of the pulse synchronization signal is detected, a PWM pulse signal with the same phase and period as the pulse synchronization signal and output simultaneously is assigned to the target channel among the N channels; different channels among the N channels correspond to different groups of power transistors in the N groups of power transistors connected to the load in the multiphase bridge. Each group of power transistors includes the upper transistor of the first bridge arm and the lower transistor of the second bridge arm. The first bridge arm and the second bridge arm are different. The first bridge arm is connected to the first end of the load, and the second bridge arm is connected to the second end of the load; wherein, N is greater than 1; the PWM pulse signal and the pulse synchronization signal are output by the PWM pulse signal transmitter in response to the enable signal; when the target edge state of the pulse synchronization signal is detected for different times, the PWM pulse signal is assigned to different channels among the N channels; Obtain the inverted signal of the PWM pulse signal, send the PWM pulse signal output by the target channel to a group of power transistors corresponding to the target channel, and send the inverted signal of the PWM pulse signal to the power transistors that belong to the same bridge arm as each power transistor in the group of power transistors. When the target edge state of the pulse synchronization signal is detected, a PWM pulse signal with the same phase and period as the pulse synchronization signal and output simultaneously is assigned to the target channel among the N channels, including: The target edge state of the pulse synchronization signal is detected; when the target edge state of the pulse synchronization signal is detected, the target channel of the N channels of the controllable switch is turned on according to the preset control sequence, so as to allocate the PWM pulse signal to the target channel, thereby realizing the allocation of the same PWM pulse signal to different power transistor groups by triggering the pulse synchronization signal. The method also includes configuring different numbers of channels to suit the control of multiphase bridges of various sizes.

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