Display substrate and manufacturing method thereof, and display device

Abstract

A display substrate includes: a base substrate, a test signal access pin layer and a signal access pin layer. The base substrate includes a display area and a frame area located around the display area, the frame area includes: a signal access area located on one side of the display area and at least one test signal access area, the test signal access area is adjacent to the signal access area. The test signal access pin layer is located in at least one test signal access area. The signal access pin layer is located in the signal access area. The height difference between the surface of the test signal access pin layer away from the base substrate and the surface of the signal access pin layer away from the base substrate is greater than 0.

Description

Technical Field

[0001] This article relates to but is not limited to the field of display technology, and in particular to a display substrate and a preparation method thereof, and a display device. Background Art

[0002] With the continuous development of display technology, there are more and more types of display products, such as liquid crystal display (LCD), organic light-emitting diode (OLED) display, plasma display panel (PDP), field emission display (FED), etc. Summary of the invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] Embodiments of the present disclosure provide a display substrate and a method for manufacturing the same, and a display device.

[0005] On the one hand, an embodiment of the present disclosure provides a display substrate, comprising: a base substrate, a test signal access pin layer and a signal access pin layer. The base substrate comprises a display area and a frame area located around the display area, the frame area comprises: a signal access area located on one side of the display area and at least one test signal access area, the at least one test signal access area being adjacent to the signal access area. The test signal access pin layer is located in the at least one test signal access area. The signal access pin layer is located in the signal access area. The height difference between the surface of the test signal access pin layer away from the base substrate and the surface of the signal access pin layer away from the base substrate is greater than 0.

[0006] In some exemplary embodiments, the signal access pin layer includes: a plurality of signal access pins arranged side by side in parallel. The at least one test signal access area is located at least on one side of the arrangement direction of the plurality of signal access pins.

[0007] In some exemplary embodiments, the test signal access pin layer includes a plurality of test signal access pins, and the plurality of test signal access pins are arranged in parallel with the plurality of signal access pins.

[0008] In some exemplary embodiments, the display substrate further comprises: a first insulating layer, disposed in the at least one test signal access region, the first insulating layer being located on a side of the test signal access pin layer close to the base substrate. A projection of the first insulating layer on the base substrate includes a projection of the test signal access pin layer on the base substrate.

[0009] In some exemplary embodiments, the first insulating layer includes: a plurality of insulating portions isolated from each other, the plurality of insulating portions corresponding one-to-one to a plurality of test signal access pins of the test signal access pin layer, and projections of the insulating portions on the base substrate include projections of corresponding test signal access pins on the base substrate.

[0010] In some exemplary embodiments, the first insulating layer is an inorganic insulating layer.

[0011] In some exemplary embodiments, the display substrate further comprises: a second insulating layer, disposed in the test signal access region and the signal access region, the second insulating layer being located on a side of the test signal access pin layer and the signal access pin layer close to the base substrate. The thickness of the second insulating layer in the test signal access region is greater than the thickness in the signal access region.

[0012] In some exemplary embodiments, the second insulating layer is an inorganic insulating layer.

[0013] In some exemplary embodiments, the test signal access pin layer includes multiple stacked and interconnected test signal access pin sub-layers, and the signal access pin layer includes multiple stacked and interconnected signal access pin sub-layers; the multiple test signal access pin sub-layers and the multiple signal access pin sub-layers correspond one-to-one, and the test signal access pin sub-layer and the corresponding signal access pin sub-layer are the same layer structure.

[0014] In some exemplary embodiments, a thickness of the test signal access pin layer is greater than a thickness of the signal access pin layer.

[0015] In some exemplary embodiments, a height difference between a surface of the test signal access pin layer away from the substrate and a surface of the signal access pin layer away from the substrate is about 1500 angstroms to 4500 angstroms.

[0016] In some exemplary embodiments, the display area at least includes: a driving structure layer disposed on the base substrate. The driving structure layer includes: a semiconductor layer, a first gate metal layer, a second gate metal layer, and a source-drain metal layer sequentially disposed on the base substrate. The test signal access pin layer includes a first test signal access pin sublayer and a second test signal access pin sublayer stacked and interconnected, and the signal access pin layer includes a first signal access pin sublayer and a second signal access pin sublayer stacked and interconnected; the first test signal access pin sublayer, the first signal access pin sublayer and the first gate metal layer are the same layer structure; the second test signal access pin sublayer, the second signal access pin sublayer and the source-drain metal layer are the same layer structure.

[0017] On the other hand, an embodiment of the present disclosure provides a display device, comprising the display substrate as described above.

[0018] On the other hand, an embodiment of the present disclosure provides a method for preparing a display substrate, which is used to prepare the display substrate as described above, including: forming a test signal access pin layer in a test signal access area of ​​a base substrate, and forming a signal access pin layer in a signal access area; wherein the height difference between the surface of the test signal access pin layer away from the base substrate and the surface of the signal access pin layer away from the base substrate is greater than 0.

[0019] In some exemplary embodiments, the preparation method further comprises: before forming the test signal access pin layer, forming a first insulating layer in the test signal access area, wherein the projection of the first insulating layer on the base substrate includes the projection of the test signal access pin layer on the base substrate.

[0020] In some exemplary embodiments, the preparation method further comprises: before forming the test signal access pin layer and the signal access pin layer, forming a second insulating layer in the signal access area and the test signal access area, wherein the thickness of the second insulating layer in the test signal access area is greater than the thickness in the signal access area.

[0021] In some exemplary embodiments, a thickness of the test signal access pin layer is greater than a thickness of the signal access pin layer.

[0022] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure. The shape and size of one or more components in the accompanying drawings do not reflect the actual proportions and are only intended to illustrate the contents of the present disclosure.

[0024] Figure 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0025] Figure 2 is a schematic structural diagram of a driving unit according to at least one embodiment of the present disclosure;

[0026] Figure 3 A schematic diagram of a first border area of ​​at least one embodiment of the present disclosure;

[0027] Figure 4 It is a schematic diagram of a partial structure of a first frame area of ​​at least one embodiment of the present disclosure;

[0028] Figure 5 for Figure 3 A partial enlarged schematic diagram of the middle area Q;

[0029] Figure 6 for Figure 3 Schematic diagram of the local section along the AA direction and the BB direction;

[0030] Figure 7 for Figure 3 Another partial cross-sectional schematic diagram along the BB direction;

[0031] Figure 8 for Figure 3 Another partial cross-sectional schematic diagram along the BB direction;

[0032] Fig. 9 for Figure 3 Another partial cross-sectional schematic diagram along the BB direction;

[0033] Fig.10 for Figure 3 Another partial cross-sectional schematic diagram along the BB direction;

[0034] Fig.11 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0035] The embodiments of the present disclosure are described in detail below in conjunction with the accompanying drawings. The embodiments can be implemented in a plurality of different forms. A person skilled in the art can easily understand the fact that the method and content can be transformed into one or more forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily.

[0036] In the drawings, the size of one or more components, the thickness of a layer, or an area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to the size, and the shape and size of each component in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0037] The ordinal numbers such as "first", "second", and "third" in the present disclosure are provided to avoid confusion of constituent elements, rather than to limit the quantity. The "plurality" in the present disclosure means a quantity of two or more.

[0038] In the present disclosure, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing the present specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which the constituent elements are described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0039] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal connection of two elements. For ordinary technicians in this field, the meanings of the above terms in the present disclosure can be understood according to the circumstances. Among them, "electrical connection" includes the situation where constituent elements are connected together through an element with some electrical function. There is no special restriction on "elements with some electrical function" as long as they can transfer electrical signals between connected constituent elements. Examples of "elements with some electrical function" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with one or more functions.

[0040] In the present disclosure, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, a channel region refers to a region where current mainly flows.

[0041] In the present disclosure, in order to distinguish the two electrodes of the transistor other than the gate, one of the electrodes is called the first electrode and the other electrode is called the second electrode. The first electrode can be a source electrode or a drain electrode, and the second electrode can be a drain electrode or a source electrode. In addition, the gate of the transistor is called a control electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0042] In the present disclosure, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, a state where the angle is greater than -5° and less than 5° may be included. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, a state where the angle is greater than 85° and less than 95° may be included.

[0043] In the present disclosure, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film" in some cases. Similarly, "insulating film" may be replaced with "insulating layer" in some cases.

[0044] The term "about" in the present disclosure refers to a numerical value that is not strictly limited to allow for process and measurement errors.

[0045] During the preparation process of the display substrate, electronic testing (ET) is required to detect whether there are poor displays (for example, bright spots or dark spots) in order to filter out defective products. Taking the OLED display substrate as an example, after the OLED display substrate completes the backplane circuit production, luminescent material evaporation, and water-proof oxygen packaging process, the ET process is required to filter out defective products and prevent defective products from flowing into the back-end process, causing waste of back-end process materials. During the ET process, when the test device contacts the test signal access pin on the display substrate through the test probe, due to the proximity of the test signal access area and the signal access area, the test device may contact the signal access pin in the signal access area, thereby causing pressure or scratches on the signal access pin; or, when the test probe of the test device is not accurately aligned with the test signal access pin, the test probe will be offset to the signal access pin, causing pressure or scratches on the signal access pin, causing adjacent signal access pins to short-circuit, causing the display substrate to be abnormal during subsequent use, resulting in yield loss.

[0046] The embodiment of the present disclosure provides a display substrate, comprising: a base substrate, a test signal access pin layer and a signal access pin layer. The base substrate comprises a display area and a frame area located around the display area, the frame area comprises: a signal access area located on one side of the display area and at least one test signal access area, at least one test signal access area is adjacent to the signal access area. The test signal access pin layer is located in the test signal access area. The signal access pin layer is located in the signal access area. The height difference between the surface of the test signal access pin layer away from the base substrate and the surface of the signal access pin layer away from the base substrate is greater than 0.

[0047] In this embodiment, a certain height difference is formed between the test signal access pin layer and the signal access pin layer, so that the surface of the test signal access pin layer away from the substrate substrate and the surface of the signal access pin layer away from the substrate substrate are not in the same plane.

[0048] In the present disclosure, "height" refers to the vertical distance between two opposite surfaces. The height in the present disclosure can be based on the lower surface or the upper surface of the substrate. However, this embodiment is not limited to this.

[0049] The display substrate provided by the embodiment of the present disclosure forms a height difference between the test signal access pin layer and the signal access pin layer, so that when the ET process is performed, the test probe of the testing device only contacts the test signal access pin layer, thereby avoiding the test probe from crushing or scratching the signal access pin layer, thereby reducing the yield loss.

[0050] In some exemplary embodiments, the display substrate of this embodiment may be an organic light-emitting diode (OLED) display, a liquid crystal display (LCD), a plasma display panel (PDP), or a field emission display (FED). However, this embodiment does not limit the type of the display substrate.

[0051] In some exemplary embodiments, the height difference between the surface of the test signal access pin layer away from the base substrate and the surface of the signal access pin layer away from the base substrate is about 1500 angstroms to 4500 angstroms. However, this embodiment is not limited thereto.

[0052] In some exemplary embodiments, the signal access pin layer includes a plurality of signal access pins arranged side by side in parallel. At least one test signal access area is located on at least one side of the arrangement direction of the plurality of signal access pins. For example, the frame area includes two test signal access areas, and the two test signal access areas are located on opposite sides of the arrangement direction of the plurality of signal access pins. However, this embodiment is not limited to this.

[0053] In some exemplary embodiments, the test signal access pin layer includes a plurality of test signal access pins, and the plurality of test signal access pins are arranged in parallel with the plurality of signal access pins. In this example, the plurality of test signal access pins and the plurality of signal access pins extend in the same direction, and the arrangement direction of the plurality of test signal access pins is parallel to the arrangement direction of the plurality of signal access pins.

[0054] The pin (pad or pin) in the embodiment of the present disclosure refers to a structure in the display substrate for obtaining signals and introducing signals into the signal line. For example, the pin can be a sheet-shaped one or more metal layers arranged on the substrate. In some examples, the signal access pin is configured to be connected to a flexible printed circuit (FPC) or a driver chip (IC) by bonding (Bonding), so as to obtain signals from the flexible printed circuit or the driver chip. Among them, at least part of the signal access pin is configured to provide a data signal to the data line, that is, at least part of the signal access pin is configured to provide a data signal to the data line when the image is displayed to control the display content of the sub-pixel connected to the data line; at least part of the signal access pin is configured to provide a power signal to the power line; at least part of the signal access pin is configured to provide a clock signal. The test signal access pin is configured to contact the test probe of the test device to obtain a signal from the test probe.

[0055] In some exemplary embodiments, the display substrate of this embodiment further includes: a first insulating layer, which is arranged in at least one test signal access area. The first insulating layer is located on a side of the test signal access pin layer close to the base substrate. The projection of the first insulating layer on the base substrate includes the projection of the test signal access pin layer on the base substrate. In this exemplary embodiment, by arranging the first insulating layer in the test signal access area, a height difference is formed between the test signal access pin layer and the signal access pin layer.

[0056] In some exemplary embodiments, the first insulating layer includes: a plurality of insulating portions isolated from each other, and the plurality of insulating portions correspond one-to-one to a plurality of test signal access pins of the test signal access pin layer. The projection of the insulating portion on the substrate substrate includes the projection of the corresponding test signal access pin on the substrate substrate. In some examples, the projection of the insulating portion on the substrate substrate coincides with the projection of the corresponding test signal access pin on the substrate substrate, or the projection of the insulating portion on the substrate substrate covers the projection of the corresponding test signal access pin on the substrate substrate. However, this embodiment is not limited to this. In some examples, the first insulating layer may cover the entire test signal access area.

[0057] In some exemplary embodiments, the first insulating layer may be an inorganic insulating layer. However, this embodiment is not limited thereto. For example, the first insulating layer may be an organic insulating layer.

[0058] In some exemplary embodiments, the display substrate of this embodiment may include: a second insulating layer, which is arranged in the test signal access area and the signal access area. The second insulating layer is located on the side of the test signal access pin layer and the signal access pin layer close to the base substrate. The thickness of the second insulating layer in the test signal access area is greater than the thickness in the signal access area. In this exemplary embodiment, by setting the second insulating layer in the test signal access area and the signal access area to have different thicknesses, a height difference is formed between the test signal access pin layer and the signal access pin layer.

[0059] In the present disclosure, “thickness” refers to the vertical distance between the surface of the film layer far from the substrate and the surface close to the substrate.

[0060] In some exemplary embodiments, the second insulating layer is an inorganic insulating layer. In some examples, the second insulating layer and the interlayer insulating layer of the display region are in the same layer structure. However, this embodiment is not limited to this.

[0061] In some exemplary embodiments, the test signal access pin layer includes a plurality of test signal access pin sub-layers stacked and interconnected, and the signal access pin layer includes a plurality of signal access pin sub-layers stacked and interconnected. The plurality of test signal access pin sub-layers correspond one-to-one to the plurality of signal access pin sub-layers, and the test signal access pin sub-layer and the corresponding signal access pin sub-layer are of the same layer structure. The test signal access pin sub-layer and the corresponding signal access pin sub-layer can be made of the same material and prepared by the same patterning process. In some examples, the test signal access pin sub-layer includes a plurality of test signal access sub-pins, and the test signal access pin includes a plurality of test signal access sub-pins stacked and interconnected; the signal access pin sub-layer includes a plurality of signal access sub-pins, and the signal access pin includes a plurality of signal access sub-pins stacked and interconnected. However, this embodiment is not limited to this.

[0062] In some exemplary embodiments, the thickness of the test signal access pin layer is greater than the thickness of the signal access pin layer. In this exemplary embodiment, by setting the thickness of the test signal access pin layer and the signal access pin layer to be different, a height difference is formed between the test signal access pin layer and the signal access pin layer. For example, the thickness of a certain test signal access pin sublayer of the test signal access pin layer is greater than the thickness of the corresponding signal access pin sublayer, while the thickness of the remaining test signal access pin sublayers is the same as the thickness of the corresponding signal access pin sublayer. However, this embodiment is not limited to this.

[0063] In some exemplary embodiments, the display area at least includes: a driving structure layer disposed on a substrate. The driving structure layer includes: a semiconductor layer, a first gate metal layer, a second gate metal layer, and a source-drain metal layer sequentially disposed on the substrate. The test signal access pin layer includes a first test signal access pin sublayer and a second test signal access pin sublayer stacked and interconnected, and the signal access pin layer includes a first signal access pin sublayer and a second signal access pin sublayer stacked and interconnected. The first test signal access pin sublayer, the first signal access pin sublayer and the first gate metal layer are of the same layer structure. The second test signal access pin sublayer, the second signal access pin sublayer and the source-drain metal layer are of the same layer structure. However, this embodiment is not limited to this.

[0064] The display substrate of this embodiment is described below by means of some examples. In the following exemplary embodiments, the display substrate is an OLED display substrate.

[0065] Figure 1 FIG. 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. Figure 1As shown, the display substrate provided by this exemplary embodiment includes: a base substrate. The base substrate includes: a display area 100 and a frame area located around the display area 100. The frame area includes: a first frame area 200 located on one side of the display area 100, and a second frame area 300 located on the periphery of the display area 100 and away from the first frame area 200. The first frame area 200 and the second frame area 300 are connected and surround the display area 100. In some examples, the first frame area 200 is the lower frame of the base substrate, and the second frame area 300 includes the upper frame, left frame and right frame of the base substrate. However, this embodiment is not limited to this.

[0066] In some exemplary embodiments, the base substrate may have a generally rectangular shape. Figure 1 As shown, the substrate substrate may include a pair of long sides parallel to each other in a first direction DR1 and a pair of short sides parallel to each other in a second direction DR2. The first direction DR1 is perpendicular to the second direction DR2. However, the present embodiment does not limit the shape of the substrate substrate. In some examples, the substrate substrate may be a closed polygon including linear edges, a circle or ellipse including curved edges, or a semicircle or semi-ellipse including linear edges and curved edges. In some examples, when the substrate substrate has linear edges, at least some corners of the substrate substrate may be curves. When the substrate substrate has a rectangular shape, the portion where adjacent linear edges meet each other may be replaced by a curve with a predetermined curvature. The curvature may be set according to the position of the curve. For example, the curvature may be changed according to the position where the curve starts, the length of the curve, etc.

[0067] In some exemplary embodiments, Figure 1 As shown, the display area 100 at least includes a plurality of sub-pixels PX, a plurality of gate lines G, and a plurality of data lines D. The plurality of gate lines G extend along a first direction DR1, and the plurality of data lines D extend along a second direction DR2. The orthographic projections of the plurality of gate lines G and the plurality of data lines D on the substrate intersect to form a plurality of sub-pixel regions, and a sub-pixel PX is arranged in each sub-pixel region. The plurality of data lines D are electrically connected to the plurality of sub-pixels PX, and the plurality of data lines D are configured to provide data signals to the plurality of sub-pixels PX. The plurality of gate lines G are electrically connected to the plurality of sub-pixels PX, and the plurality of gate lines G are configured to provide gate control signals to the plurality of sub-pixels PX.

[0068] In some exemplary embodiments, a pixel unit may include three sub-pixels, and the three sub-pixels are respectively a red sub-pixel, a green sub-pixel, and a blue sub-pixel. However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, and the four sub-pixels are respectively a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel.

[0069] In some exemplary embodiments, the shape of the sub-pixel may be a rectangle, a rhombus, a pentagon, or a hexagon. When a pixel unit includes three sub-pixels, the three sub-pixels may be arranged in parallel horizontally, vertically, or in a triangle; when a pixel unit includes four sub-pixels, the four sub-pixels may be arranged in parallel horizontally, vertically, or in a square. However, this embodiment is not limited to this.

[0070] In some exemplary embodiments, the sub-pixel may include: a pixel driving circuit and a light-emitting element connected to the pixel driving circuit. The pixel driving circuit may include a plurality of transistors and at least one capacitor, for example, the pixel driving circuit may be a 7T1C (7 transistors and 1 capacitor) or 5T1C structure. The light-emitting element may include: a first electrode, a second electrode, and an organic layer located between the first electrode and the second electrode. The first electrode of the light-emitting element may be connected to the corresponding pixel driving circuit.

[0071] In some exemplary embodiments, a driving unit is disposed on the substrate, configured to provide data signals to the sub-pixels through data lines and provide gate control signals to the sub-pixels through gate lines. In some examples, the gate control signals include scan signals and emission signals.

[0072] Figure 2 FIG. 1 is a schematic diagram of the structure of a drive unit according to at least one embodiment of the present disclosure. In some exemplary embodiments, Figure 2 As shown, the driving unit includes: a timing controller 31, a data driver 32, a scan driver 33 and an emission driver 34. The sub-pixel array 35 located in the display area includes a plurality of sub-pixels PX arranged regularly. The scan driver 33 is configured to provide a scan signal to the sub-pixel along a scan line; the data driver 32 is configured to provide a data voltage to the sub-pixel along a data line; the emission driver 34 is configured to provide an emission signal to the sub-pixel along an emission line; the timing controller 31 is configured to control the scan driver 33, the emission driver 34 and the data driver 32.

[0073] In some exemplary embodiments, the timing controller 31 may provide the data driver 32 with a grayscale value and a control signal suitable for the specifications of the data driver 32; the timing controller 31 may provide the scan driver 33 with a clock signal, a scan start signal, etc. suitable for the specifications of the scan driver 33; the timing controller 31 may provide the emission driver 34 with a clock signal, an emission stop signal, etc. suitable for the specifications of the emission driver 34. The data driver 32 may generate a data voltage to be provided to the data lines D1 to Dn using the grayscale value and the control signal received from the timing controller 31. For example, the data driver 32 may sample the grayscale value using the clock signal, and apply the data voltage corresponding to the grayscale value to the data lines D1 to Dn in units of sub-pixel rows. The scan driver 33 may generate a scan signal to be provided to the scan lines S1 to Sm using the clock signal, the scan signal, etc. received from the timing controller 31. For example, the scan driver 33 may sequentially provide a scan signal having an on-level pulse to the scan lines. In some examples, the scan driver 33 may include a shift register, and the scan signal may be generated by sequentially transmitting the scan start signal provided in the form of an on-level pulse to the next stage circuit under the control of the clock signal. The emission driver 34 may generate an emission signal to be provided to the emission lines E1 to Eo by the clock signal, the emission stop signal, etc. received from the timing controller 31. For example, the emission driver 34 may sequentially provide an emission signal with an off-level pulse to the emission line. The emission driver 34 may include a shift register, and the emission signal may be generated by sequentially transmitting the emission stop signal provided in the form of an off-level pulse to the next stage circuit under the control of the clock signal. Wherein, n, m and o are all natural numbers.

[0074] In some exemplary embodiments, the scan driver and the emission driver may be directly disposed on the substrate substrate. For example, the scan driver and the emission driver may be disposed in the second border area 300. In some examples, the scan driver and the emission driver may be formed together with the sub-pixel in the process of forming the sub-pixel. However, the present embodiment does not limit the position or formation method of the scan driver and the emission driver. In some examples, the scan driver or the emission driver may be disposed on a separate chip or printed circuit board to be connected to a pad or pad formed on the substrate substrate.

[0075] In some exemplary embodiments, the data driver may be disposed on a separate chip or printed circuit board to be connected to the sub-pixel through a signal access pin on the substrate. For example, the data driver may be formed by a chip on glass, a chip on plastic, a chip on a film, etc., disposed in the first frame area 200 to be connected to the signal access pin on the substrate. The timing controller may be disposed separately from the data driver or integrally with the data driver. However, this embodiment is not limited to this. In some examples, the data driver may be disposed directly on the substrate.

[0076] In some exemplary embodiments, the second frame area 300 is further provided with a plurality of test units. The plurality of test units may be connected to a plurality of data lines and configured to provide data test signals to the sub-pixels of the display area through the data lines. For example, the plurality of test units may be arranged on a side of the display area away from the first frame area. The plurality of test units receive test signals from the test signal input area of ​​the first frame area through the test wiring. However, this embodiment is not limited to this. For example, the plurality of test units may be arranged in the first frame area and adjacent to the display area.

[0077] Figure 3 is a schematic diagram of a first border region of at least one embodiment of the present disclosure. In some exemplary embodiments, Figure 3 As shown, the first frame area 200 includes: a fan-out area 201 located on one side of the display area 100, a signal access area 202 located on the side of the fan-out area 201 away from the display area 100, and two test signal access areas (for example, a first test signal access area 203a and a second test signal access area 203b). The first test signal access area 203a and the second test signal access area 203b are both adjacent to the signal access area 202. A plurality of signal access pins arranged side by side and in parallel are arranged in the signal access area 202, and the plurality of signal access pins are arranged in sequence along the first direction DR1. The first test signal access area 203a and the second test signal input access 203b are located on opposite sides of the signal access area 202 along the first direction DR1. In this exemplary embodiment, by arranging the two test signal access areas on opposite sides of the signal access area along the first direction, the first frame area can be prevented from being too large, thereby realizing a narrow frame design. However, this embodiment does not limit the number and position of the test signal access areas. In some examples, the test signal access area can be located on the side of the signal access area away from the display area. In some examples, the first border area may include a test signal access area adjacent to the signal access area.

[0078] In some exemplary embodiments, Figure 3As shown, a first alignment mark 204a is provided between the first test signal access area 203a and the signal access area 202, and a second alignment mark 204b is provided on the side of the first test signal access area 203a away from the signal access area 202. A third alignment mark 204c is provided between the second test signal access area 203b and the signal access area 202, and a fourth alignment mark 204d is provided on the side of the second test signal access area 203b away from the signal access area 202. The first alignment mark 204a and the third alignment mark 204c are in a cross shape, the second alignment mark 204b is in a "┙" shape, and the fourth alignment mark 204d is in a "┕" shape. However, this embodiment is not limited to this. This exemplary embodiment helps to accurately align the test probe with the test signal access pin in the test signal access area during the ET process by providing alignment marks around the test signal access area. In some exemplary embodiments, the first to fourth alignment marks may be in the same layer structure as the first gate metal layer of the display area. However, this embodiment is not limited to this.

[0079] In some exemplary embodiments, the fan-out region 201 is provided with a plurality of signal fan-out lines and a plurality of power lines. The plurality of signal fan-out lines include a plurality of data fan-out lines, and the plurality of data fan-out lines are configured to be connected to the plurality of data lines of the display region 100 in a fan-out routing manner, for example, one-to-one. The plurality of power lines include a first power line and a second power line. The first power line is configured to connect a high voltage power line (VDD) of the display region 100. The second power line is configured to connect a low voltage power line (VSS) provided in the first frame region. In some examples, the first power line and the second power line are provided in the same layer, and the first power line and the second power line are provided in different layers with the plurality of data fan-out lines; the orthographic projections of the plurality of data fan-out lines on the substrate substrate overlap with the orthographic projections of the first power line on the substrate substrate, and the orthographic projections of the plurality of data fan-out lines on the substrate substrate overlap with the orthographic projections of the second power line on the substrate substrate. In some examples, the plurality of data fan-out lines are arranged sequentially along the first direction DR1. The plurality of data fan-out lines may be numbered in an arrangement order, and the odd-numbered data fan-out lines and the even-numbered data fan-out lines may be arranged alternately in sequence along the first direction DR1. The odd-numbered data fan-out lines and the even-numbered data fan-out lines may be arranged in different layers. For example, the odd-numbered data fan-out lines and the first gate metal layer of the display area are in the same layer structure, and the even-numbered data fan-out lines and the second gate metal layer of the display area are in the same layer structure. However, this embodiment is not limited to this. For example, the plurality of data fan-out lines may be arranged in the same layer.

[0080] Figure 4 FIG. 1 is a schematic diagram of a partial structure of the first border region of at least one embodiment of the present disclosure. In some exemplary embodiments, Figure 4As shown, the signal access area 202 includes a plurality of signal access pins 221 arranged in sequence along the first direction DR1. The plurality of signal access pins 221 are configured to be bound and connected with the flexible circuit board or the driver chip, so as to obtain the signal from the flexible circuit board or the driver chip. The plurality of signal access pins may include: a plurality of first signal access pins and a plurality of second signal access pins. The first signal access pin may be connected to the power line 301 of the fan-out area, at least part of the second signal access pin may be connected to the signal fan-out line 302 of the fan-out area, and at least part of the second signal access pin may be connected to the test unit and the scan driver of the second frame area through the signal routing 303. In some examples, in the first direction DR1, the plurality of first signal access pins may be located on opposite sides of the plurality of second signal access pins. The first signal access pin may be adjacent to the test signal access area. In some examples, the length of the first signal access pin along the first direction DR1 may be greater than the length of the second signal access pin along the first direction DR1, and the length of the first signal access pin and the second signal access pin along the second direction DR2 may be the same. In this example, the size of the first signal access pin is greater than the size of the second signal access pin. For example, the length of each second signal access pin along the first direction is about 14 micrometers (μm), the length of each first signal access pin along the first direction is about 90 μm, and the spacing between adjacent signal access pins is about 13 μm. However, this embodiment is not limited to this.

[0081] In some exemplary embodiments, Figure 4 As shown, the first test signal access area 203a is provided with a plurality of test signal access pins 231 arranged in sequence along the first direction DR1. The plurality of test signal access pins 231 are arranged in parallel with the plurality of signal access pins 221 of the signal access area 202. The plurality of test signal access pins 231 are configured to contact the test probe of the test device (e.g., a flexible circuit board) during the ET process, thereby obtaining a signal from the test probe. In some examples, the test signal access pin of the first test signal access area 203a can be connected to the test unit and the scan driver in the second frame area through the first test trace 401, and is configured to provide a test signal to the test unit and the scan driver. However, this embodiment is not limited to this.

[0082] In some exemplary embodiments, Figure 4As shown, the lengths of the plurality of test signal access pins 231 along the first direction DR1 may be the same, and the lengths of the plurality of test signal access pins 231 along the second direction DR2 may be the same. For example, the length of each test signal access pin 231 along the first direction DR1 is about 90 μm, and the spacing between adjacent test signal access pins 231 is about 62 μm. In this exemplary embodiment, the sizes of the plurality of test signal access pins may be the same. However, this embodiment is not limited thereto.

[0083] In some exemplary embodiments, Figure 3 As shown, the second test signal access area 203b is provided with a plurality of test signal access pins arranged in sequence along the first direction DR1. At least some of the test signal access pins of the second test signal access area 203b are connected to the test unit and the emission driver in the second frame area, and at least some of the test signal access pins can be connected to some of the signal access pins of the signal access area 202. The structure of the second test signal access area 203b is similar to that of the first test signal access area 203a, so it will not be repeated here.

[0084] In some exemplary embodiments, during the ET process, a power signal can be provided to the display substrate through a first signal access pin (i.e., a pin connected to a power line) in the signal access area. In this example, during the ET process, the first signal access pin in the signal access area can be used to provide a power signal. However, this embodiment is not limited to this. For example, at least some of the test signal access pins are connected to the power line.

[0085] Figure 5 for Figure 3 A partial enlarged schematic diagram of the middle area Q. Figure 6 for Figure 3 Schematic diagram of the local section along the AA and BB directions. Figure 6 In the display area 100, only a cross-sectional structure of a thin film transistor and a capacitor is illustrated, only three test signal access pins are illustrated in the first test signal access area 203a, and only six signal access pins are illustrated in the signal access area 202. However, this embodiment is not limited to this.

[0086] In some exemplary embodiments, Figure 6As shown, in a plane perpendicular to the base substrate, the display area 100 includes: a base substrate 10, a driving structure layer and a light-emitting element (not shown) sequentially arranged on the base substrate 10. The driving structure layer includes a pixel driving circuit connected to the light-emitting element. For example, the pixel driving circuit can be a 7T1C or 5T1C structure. The driving structure layer includes: a buffer layer 11, a semiconductor layer, a first gate insulating layer 12, a first gate metal layer, a second gate insulating layer 13, a second gate metal layer, a first interlayer insulating layer (ILD) 14 and a source-drain metal layer sequentially arranged on the base substrate 10. Among them, the semiconductor layer at least includes a first active layer of the first transistor 101, the first gate metal layer at least includes a first gate electrode of the first transistor 101 and a first capacitor electrode of the storage capacitor 102, the second gate metal layer at least includes a second capacitor electrode of the storage capacitor 102, and the source-drain metal layer at least includes a first source electrode and a first drain electrode of the first transistor 101.

[0087] In some exemplary embodiments, Figure 6 As shown, in a plane perpendicular to the base substrate, the signal access area 202 in the first frame area includes: a base substrate 10, a buffer layer 11, a first gate insulating layer 12, a first signal access pin sublayer, a second gate insulating layer 13, a first interlayer insulating layer 14, and a second signal access pin sublayer. The first signal access pin sublayer includes a plurality of first signal access sub-pins 2211 arranged along the first direction. The second signal access pin sublayer includes a plurality of second signal access sub-pins 2212 arranged along the first direction. The signal access pin 221 in the signal access area 202 includes a first signal access sub-pin 2211 and a second signal access sub-pin 2212 that are stacked and connected to each other. In some examples, the orthographic projection of the second signal access sub-pin 2212 on the base substrate 10 may coincide with the orthographic projection of the correspondingly connected first signal access sub-pin 2211 on the base substrate 10. In this example, the first signal access pin sublayer and the first gate metal layer of the display area 100 are in the same layer structure; the second signal access pin sublayer and the source and drain metal layer of the display area 100 are in the same layer structure. However, this embodiment is not limited to this.

[0088] In some exemplary embodiments, Figure 6As shown, in a plane perpendicular to the base substrate, the first test signal access area 203a in the first frame area includes: a base substrate 10, a buffer layer 11, a first gate insulating layer 12, a first test signal access pin sublayer, a second gate insulating layer 13, a first interlayer insulating layer 14, a second interlayer insulating layer 15, and a second test signal access pin sublayer. The second interlayer insulating layer 15 in this embodiment is the first insulating layer in the above embodiment. The first test signal access pin sublayer includes a plurality of first test signal access subpins 2311 arranged along the first direction. The second test signal access pin sublayer includes a plurality of second test signal access subpins 2312 arranged along the first direction. The test signal access pin 231 of the first test signal access area 203a includes a first test signal access subpin 2311 and a second test signal access subpin 2312 that are stacked and connected to each other. In some examples, the orthographic projection of the second test signal access subpin 2312 on the base substrate 10 may coincide with the orthographic projection of the correspondingly connected first test signal access subpin 2311 on the base substrate 10. In this example, the first test signal access pin sublayer and the first gate metal layer of the display area 100 are in the same layer structure; the second test signal access pin sublayer and the source and drain metal layer of the display area 100 are in the same layer structure. However, this embodiment is not limited to this.

[0089] In some exemplary embodiments, Figure 6 As shown, the first height h1 between the surface of the test signal access pin layer away from the substrate substrate 10 (for example, the upper surface of the second test signal access pin sublayer) and the substrate substrate 10 is greater than the second height h2 between the surface of the signal access pin layer away from the substrate substrate 10 (for example, the upper surface of the second signal access pin sublayer) and the substrate substrate 10. In this example, the first height h1 and the second height h2 are both based on the upper surface of the substrate substrate 10. However, this embodiment is not limited to this. For example, the first height and the second height can be based on the lower surface of the substrate substrate. In this example, there is a height difference between the test signal access pin layer and the signal access pin layer, and the upper surface of the test signal access pin layer is farther away from the substrate substrate than the upper surface of the signal access pin layer. By setting the height difference between the test signal access pin layer and the signal access pin layer, during the ET process, when the test probe of the test device contacts the test signal access pin, the test probe only contacts the test signal access pin, and can avoid contact with the signal access pin layer. Even if the test probe is shifted due to poor alignment, since the signal access pin layer is located relatively low, the test probe is suspended above the signal access pin layer and will not cause damage to the signal access pin layer. It can also avoid short circuits between the signal access pins, thereby improving the yield of the display substrate.

[0090] In some exemplary embodiments, the substrate 10 may be a rigid substrate, such as a glass substrate. However, this embodiment is not limited thereto. For example, the substrate may be a flexible substrate, such as one made of an insulating material such as a resin. In addition, the substrate may be a single-layer structure or a multi-layer structure. When the substrate is a multi-layer structure, inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride may be placed between multiple layers in a single layer or multiple layers.

[0091] In some exemplary embodiments, the buffer layer 11 covers the base substrate 10. The buffer layer 11 is an inorganic insulating layer made of an inorganic material. For example, the buffer layer may be any one or more inorganic materials of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer. In some examples, the buffer layer may be omitted according to the material and process conditions of the base substrate.

[0092] In some exemplary embodiments, the semiconductor layer is located on the buffer layer. The semiconductor layer can be doped and patterned to form a channel region, a source region, and a drain region of a transistor, or to form a trace. For example, the channel region can be a semiconductor pattern that is not doped with impurities. Impurities may include, for example, n-type impurities, p-type impurities, and other metal impurities. The semiconductor layer can be made of one or more materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, polythiophene, etc., that is, the embodiments of the present disclosure are applicable to transistors manufactured based on oxide technology, silicon technology, and organic technology.

[0093] In some exemplary embodiments, the first gate insulating layer 12 covers the channel region of the semiconductor layer and part of the source region and part of the drain region. The first gate insulating layer 12 is an inorganic insulating layer made of an inorganic material. The first gate insulating layer 12 may be made of any one or more inorganic materials of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer.

[0094] In some exemplary embodiments, the first gate metal layer includes at least: a first gate electrode of the first transistor 101 and a first capacitor electrode of the storage capacitor 102. The projection of the first gate electrode on the substrate 10 overlaps with the projection of the channel region on the substrate 10. The first gate metal layer may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or an alloy material of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure, or a multi-layer composite structure, such as Ti / Al / Ti.

[0095] In some exemplary embodiments, the second gate insulating layer 13 may cover the first gate metal layer. The second gate insulating layer 13 is an inorganic insulating layer made of an inorganic material. The second gate insulating layer 13 may be made of any one or more inorganic materials of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer.

[0096] In some exemplary embodiments, the second gate metal layer is located on the second gate insulating layer 13, and at least includes: a second capacitor electrode of the storage capacitor 102. The projection of the second capacitor electrode of the storage capacitor 102 on the substrate 10 overlaps with the projection of the first capacitor electrode on the substrate 10. The second gate metal layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single-layer structure, or a multi-layer composite structure, such as Ti / Al / Ti, etc.

[0097] In some exemplary embodiments, the storage capacitor 102 is composed of a first capacitor electrode and a second capacitor electrode, and the second gate insulating layer 13 is disposed between the first capacitor electrode and the second capacitor electrode. Figure 6 The capacitor shown in FIG. 1 is a two-layer electrode structure. However, this embodiment is not limited to this. In some examples, the storage capacitor can be constructed as a three-layer electrode structure using an active layer, or a three-layer electrode structure using an electrode in the same film layer as the source and drain metal layer, or an electrode structure having four or more layers.

[0098] In some exemplary embodiments, the first interlayer insulating layer 14 may cover the second gate metal layer. The first interlayer insulating layer 14 may be an inorganic insulating layer made of an inorganic material. The first interlayer insulating layer 14 may be any one or more inorganic materials of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer.

[0099] In some exemplary embodiments, the source-drain metal layer is located on the first interlayer insulating layer 14 and includes at least: a first source electrode and a first drain electrode of the first transistor 101. The first source electrode may contact the source region of the first active layer through a via formed in the first interlayer insulating layer 14, the second gate insulating layer 13, and the first gate insulating layer 12, and the first drain electrode may contact the drain region of the first active layer through a via formed in the first interlayer insulating layer 14, the second gate insulating layer 13, and the first gate insulating layer 12. The source-drain metal layer may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure, or a multi-layer composite structure, such as Ti / Al / Ti, etc.

[0100] In some exemplary embodiments, the light-emitting element may include: a first electrode, a second electrode, an organic layer and a pixel definition layer (PDL). In some examples, the first electrode may be an anode and the second electrode may be a cathode. The first electrode is connected to a pixel driving circuit. The first electrode may be made of any one or more of silver, magnesium, aluminum, nickel (Ni), chromium (Cr), or alloy materials of the above metals, or transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (IZTO); the first electrode may be a single-layer structure or a multi-layer composite structure, such as ITO / Ag / ITO. The second electrode may be made of any one or more of silver, magnesium, aluminum, nickel (Ni), chromium (Cr), or alloy materials of the above metals, or transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (IZTO). The second electrode may be made of an alloy of two metals (e.g., Ag and Mg). However, this embodiment is not limited to this. For example, when the first electrode is a cathode, the second electrode is an anode.

[0101] In some exemplary embodiments, the display substrate may be a top emission structure or a bottom emission structure. However, this embodiment is not limited thereto.

[0102] In some exemplary embodiments, a pixel definition layer defining a light emitting area of ​​each sub-pixel is disposed on a substrate base having a first electrode formed thereon. The pixel definition layer exposes an upper surface of the first electrode and protrudes from the substrate base along the circumference of the sub-pixel. An organic layer may be disposed in an area of ​​the sub-pixel exposed by the pixel definition layer. The pixel definition layer may be an organic insulating layer made of an organic material. The organic material may include an organic insulating material such as a polyacrylic compound, a polyimide compound, a fluorine compound (e.g., Teflon) or a benzocyclobutene compound.

[0103] In some exemplary embodiments, the organic layer may be set as a single layer, or include multiple layers with different functions. In some examples, the organic layer may include an emitting layer (EML), and one or more film layers including a hole injection layer (HIL), a hole transport layer (HTL), a hole blocking layer (HBL), an electron blocking layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Driven by the voltage of the anode and the cathode, the organic layer can emit light according to the grayscale required by the luminescent properties of the organic material. In some examples, the organic layer can be formed by screen printing, inkjet printing, laser induced thermal imaging (LITI), and the like.

[0104] In some exemplary embodiments, at least a portion of the organic layer may be integrally formed throughout the plurality of first electrodes, or may be individually provided to correspond to each of the plurality of first electrodes, respectively.

[0105] In some exemplary embodiments, the second electrode is disposed on the organic layer. For example, the second electrode may be disposed for each sub-pixel, or the second electrode may be disposed to cover a large portion of the display area and be shared by a plurality of sub-pixels. However, this embodiment is not limited thereto.

[0106] In some exemplary embodiments, the encapsulation layer may be disposed on the second electrode. The encapsulation layer may be configured as a single layer, or multiple layers. For example. The encapsulation layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked in sequence. The first encapsulation layer and the third encapsulation layer may be prepared using inorganic materials, and the second encapsulation layer may be prepared using organic materials. Compared with organic materials, moisture or oxygen penetrates less into inorganic materials, but inorganic materials are easily broken due to their smaller elasticity or flexibility. The encapsulation layer of the three-layer structure of inorganic / organic / inorganic stacking can prevent the propagation of cracks. The organic material may include an organic insulating material of a polyacrylic compound, a polyimide compound, a fluorine compound (such as Teflon) or a benzocyclobutene compound. The inorganic material may include an inorganic insulating material of polysiloxane, silicon nitride, silicon oxide, and silicon oxynitride. In some examples, the encapsulation layer may include a plurality of organic material layers and a plurality of inorganic material layers stacked alternately.

[0107] In some exemplary embodiments, Figure 5 and Figure 6 As shown, the second interlayer insulating layer 15 is arranged in the test signal access area, and the second interlayer insulating layer 15 is located on the side of the first interlayer insulating layer 14 away from the substrate 10. The second interlayer insulating layer 15 includes a plurality of insulating portions 150 isolated from each other, and the plurality of insulating portions 150 correspond to a plurality of second test signal access sub-pins 2312 one by one. Each insulating portion 150 is located between the corresponding second test signal access sub-pin 2312 and the first interlayer insulating layer 14. Figure 5 and Figure 6 As shown, the projection of each second test signal access sub-pin 2312 on the substrate 10 is located within the projection of the corresponding insulating portion 150 on the substrate 10. However, this embodiment is not limited to this. In some examples, adjacent insulating portions can be connected, and the height of the connection area of ​​the insulating portion is lower than the height of the insulating portion; or, at least some of the insulating portions in the plurality of insulating portions are connected to each other.

[0108] Refer to the following Figures 3 to 6 The structure of the display substrate of the present disclosure is explained by an example of the preparation process of the display substrate. The "composition process" mentioned in the present disclosure includes processes such as depositing a film layer, coating a photoresist, mask exposure, development, etching and stripping the photoresist. Deposition can be carried out by any one or more selected from sputtering, evaporation and chemical vapor deposition, coating can be carried out by any one or more selected from spraying and spin coating, and etching can be carried out by any one or more selected from dry etching and wet etching. "Thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a composition process during the entire production process, the "thin film" can also be called a "layer". When the "thin film" still requires a composition process during the entire production process, it is called a "thin film" before the composition process and a "layer" after the composition process. The "layer" after the composition process contains at least one "pattern".

[0109] In the present disclosure, "A and B are of the same layer structure" means that A and B are formed simultaneously by the same patterning process. "The same layer" does not always mean that the thickness of the layer or the height of the layer is the same in the cross-sectional view. "The orthographic projection of A includes the orthographic projection of B" means that the orthographic projection of B falls within the range of the orthographic projection of A, or the orthographic projection of A covers the orthographic projection of B.

[0110] In some exemplary embodiments, the process of preparing the display substrate of this embodiment may include the following steps (1) to (8).

[0111] (1) Provide a substrate.

[0112] In some exemplary embodiments, the base substrate 10 is a rigid substrate, such as a glass substrate. However, this embodiment is not limited to this. For example, the base substrate is a flexible substrate.

[0113] (2) Preparing a semiconductor layer pattern on a substrate.

[0114] In some exemplary embodiments, a first insulating film and a semiconductor film are sequentially deposited on the base substrate 10, and the semiconductor film is patterned by a patterning process to form a buffer layer 11 covering the entire base substrate 10, and a semiconductor layer pattern disposed on the buffer layer 11. Figure 6 As shown, a semiconductor layer pattern is formed in the display area 100, and includes at least a first active layer.

[0115] After this process, a buffer layer 11 is formed on the base substrate 10 of the first test signal access area 203 a , the second test signal access area 203 b and the signal access area 202 .

[0116] (3) Preparing a first gate metal layer pattern on the substrate.

[0117] In some exemplary embodiments, on the base substrate 10 forming the above structure, a second insulating film and a first metal film are sequentially deposited, and the first metal film is patterned by a patterning process to form a first gate insulating layer 12 covering the semiconductor layer pattern, and a first gate metal layer, a first test signal access pin sublayer, and a first signal access pin sublayer pattern disposed on the first gate insulating layer 12, such as Figure 6 As shown. The first gate metal layer pattern is formed in the display area 100, and at least includes a first gate electrode and a first capacitor electrode. The first test signal access pin sub-layer pattern is formed in the first test signal access area 203a and the second test signal access area 203b, and at least includes a plurality of first test signal access sub-pins 2311; the first signal access pin sub-layer pattern is formed in the signal access area 202, and at least includes a plurality of first signal access sub-pins 2211.

[0118] In some exemplary embodiments, the first to fourth alignment marks of the first frame region may be formed by the same patterning process as the first gate metal layer. However, this embodiment is not limited to this. For example, the first to fourth alignment marks may be in the same layer structure as the second gate metal layer.

[0119] (4) Preparing a second gate metal layer pattern on the base substrate.

[0120] In some exemplary embodiments, on the base substrate 10 forming the above structure, a third insulating film and a second metal film are sequentially deposited, and the second metal film is patterned by a patterning process to form a second gate insulating layer 13 covering the first gate metal layer, the first signal access pin sublayer, the first test signal access pin sublayer pattern and the first gate insulating layer 12, and a second gate metal layer pattern disposed on the second gate insulating layer 13. Figure 6 As shown, the second gate metal layer pattern is formed in the display area 100 and at least includes a second capacitor electrode.

[0121] After this process, a stacked buffer layer 11, a first gate insulation layer 12, a first test signal access pin sublayer and a second gate insulation layer 13 are formed on the substrate substrate 10 of the first test signal access area 203a and the second test signal access area 203b, and a stacked buffer layer 11, a first gate insulation layer 12, a first signal access pin sublayer and a second gate insulation layer 13 are formed on the substrate substrate 10 of the signal access area 202.

[0122] (5) Preparing a first interlayer insulating layer pattern on the substrate.

[0123] In some exemplary embodiments, a fourth insulating film is deposited on the base substrate 10 forming the above structure, and the fourth insulating film is patterned by a patterning process to form a second interlayer insulating layer 14 pattern covering the second gate metal layer pattern. Figure 6 As shown, at least a plurality of first via holes and a plurality of second via holes are provided on the first interlayer insulating layer 14, wherein the plurality of first via holes are located in the display area 100, exposing the surface of the first active layer, and the plurality of second via holes are located in the signal access area 202, exposing the surface of the first signal access pin sublayer.

[0124] After this process, a stacked buffer layer 11, a first gate insulation layer 12, a first test signal access pin sublayer, a second gate insulation layer 13 and a first interlayer insulation layer 14 are formed on the substrate substrate 10 of the first test signal access area 203a and the second test signal access area 203b; a stacked buffer layer 11, a first gate insulation layer 12, a first signal access pin sublayer, a second gate insulation layer 13 and a first interlayer insulation layer 14 are formed on the substrate substrate 10 of the signal access area 202.

[0125] (6) Prepare a second interlayer insulating layer pattern on the base substrate.

[0126] In some exemplary embodiments, a fifth insulating film is deposited on the base substrate 10 having the above structure, and the fifth insulating film is patterned by a patterning process to form a pattern of the second interlayer insulating layer 15. Figure 6 As shown, the second interlayer insulating layer 15 is formed in the first test signal access area 203a and the second test signal access area 203b. Figure 5 and Figure 6As shown, the second interlayer insulating layer 15 includes a plurality of insulating portions 150 isolated from each other. The plurality of insulating portions 150 are arranged in sequence along the first direction. A plurality of third vias are formed on the second interlayer insulating layer 15, exposing the surface of the first test signal access pin sublayer. In some examples, the orthographic projection of the second interlayer insulating layer 15 on the base substrate 10 may cover the orthographic projection of the first test signal access pin sublayer on the base substrate 10.

[0127] In some exemplary embodiments, the thickness of the second interlayer insulating layer 15 is about 1500 angstroms to 4500 angstroms. In this exemplary embodiment, by providing the second interlayer insulating layer, a height difference is formed between the test signal access pin layer and the signal access pin layer.

[0128] After this process, the film structure of the display area 100 and the signal access area 202 remains unchanged.

[0129] (7) Prepare a source-drain metal layer, a second signal access pin sublayer, and a second test signal access pin sublayer on the substrate.

[0130] In some exemplary embodiments, a third metal film is deposited on the base substrate 10 forming the above structure, and the third metal film is patterned by a patterning process to form a source-drain metal layer pattern on the first interlayer insulating layer 14 of the display area 100, a second signal access pin sublayer pattern is formed on the first interlayer insulating layer 14 of the signal access area 202, and a second test signal access pin sublayer pattern is formed on the second interlayer insulating layer 15 of the first test signal access area 203a and the second test signal access area 203b. Figure 6 As shown, the source-drain metal layer pattern is formed in the display area 100, and at least includes a first source electrode, a first drain electrode, and a plurality of data lines (not shown) patterns. The first source electrode and the first drain electrode are respectively connected to the source region and the drain region of the first active layer through the first via hole. The second signal access pin sublayer is formed in the signal access area 202, and at least includes a plurality of second signal access sub-pins 2212, and the plurality of second signal access sub-pins 2212 are arranged in sequence along the first direction. The second test signal access pin sublayer is formed in the first test signal access area 203a and the second test signal access area 203b, and at least includes a plurality of second test signal access sub-pins 2312, and the plurality of second test signal access sub-pins 2312 are arranged in sequence along the first direction. The second signal access sub-pin 2212 is connected to the corresponding first signal access sub-pin 2211 through the second via hole. The second test signal access sub-pin 2312 is connected to the corresponding first test signal access sub-pin 2311 through the third via hole.

[0131] like Figure 6As shown, the projection of each second test signal access sub-pin 2312 on the base substrate 10 is located within the projection of the corresponding insulating portion 150 on the base substrate 10, and the projection of the first test signal access sub-pin 2311 corresponding to the second test signal access sub-pin 2312 on the base substrate 10 is also located within the projection of the corresponding insulating portion 150 on the base substrate 10. However, this embodiment is not limited to this.

[0132] At this point, the driving structure layer of the display area 100 is prepared on the base substrate 10. Figure 6 In the driving structure layer of the display area 100 , the first active layer, the first gate electrode, the first source electrode and the first drain electrode constitute the first transistor 101 , and the first capacitor electrode and the second capacitor electrode constitute the storage capacitor 102 .

[0133] In some exemplary embodiments, the first to fifth insulating films are all made of inorganic materials, for example, any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer.

[0134] (8) A planarization layer, a light-emitting element and a packaging layer are sequentially prepared on the substrate.

[0135] In some exemplary embodiments, a flat film is coated on the base substrate 10 forming the aforementioned structure to form a flat layer, and a surface exposing the first drain electrode of the first transistor 101 is formed on the flat layer by a patterning process. Subsequently, a first conductive film is deposited, and the first conductive film is patterned by a patterning process to form a first electrode pattern. The first electrode is connected to the first drain electrode of the thin film transistor through a via on the flat layer. Subsequently, a pixel definition film is coated, and a pixel definition layer pattern is formed by masking, exposure, and development processes. The pixel definition layer is formed in the display area. A pixel opening is opened on the pixel definition layer in the display area, and the pixel definition film in the pixel opening is developed to expose the surface of the first electrode. Subsequently, an organic layer and a second electrode are sequentially formed on the base substrate forming the aforementioned pattern. For example, the organic layer includes a stacked hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer, which are formed in the pixel opening of the display area to realize the connection between the organic layer and the first electrode. Since the first electrode is connected to the first drain electrode of the first transistor, the light emission control of the organic layer is realized. A portion of the second electrode is formed on the organic layer.

[0136] In some exemplary embodiments, an encapsulation layer is formed on the substrate substrate on which the aforementioned pattern is formed. The encapsulation layer can be formed in the display area, and can adopt a laminated structure of inorganic material / organic material / inorganic material. The organic material layer is disposed between two inorganic material layers. After this patterning process, the film layer structure of the signal access area and the test signal access area does not change.

[0137] In some exemplary embodiments, the planar layer and the pixel definition layer may be made of organic materials such as polyimide, acryl or polyethylene terephthalate.

[0138] In the above preparation process, the preparation process of the test unit, the scan driver and the emission driver in the second frame area is similar to the preparation process of the driving structure layer in the display area, so it will not be repeated here.

[0139] The preparation process of this exemplary embodiment can be realized by using existing mature preparation equipment, and can be well compatible with existing preparation processes. The process is simple to realize, easy to implement, high in production efficiency, low in production cost, and high in yield rate.

[0140] The structure of the display substrate of this exemplary embodiment and its preparation process are merely an exemplary description. In some exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs. For example, a first source-drain metal layer and a second source-drain metal layer can be provided in the display area, the first source-drain metal layer can include a first source electrode and a first drain electrode of a first transistor, the second source-drain metal layer can include a connecting electrode between a light-emitting element and a first drain electrode, and the second signal access pin sublayer and the second test signal access pin sublayer can be the same layer structure as the second source-drain metal layer. For another example, the signal access pin layer can include three signal access pin sublayers stacked and interconnected, and the test signal access pin layer can include three test signal access pin sublayers stacked and interconnected. However, this embodiment is not limited to this.

[0141] In this exemplary embodiment, a first insulating layer is set in the test signal access area to form a height difference between the test signal access pin layer and the signal access pin layer. Therefore, when the ET process is performed, the test probe of the test device only contacts the test signal access pin layer, thereby preventing the test probe from crushing or scratching the signal access pin layer, thereby reducing yield loss.

[0142] The structure (or method) described in this embodiment mode can be combined with the structure (or method) described in other embodiment modes as appropriate.

[0143] Figure 7 for Figure 3 Another cross-sectional schematic diagram along the BB direction in FIG. In some exemplary embodiments, as Figure 7As shown, the second interlayer insulating layer 15 of the test signal access area (e.g., the first test signal access area 203a) includes a plurality of mutually isolated insulating portions 150. The plurality of insulating portions 150 correspond one-to-one to the plurality of test signal access pins 231. The projection of the insulating portion 150 on the base substrate 10 coincides with the projection of the corresponding test signal access pin 231 on the base substrate. In this example, the test signal access pin 231 includes two stacked and connected test signal access sub-pins, and the signal access pin 221 includes two stacked and connected signal access sub-pins.

[0144] The test signal access pin, signal access pin, display area and other structures of the first frame area in this exemplary embodiment are similar to the corresponding structures described in the previous embodiments, so they are not described again here.

[0145] The structure (or method) described in this embodiment mode can be combined with the structure (or method) described in other embodiment modes as appropriate.

[0146] Figure 8 for Figure 3 Another cross-sectional schematic diagram along the BB direction in FIG. In some exemplary embodiments, as Figure 8 As shown, the second interlayer insulating layer 15 can cover the first test signal access area 203a and the second test signal access area 203b. In areas other than the first test signal access area 203a and the second test signal access area 203b, the second interlayer insulating layer 15 is not provided. The projections of the plurality of test signal access pins 231 on the base substrate 10 are located within the projections of the second interlayer insulating layer 15 on the base substrate 10. In this example, the test signal access pin 231 includes two stacked and connected test signal access sub-pins, and the signal access pin 221 includes two stacked and connected signal access sub-pins.

[0147] The test signal access pin, signal access pin, display area and other structures of the first frame area in this exemplary embodiment are similar to the corresponding structures described in the previous embodiments, so they are not described again here.

[0148] The structure (or method) described in this embodiment mode can be combined with the structure (or method) described in other embodiment modes as appropriate.

[0149] Fig. 9 for Figure 3 Another cross-sectional schematic diagram along the BB direction in FIG. In some exemplary embodiments, as Fig. 9As shown, the test signal access pin 231 includes a first test signal access sub-pin and a second test signal access sub-pin that are stacked and connected, and the signal access pin 221 includes a first signal access sub-pin and a second signal access sub-pin that are stacked and connected. The second signal access sub-pin of the multiple signal access pins 221 of the signal access area 202 is located on the first interlayer insulating layer 14, and the second test signal access sub-pin of the multiple test signal access pins 231 of the test signal access area (for example, the first test signal access area 203a) is also located on the first interlayer insulating layer 14. The thickness of the first interlayer insulating layer 14 in the test signal access area is greater than the thickness in the signal access area 202. For example, in the preparation process of the first interlayer insulating layer, the thickness of the first interlayer insulating layer in the signal access area can be made smaller than the thickness in the test signal access area by digging grooves in the signal access area. The first interlayer insulating layer in this exemplary embodiment is the second insulating layer in the above embodiment.

[0150] In this exemplary embodiment, by setting the test signal access area and the first interlayer insulating layer in the signal access area to have different thicknesses, a height difference is formed between the test signal access pin layer and the signal access pin layer. As a result, when the ET process is performed, the test probe of the test device only contacts the test signal access pin layer, thereby preventing the test probe from crushing or scratching the signal access pin layer, thereby reducing yield loss.

[0151] The test signal access pin, signal access pin, display area and other structures of the first frame area in this exemplary embodiment are similar to the corresponding structures described in the previous embodiments, so they are not described again here.

[0152] The structure (or method) described in this embodiment mode can be combined with the structure (or method) described in other embodiment modes as appropriate.

[0153] Fig.10 for Figure 3 Another cross-sectional schematic diagram along the BB direction in FIG. In some exemplary embodiments, as Fig.10As shown, the test signal access pin includes a first test signal access sub-pin 2311 and a second test signal access sub-pin 2312 that are stacked and connected, and the signal access pin includes a first signal access sub-pin 2211 and a second signal access sub-pin 2212 that are stacked and connected. The thickness of the second test signal access sub-pin 2312 of the test signal access area (for example, the first test signal access area 203a) is greater than the thickness of the second signal access sub-pin 2212 of the signal access area 202. The thickness of the first test signal access sub-pin 2311 and the thickness of the first signal access sub-pin 2212 may be substantially the same. In some examples, after forming the second signal access pin sub-layer on the base substrate 10, the second test signal access pin sub-layer is formed, wherein the second signal access pin sub-layer can be prepared by the same patterning process as the source and drain metal layer of the display area, or the second test signal access pin sub-layer can be prepared by the same patterning process as the source and drain metal layer of the display area. In other examples, after forming the second test signal access pin sub-layer on the base substrate 10, the second signal access pin sub-layer is formed. However, this embodiment is not limited to this. In this exemplary embodiment, by setting the thickness of the second test signal access pin sublayer and the second signal access pin sublayer to be different, a height difference is formed between the test signal access pin layer and the signal access pin layer, so that when performing the ET process, the test probe of the test device only contacts the test signal access pin layer, avoiding the test probe from crushing or scratching the signal access pin layer, thereby reducing yield loss.

[0154] The test signal access pin, signal access pin, display area and other structures of the first frame area in this exemplary embodiment are similar to the corresponding structures described in the previous embodiments, so they are not described again here.

[0155] The structure (or method) described in this embodiment mode can be combined with the structure (or method) described in other embodiment modes as appropriate.

[0156] At least one embodiment of the present disclosure further provides a method for preparing a display substrate, which is used to prepare the display substrate of the above embodiment, comprising: forming a test signal access pin layer in a test signal access area of ​​a base substrate, and forming a signal access pin layer in a signal access area. The height difference between the surface of the test signal access pin layer away from the base substrate and the surface of the signal access pin layer away from the base substrate is greater than 0.

[0157] In some exemplary embodiments, the preparation method further includes: before forming the test signal access pin layer, forming a first insulating layer in the test signal access area. The projection of the first insulating layer on the substrate substrate includes the projection of the test signal access pin layer on the substrate substrate. For example, the test signal access pin layer includes a first test signal access pin sublayer and a second test signal access pin sublayer stacked together; after forming the first test signal access pin sublayer and before forming the second test signal access pin sublayer, a first insulating layer is formed in the test signal access area. However, this embodiment is not limited to this.

[0158] In some exemplary embodiments, the preparation method further includes: before forming the test signal access pin layer and the signal access pin layer, forming a second insulating layer in the signal access area and the test signal access area. The thickness of the second insulating layer in the test signal access area is greater than the thickness in the signal access area. For example, the test signal access pin layer includes a first test signal access pin sublayer and a second test signal access pin sublayer stacked, and the signal access pin layer includes a first signal access pin sublayer and a second signal access pin sublayer stacked; after forming the first test signal access pin sublayer and the first signal access pin sublayer, and before forming the second test signal access pin sublayer and the second signal access pin sublayer, a second insulating layer is formed in the signal access area and the test signal access area. However, this embodiment is not limited to this.

[0159] In some exemplary embodiments, the thickness of the test signal access pin layer is greater than the thickness of the signal access pin layer.

[0160] The preparation method of this exemplary embodiment can refer to the relevant description of the above embodiment, so it will not be repeated here.

[0161] Fig.11 FIG. 1 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Fig.11 As shown, this embodiment provides a display device 91, including: a display substrate 910. The display substrate 910 is the display substrate provided in the above embodiment. Among them, the display substrate 910 can be an OLED display substrate. The display device 91 can be: an OLED display device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, and any other product or component with a display function. However, this embodiment is not limited to this.

[0162] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures may refer to the general design. In the absence of conflict, the embodiments of this disclosure and the features in the embodiments may be combined with each other to obtain new embodiments.

[0163] Those skilled in the art should understand that the technical solutions of the present disclosure may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present disclosure, and all should be included in the scope of the claims of the present disclosure.

Claims

1. A display substrate, comprising: A substrate, comprising a display area and a frame area located around the display area, wherein the frame area comprises: a signal access area located on one side of the display area and at least one test signal access area, wherein the at least one test signal access area is adjacent to the signal access area; A test signal access pin layer, located in the at least one test signal access area; A signal access pin layer, located in the signal access area; The height difference between the surface of the test signal access pin layer away from the substrate and the surface of the signal access pin layer away from the substrate is greater than 0; The display substrate further includes: a first insulating layer or a second insulating layer; The first insulating layer is arranged in the at least one test signal access area, the first insulating layer is located on a side of the test signal access pin layer close to the base substrate, and the projection of the first insulating layer on the base substrate includes the projection of the test signal access pin layer on the base substrate; the test signal access pin layer includes a plurality of test signal access pins, the first insulating layer includes: a plurality of mutually isolated insulating parts, the plurality of insulating parts correspond one-to-one to the plurality of test signal access pins of the test signal access pin layer, and the projection of the insulating part on the base substrate includes the projection of the corresponding test signal access pin on the base substrate; The second insulating layer is arranged in the test signal access area and the signal access area. The second insulating layer is located on the side of the test signal access pin layer and the signal access pin layer close to the substrate. The thickness of the second insulating layer in the test signal access area is greater than the thickness in the signal access area.

2. The display substrate according to claim 1, wherein: The signal access pin layer comprises: a plurality of signal access pins arranged in parallel side by side; The at least one test signal access area is located at least on one side in the arrangement direction of the plurality of signal access pins.

3. The display substrate according to claim 2, wherein: The plurality of test signal access pins are arranged in parallel with the plurality of signal access pins.

4. The display substrate according to claim 1, wherein: The first insulating layer is an inorganic insulating layer.

5. The display substrate according to claim 1, wherein: The second insulating layer is an inorganic insulating layer.

6. The display substrate according to claim 1, wherein: The test signal access pin layer includes multiple stacked and interconnected test signal access pin sub-layers, and the signal access pin layer includes multiple stacked and interconnected signal access pin sub-layers; the multiple test signal access pin sub-layers and the multiple signal access pin sub-layers correspond one-to-one, and the test signal access pin sub-layer and the corresponding signal access pin sub-layer are the same layer structure.

7. The display substrate according to claim 1, wherein: The thickness of the test signal access pin layer is greater than the thickness of the signal access pin layer.

8. The display substrate according to claim 1, wherein: A height difference between a surface of the test signal access pin layer away from the substrate and a surface of the signal access pin layer away from the substrate is 1500 angstroms to 4500 angstroms.

9. The display substrate according to claim 1, wherein: The display area at least includes: a driving structure layer disposed on the base substrate; The driving structure layer comprises: a semiconductor layer, a first gate metal layer, a second gate metal layer and a source-drain metal layer which are sequentially arranged on the substrate; The test signal access pin layer includes a first test signal access pin sublayer and a second test signal access pin sublayer that are stacked and connected to each other, and the signal access pin layer includes a first signal access pin sublayer and a second signal access pin sublayer that are stacked and connected to each other; The first test signal access pin sublayer, the first signal access pin sublayer and the first gate metal layer are in the same layer structure; The second test signal access pin sublayer, the second signal access pin sublayer and the source / drain metal layer are in the same layer structure.

10. A display device comprising the display substrate according to any one of claims 1 to 9.

11. A method for preparing a display substrate, for preparing the display substrate according to any one of claims 1 to 9, the method comprising: Forming a first insulating layer in the test signal access area of ​​the substrate, or forming a second insulating layer in the test signal access area and the signal access area; A test signal access pin layer is formed in the test signal access area of ​​the base substrate, and a signal access pin layer is formed in the signal access area; wherein a height difference between a surface of the test signal access pin layer away from the base substrate and a surface of the signal access pin layer away from the base substrate is greater than 0; Wherein, the first insulating layer is located on a side of the test signal access pin layer close to the base substrate, and the projection of the first insulating layer on the base substrate includes the projection of the test signal access pin layer on the base substrate; the test signal access pin layer includes a plurality of test signal access pins, and the first insulating layer includes: a plurality of insulating parts isolated from each other, the plurality of insulating parts correspond one-to-one to the plurality of test signal access pins of the test signal access pin layer, and the projection of the insulating part on the base substrate includes the projection of the corresponding test signal access pin on the base substrate; The second insulating layer is located on a side of the test signal access pin layer and the signal access pin layer close to the base substrate, and the thickness of the second insulating layer in the test signal access area is greater than the thickness in the signal access area.

12. The preparation method according to claim 11, wherein The thickness of the test signal access pin layer is greater than the thickness of the signal access pin layer.

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