Calibration and testing methods, systems and devices for antenna arrays

Abstract

The present invention discloses a calibration and testing method, system and device for an antenna array surface, belonging to the technical field of digital array radars. The method includes obtaining a test instruction and generating a first control parameter based on the test instruction. The first control parameter includes a plurality of beam control words, and each beam control word includes a plurality of timing control words; based on the beam control words, calculating a second control parameter required by the digital array TR component; generating a TTL timing signal according to the timing control words based on an internal timer or a trigger signal of an external anechoic chamber; sending the second control parameter to the digital array TR component according to the TTL timing signal, so that the digital array TR component sends or receives radio frequency pulses to generate digital IQ data; collecting and storing the digital IQ data. The present invention adopts a two-layer timing soft architecture to realize flexible parameter configuration, greatly improve the universality of antenna testing, realize the calibration and lobe testing of a high-efficiency digital array antenna, and shorten the testing time and cost.

Description

Technical Field

[0001] The present invention relates to the technical field of digital array radar, and particularly relates to a calibration and testing method, system and device for an antenna array surface. Background Art

[0002] Ultra-low sidelobe antennas play a crucial role in airborne radar for combating clutter and interference. The emergence of digital arrays enables higher radar amplitude-phase control accuracy and lower antenna sidelobes compared to active analog phased arrays. For the development of ultra-low sidelobe antennas with sidelobes below -45 dB and other high-performance radar antennas, conventional outdoor far-field tests can no longer meet the testing requirements of ultra-low sidelobe antennas. In recent years, planar near-field anechoic chamber measurements have become an important means of modern antenna testing technology at home and abroad.

[0003] For radars or telemetry systems using digital array systems, most of them, after each power-on or after a long working time, due to the initial phase change of digital devices and the phase drift of microwave devices, the antenna sidelobe performance deteriorates or even the antenna cannot form a normal beam, so antenna calibration is required.

[0004] For airborne array antennas, due to their ultra-low sidelobes and the low elevation angle of the installation method, it is not suitable to use the calibration tower or calibration vehicle method for outdoor calibration. Generally, a combination of outdoor calibration in an anechoic chamber and internal calibration is used. The coupling network for internal calibration is integrally processed and installed with the antenna array surface, which has the advantages of good stability and high calibration accuracy. The radar antenna is calibrated internally and externally in a microwave anechoic chamber to obtain the calibration fixed coefficients of the array antenna. After going to the outfield, internal calibration is directly performed and then the final antenna calibration parameters can be obtained through backend software calculation. To ensure calibration accuracy and suppress the mutual coupling of antenna elements to form pits in some elements, internal calibration mostly uses the sequential calibration method for antennas row by row / column by column.

[0005] Airborne array antennas have the characteristics of many antenna elements and many frequency points, and due to the influence of conformal radomes, lobe tests in different directions are required to finely correct the beam pointing deviation, especially during large-angle scanning, so the test workload is extremely large. For systems using the Compact Peripheral Component Interconnect (CPCI) architecture in the past, due to communication delay and data storage bandwidth limitations, the test parallelism is extremely limited. Taking an array surface with 1000 elements and 50 frequency points as an example, during the microwave anechoic chamber test stage, internal and external calibration and lobe tests often take more than 1 month or even longer. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to improve the efficiency of calibration and lobe testing of digital array antennas.

[0007] The present invention solves the above technical problems through the following technical means:

[0008] The present invention provides a calibration and testing method for an antenna array surface, and the method includes:

[0009] Obtaining a test instruction and generating a first control parameter based on the test instruction, where the first control parameter includes a plurality of beam control words, and each beam control word includes a plurality of timing control words;

[0010] Based on the beam control word, calculating a second control parameter required by the digital array TR component;

[0011] Based on an internal timer or a trigger signal of an external anechoic chamber, generating a TTL timing signal according to the timing control word;

[0012] According to the TTL timing signal, sending the second control parameter to the digital array TR component, so that the digital array TR component sends or receives radio frequency pulses to generate digital IQ data;

[0013] Collecting and storing the digital IQ data.

[0014] The present invention adopts a two-layer timing soft architecture, which can well be compatible with the main timing architecture of a general system, realizes flexible parameter configuration, greatly improves the universality of antenna testing, realizes high-efficiency calibration and lobe testing of a digital array antenna, and shortens the test time and cost.

[0015] Further, the information carried by the test instruction includes frequency point, polarization, test mode, and test row-column grid points;

[0016] The beam control word includes beam pointing, antenna element number, antenna row / column number, antenna polarization mode, frequency, and calibration power;

[0017] The timing control word includes timing mode, the number of two-layer TTLs, width, and repetition interval.

[0018] Further, the method further includes:

[0019] Responding to a control parameter request, and sending each beam control word one by one in a packet-by-packet sending manner.

[0020] In addition, the present invention also provides a calibration and testing system for an antenna array surface, and the system includes:

[0021] An obtaining module, configured to obtain a test instruction and generate a first control parameter based on the test instruction, where the first control parameter includes a plurality of beam control words, and each beam control word includes a plurality of timing control words;

[0022] A solution module, configured to calculate second control parameters required by a digital array TR component based on the beam control word;

[0023] A timing signal generation module, configured to generate a TTL timing signal according to the timing control word based on an internal timer or a trigger signal of an external darkroom;

[0024] An array surface control and test module, configured to send the second control parameters to the digital array TR component according to the TTL timing signal, so that the digital array TR component sends or receives radio frequency pulses to generate digital IQ data;

[0025] A data acquisition module, configured to acquire and store the digital IQ data.

[0026] Further, the beam control word includes a beam pointing direction, an antenna element number, an antenna row / column number, an antenna polarization mode, a frequency, and a calibration power;

[0027] The timing control word includes a timing mode, the number of two layers of TTLs, a width, and a repetition interval.

[0028] Further, the system further includes:

[0029] A response module, configured to respond to a control parameter request and send one beam control word each time in a packet-by-packet sending manner.

[0030] In addition, the present invention further provides a calibration and test device for an antenna array surface. The device includes: a beam scheduling computer, an optical interface board, a timing board, a digital beam control board, and a data storage unit; the beam scheduling computer is connected to the optical interface board through a PCIE interface for communication. The optical interface board converts the PCIE interface into a RapidIO interface and is connected to the timing board through a multimode optical fiber. The timing board is connected to the digital beam control board through a RapidIO interface. The timing board is connected to the data storage unit through an optical fiber, wherein:

[0031] The beam scheduling computer is configured to obtain a test instruction issued by a control terminal and generate first control parameters based on the test instruction and send the first control parameters to the timing board. The first control parameters include a plurality of beam control words, and each beam control word includes a plurality of timing control words;

[0032] The timing board forwards the beam control word to the digital beam control board and generates a TTL timing signal according to the timing control word based on an internal timer or a trigger signal of an external darkroom and sends the TTL timing signal to the digital beam control board;

[0033] Based on the beam control word, the digital beam control board calculates the second control parameters required by the digital array TR components, and sends the second control parameters to the digital array TR components according to the TTL timing signal, so that the digital array TR components send or receive radio frequency pulses to generate digital IQ data;

[0034] The digital beam control board collects the digital IQ data and forwards it to the data storage unit through the timing board.

[0035] Further, the digital beam control board includes a DSP chip and an FPGA chip, wherein:

[0036] The DSP chip is used to calculate the second control parameters required by the digital array TR components based on the beam control word and send them to the FPGA chip;

[0037] The FPGA chip is used to communicate with the digital array TR components and collect the digital IQ data.

[0038] Further, the beam control word includes beam pointing, antenna element number, antenna row / column number, antenna polarization mode, frequency, and calibration power;

[0039] The timing control word includes timing mode, the number of two layers of TTLs, width, and repetition interval.

[0040] Further, in response to the control parameter request sent by the timing board, the beam scheduling computer sends one beam control word each time in a packet-by-packet sending manner.

[0041] The advantages of the present invention are as follows:

[0042] (1) The present invention adopts the soft architecture of two-layer timing, which can be well compatible with the main timing architecture of general systems, realizes flexible parameter configuration, greatly improves the universality of antenna testing, realizes the calibration and lobe testing of high-efficiency digital array antennas, and shortens the testing time and cost.

[0043] (2) The transmission method of the present invention adopts high-speed transmission methods such as PCIE and RapidIO, reduces the transmission time of control parameters, and uses chips such as DSP and FPGA with timely response and fast calculation to realize real-time calculation and data up and down transmission. Data storage is realized through RapidIO fast transmission plus a large-capacity recorder, with large capacity and high bandwidth (fast speed). Therefore, the present invention adopts a control flow with low latency and fast response and a data storage method with large capacity and high bandwidth, which greatly improves the testing efficiency and is also conducive to being promoted to larger-scale systems.

[0044] (3) The present invention adopts a parametric design based on two - layer timing, with high communication and storage performance, good upgrade and scalability, and can be applied to digital array radar systems such as vehicle - mounted and space - borne systems. It is also applicable to antenna calibration and anechoic chamber lobe testing of digital array telemetry systems.

[0045] Additional aspects and advantages of the present invention will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present invention. Brief Description of the Drawings

[0046] Figure 1 is a schematic flow chart of the calibration and testing method for the antenna array surface in the first embodiment of the present invention;

[0047] Figure 2 is a schematic structural diagram of the calibration and testing system for the antenna array surface in the second embodiment of the present invention;

[0048] Figure 3 is a schematic structural diagram of the calibration and testing device for the antenna array surface in the third embodiment of the present invention;

[0049] Figure 4 is the lobe testing flow chart in the present invention;

[0050] Figure 5 is a schematic diagram of the internal antenna calibration timing in the present invention;

[0051] Figure 6 is a schematic diagram of the lobe testing timing in the present invention. Detailed Description of the Embodiments

[0052] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of them. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0053] As Figure 1 shown, the first embodiment of the present invention proposes a calibration and testing method for the antenna array surface, and the method includes the following steps:

[0054] S10. Obtain a test instruction and generate a first control parameter based on the test instruction. The first control parameter includes a number of beam control words, and each beam control word includes a number of timing control words;

[0055] S20. Based on the beam control word, calculate the second control parameter required for the digital array TR component;

[0056] S30. Generate a TTL timing signal according to the timing control word based on a trigger signal from an internal timer or an external darkroom.

[0057] Among them, the internal timer corresponds to two modes of internal calibration for transceiver; the external darkroom trigger corresponds to four modes of external calibration and beam test.

[0058] S40. Send the second control parameter to the digital array TR component according to the TTL timing signal, so that the digital array TR component transmits or receives radio frequency pulses to generate digital IQ data.

[0059] S50. Collect and store the digital IQ data.

[0060] The timing adopted in this embodiment is divided into two levels. For the convenience of description, it is denoted as the first-level control word BW and the second-level control word CPI. Each test consists of several BWs, and each BW consists of several CPIs. At the BW and CPI levels, the corresponding parameters are controlled respectively. For example: one BW contains dozens of CPIs. For example, there are 20 in the first-level BW and 50 CPIs in each BW, so there are a total of 20×50 = 1000 CPIs. Dividing into two levels is convenient for compressing the length of the control parameters to achieve fast transmission; and it is also convenient for improving the system response time.

[0061] It should be noted that the so-called two-level control words both refer to the beam control words. The timing control word has different contents from the beam control word, but the structures are the same and match; the timing control word: generates two description words for TTL; the beam control word: finally controls the parameters of the TR component.

[0062] This embodiment adopts this soft architecture of two-level timing, which can well be compatible with the main timing architecture of general systems, realize flexible parameter configuration, greatly improve the universality of antenna testing, realize the calibration and lobe testing of high-efficiency digital array antennas, and shorten the testing time and cost.

[0063] In one embodiment, the information carried by the test instruction includes frequency point, polarization, test mode, and the number of test row-column grid points.

[0064] In one embodiment, as shown in Table 1, the beam control word includes beam pointing, antenna element number, antenna row / column number, antenna polarization mode, frequency, and calibration power.

[0065] The timing control word includes timing mode, the number of two-level TTls, width, and repetition interval.

[0066] Table 1 Two-level control parameter table

[0067]

[0068]

[0069] It should be noted that for each change of the BW, the beam scheduling, DSP, and timing module are involved. Relatively speaking, there is more software implementation and the switching time is relatively slower; while the CPI is inside the digital beam control board, between the DSP chip and the FPGA chip, with fast switching. After comparison, the speed difference between the two is more than 5 times, even more than 10 times. Therefore, in order to achieve the highest overall efficiency and combined with the normal working mode of the radar, a two-layer beam control word structure is formed, which has high efficiency and good compatibility.

[0070] In one embodiment, the method further includes:

[0071] In response to a control parameter request, in a per-packet sending manner, each time one of the beam control words is sent.

[0072] It should be noted that in response to a control parameter request, in a per-packet sending manner, the control parameters of one BW (including several CPIs) are sent each time; after the sending is completed, the control parameters of the next BW are immediately calculated and generated.

[0073] In addition, as Figure 2 shown, a calibration and test system for an antenna array surface is proposed in the second embodiment of the present invention. The system includes:

[0074] An acquisition module 10, configured to acquire a test instruction and generate first control parameters based on the test instruction. The first control parameters include several beam control words, and each beam control word includes several timing control words;

[0075] A solution module 20, configured to solve the second control parameters required by the digital array TR component based on the beam control word;

[0076] A timing signal generation module 30, configured to generate a TTL timing signal based on an internal timer or a trigger signal of an external anechoic chamber according to the timing control word;

[0077] An array surface control and test module 40, configured to send the second control parameters to the digital array TR component according to the TTL timing signal, so that the digital array TR component sends or receives radio frequency pulses to generate digital IQ data;

[0078] A data acquisition module 50, configured to acquire and store the digital IQ data.

[0079] This embodiment adopts a two-layer timing soft architecture, which can well be compatible with the main timing architecture of a general system, realizes flexible parameter configuration, greatly improves the universality of antenna testing, realizes the calibration and lobe testing of a high-efficiency digital array antenna, and shortens the testing time and cost.

[0080] In one embodiment, the beam control word includes beam pointing, antenna element number, antenna row / column number, antenna polarization mode, frequency, and calibration power;

[0081] The timing control word includes timing mode, the number of two - layer TTLs, width, and repetition interval.

[0082] In one embodiment, the system further includes:

[0083] A response module, configured to respond to a control parameter request and send one of the beam control words each time in a packet - by - packet sending manner.

[0084] It should be noted that for other embodiments or implementation methods of the calibration and test system for the antenna array surface according to the present invention, reference can be made to the above - mentioned method embodiments, and details are not repeated here.

[0085] In addition, as Figure 3 shown, the third embodiment of the present invention proposes a calibration and test device for an antenna array surface. The device includes: a beam scheduling computer 1, an optical interface board 2, a timing board 4, a digital beam control board 3, and a data storage unit 5; the beam scheduling computer 1 is connected to the optical interface board 2 through a PCIE interface for communication. The optical interface board 2 converts the PCIE interface into a RapidIO interface and is connected to the timing board 4 through a multimode optical fiber. The timing board 4 is connected to the digital beam control board 3 through a RapidIO interface, and the timing board 4 is connected to the data storage unit 5 through an optical fiber, where:

[0086] The beam scheduling computer 1 is configured to obtain a test instruction sent by a control terminal 6 and generate first control parameters based on the test instruction and send them to the timing board 4. The first control parameters include a plurality of beam control words, and each beam control word contains a plurality of timing control words;

[0087] The timing board 4 forwards the beam control word to the digital beam control board 3 and generates a TTL timing signal based on the timing control word according to an internal timer or a trigger signal from an external anechoic chamber and sends it to the digital beam control board 3;

[0088] The digital beam control board 3 calculates second control parameters required for the digital array TR component based on the beam control word and sends the second control parameters to the digital array TR component according to the TTL timing signal, so that the digital array TR component sends or receives radio frequency pulses to generate digital IQ data;

[0089] The digital beam control board 3 collects the digital IQ data and forwards it to the data storage unit 5 through the timing board 4.

[0090] Among them, the beam scheduling computer 1 is used to complete the generation of beam control words and beam timing control.

[0091] The optical interface board 2 is used to assist the beam scheduling computer 1 to complete external RapidIO optical fiber communication.

[0092] The timing board 4, under the control of the beam scheduling computer 1, generates the TTL timing signals required by the system, and sends the test data to the storage board through the RapidIO interface.

[0093] The digital beam control board 3 completes the control of the active antenna array and the acquisition of test data.

[0094] The data storage unit 5 is used to complete the real-time storage of a large amount of high-speed test data.

[0095] Furthermore, when a board can complete more than two functions, they can be combined, such as the timing board 4 and the digital beam control board 3.

[0096] This embodiment adopts a two-layer timing soft architecture, which can well be compatible with the main timing architecture of general systems, realize flexible parameter configuration, greatly improve the generality of antenna testing, realize the calibration and lobe testing of high-efficiency digital array antennas, and shorten the testing time and cost.

[0097] In an embodiment, the digital beam control board 3 includes a DSP chip and an FPGA chip, where:

[0098] The DSP chip is used to calculate the second control parameters required by the digital array TR components based on the beam control words and send them to the FPGA chip;

[0099] The FPGA chip is used to communicate with the digital array TR components and collect the digital IQ data.

[0100] Furthermore, the architecture of the digital beam control board 3 can be in the form of 1×DSP + 2×FPGA, or 1 + 1, and this embodiment does not make specific limitations.

[0101] The digital beam control board 3 includes two types of chips, DSP and FPGA. The DSP is responsible for calculating the array control parameters, and the FPGA is responsible for fiber optic communication with the array TR components and data acquisition and packaging. The digital beam control board 3 operates under the provisions of the beam control word and the TTL timing signal. The timing board 4, after receiving the beam control word and the timing control word through the optical fiber, forwards the beam control word to the digital beam control board 3 through RapidIO, parses the timing control word, generates the TTL timing signal according to the protocol for the digital beam control board 3 to use, and after receiving the calibration and lobe test data returned by the digital beam control board 3 through RapidIO, sends the data to the data storage unit 5 through the optical fiber using the RapidIO protocol. Since the transmission method uses high-speed transmission methods such as PCIE and RapidIO, the transmission time of the control parameters is reduced, and chips such as DSP and FPGA with timely response and fast calculation are used to achieve real-time calculation and data upload and download. Data storage is achieved through rapid transmission of RapidIO plus a large-capacity recorder, with large capacity and high bandwidth (fast speed). Therefore, this embodiment adopts a control flow with low latency and fast response and a data storage method with large capacity and high bandwidth, greatly improving the test efficiency and also facilitating the promotion to larger-scale systems.

[0102] The reason why the architecture of this embodiment has universality lies in adopting a control flow with low latency and fast response and a data storage method with large capacity and high bandwidth, and adopting reasonable software and hardware program designs; the variable settings are in the software, and the invariable ones, such as timing and FPGA communication, are inherently highly universal. The beam control word and the timing control word are convenient for expansion and upgrade and are less restricted by hardware performance.

[0103] In one embodiment, the beam control word includes beam pointing, antenna element number, antenna row / column number, antenna polarization mode, frequency, and calibration power;

[0104] The timing control word includes timing mode, the number of two layers of TTLs, width, and repetition interval.

[0105] In one embodiment, the information carried by the test instruction includes frequency point, polarization, test mode, and the number of test row and column grid points.

[0106] It should be noted that the specific arrangement information of the array surface is pre-stored in the beam scheduling computer 1.

[0107] In one embodiment, the beam scheduling computer 1 responds to the control parameter request sent by the timing board 4 and sends each beam control word one by one in a packet-by-packet sending manner.

[0108] The architecture and communication method, through the 3.125 Gbps high speed of PCIE and RapidIO, achieve the time consumption of each link as shown in Table 2 below:

[0109] Table 2 Time Consumption of Each Link in the Architecture (1 BW Contains 50 CPIs)

[0110]

[0111] In this embodiment, by proposing a two - layer timing and test system architecture, adopting a general platform and high - speed communication methods such as general PCIE and RapidIO, the antenna calibration and anechoic chamber lobe test efficiency are greatly improved, and the test time is reduced to one - fraction or even one - fortieth of the serial test. Moreover, it can be applied to digital array radar systems such as vehicle - mounted and space - borne, and is also suitable for antenna calibration and anechoic chamber lobe test of digital array telemetry systems. The internal calibration timing diagram of the antenna and the lobe test timing diagram are respectively as Figure 5 and Figure 6 shown.

[0112] As Figure 4 shown, the lobe test process is as follows:

[0113] (1) At the control terminal (usually called the display and control), set the data storage unit, including data rate, header, etc.; select the mode on the control terminal, the number of probe scan rows and columns for anechoic chamber test, click start, and send the test instruction to the beam scheduling computer.

[0114] (2) After receiving the control terminal instruction, the beam scheduling computer forms beam and timing control parameters and sends them to the timing board. Among them, 1 BW packet of timing control parameters mainly includes the number of CPIs, CPI repetition interval, CPI trigger type, including internal and external triggers: internal timing, external anechoic chamber trigger.

[0115] (3) After receiving the control parameters, the timing board first sends the beam control parameters to the digital beam control board. After receiving the trigger signal from the internal timer or external anechoic chamber (usually using TTL signal, 1 probe scan grid point corresponds to 1 trigger signal), it generates timing signals according to the timing control parameters and sends them to the digital beam control board.

[0116] (4) After receiving the beam control word, the digital beam control board immediately resolves and forms the control parameters required for the specific array TR. When receiving the timing signal, it sends the control parameters to the digital array TR and the calibration channel.

[0117] Among them, the control parameters required for the array TR component obtained by settlement include frequency, bandwidth, pulse width, signal form, receive / transmit enable, etc.

[0118] (5) After receiving the control parameters from the digital beam control board, the digital array TR component and the calibration channel send or receive RF pulses (for receiving lobe test, the calibration channel emits pulse signals and the TR component receives; for transmitting lobe test, it is the opposite), and the measured digital IQ is sent to the digital beam control board.

[0119] (6) After the digital beam control board collects the digital IQ, it sends the timing board through the RapidIO within the extension unit.

[0120] (7) The timing board sends data to the data storage unit in real time through the optical fiber according to the RapidIO protocol.

[0121] When the probe completes all grid scans, perform mode switching and stop recording operation of the data storage unit on the control terminal.

[0122] (8) If continuing the test, repeat the above process.

[0123] It should be noted that the logic and / or steps represented in the flowchart or described in other ways herein, for example, can be considered as a defined sequence list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device), or used in combination with these instruction execution systems, apparatus, or devices. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transmit a program for use by or in combination with an instruction execution system, apparatus, or device. More specific examples (non-exhaustive list) of computer-readable media include the following: electrical connection parts with one or more wirings (electronic devices), portable computer disk cartridges (magnetic devices), random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber devices, and portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium can even be paper or other suitable media on which the program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other media, then editing, interpreting, or otherwise processing it as appropriate, and then storing it in a computer memory.

[0124] It should be understood that various parts of the present invention can be implemented by hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, any one or a combination of the following techniques well known in the art can be used: discrete logic circuits with logic gate circuits for implementing logical functions on data signals, application-specific integrated circuits with suitable combinational logic gate circuits, programmable gate arrays (PGA), field programmable gate arrays (FPGA), etc.

[0125] In the description of this specification, the descriptions referring to terms such as "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0126] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" can explicitly or implicitly include at least one of such features. In the description of the present invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise specifically and clearly defined.

[0127] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention.

Claims

1. A calibration and testing method for an antenna array surface, characterized in that The method includes: Obtaining a test instruction and generating a first control parameter based on the test instruction, where the first control parameter includes a data packet composed of several beam control fields, each beam control field includes several timing control words, and the timing control word includes a first-layer control word and a second-layer control word. The first-layer control words respectively control the beam pointing, antenna element number, antenna row / column number, and antenna polarization mode, and the second-layer control words respectively control the frequency point and calibration power; Based on the beam control word, calculating a second control parameter required by the digital array TR component; Based on the trigger signal of the internal timer or the external anechoic chamber, generating a TTL timing signal according to the timing control word; According to the TTL timing signal, sending the second control parameter to the digital array TR component, so that the digital array TR component sends or receives radio frequency pulses to generate digital IQ data; Collecting and storing the digital IQ data.

2. The calibration and testing method for an antenna array surface according to claim 1, wherein The information carried by the test instruction includes the frequency point, polarization, test mode, and test row-column grid points.

3. The calibration and testing method for an antenna array surface according to claim 1, characterized in that The method further includes: Responding to a control parameter request and sending each beam control word one by one in a packet-by-packet sending manner.

4. An antenna array-facing calibration and testing system, characterized in that, The system includes: An acquisition module, configured to obtain a test instruction and generate a first control parameter based on the test instruction, where the first control parameter includes a data packet composed of several beam control fields, each beam control field includes several timing control words, the first control parameter includes the first-layer control word and the second-layer control word that are both beam control words, the timing control word includes the first-layer control word and the second-layer control word, the first-layer control words respectively control the beam pointing, antenna element number, antenna row / column number, and antenna polarization mode, and the second-layer control words respectively control the frequency point and calibration power; A calculation module, configured to calculate a second control parameter required by the digital array TR component based on the beam control word; A timing signal generation module, configured to generate a TTL timing signal according to the timing control word based on the trigger signal of the internal timer or the external anechoic chamber; An array surface control and test module, configured to send the second control parameter to the digital array TR component according to the TTL timing signal, so that the digital array TR component sends or receives radio frequency pulses to generate digital IQ data; A data acquisition module, configured to collect and store the digital IQ data.

5. The calibration and testing system for an antenna array surface according to claim 4, wherein The system further includes: A response module, configured to respond to a control parameter request and send each beam control word one by one in a packet-by-packet sending manner.

6. An antenna array-facing calibration and testing device, characterized in that, The device includes: a beam scheduling computer, an optical interface board, a timing board, a digital beam control board, and a data storage unit; the beam scheduling computer is connected to the optical interface board through a PCIE interface for communication, the optical interface board converts the PCIE interface into a RapidIO interface and is connected to the timing board through a multimode optical fiber, the timing board is connected to the digital beam control board through a RapidIO interface, and the timing board is connected to the data storage unit through an optical fiber, where: The beam scheduling computer is used to obtain the test instructions sent by the control terminal, and generate first control parameters based on the test instructions and send them to the timing board. The first control parameters include a data packet composed of a number of beam control fields. Each beam control field contains a number of timing control words. The timing control word includes a first-layer control word and a second-layer control word. The first-layer control words respectively control the beam pointing, antenna element number, antenna row / column number, and antenna polarization mode. The second-layer control words respectively control the frequency point and calibration power; The timing board forwards the beam control word to the digital beam control board, and based on the internal timer or the trigger signal of the external darkroom, generates a TTL timing signal according to the timing control word and sends it to the digital beam control board; The digital beam control board calculates the second control parameters required by the digital array TR component based on the beam control word, and sends the second control parameters to the digital array TR component according to the TTL timing signal, so that the digital array TR component sends or receives radio frequency pulses and generates digital IQ data; The digital beam control board collects the digital IQ data and forwards it to the data storage unit through the timing board.

7. The calibration and testing device for an antenna array according to claim 6, wherein The digital beam control board includes a DSP chip and an FPGA chip, where: The DSP chip is used to calculate the second control parameters required by the digital array TR component based on the beam control word and send them to the FPGA chip; The FPGA chip is used to communicate with the digital array TR component and collect the digital IQ data.

8. The calibration and testing device for an antenna array surface according to claim 6, characterized in that, The beam scheduling computer responds to the control parameter request sent by the timing board and sends each beam control word one by one in a packet-by-packet sending manner.

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