Power electronic short-time over-stress test system and method based on working condition simulation

Abstract

The application discloses a power electronic short-time over-stress test system and method based on working condition simulation, which comprises a power hardware module, a to-be-tested converter, a simulation side converter, a power level restoration of a power semiconductor device in the to-be-tested converter, an electrical stress control module, a control of the to-be-tested converter and the simulation side converter, a restoration of electrical stress at an outlet of the to-be-tested converter, a thermal stress control module, a control of thermal stress of the to-be-tested power semiconductor device at different temperature nodes, a state detection module, a detection of temperature at each part node of the power semiconductor device in the to-be-tested converter under short-time over-stress working condition, a conduction voltage drop and thermal impedance, a reflection of a device health state, and an upper computer interaction module, which controls the above modules. Correspondingly, the application also provides a power electronic short-time over-stress test method using the above system. The application can automatically depict a safe operation domain for short-time over-stress working condition of the to-be-tested converter.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and more specifically, to a power electronics short-time overstress testing system and method based on operating condition simulation. Background Technology

[0002] With the emergence of concepts such as power interconnection and the Internet of Things, the conversion and application of electrical energy have become increasingly important. Since the advent of silicon controlled rectifier (SCR) technology, the power electronics technology it spurred has permeated every corner of the history of power development. In fields such as electric drives and photovoltaic energy storage grid connection, the reliability of power electronic devices in the drive system is directly related to the stable operation of the entire system. Taking photovoltaic energy storage grid connection as an example, when a voltage drop occurs in the grid, the photovoltaic energy storage inverter operates under low voltage ride-through conditions, requiring it to provide reactive current of 2 to 3 times its rated current for a short period to support the grid voltage. Under such short-term overstress conditions, accurately characterizing the safe operating domain of power semiconductor devices plays a crucial role in the reliable and safe operation of the overall system.

[0003] Traditional methods for testing short-time overstress failure and safe operating domain of power semiconductor devices are typically based on simple test circuits, such as dual-pulse test circuits or full-bridge test circuits. Applying a single cyclic electrothermal stress to the power semiconductor device, and conducting multiple parallel experiments under constant conduction time, constant power loss, and constant electrothermal stress, leads to conclusions after extensive data analysis.

[0004] A search revealed Chinese patent CN201610841604.8, which discloses a "Method for Intermittent Life Test of IGBT Based on Simulation Modeling and Short-Time Testing." This method uses controlled cyclic temperature rise amplitude and time to test the intermittent life of power semiconductor devices (IGBTs). The core idea of ​​this patent is to maintain stable power and current of the power semiconductor device within a short time, control the temperature rise amplitude and time under constant power loss, and combine simulation experiments with a large amount of multi-set experimental data to characterize the lifespan and safe operating range of the target device.

[0005] However, such patents have the following drawbacks:

[0006] 1. Failure mechanism analysis and safe operating domain characterization of power semiconductor devices under short-time overstress should be conducted under real-world operating conditions. In real-world conditions, power semiconductor devices are affected by complex electrothermal stress factors such as alternating voltage and current stress, and changes in ambient temperature. Methods that apply constant DC current, duty cycle, and external heat dissipation conditions to the target device completely ignore the electrothermal stress factors under real-world operating conditions, focusing only on temperature cycling, and are therefore one-sided and inaccurate.

[0007] 2. The temperature rise of power semiconductor devices is not only related to the operating time, but also to the electrothermal stress on the device, including the conduction current, conduction time and external temperature conditions. Such methods mainly focus on characterizing the failure mechanism and the relationship between the safe operating domain and the number of cycles and cycle time, ignoring the influence of other parameters under real operating conditions, and are therefore incomplete and inadequate.

[0008] Therefore, there is an urgent need in this field to develop a power electronics short-time overstress testing system and method based on operating condition simulation in order to overcome the above-mentioned technical problems. Summary of the Invention

[0009] In view of the deficiencies in the prior art, the purpose of this invention is to provide a power electronic short-time overstress testing system and method based on operating condition simulation.

[0010] One aspect of the present invention provides a power electronics short-time overstress testing system based on operating condition simulation, comprising:

[0011] The power hardware module adopts a dual-drive structure of the converter under test and the analog-side converter to restore the electrical stress of the power semiconductor devices in the converter under test at the power level.

[0012] An electrical stress control module, connected to the power hardware module, is used to generate control signals for the power semiconductor devices within the power hardware module, and to control the converter under test and the analog-side converter to restore the electrical stress at the outlet of the converter under test.

[0013] A thermal stress control module is connected to the power hardware module to simulate the thermal stress of the power semiconductor devices in the converter under test at different temperature nodes.

[0014] The status detection module is connected to the power hardware module to detect the temperature changes of various nodes of the power semiconductor device in the converter under short-term over-stress conditions, as well as the on-state voltage drop and thermal impedance of the power semiconductor device, reflecting the health status of the device.

[0015] The host computer interaction module controls the aforementioned power hardware module, electrical stress control module, thermal stress control module, and status detection module through human-computer interaction, thereby realizing the detection of electrical stress, thermal stress, and health status of power semiconductor devices.

[0016] Optionally, the power hardware module includes:

[0017] The converter to be tested;

[0018] Analog-side converter;

[0019] The output impedance network of the converter under test is connected at one end to the converter under test.

[0020] A simulated-side converter output impedance network, one end of which is connected to the simulated-side converter;

[0021] The other end of the output impedance network of the converter under test is connected to the other end of the output impedance network of the analog converter. The converter under test and the analog converter share a DC bus and a DC power supply module. Based on their respective output impedance networks, the converter under test and the analog converter simulate and reproduce the electrical characteristics under short-time over-stress conditions at the power level.

[0022] Optionally, the electrical stress control module includes:

[0023] The control system on the side of the converter under test generates control signals for the converter under test in order to control the converter under test.

[0024] The analog-side converter control system generates control signals for the analog-side converter to control the converter under test. The analog-side converter control system can adapt to the control system of the converter under test, and the adaptation includes control cycle and control parameters.

[0025] The analog-side converter control system adopts an electrical control structure based on direct impedance compensation. There is voltage modulation signal interaction between the control system of the converter under test and the control system of the analog-side converter, which is used to improve the steady-state and transient performance of the short-time over-stress electrothermal integrated working condition simulation test system.

[0026] Optionally, the thermal stress control module includes:

[0027] The heating element heats the radiator to reach the set temperature.

[0028] The cooling unit cools the radiator to achieve the set temperature.

[0029] The temperature control unit controls the temperature of the heating unit and the cooling unit, and performs closed-loop control of the thermal stress of the analog power semiconductor device at each node based on different temperature sampling locations.

[0030] Optionally, the state detection module includes:

[0031] The thermal stress temperature detection unit detects the temperature changes of various nodes in power semiconductor devices under short-term over-stress conditions.

[0032] The health status detection department detects the forward voltage drop of power semiconductor devices under short-term over-stress conditions to calculate the device conduction loss and reflect the device's health and / or aging status; it also detects the thermal resistance of power semiconductor devices after short-term over-stress conditions to reflect the device's health and / or aging status.

[0033] Optionally, the host computer interaction module performs programming input and monitoring of the short-time overstress condition of power electronics, including:

[0034] Electrical characteristic parameter monitoring interface, used to monitor key electrical characteristic parameters;

[0035] The thermal parameter monitoring interface is used to monitor the junction temperature, case temperature, and heat sink temperature of the power semiconductor devices in the converter under test.

[0036] The programming interface for inputting operating parameters is used to output operating parameters during the test.

[0037] The device health status monitoring interface is used to display the online test on-state voltage drop of the power semiconductors in the converter under test, as well as the thermal resistance of the power semiconductor devices in the converter under test.

[0038] The DC power supply module interface is used to output and display DC power supply parameters.

[0039] A second aspect of the present invention provides a power electronics short-time overstress testing method based on operating condition simulation. Using the aforementioned testing system, electrical and / or thermal stresses under actual short-time overstress conditions are applied to the power semiconductor devices within the converter under test. Specifically, this includes:

[0040] S11: Through the host computer interaction module, select and set the test condition type of the power semiconductor device in the converter to be tested. The test condition types include grid-connected photovoltaic energy storage inverter and motor drive condition.

[0041] S12: Based on the operating condition type set in S11, and according to the high-bandwidth operating condition simulation strategy, set the control system type of the converter under test, and set the control system type of the simulation-side converter.

[0042] S13: Based on the operating condition type set in S11, the type of control system on the converter side and the type of control system on the analog side set in S12, set the key operating condition parameters and key control parameters in the control system on the converter side and the control system on the analog side respectively.

[0043] S14: Based on the thermal stress control module, the thermal stress control object node and target temperature are set through the host computer interaction module, and the target node temperature is waited for to reach the set test temperature and reach thermal steady state.

[0044] S15: After the target power board conductor devices reach thermal steady state, the DC source in the DC power supply module is started through the host computer interaction module and connected to the positive and negative buses of the converter under test and the analog side converter, so that its output voltage value is the DC bus voltage under real working conditions.

[0045] S16: After reaching thermal steady state in S14 and stabilizing the target DC bus voltage in S15, the start command for the power semiconductor devices in the converter under test and the analog-side converter is issued, and the drive signal is sent out, and the system starts running.

[0046] Optionally, the high-bandwidth operating condition simulation strategy, wherein:

[0047] The control system on the converter under test side and the control system on the analog converter side are used to control the electrical characteristics of the converter under test and the analog converter side, mainly voltage and current, respectively.

[0048] Under the premise of matching the signal source port of the control system on the side of the converter under test, signal transmission is used to avoid additional bandwidth limitations. At the same time, the control object, control strategy and signal interaction type are selected according to the application range of short-time overstress conditions.

[0049] Optionally, the selection of the control object, control strategy, and signal interaction type based on the application range of the short-time overstress condition, wherein:

[0050] -For the inverter's grid-connected operating condition:

[0051] The control object of the converter under test is current, and the selected control strategy can be any one of the following: current control strategy, power control strategy, virtual synchronous machine strategy, and droop control strategy.

[0052] The control object of the analog-side converter is voltage, and the selected control strategy is either a single voltage loop voltage control strategy or a voltage control strategy with the outer voltage loop or the inner current loop as the main components.

[0053] The signal interaction type is one where the analog-side converter control system transmits grid-connected phase angle and grid-connected frequency signals to the converter control system under test.

[0054] -For the aforementioned motor drive conditions:

[0055] The controlled object of the converter under test is current, and the selected control strategy is any one of field-oriented control, direct torque control, current hysteresis control, and maximum torque-current ratio control.

[0056] The controlled object of the analog-side converter is current, and the control strategy is a current control strategy based on direct impedance compensation.

[0057] The signal interaction type is as follows: the analog-side converter control system transmits the motor rotor position and motor speed signals to the converter control system under test, and the converter control system under test transmits the motor stator voltage reference value signal to the analog-side converter control system.

[0058] Optionally, the current control strategy based on direct impedance compensation includes:

[0059] The analog-side converter control system receives the reference value of the motor armature port voltage transmitted by the converter under test, and obtains the reference value of the motor armature current response through the mathematical model of motor operating conditions.

[0060] Using the reference values ​​of the motor armature port voltage and the current response of the motor armature as control references, and through impedance compensation via the mathematical model of the analog-side converter output impedance network, the pulse width modulation switching signal of the analog-side converter is generated. This allows for full-bandwidth simulation and restoration of the current response reference value of the target electric drive system motor without closed-loop control or direct use of differential operators.

[0061] Optionally, after applying electrical and thermal stress under actual short-time overstress conditions to the power semiconductor device under test, a safe operating domain characterization of the power semiconductor device based on the short-time overstress conditions is performed, specifically:

[0062] S21: Set the initial values ​​of operating condition type, key operating condition parameters, operating condition duration, control system type, key parameters within the control system, thermal stress control node object, thermal stress control node temperature, and DC bus voltage.

[0063] S22: Set the operating condition type, key operating condition parameters, operating condition duration, control system type, key parameters within the control system, thermal stress control node object, thermal stress control node temperature, and the variation range and step size of DC bus voltage.

[0064] S23: Based on the initial values ​​of the target operating condition parameters set in S21, the drive signals of the power semiconductor devices in the converter under test and the analog-side converter are automatically issued through the host computer interaction module to start the test;

[0065] S24: During the continuous operation of the test, the junction temperature of the target power semiconductor device is read online using the power semiconductor device junction temperature reading method; after the test operation ends, the junction temperature, on-state voltage drop and thermal resistance of the target power semiconductor device are read offline using the power semiconductor device junction temperature reading method and health status monitoring method.

[0066] S25: Based on the target operating condition parameter variation range and variation compensation set in S22, automatically calculate the operating condition parameters under the next test operating condition scenario;

[0067] S26: Repeat S24 and S25 to obtain online junction temperature, offline junction temperature, on-state voltage drop and thermal impedance data of power semiconductor devices in all operating conditions;

[0068] S27: The host computer automatically controls the operation based on the pre-set data and performs a safe operation domain characterization of power semiconductor devices based on short-time over-stress conditions.

[0069] Compared with the prior art, the embodiments of the present invention have at least one of the following beneficial effects:

[0070] This invention provides a power electronics short-time overstress testing system and method based on operating condition simulation. During the testing phase, electrical and thermal stresses under real operating conditions can be applied to power semiconductor devices, and based on the time constants of the electrical and thermal stresses themselves, high-control-bandwidth electrical and thermal stress simulation and reconstruction can be achieved. All factors affecting the analysis of the short-time overstress failure mechanism and the characterization of the safe operating domain of the target device are considered.

[0071] This invention provides a power electronics short-time overstress testing system and method based on operating condition simulation. In parallel experiments with multiple control groups, the system allows for more comprehensive definition and modification of variables and parameters. These parameters not only include the DC conduction current and conduction time of traditional methods, but also key parameters such as: operating condition type, key operating condition parameters, operating condition duration, control system type, key parameters within the control system, thermal stress control node objects, thermal stress control node temperatures, and DC bus voltage. This provides a more valuable reference for the safe operation design of power semiconductor devices before their actual use. Attached Figure Description

[0072] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0073] Figure 1 This is a schematic diagram of the structural principle of a power electronic short-time overstress testing system based on working condition simulation in one embodiment of the present invention;

[0074] Figure 2 This is a control principle diagram of the thermal stress control module in a preferred embodiment of the present invention;

[0075] Figure 3 This is a schematic diagram of the power hardware module of the photovoltaic energy storage inverter under grid-connected operation in a preferred embodiment of the present invention. Figure 1 ;

[0076] Figure 4 This is a schematic diagram of the power hardware module under motor drive conditions in a preferred embodiment of the present invention. Figure 2 . Detailed Implementation

[0077] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention. These all fall within the scope of protection of the present invention.

[0078] Reference Figure 1 As shown, this embodiment of the invention provides a power electronics short-time over-stress testing system based on operating condition simulation. This system can be used to characterize the reliability and safe operating domain of power semiconductor devices in a converter under test under short-time over-stress. Specifically, the testing system includes: a power hardware module, an electrical stress control module, a thermal stress control module, a state detection module, and a host computer interaction module. The power hardware module adopts a dual-mode structure of the converter under test and the analog-side converter, which can recreate the electrical stress of the power semiconductor devices within the converter under test at the power level. The electrical stress control module, connected to the power hardware module, is used to generate control signals for the power semiconductor devices within the power hardware module, controlling the converter under test and the analog-side converter to recreate the electrical stress at the outlet of the converter under test. The thermal stress control module, connected to the power hardware module, generates ... The system includes a hardware module that simulates the thermal stress of power semiconductor devices within the converter under test at different temperature nodes; a status detection module connected to the power hardware module that detects temperature changes at various nodes of the power semiconductor devices within the converter under test under short-term over-stress conditions, as well as the on-state voltage drop and thermal impedance of the power semiconductor devices, reflecting the health status of the devices; and a host computer interaction module that controls the power hardware module, electrical stress control module, thermal stress control module, and status detection module through human-computer interaction, thereby realizing the detection of electrical stress, thermal stress, and health status of the power semiconductor devices.

[0079] In the embodiments described above, during testing, electrical and thermal stresses under real-world operating conditions can be applied to power semiconductor devices, and based on the time constants of the electrical and thermal stresses themselves, high-control-bandwidth electrical and thermal stress simulation can be achieved. Simultaneously, for short-term over-stress conditions of the converter under test, reliability indicators, represented by the safe operating domain, can be automatically acquired.

[0080] In some embodiments, the power hardware module described above adopts a converter-to-charge structure, specifically including a converter under test (DUT), an output impedance network of the DUT, an output impedance network of the analog-side converter, and an analog-side converter. These components are connected sequentially, with one end of the DUT's output impedance network connected to the DUT, one end of the analog-side converter's output impedance network connected to the analog-side converter, and the other end of the DUT's output impedance network connected to the other end of the analog-side converter's output impedance network. The DUT and the analog-side converter share a common DC bus and DC power supply module. Based on the DUT's output impedance network and the analog-side converter's output impedance network, the electrical characteristics of the two converters under short-term over-stress conditions can be simulated and reproduced at the power level.

[0081] In some embodiments, the electrical stress control module can achieve high control bandwidth. Specifically, the electrical stress control module includes a control system for the converter under test (DUT) and a control system for the analog converter. The DUT control system generates control signals for the DUT to control the DUT; the analog converter control system generates control signals for the analog converter to control the DUT. The analog converter control system can adaptively adapt to the DUT control system, including key variables such as control cycle and control parameters. In some embodiments, the analog converter control system employs a high-bandwidth electrical control strategy based on direct impedance compensation (corresponding to the control method in the electric drive condition of the embodiment) and single / multi-closed-loop control (corresponding to the control method in the electric drive and grid-connected conditions of the embodiment). There is voltage modulation signal interaction between the DUT control system and the analog converter control system to improve the steady-state and transient performance of the short-time over-stress electrothermal integrated operating condition simulation test system.

[0082] In the above embodiments of the present invention, the electrical stress control module is connected to the power hardware module and is used to generate control signals for the power semiconductor devices within the power hardware module; at the same time, the electrical stress control module is connected to the host computer interaction module and receives parameter instructions issued by the host computer interaction module.

[0083] In some embodiments, the thermal stress control module includes a heating unit, a cooling unit, and a temperature control unit. The heating unit heats the heat sink to a set temperature; the cooling unit cools the heat sink to a set temperature; and the temperature control unit controls the temperature of the heating and cooling units, performing closed-loop control of the thermal stress of the analog power semiconductor device at each node based on different temperature sampling locations. Specifically, the temperature control unit uses a closed-loop control strategy, controlling the heating and cooling units with PWM signals, and can perform closed-loop control of the thermal stress of the analog power semiconductor device at each node based on different temperature sampling locations.

[0084] In some embodiments, the thermal stress control module may further include a setting unit, which includes: setting the temperature object of the thermal stress control node, specifically including but not limited to: the junction temperature of the power semiconductor device, the case temperature of the power semiconductor device, and the heat sink temperature of the power semiconductor device; setting the temperature of the thermal stress control node object, the temperature adjustment range of which can be from room temperature to the maximum safe temperature of the power semiconductor device.

[0085] In some embodiments, the status detection module includes two parts: a thermal stress temperature detection unit and a health status detection unit. The thermal stress temperature detection unit, based on a temperature sampling and conversion device, can detect online temperature changes at various nodes of the power semiconductor device under short-term over-stress conditions. The health status detection unit, based on clamping and withstand voltage circuits, can detect the forward voltage drop of the power semiconductor device under short-term over-stress conditions online or semi-online, while ensuring measurement accuracy. The obtained forward voltage drop can be used to calculate the device's conduction loss and reflect the health and aging status of the device chip and bonding lines. Thermal impedance extraction is based on the heating principle of a switching power supply. By recording the junction temperature, case temperature, and heat sink temperature of the device under test, thermal impedance is calculated to reflect the health and aging status of the thermally conductive layer, bonding layer, etc. Furthermore, the device conduction loss, health, and aging status obtained in this embodiment can be directly output to the host computer interaction module for monitoring or early warning.

[0086] In the above embodiments of the present invention, the status monitoring module is used to monitor the temperature and health status of power semiconductor devices in the power hardware module. At the same time, it is connected to the host computer interaction module, and the monitored node temperature and health status are uploaded to the host computer interaction module. That is, the host computer displays the node temperature and status of the power semiconductor devices. The data is used to characterize the final short-time over-stress safe operating domain, and temperature and status monitoring can be realized.

[0087] In the above embodiments, the thermal stress control module sets the specific thermal stress control node object and node temperature through the setting unit, and then controls the heating unit and cooling unit, using the temperature of the specific power semiconductor device thermal stress application node as the sampling feedback, and simulates and restores the thermal stress of the power semiconductor device through closed-loop control.

[0088] In some embodiments, the heating element of the thermal stress control module includes, but is not limited to, heating methods such as metal heating rods, infrared heating, and water bath heating. The heat dissipation element of the thermal stress control module includes, but is not limited to, air-cooled convection cooling and water-cooled conduction cooling. Furthermore, the control unit of the thermal stress control module uses the temperature set by the thermal stress control setting unit as a reference value and the node temperature sampled by the temperature detection unit as a feedback value. Through closed-loop control, it generates control signals for the heating element and the heat dissipation element to achieve zero steady-state error temperature control, such as... Figure 2 As shown.

[0089] In specific embodiments, the temperature nodes that the temperature detection unit can detect include, but are not limited to: the junction temperature of the power semiconductor device, the case temperature of the power semiconductor device, and the heatsink temperature of the power semiconductor device. The heatsink temperature detection method can include: thermocouple contact temperature measurement and fiber optic contact temperature measurement. The power semiconductor device case temperature detection method includes: any one of thermocouple contact temperature measurement and fiber optic contact temperature measurement. The power semiconductor device junction temperature detection method includes: any one of fiber optic contact temperature measurement and indirect calculation of the junction temperature by detecting the on-state voltage drop.

[0090] Furthermore, the detection of junction temperature indirectly calculated from the on-state voltage drop is divided into two methods: online detection and semi-on-line detection. Online detection requires pre-setting the relationship between the on-state voltage drop and junction temperature of the power semiconductor device under high current. The on-state voltage drop of the device is detected online, and the junction temperature is indirectly calculated under high current. Semi-on-line detection requires pre-setting the relationship between the on-state voltage drop and junction temperature of the power semiconductor device under low current. During system operation, the switching signal of the power semiconductor device under test must be blocked, the high operating current is cut off, and a small current is injected into the power semiconductor device to indirectly calculate the junction temperature by detecting the on-state voltage drop.

[0091] In some embodiments, the thermal stress temperature detection unit is used to monitor the temperature of each node of the power semiconductor device, including junction temperature, case temperature, heat sink temperature, etc. The detection results can be used as the temperature closed-loop control feedback quantity of the temperature control section, reflecting the key junction temperature parameters of the power semiconductor device, and finally used to characterize the failure mechanism and safe operating domain.

[0092] In some embodiments, the health status detection unit includes, but is not limited to, on-state voltage drop detection and thermal impedance detection functions. The on-state voltage drop detection function can be implemented by a clamping circuit. The clamping circuit clamps the high voltage when the power semiconductor device is turned off to a lower value without affecting the low on-state voltage drop when the power semiconductor device is turned on, thereby obtaining a high-precision on-state voltage drop while the power semiconductor device is in the switching state. Thermal impedance extraction is based on the heating principle of a switching power supply. During the heating phase, the device under test (DUT) operates in a switching state, and the duty cycle and load current of the DUT are controlled to constant values, creating a special operating condition where the DUT generates stable power loss, thus producing thermal behavior closer to actual operating conditions. During the off-state phase, all fully controlled devices are turned off, and the load current is reduced using the bus voltage, eliminating the need for additional auxiliary switches to cut off the heating current. During the cooling phase, the junction temperature, case temperature, and heat sink temperature of the DUT are recorded for calculating the thermal impedance. This embodiment of the invention reflects the health status of the device under short-time overstress conditions through characteristic quantities such as on-state voltage drop and thermal impedance.

[0093] In some embodiments, the host computer interaction module can programmatically input target electrical and thermal operating conditions, and can also monitor electrical and thermal operating condition characteristic parameters based on an oscilloscope interface with an adjustable time scale. Furthermore, it can automatically characterize the safe operating domain of power semiconductor devices. The host computer interaction module specifically includes: an electrical characteristic parameter monitoring interface, a thermal characteristic parameter monitoring interface, an operating condition parameter input programming interface, a device health status monitoring interface, and a DC power supply module interface, which are used to realize the detection and programming input of various parameters, respectively.

[0094] Specifically, the electrical characteristic parameter monitoring interface is mainly used to monitor key electrical characteristic parameters, including DC-side bus voltage, DC-side current, AC-side voltage, and AC-side current, with a monitoring time scale ranging from milliseconds to seconds.

[0095] Taking the grid-connected photovoltaic energy storage system as an example:

[0096] The electrical characteristic parameter monitoring interface can display: DC side bus voltage, DC side current, three-phase AC voltage at grid connection point, and three-phase AC current at grid connection point;

[0097] Taking the motor drive condition as an example:

[0098] The electrical characteristic parameter monitoring interface can display: DC side bus voltage, DC side current, three-phase AC voltage of motor armature winding, three-phase AC current of motor armature winding, motor speed, motor load torque, and motor electromagnetic torque.

[0099] The thermal characteristic parameter monitoring interface is mainly used to monitor the junction temperature, case temperature, and heat sink temperature of the power semiconductor devices in the converter under test, and the monitoring time scale is in the second range.

[0100] The programming interface for inputting operating parameters is mainly used for human-machine interaction to set key operating parameters such as the type of operating condition, the specific form of the operating condition, and specific control parameters.

[0101] Taking the grid-connected photovoltaic energy storage system as an example:

[0102] The operating condition parameter input programming interface allows input of: the effective value of the three-phase AC voltage at the grid connection point under normal grid-connected conditions, the effective value of the three-phase AC current at the grid connection point under normal grid-connected conditions, and the grid frequency under normal grid-connected conditions; the effective value of the three-phase AC voltage at the grid connection point under over / under voltage conditions and the duration of over / under voltage conditions; the grid connection point frequency under over / under frequency conditions and the duration of over / under frequency conditions; the three-phase voltage imbalance coefficient under three-phase voltage imbalance conditions and the duration of three-phase voltage imbalance conditions; the harmonic voltage injection component under harmonic voltage injection conditions and the duration of harmonic voltage injection conditions; the effective value of the three-phase AC voltage at the grid connection point under high / low voltage ride-through conditions and the duration of high / low voltage ride-through conditions; and the control parameters of the grid-connected inverter voltage control loop and current control loop. These parameters serve as key operating condition and control parameters.

[0103] Taking the motor drive condition as an example:

[0104] The programming interface for inputting operating parameters allows input of: motor rated speed; motor rated load torque; key physical parameters of the motor such as the equivalent inductance of the motor's d-axis, equivalent inductance of the motor's q-axis, equivalent resistance of the motor's armature winding, and equivalent moment of inertia; motor speed and duration under high-speed operating conditions; motor speed and duration under low-speed operating conditions; acceleration and duration under rapid acceleration; deceleration and duration under rapid deceleration; load torque and duration under stall and climbing conditions; and the outer loop control parameters of the motor controller for speed, the inner loop control parameters of the motor controller for current, and the inner loop control parameters of the motor controller for torque. These parameters serve as key operating and control parameters.

[0105] The device health monitoring interface can display: the online on-state voltage drop of the power semiconductor in the converter under test, and the thermal impedance of the power semiconductor device in the converter under test.

[0106] The DC power supply module interface can display: current DC bus voltage, current DC bus current, and the operating status of the DC power supply module; the DC power supply module interface can input: DC power supply module output DC voltage and DC power supply module output maximum DC current.

[0107] In the above embodiments of the present invention, the application scope of short-time overstress conditions includes, but is not limited to, photovoltaic energy storage grid-connected conditions and motor drive conditions. Specifically, taking photovoltaic energy storage grid-connected conditions as an example, short-time overstress conditions include, but are not limited to, transient conditions such as over / under voltage, over / under frequency, three-phase voltage imbalance, harmonic voltage injection, voltage flicker, and high / low voltage ride-through. Taking motor drive conditions as an example, short-time overstress conditions include, but are not limited to, short-time severe transient conditions such as high speed, low speed, rapid acceleration, rapid deceleration, hill climbing, and stall.

[0108] In the above embodiments of the present invention, the power electronic semiconductor device under test includes IGBT, MOSFET, and diode, and its packaging includes, but is not limited to, single tube, module, and press-fit forms.

[0109] In the above embodiments of the present invention, the converter-to-charge structure includes: a converter under test and a simulation-side converter. The converter topology can be selected based on the application range of short-time overstress conditions. Selectable converter topologies for the test include, but are not limited to: single-phase two-level half-bridge, single-phase three-level half-bridge, three-phase two-level half-bridge, three-phase three-level half-bridge, and cascaded multi-level topology. Selectable simulation-side converter topologies include, but are not limited to: single-phase two-level half-bridge, single-phase three-level half-bridge, three-phase two-level half-bridge, three-phase three-level half-bridge, and cascaded multi-level topology.

[0110] In the above embodiments of the present invention, the DC power supply module is used to provide electrical energy to the converter under test and the analog-side converter. Based on the power cycle structure, the DC power supply module needs to provide the power loss of each part of the test system. In some embodiments, the DC power supply module can adopt a single DC power supply structure, or a multiple DC power supply series or parallel power supply structure, or a power supply structure with an adjustable single-phase or three-phase transformer and rectifier on the AC grid side, and the output terminal of the rectifier connected to the power supply side.

[0111] In the above embodiments of the present invention, the outlet impedance network of the converter under test and the outlet impedance network of the analog-side converter can be selected according to the application range of short-time overstress conditions.

[0112] Specifically, such as Figure 3 As shown, taking the photovoltaic energy storage grid-connected working condition as an example: the converter under test is mainly a current-source inverter, and the selectable output impedance network includes, but is not limited to: an L filter network mainly composed of inductors and resistors, and an LCL filter network mainly composed of inductors, capacitors and resistors; the analog-side converter is mainly a voltage-source inverter, and the selectable output impedance network includes, but is not limited to: an LC filter network mainly composed of inductors and capacitors.

[0113] like Figure 4 As shown, taking the motor drive condition as an example: the converter under test is mainly a voltage-source inverter, and the selectable output impedance network includes, but is not limited to: a filterless network and an LC filter network mainly composed of inductors and capacitors; the analog-side converter is mainly a current-source inverter, and the selectable output impedance network includes, but is not limited to: an L filter network mainly composed of inductors and resistors and an LCL filter network mainly composed of inductors, capacitors and resistors.

[0114] In this embodiment of the invention, a short-time overstress test method for power electronics based on operating condition simulation is also provided. Specifically, the above-mentioned short-time overstress test system for power electronics based on operating condition simulation is used to apply electrical stress and / or thermal stress under actual short-time overstress conditions to the power semiconductor devices in the converter under test, and then the test is performed.

[0115] Specifically, in one embodiment, applying electrical and / or thermal stress under actual short-time overstress conditions to the power semiconductor devices within the converter under test includes:

[0116] S11: Through the host computer interaction module, select and set the test condition type of the power semiconductor device in the converter to be tested. The test condition types include grid-connected photovoltaic energy storage inverter and motor drive condition.

[0117] S12: Based on the operating condition type set in S11, and according to the high-bandwidth operating condition simulation strategy, set the control system type of the converter under test, and set the control system type of the simulation-side converter.

[0118] S13: Based on the operating condition type set in S11, the type of control system on the converter side and the type of control system on the analog side set in S12, set the key operating condition parameters and key control parameters in the control system on the converter side and the control system on the analog side respectively.

[0119] S14: Based on the thermal stress control module, the thermal stress control object node and target temperature are set through the host computer interaction module, and the target node temperature is waited for to reach the set test temperature and reach thermal steady state.

[0120] S15: After the target power board conductor devices reach thermal steady state, the DC source in the DC power supply module is started through the host computer interaction module and connected to the positive and negative buses of the converter under test and the analog side converter, so that its output voltage value is the DC bus voltage under real working conditions.

[0121] S16: After reaching thermal steady state in S14 and stabilizing the target DC bus voltage in S15, the start command for the power semiconductor devices in the converter under test and the analog-side converter is issued, and the drive signal is sent out, and the system starts running.

[0122] In some embodiments, the high-bandwidth operating condition simulation strategy in S12 may include: a control system on the converter side under test and a control system on the simulation side of the converter, which can be used to control electrical characteristic quantities mainly composed of voltage and current, respectively. Under the premise of matching the signal source port of the control system on the converter side under test, the additional bandwidth limitations introduced by steps such as voltage low-pass filtering sampling and motor speed encoding are eliminated through signal transmission. Depending on the application scope of the short-time overstress condition, the controlled object, control strategy, and signal interaction type can be selected.

[0123] Specifically, taking the grid-connected photovoltaic energy storage system as an example:

[0124] The primary control object of the converter under test is current, and the selectable control strategies include, but are not limited to: current control strategy, power control strategy, virtual synchronous machine strategy, and droop control strategy. The primary control object of the analog-side converter is voltage, and the selectable control strategies include, but are not limited to: single-voltage-loop voltage control strategy, and voltage control strategy based on an outer voltage loop and an inner current loop. The signal interaction method is as follows: the analog-side converter control system transmits the grid-connected phase angle and grid-connected frequency signals to the control system of the converter under test.

[0125] Specifically, taking the motor drive condition as an example:

[0126] The primary control object of the converter under test is current, and selectable control strategies include, but are not limited to: field-oriented control, direct torque control, current hysteresis control, and maximum torque-to-current ratio control. The analog-side converter can also control current, with a current control strategy based on direct impedance compensation. Signal interaction types include: the analog-side converter control system transmitting motor rotor position and speed signals to the converter under test control system; and the converter under test control system transmitting motor stator voltage reference values ​​to the analog-side converter control system.

[0127] Furthermore, in some embodiments, the current control strategy based on direct impedance compensation is suitable for motor drive conditions. Specifically, the analog-side converter control system employing the direct impedance compensation current control strategy receives the motor stator reference value signal u transmitted by the converter under test. sd_ref u sq_ref By using a mathematical model of motor operating conditions, the reference value i of the motor stator current response is obtained. sd_ref i sq_ref Then, using the reference values ​​of the motor armature port voltage and the motor armature current response as control references, and through voltage drop compensation of the analog-side inverter output filter, a pulse width modulation switching signal u for the analog-side converter is generated. d_mod u q_modIt can perform full-bandwidth simulation and reconstruction of the current response reference value of the target electric drive system motor without closed-loop control or direct use of differential operators. The main impedance compensation transfer function can be expressed as:

[0128]

[0129] Among them, R f L f To simulate the parasitic resistance and inductance values ​​of the L-filter at the output of the analog converter, R s L s The values ​​of resistance and inductance of the target motor when it is considered as an inductive load.

[0130] Furthermore, after applying electrical and thermal stresses under actual short-time overstress conditions to the power semiconductor device under test, the test method further includes: characterizing the safe operating domain of the power semiconductor device based on the short-time overstress conditions; specifically,

[0131] S21: Set the initial values ​​of operating condition type, key operating condition parameters, operating condition duration, control system type, key parameters within the control system, thermal stress control node object, thermal stress control node temperature, and DC bus voltage.

[0132] S22: Set the operating condition type, key operating condition parameters, operating condition duration, control system type, key parameters within the control system, thermal stress control node object, thermal stress control node temperature, and the variation range and step size of DC bus voltage.

[0133] S23: Based on the initial values ​​of the target operating condition parameters set in S21, the drive signals of the power semiconductor devices in the converter under test and the analog-side converter are automatically issued through the host computer interaction module to start the test;

[0134] S24: During the continuous operation of the test, the junction temperature of the target power semiconductor device is read online using the power semiconductor device junction temperature reading method; after the test operation ends, the junction temperature, on-state voltage drop and thermal resistance of the target power semiconductor device are read offline using the power semiconductor device junction temperature reading method and health status monitoring method.

[0135] S25: Based on the target operating condition parameter variation range and variation compensation set in S22, automatically calculate the operating condition parameters under the next test operating condition scenario;

[0136] S26: Repeat S24 and S25 to obtain online junction temperature, offline junction temperature, on-state voltage drop and thermal impedance data of power semiconductor devices in all operating conditions;

[0137] S27: The host computer automatically controls the operation based on the pre-set data and performs a safe operation domain characterization of power semiconductor devices based on short-time over-stress conditions.

[0138] Specifically, characterizing the safe operating domain of power semiconductor devices involves selecting specific parameters of interest, such as: DC on-current, on-time, operating condition type, key parameters of the operating condition, operating condition duration, control system type, key parameters within the control system, thermal stress control node objects, thermal stress control node temperatures, and DC bus voltage. With other parameters remaining constant, the aforementioned automated testing process is performed on the specific parameters of interest to ultimately obtain the impact of these parameters on the safe operation of the device. For example, if the operating condition duration and DC bus voltage are selected as the parameters of interest, then the other parameters remain at their default values. The test method is initiated, setting the range and step size of the operating condition duration and the range and step size of the DC bus voltage. For the test results under each parameter, the temperature and health status of each node of the device are detected, ultimately characterizing the safe operating domain in a two-dimensional plane.

[0139] In the above embodiments of the invention, all factors affecting the short-time overstress failure mechanism analysis and safe operation domain characterization of the target device are considered during testing. Various variable parameters can be defined and modified, including DC conduction current, conduction time, operating condition type, key operating condition parameters, operating condition duration, control system type, key parameters within the control system, thermal stress control node object, thermal stress control node temperature, DC bus voltage, and other key parameters. This conforms to the electrothermal stress factors under real operating conditions, resulting in more realistic and accurate results. It provides good assistance for the safe operation design of power semiconductor devices before they are put into actual use.

[0140] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various modifications or variations within the scope of the claims, which do not affect the essence of the present invention. The above preferred features can be used in any combination without conflict.

Claims

1. A power electronic short-term overstress test system based on operating condition simulation, characterized in that, include: The power hardware module adopts a dual-drive structure of the converter under test and the analog-side converter to restore the electrical stress of the power semiconductor devices in the converter under test at the power level. An electrical stress control module, connected to the power hardware module, is used to generate control signals for the power semiconductor devices within the power hardware module, and to control the converter under test and the analog-side converter to restore the electrical stress at the outlet of the converter under test. A thermal stress control module is connected to the power hardware module to simulate the thermal stress of the power semiconductor devices in the converter under test at different temperature nodes. The status detection module is connected to the power hardware module to detect the temperature changes of various nodes of the power semiconductor device in the converter under short-term over-stress conditions, as well as the on-state voltage drop and thermal impedance of the power semiconductor device, reflecting the health status of the device. The host computer interaction module controls the aforementioned power hardware module, electrical stress control module, thermal stress control module, and status detection module through human-computer interaction, thereby realizing the detection of electrical stress, thermal stress, and health status of power semiconductor devices. The power hardware module includes: The converter to be tested; Analog-side converter; The output impedance network of the converter under test is connected at one end to the converter under test. A simulated-side converter output impedance network, one end of which is connected to the simulated-side converter; The other end of the output impedance network of the converter under test is connected to the other end of the output impedance network of the analog-side converter. The converter under test and the analog converter share a DC bus and a DC power supply module. Based on their respective output impedance networks, the converter under test and the analog converter simulate and reproduce the electrical characteristics under short-time over-stress conditions at the power level.

2. The operating condition simulation based power electronic short time overstress test system of claim 1, wherein, The electrical stress control module includes: The control system on the side of the converter under test generates control signals for the converter under test in order to control the converter under test. The analog-side converter control system generates control signals for the analog-side converter to control it; the analog-side converter control system can adapt to the control system of the converter under test, and the adaptation includes control cycle and control parameters. The analog converter control system adopts a high-bandwidth electrical control structure based on direct impedance compensation and single / multi-loop control. There is voltage modulation signal interaction between the converter control system under test and the analog converter control system to improve the steady-state and transient performance of the short-time over-stress electrothermal integrated working condition simulation test system.

3. The operating condition simulation based power electronic short time overstress test system of claim 1, wherein, The thermal stress control module includes: The heating element heats the radiator to reach the set temperature. The cooling unit cools the radiator to achieve the set temperature. The temperature control unit controls the temperature of the heating unit and the cooling unit, and performs closed-loop control of the thermal stress of the analog power semiconductor device at each node based on different temperature sampling locations.

4. The operating condition simulation based power electronic short duration overstress test system of claim 1, wherein, The status detection module includes: The thermal stress temperature detection unit detects the temperature changes of various nodes in power semiconductor devices under short-term over-stress conditions. The health status detection department detects the forward voltage drop of power semiconductor devices under short-term over-stress conditions to calculate the device conduction loss and reflect the device's health and / or aging status; it also detects the thermal resistance of power semiconductor devices after short-term over-stress conditions to reflect the device's health and / or aging status.

5. The operating condition simulation based power electronic short duration overstress test system of claim 1, wherein, The host computer interaction module performs programming input and monitoring of short-time overstress conditions in power electronics, including: Electrical characteristic parameter monitoring interface, used to monitor key electrical characteristic parameters; The thermal parameter monitoring interface is used to monitor the junction temperature, case temperature, and heat sink temperature of the power semiconductor devices in the converter under test. The programming interface for inputting operating parameters is used to input operating parameters during the test. The device health status monitoring interface is used to display the online test on-state voltage drop of the power semiconductors in the converter under test, as well as the thermal impedance of the power semiconductor devices in the converter under test. The DC power supply module interface is used to input and / or display DC power supply parameters.

6. A power electronic short-term overstress test method based on operating condition simulation, characterized in that, Using the test system described in any one of claims 1-5, applying electrical and / or thermal stress under actual short-time overstress conditions to the power semiconductor devices in the converter under test specifically includes: S11: Through the host computer interaction module, select and set the test condition type of the power semiconductor device in the converter to be tested. The test condition types include grid-connected photovoltaic energy storage inverter and motor drive condition. S12: Based on the operating condition type set in S11, and according to the high-bandwidth operating condition simulation strategy, set the control system type of the converter under test, and set the control system type of the simulation-side converter. S13: Based on the operating condition type set in S11, the control system type of the converter side under test set in S12, and the control system type of the analog converter side, set the key operating condition parameters and key control parameters in the control system of the converter side under test, and the key operating condition parameters and key control parameters in the control system of the analog converter side, respectively. S14: Based on the thermal stress control module, the thermal stress control object node and target temperature are set through the host computer interaction module, and the target node temperature is waited for to reach the set test temperature and reach thermal steady state. S15: After the target power semiconductor device reaches thermal steady state, the DC source in the DC power supply module is started through the host computer interaction module and connected to the positive and negative buses of the converter under test and the analog side converter, so that its output voltage value is the DC bus voltage under real working conditions. S16: After reaching thermal steady state in S14 and stabilizing the target DC bus voltage in S15, the start command for the power semiconductor devices in the converter under test and the analog-side converter is issued, and the drive signal is sent out, and the system starts running.

7. The power electronic short-term overstress test method based on operating condition simulation according to claim 6, characterized in that, The high-bandwidth operating condition simulation strategy, wherein: The control system on the converter under test side and the control system on the analog converter side are used to control the electrical characteristics of the converter under test and the analog converter side, mainly voltage and current, respectively. Under the premise of matching the signal source port of the control system on the side of the converter under test, signal transmission is used to avoid additional bandwidth limitations. At the same time, the control object, control strategy and signal interaction type are selected according to the application range of short-time overstress conditions.

8. The short-time overstress testing method for power electronics based on operating condition simulation according to claim 7, characterized in that, The selection of the control object, control strategy, and signal interaction type is based on the application range of short-time overstress conditions, wherein: - For the grid-connected operating condition of the photovoltaic energy storage inverter: The control object of the converter under test is current, and the selected control strategy can be any one of the following: current control strategy, power control strategy, virtual synchronous machine strategy, and droop control strategy. The control object of the analog-side converter is voltage, and the selected control strategy is either a single voltage loop voltage control strategy or a voltage control strategy with the outer voltage loop or the inner current loop as the main components. The signal interaction type is one of the following: the analog-side converter control system transmits the grid-connected phase angle to the converter control system under test, and the analog-side converter control system transmits the grid-connected frequency signal to the converter control system under test. - For the aforementioned motor drive conditions: The controlled object of the converter under test is current, and the selected control strategy is any one of field-oriented control, direct torque control, current hysteresis control, and maximum torque-current ratio control. The controlled object of the analog-side converter is current, and the control strategy is a current control strategy based on direct impedance compensation. The signal interaction type is as follows: the analog-side converter control system transmits the motor rotor position and motor speed signals to the converter control system under test, and the converter control system under test transmits the motor stator voltage reference value signal to the analog-side converter control system.

9. The power electronic short-term overstress test method based on operating condition simulation according to claim 8, characterized in that, The current control strategy based on direct impedance compensation includes: The analog-side converter control system receives the reference value of the motor armature port voltage transmitted by the converter under test, and obtains the reference value of the motor armature current response through the mathematical model of motor operating conditions. Using the reference values ​​of the motor armature port voltage and the current response of the motor armature as control references, and through impedance compensation via the mathematical model of the analog-side converter output impedance network, the pulse width modulation switching signal of the analog-side converter is generated. This allows for full-bandwidth simulation and restoration of the current response reference value of the target electric drive system motor without closed-loop control or direct use of differential operators.

10. The power electronic short-term overstress test method based on operating condition simulation according to claim 6, characterized in that, After applying electrical and / or thermal stresses under actual short-time overstress conditions to the power semiconductor devices within the converter under test, a safe operating domain characterization of the power semiconductor devices based on the short-time overstress conditions is performed, specifically: S21: Set the initial values ​​of operating condition type, key operating condition parameters, operating condition duration, control system type, key parameters within the control system, thermal stress control node object, thermal stress control node temperature, and DC bus voltage. S22: Set the operating condition type, key operating condition parameters, operating condition duration, control system type, key parameters within the control system, thermal stress control node object, thermal stress control node temperature, and the variation range and step size of DC bus voltage. S23: Based on the initial values ​​of the target operating condition parameters set in S21, the drive signals of the power semiconductor devices in the converter under test and the analog-side converter are automatically issued through the host computer interaction module to start the test; S24: During the continuous operation of the test, the junction temperature of the target power semiconductor device is read online using the power semiconductor device junction temperature reading method; after the test operation ends, the junction temperature, on-state voltage drop and thermal resistance of the target power semiconductor device are read offline using the power semiconductor device junction temperature reading method and health status monitoring method. S25: Based on the target operating condition parameter change range and change step size set in S22, automatically calculate the operating condition parameters under the next test operating condition scenario; S26: Repeat S24 and S25 to obtain online junction temperature, offline junction temperature, on-state voltage drop and thermal impedance data of power semiconductor devices in all operating conditions; S27: The host computer interaction module automatically controls the operation based on the pre-set data and performs a safe operation domain characterization of power semiconductor devices based on short-time over-stress conditions.

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