Bonding wire failure detection circuit, method and electronic device for capacitive isolator

Abstract

The application provides a bonding wire failure detection circuit and method of a capacitive isolator and electronic equipment. The first detection unit and the second detection unit are respectively used for detecting the output signal of the output end of the capacitive isolator under the action of the system input signal under the control of the corresponding enable signal, so as to determine whether the bonding wire corresponding to the first capacitor group and the bonding wire corresponding to the second capacitor group are failed. Since the bonding wire corresponding to the first capacitor group and the bonding wire corresponding to the second capacitor group can be alternately detected, the connection of the two bonding wires can be accurately detected and determined.

Description

Technical Field

[0001] This invention relates to the field of semiconductor testing, and more particularly to a bonding wire failure detection circuit, method, and electronic device for capacitive isolators. Background Technology

[0002] When signals or energy are transferred between two circuits with different voltage domains, the difference in voltage domains may cause interference or damage to surrounding circuits during transmission. Therefore, isolators are typically used to protect the circuits and improve their reliability when transmitting signals between circuits in different voltage domains.

[0003] Compared to traditional optocouplers, digital isolators offer advantages such as high integration, no optical decay, and low power consumption. Among them, capacitive isolators, as a type of digital isolator, are widely used due to their excellent reliability and stability.

[0004] A capacitive isolator typically includes a transmitter chip, a receiver chip, and an isolation capacitor. The isolation capacitor can be a single capacitor or a dual capacitor. For a single capacitor configuration, the isolation capacitor can be integrated into the receiver chip (e.g., ...). Figure 1 (As shown) can also be placed in the transmitter chip (such as Figure 1 (As shown). In the packaging process of a capacitive isolator, if the isolation capacitor is placed in the receiver chip, the transmitter chip needs to be connected to the upper plate of the isolation capacitor via bonding wires; if the isolation capacitor is placed in the transmitter chip, the upper plate of the isolation capacitor is connected to the receiver chip via bonding wires; and if... Figure 3 As shown, in the case of a dual-capacitor configuration, the upper plates of the two isolation capacitors are connected by a bonding wire.

[0005] Furthermore, to achieve high common-mode transient rejection ratio (CMTI) performance, capacitive isolators often employ a differential structure, which cancels out changes in the common-mode signal. Therefore, regardless of whether it is a single-capacitor or dual-capacitor configuration, the transmitter chip and receiver chip are connected via two bonding wires.

[0006] During the manufacturing process, the bonding wires connecting the transmitter and receiver chips may break or be missing, affecting the common-mode rejection capability of the capacitive isolator. Therefore, it is necessary to perform failure testing on the bonding wires to check their connection status.

[0007] Existing methods for testing the failure of bonding wires determine whether the bonding wires are effectively connected by measuring the output signal. If both bonding wires fail, there will be no normal output signal, thus indicating that the bonding wires have failed.

[0008] However, existing failure detection methods are not suitable for cases where only one bond wire fails (such as...). Figure 4 As shown in the figure, it cannot be used to conduct tests accurately and effectively.

[0009] Therefore, it is necessary to improve the bond wire failure detection method to enhance its accuracy. Summary of the Invention

[0010] This invention provides a bonding wire failure detection circuit, method, and electronic device for capacitive isolators, to solve the problem that when the transmitter chip and receiver chip are connected by two bonding wires, it is not possible to accurately and effectively detect the failure of only one bonding wire.

[0011] According to a first aspect of the present invention, a bonding wire failure detection circuit for a capacitive isolator is provided for detecting the bonding wires of a packaged capacitive isolator; wherein the capacitive isolator includes a transmitter chip, a receiver chip, and a differential capacitor bank, the differential capacitor bank including a first capacitor bank and a second capacitor bank, the transmitter chip including a first path and a second path, the first path and the second path being used to form a differential signal pair, the differential signal pair including a first differential signal and a second differential signal, the first differential signal and the second differential signal being transmitted to the receiver chip respectively through the first capacitor bank and the second capacitor bank, the detection circuit including: a first detection unit and a second detection unit, the first detection unit being electrically connected to the first path, and the second detection unit being electrically connected to the second path; the first detection unit and the second detection unit respectively receiving a first detection enable signal and a second detection enable signal; wherein the first detection unit and the second detection unit are configured to:

[0012] When both the first detection enable signal and the second detection enable signal are at a low level, the capacitive isolator operates normally.

[0013] When either the first detection enable signal or the second detection enable signal is high, the capacitive isolator enters a test mode. Specifically, when the first detection enable signal is high and the second detection enable signal is low, the output signal at the output terminal of the capacitive isolator is used to determine whether the bonding wires corresponding to the first capacitor bank are faulty. When the second detection enable signal is high and the first detection enable signal is low, the output signal at the output terminal of the capacitive isolator is used to determine whether the bonding wires corresponding to the second capacitor bank are faulty.

[0014] Optionally, the first detection unit includes a first inverter and a first AND gate; the second detection unit includes a second inverter and a second AND gate.

[0015] The input terminal of the first inverter is used to receive the first detection enable signal, and the output terminal of the first inverter is electrically connected to the first input terminal of the first AND gate; the second input terminal of the first AND gate is used to receive the first input signal; the output terminal of the first AND gate outputs a first output signal.

[0016] The input terminal of the second inverter is used to receive the second detection enable signal, and the output terminal of the second inverter is electrically connected to the first input terminal of the second AND gate; the second input terminal of the second AND gate is used to receive the second input signal; and the output terminal of the second AND gate outputs a second output signal.

[0017] Optionally, the transmitter chip is an on / off keyed transmitter chip; both the first input signal and the second input signal are system input signals of the transmitter chip;

[0018] The on / off keyed transmitter chip includes an oscillator, the output signal of the oscillator is used as the input signal of the first input terminal of the first channel; the first output signal is used as the input signal of the second input terminal of the first channel;

[0019] The output signal of the oscillator is inverted by the third inverter and used as the input signal of the first input terminal of the second path; the second output signal is used as the input signal of the second input terminal of the second path.

[0020] Optionally, the first path includes a third AND gate and a first buffer, wherein the first input terminal and the second input terminal of the third AND gate are respectively the first input terminal and the second input terminal of the first path; the output terminal of the third AND gate is connected to the input terminal of the first buffer, and the output terminal of the first buffer outputs the first differential signal.

[0021] Optionally, the second path includes a fourth AND gate and a second buffer, wherein the first input terminal and the second input terminal of the fourth AND gate are respectively the first input terminal and the second input terminal of the second path; the output terminal of the fourth AND gate is connected to the input terminal of the second buffer, and the output terminal of the second buffer outputs the second differential signal.

[0022] Optionally, the transmitting chip is an edge-triggered transmitting chip;

[0023] The edge-triggered transmitter chip includes an edge trigger, the input of which is the system input signal of the transmitter chip.

[0024] The first path includes a third buffer;

[0025] The output of the edge trigger is connected to the input of the third buffer, and the output of the third buffer is used to output the first input signal to the second input of the first AND gate; the first output signal output by the first AND gate is used as the first differential signal.

[0026] Optionally, the second path includes a fourth inverter;

[0027] The output terminal of the edge-triggered flip-flop is connected to the input terminal of the fourth inverter, and the output terminal of the fourth inverter is used to output the second input signal to the second input terminal of the second AND gate; the second output signal output by the output terminal of the second AND gate serves as the second differential signal.

[0028] Optionally, the first capacitor bank may include a first capacitor or the first capacitor bank may include a first capacitor and a second capacitor;

[0029] The second capacitor bank includes a third capacitor or the second capacitor bank includes a third capacitor and a fourth capacitor.

[0030] According to a second aspect of the present invention, a method for detecting bond wire failure in a capacitive isolator is provided, which utilizes the bond wire failure detection circuit of the capacitive isolator in the first aspect and optional embodiments of the present invention to detect bond wire failure. The method includes:

[0031] When the first detection enable signal is set to high and the second detection enable signal is set to low, the output signal of the capacitive isolator is detected when the system input signal of the transmitter chip is normal; based on the output signal, it is determined whether the bonding wires corresponding to the first capacitor bank are faulty; and

[0032] When the second detection enable signal is set to high and the first detection enable signal is set to low, the output signal of the capacitive isolator is detected when the system input signal of the transmitter chip is normal; based on the output signal, it is determined whether the bonding wire corresponding to the second capacitor bank is faulty.

[0033] According to a third aspect of the present invention, an electronic device is provided, comprising a bonding wire failure detection circuit of a capacitive isolator as described in the first aspect and alternative embodiments of the present invention, and the capacitive isolator.

[0034] The present invention provides a bonding wire failure detection circuit, method, and electronic device for capacitive isolators. By setting up a first detection unit and a second detection unit, each controlled by a corresponding enable signal, to detect the output signal at the output terminal of the capacitive isolator under the action of a system input signal, the method determines whether the bonding wires corresponding to the first capacitor group and the second capacitor group have failed. Since the bonding wires corresponding to the first capacitor group and the second capacitor group can be detected alternately, the connection status of the two bonding wires can be accurately detected and determined. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This diagram illustrates the placement of the isolation capacitor within the receiver chip in a single-capacitor configuration.

[0037] Figure 2 This diagram illustrates the placement of the isolation capacitor within the transmitter chip in the form of a single capacitor.

[0038] Figure 3 A schematic diagram illustrating the configuration of the isolation capacitor in a dual-capacitor configuration is provided.

[0039] Figure 4 A schematic diagram illustrating the failure of only one bond wire;

[0040] Figure 5 This is a schematic diagram of a bonding wire failure detection circuit for a capacitive isolator in one embodiment of the present invention. Figure 1 ;

[0041] Figures 6A-6C This is a schematic diagram of the working waveform provided in an embodiment of the present invention;

[0042] Figure 7 This is a schematic diagram of a bonding wire failure detection circuit for a capacitive isolator in one embodiment of the present invention. Figure 2 .

[0043] Explanation of reference numerals in the attached figures

[0044] IN - System input signal;

[0045] OUT - Output signal

[0046] Test_cn - First detection enable signal;

[0047] Test_cp - Second detection enable signal;

[0048] 100 - Detection circuit;

[0049] 200-Capacitor-type isolator;

[0050] 210 - Transmitter chip;

[0051] 220 - Receiver chip;

[0052] 111 - First inverter;

[0053] 112 - First AND Gate;

[0054] 121 - Second inverter;

[0055] 122 - Second AND gate;

[0056] 201 - Oscillator;

[0057] 202 - Edge-triggered trigger;

[0058] 211-The Third AND Gate;

[0059] 212 - First Buffer;

[0060] 213 - Third inverter;

[0061] 214 - Fourth AND Gate;

[0062] 215 - Second buffer;

[0063] 216 - Second buffer;

[0064] 217 - Fourth Inverter;

[0065] C11 - First capacitor;

[0066] C12 - Second capacitor;

[0067] C21 - Third capacitor;

[0068] C22 - Four capacitors;

[0069] CP_TX1, CP_TX2 - First differential signals;

[0070] CN_TX1, CN_TX2 - Second differential signals;

[0071] CP_RX - First differential signal at the receiver;

[0072] CN_RX - The second differential signal at the receiver. Detailed Implementation

[0073] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0074] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0075] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0076] Furthermore, the term "connection" in the specification and claims of this invention refers to an electrical connection, which may include a direct connection or an indirect connection.

[0077] Please refer to Figure 5 This invention provides a bonding wire failure detection circuit for a capacitive isolator, used to detect the bonding wires of the capacitive isolator package. The capacitive isolator 200 includes a transmitter chip 210, a receiver chip 220, and a differential capacitor bank. The differential capacitor bank includes a first capacitor bank and a second capacitor bank. The transmitter chip 210 includes a first path and a second path, which are used to form a differential signal pair. The differential signal pair includes a first differential signal CP_TX1 and a second differential signal CN_TX1. The first differential signal CP_TX1 and the second differential signal CN_TX1 are transmitted to the receiver chip 220 through the first capacitor bank and the second capacitor bank, respectively. Figure 5In order to distinguish the differential signals at both ends of the capacitor, CP_TX1 and CP_TX2 are used to represent the differential signals at both ends of the capacitor of the transmitter chip, respectively; where CP_TX1 represents the differential signal at the input end of the capacitor and CP_TX2 represents the differential signal at the output end of the capacitor; the same applies to CN_TX1 and CN_TX2.

[0078] The detection circuit 100 includes a first detection unit and a second detection unit, wherein the first detection unit is electrically connected to the first path, and the second detection unit is electrically connected to the second path; the first detection unit and the second detection unit respectively receive a first detection enable signal Test_cn and a second detection enable signal Test_cp; wherein the first detection unit and the second detection unit are configured to:

[0079] When both the first detection enable signal Test_cn and the second detection enable signal Test_cp are at a low level, the capacitive isolator 200 operates normally.

[0080] When either the first detection enable signal Test_cn or the second detection enable signal Test_cp is high, the capacitive isolator 200 enters a test mode. Specifically, when the first detection enable signal Test_cn is high and the second detection enable signal Test_cp is low, the output signal OUT of the capacitive isolator 200 is used to determine whether the bonding wires corresponding to the first capacitor bank are faulty. When the second detection enable signal Test_cp is high and the first detection enable signal Test_cn is low, the output signal OUT of the capacitive isolator 200 is used to determine whether the bonding wires corresponding to the second capacitor bank are faulty.

[0081] The first detection unit includes a first inverter 111 and a first AND gate 112; the second detection unit includes a second inverter 121 and a second AND gate 122.

[0082] The input terminal of the first inverter 111 is used to receive the first detection enable signal Test_cn, and the output terminal of the first inverter 111 is electrically connected to the first input terminal of the first AND gate 112.

[0083] The second input terminal of the first AND gate 112 is used to receive the first input signal; the output terminal of the first AND gate 112 outputs a first output signal.

[0084] The input terminal of the second inverter 121 is used to receive the second detection enable signal Test_cp, and the output terminal of the second inverter 121 is electrically connected to the first input terminal of the second AND gate 122;

[0085] The second input terminal of the second AND gate 122 is used to receive a second input signal; the output terminal of the second AND gate outputs a second output signal.

[0086] In one example, the transmitter chip 210 is an on-off keyed transmitter chip, that is, a transmitter chip that uses on-off keying (OOK) modulation. In this case, the first input signal and the second input signal are both the system input signal IN of the transmitter chip.

[0087] Specifically, the on / off keyed transmitter chip includes an oscillator (OSC) 201, the output signal of the oscillator 201 is used as the input signal of the first input terminal of the first path; the first output signal is used as the input signal of the second input terminal of the first path;

[0088] The output signal of the oscillator 201 is inverted by the third inverter 213 and used as the input signal of the first input terminal of the second path; the second output signal is used as the input signal of the second input terminal of the second path.

[0089] The first path includes a third AND gate 211 and a first buffer 212. The first input terminal and the second input terminal of the third AND gate 211 are respectively the first input terminal and the second input terminal of the first path. The output terminal of the third AND gate 211 is connected to the input terminal of the first buffer 212, and the output terminal of the first buffer 212 outputs the first differential signal CP_TX1.

[0090] The second path includes a fourth AND gate 214 and a second buffer 215. The first input terminal and the second input terminal of the fourth AND gate 214 are the first input terminal and the second input terminal of the second path, respectively. The output terminal of the fourth AND gate 214 is connected to the input terminal of the second buffer 215, and the output terminal of the second buffer 215 outputs the second differential signal CN_TX1.

[0091] about Figure 5 For the working principle of the detection circuit shown, please refer to [link / reference]. Figures 6A-6C ,in:

[0092] If both the first detection enable signal Test_cn and the second detection enable signal Test_cp are low, the capacitive isolator will operate normally. See details below. Figure 6A;

[0093] When either the first detection enable signal Test_cn or the second detection enable signal Test_cp is high, the system enters detection mode. Specifically:

[0094] If the first detection enable signal Test_cn is high and the second detection enable signal Test_cp is low, then the first differential signal CP_RX at the receiver corresponding to the first path will show no signal transmission. Under normal path conditions, the second differential signal CN_RX at the receiver corresponding to the second path will have normal transmission, and the output signal OUT at the output of the capacitive isolator will also have signal output. Figure 6B As shown; therefore, in this case, if the output signal OUT has a signal output, then the bond wire corresponding to the second path is normal. If, in this case, the output signal OUT does not have a signal output, as shown... Figure 6C As shown, the bonding wire corresponding to the second path fails (including disconnection or missing connection).

[0095] Similarly, if the first detection enable signal Test_cn is low and the second detection enable signal Test_cp is high, the condition of the output signal OUT can also be used to determine whether the bonding wire corresponding to the first path is normal or faulty.

[0096] Therefore, the bonding wire failure detection circuit for the capacitive isolator provided in this embodiment of the invention, by setting a first detection unit and a second detection unit, respectively under the control of corresponding enable signals, to detect the output signal at the output terminal of the capacitive isolator under the action of the system input signal, so as to determine whether the bonding wires corresponding to the first capacitor group and the second capacitor group are failed. Since the bonding wires corresponding to the first capacitor group and the second capacitor group can be detected alternately, the connection status of the two bonding wires can be accurately detected and judged.

[0097] Please continue to refer to this. Figure 7 , Figure 7 A schematic diagram illustrating the application of the detection circuit provided by this invention in another type of transmitter chip, specifically, as shown below. Figure 7 The transmitter chip 210 shown is an edge-triggered transmitter chip.

[0098] and Figure 5 Compared to the previously described embodiments, the only difference in this embodiment lies in the composition of the transmitter chip 210 and the input signal of the detection circuit 100; other aspects are the same. Figure 5 The embodiments shown are the same and will not be repeated here. Specifically, the differences are reflected in the following aspects:

[0099] The edge-triggered transmitter chip includes an edge trigger 202, the input of which is the system input signal IN of the transmitter chip.

[0100] The first path includes a third buffer 211; the output terminal of the edge trigger 202 is connected to the input terminal of the third buffer 211, and the output terminal of the third buffer 211 is used to output the first input signal to the second input terminal of the first AND gate 112; the first output signal output by the output terminal of the first AND gate 112 is used as the first differential signal CP_TX1.

[0101] The second path includes a fourth inverter 221; the output terminal of the edge-triggered trigger 202 is connected to the input terminal of the fourth inverter 221, and the output terminal of the fourth inverter 221 is used to output the second input signal to the second input terminal of the second AND gate 122; the second output signal output by the output terminal of the second AND gate 122 is used as the second differential signal CN_TX1.

[0102] in, Figure 7 The circuit shown is similar in principle to the circuit for detecting whether a bonding wire has failed. Figure 5 The circuit shown is the same, so it will not be described again.

[0103] Among them, Figure 5 and Figure 7 In the illustrated embodiment, the capacitive isolator is a dual-capacitor type, specifically the first capacitor group includes a first capacitor C11 and a second capacitor C12; the second capacitor group includes a third capacitor C21 and a fourth capacitor C22.

[0104] In practical use, the first capacitor C11 and the third capacitor C21 can be packaged in the transmitter chip, for example, and the second capacitor C12 and the fourth capacitor C22 can be packaged in the receiver chip, for example.

[0105] In addition, in practical use, the detection circuit 100 can usually be packaged in the transmitter chip.

[0106] Of course, it should be recognized that capacitive isolators can also be in the form of a single capacitor. For example, the first capacitor bank can include only one capacitor, specifically the first capacitor C11 or the second capacitor C12; at the same time, the second capacitor bank can also include only one capacitor, specifically the third capacitor C21 or the fourth capacitor C22.

[0107] The specific composition of each circuit module can be adapted to actual needs. This invention is not limited to this. As long as the technical concept of this invention is adopted, and a test mode and test circuit are introduced to detect the failure of the bonding wire, they cannot be separated from the protection of this invention.

[0108] Furthermore, the present invention also provides a method for detecting bond wire failure in a capacitive isolator, which utilizes the aforementioned bond wire failure detection circuit of the capacitive isolator to detect bond wire failure. The method includes:

[0109] When the first detection enable signal is set to high and the second detection enable signal is set to low, the output signal of the capacitive isolator is detected when the system input signal of the transmitter chip is normal; based on the output signal, it is determined whether the bonding wires corresponding to the first capacitor bank are faulty; and

[0110] When the second detection enable signal is set to high and the first detection enable signal is set to low, the output signal of the capacitive isolator is detected when the system input signal of the transmitter chip is normal; based on the output signal, it is determined whether the bonding wire corresponding to the second capacitor bank is faulty.

[0111] In addition, the present invention also provides an electronic device, including the bonding wire failure detection circuit of the capacitive isolator in the foregoing solution of the present invention and the capacitive isolator.

[0112] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A bonding wire failure detection circuit for a capacitive isolator, used to detect the bonding wires of the capacitive isolator package; wherein, The capacitive isolator includes a transmitter chip, a receiver chip, and a differential capacitor bank. The differential capacitor bank includes a first capacitor bank and a second capacitor bank. The transmitter chip includes a first path and a second path, which are used to form a differential signal pair. The differential signal pair includes a first differential signal and a second differential signal. The first differential signal and the second differential signal are transmitted to the receiver chip through the first capacitor bank and the second capacitor bank, respectively. The detection circuit includes a first detection unit and a second detection unit. The first detection unit is electrically connected to the first path, and the second detection unit is electrically connected to the second path. The first detection unit and the second detection unit respectively receive a first detection enable signal and a second detection enable signal. The first detection unit and the second detection unit are configured as follows: When both the first detection enable signal and the second detection enable signal are at a low level, the capacitive isolator operates normally. When either the first detection enable signal or the second detection enable signal is high, the capacitive isolator enters a test mode. Specifically, when the first detection enable signal is high and the second detection enable signal is low, the output signal at the output terminal of the capacitive isolator is used to determine whether the bonding wires corresponding to the first capacitor bank are faulty. When the second detection enable signal is high and the first detection enable signal is low, the output signal at the output terminal of the capacitive isolator is used to determine whether the bonding wires corresponding to the second capacitor bank are faulty.

2. The bonding wire failure detection circuit for a capacitive isolator according to claim 1, characterized in that, The first detection unit includes a first inverter and a first AND gate; the second detection unit includes a second inverter and a second AND gate. The input terminal of the first inverter is used to receive the first detection enable signal, and the output terminal of the first inverter is electrically connected to the first input terminal of the first AND gate; the second input terminal of the first AND gate is used to receive the first input signal. The first AND gate outputs a first output signal; The input terminal of the second inverter is used to receive the second detection enable signal, and the output terminal of the second inverter is electrically connected to the first input terminal of the second AND gate; the second input terminal of the second AND gate is used to receive the second input signal; and the output terminal of the second AND gate outputs a second output signal.

3. The bonding wire failure detection circuit for a capacitive isolator according to claim 2, characterized in that, The transmitter chip is an on / off keyed transmitter chip; the first input signal and the second input signal are both system input signals of the transmitter chip; The on / off keyed transmitter chip includes an oscillator, and the output signal of the oscillator is used as the input signal of the first input terminal of the first channel. The first output signal serves as the input signal to the second input terminal of the first path; The output signal of the oscillator is inverted by the third inverter and used as the input signal of the first input terminal of the second path; the second output signal is used as the input signal of the second input terminal of the second path.

4. The bond wire failure detection circuit for a capacitive isolator according to claim 3, characterized in that, The first path includes a third AND gate and a first buffer. The first input terminal and the second input terminal of the third AND gate are respectively the first input terminal and the second input terminal of the first path. The output terminal of the third AND gate is connected to the input terminal of the first buffer, and the output terminal of the first buffer outputs the first differential signal.

5. The bond wire failure detection circuit for a capacitive isolator according to claim 3, characterized in that, The second path includes a fourth AND gate and a second buffer. The first input terminal and the second input terminal of the fourth AND gate are respectively the first input terminal and the second input terminal of the second path. The output terminal of the fourth AND gate is connected to the input terminal of the second buffer, and the output terminal of the second buffer outputs the second differential signal.

6. The bonding wire failure detection circuit for a capacitive isolator according to claim 2, characterized in that, The transmitter chip is an edge-triggered transmitter chip; The edge-triggered transmitter chip includes an edge trigger, the input of which is the system input signal of the transmitter chip. The first path includes a third buffer; The output of the edge trigger is connected to the input of the third buffer, and the output of the third buffer is used to output the first input signal to the second input of the first AND gate; the first output signal output by the first AND gate is used as the first differential signal.

7. The bond wire failure detection circuit for a capacitive isolator according to claim 6, characterized in that, The second path includes a fourth inverter; The output terminal of the edge-triggered flip-flop is connected to the input terminal of the fourth inverter, and the output terminal of the fourth inverter is used to output the second input signal to the second input terminal of the second AND gate; the second output signal output by the output terminal of the second AND gate serves as the second differential signal.

8. The bond wire failure detection circuit for a capacitive isolator according to any one of claims 1-7, characterized in that, The first capacitor bank includes a first capacitor or the first capacitor bank includes a first capacitor and a second capacitor; The second capacitor bank includes a third capacitor or the second capacitor bank includes a third capacitor and a fourth capacitor.

9. A method for detecting bond wire failure in a capacitive isolator, comprising using the bond wire failure detection circuit of the capacitive isolator according to any one of claims 1-8 to detect bond wire failure, characterized in that, The method includes: When the first detection enable signal is set to high and the second detection enable signal is set to low, the output signal of the capacitive isolator is detected when the system input signal of the transmitter chip is normal; based on the output signal, it is determined whether the bonding wires corresponding to the first capacitor bank are faulty; and When the second detection enable signal is set to high and the first detection enable signal is set to low, the output signal of the capacitive isolator is detected when the system input signal of the transmitter chip is normal; based on the output signal, it is determined whether the bonding wire corresponding to the second capacitor bank is faulty.

10. An electronic device, characterized in that, The invention includes the bond wire failure detection circuit of the capacitive isolator according to any one of claims 1-8, and the capacitive isolator itself.

Images