FPGA timing model verification method and system

Abstract

The present invention provides an FPGA timing model verification method, including performing timing analysis on the timing model to generate a timing diagram, checking the timing diagram, and correcting the timing model according to the inspection result until the inspection result of the timing diagram is correct, the timing diagram can more accurately and comprehensively reflect the timing model, and any change of the timing model is reflected in the change of the timing diagram. Therefore, using the timing diagram as the calibration of the timing model can ensure accuracy and avoid the wrong introduction of the timing model, matching the timing arcs in the corrected timing model with the timing arcs in the timing library, correcting the timing model until all the timing arcs in the timing model match the timing arcs in the timing library, calculating the ratio of the number of timing arcs in the corrected timing model to the number of timing arcs in the timing library as the coverage rate, correcting the timing model until the coverage rate is 100%, and further ensuring the avoidance of the wrong introduction of the timing model through the coverage rate. The present invention also discloses an FPGA timing model verification system.

Description

Technical Field

[0001] The present invention relates to the field of FPGA technology, and in particular to an FPGA timing model verification method and system. Background Art

[0002] Static timing analysis is an important analysis method for evaluating the performance of Field Programmable Gate Array (FPGA) chips. As FPGA chips become more powerful, they integrate more and more functional modules, and each functional module can work in multiple functional modes. The above characteristics of FPGA chips will affect the timing information of the chip, and also put forward higher requirements for static timing analysis.

[0003] In the existing FPGA chip computer-aided design software technology, the timing information consists of a timing model and a timing library. The timing model appears in the hierarchical design and is generated by the chip design software. The timing model is abstract. How to convert the abstract timing model into an easy-to-read test calibration is the first problem that the test system needs to solve. The timing library is a file that describes the timing information of the chip. The timing library records all the timing information of the chip in the form of a timing arc. The timing library is usually provided by hardware design engineers and is repeatedly checked by software and hardware engineers to ensure the accuracy of the information in the timing library. The FPGA timing model associates the FPGA software with the timing library, and is usually provided by hardware designers separately by module. Deviations in the understanding of hardware design by software and hardware engineers will inevitably introduce errors into the timing model.

[0004] Therefore, it is necessary to provide a new FPGA timing model verification method and system to solve the above problems existing in the prior art. Summary of the invention

[0005] The purpose of the present invention is to provide a FPGA timing model verification method and system to reduce the introduced errors of the timing model.

[0006] To achieve the above object, the FPGA timing model verification method of the present invention includes:

[0007] Perform timing analysis on the timing model to generate a timing diagram;

[0008] Checking the timing diagram, and correcting the timing model according to the checking result, until the checking result of the timing diagram is correct;

[0009] Mark the timing arcs in the modified timing model, and match the timing arcs in the modified timing model with the timing arcs in the timing library. If the timing arcs in the modified timing model do not match the timing arcs in the timing library, modify the timing model according to the matching result until all the timing arcs in the modified timing model match the timing arcs in the timing library.

[0010] The ratio of the number of timing arcs in the modified timing model to the number of timing arcs in the timing library is calculated as the coverage rate. If the coverage rate is less than 100%, the timing model is modified according to the uncovered timing arcs in the timing library until the coverage rate reaches 100%.

[0011] The beneficial effects of the FPGA timing model verification method are: performing timing analysis on the timing model to generate a timing diagram, checking the timing diagram, and correcting the timing model according to the inspection result until the inspection result of the timing diagram is correct. The timing diagram can more accurately and comprehensively reflect the timing model, and any changes in the timing model are reflected in the changes in the timing diagram. Therefore, using the timing diagram as the calibration of the timing model can ensure accuracy and avoid the introduction of errors in the timing model. The timing arcs in the corrected timing model are marked, and the timing arcs in the corrected timing model are compared with those in the timing library. The timing arcs are matched; if the timing arcs in the timing model after correction do not match the timing arcs in the timing library, the timing model is corrected according to the matching result until all the timing arcs in the timing model after correction match the timing arcs in the timing library; the ratio of the number of timing arcs in the timing model after correction to the number of timing arcs in the timing library is calculated as the coverage rate; if the coverage rate is less than 100%, the timing model is corrected according to the uncovered timing arcs in the timing library until the coverage rate is 100%. The coverage rate can further ensure that the introduction of errors in the timing model is avoided.

[0012] Optionally, performing timing analysis on the timing model to generate a timing diagram includes:

[0013] Obtaining a circuit netlist of the timing model;

[0014] Marking timing nodes in the circuit netlist;

[0015] The timing diagram is generated according to the interconnection relationship of the timing nodes and the timing arcs.

[0016] Optionally, before performing timing analysis on the timing model to generate a timing diagram, the method includes:

[0017] Perform timing analysis on the timing model according to the working mode to generate a timing diagram.

[0018] Optionally, before performing timing analysis on the timing model to generate a timing diagram, the method includes:

[0019] Perform timing analysis on the timing model in a fully connected manner to generate a timing diagram.

[0020] Optionally, the calculating the ratio of the number of timing arcs in the modified timing model to the number of timing arcs in the timing library as coverage includes:

[0021] Counting the number of timing arcs in the timing library as a complete set;

[0022] Marking the timing arcs in the timing model, and then counting the number of timing arcs in the timing model as a collection;

[0023] The ratio of the entire set to the collection is calculated to obtain the coverage rate.

[0024] Optionally, the FPGA timing model verification method further includes a timing model acquisition step, and the timing model acquisition step includes:

[0025] Read the time series model from a fixed database.

[0026] Optionally, the FPGA timing model verification method further includes a fixed database generation step, and the fixed database generation step includes:

[0027] Save data at any completed stage in the circuit realization process as a fixed database.

[0028] Optionally, the storing of data at any completed stage in the circuit implementation process as a fixed database includes:

[0029] The data after the winding is completed in the circuit realization process is saved as a fixed database.

[0030] Optionally, before performing the timing analysis on the timing model to generate the timing diagram, a module division step is also included, and the module division step includes:

[0031] The circuit to be tested is divided into different functional modules according to the functions, and timing tests are performed on different functional modules respectively.

[0032] The present invention also discloses an FPGA timing model verification system, which is used to implement the FPGA timing model verification method. The timing test system includes a test module and a test evaluation module. The test module is used to perform timing analysis on the timing model to generate a timing diagram, then check the timing diagram, and correct the timing model according to the inspection result until the inspection result of the timing diagram is correct; the test evaluation module is used to mark the timing arcs in the corrected timing model, and match the timing arcs in the corrected timing model with the timing arcs in the timing library. If the timing arcs in the corrected timing model do not match the timing arcs in the timing library, the timing model is corrected according to the matching result until all the timing arcs in the corrected timing model match the timing arcs in the timing library, and the ratio of the number of timing arcs in the corrected timing model to the number of timing arcs in the timing library is calculated as the coverage rate. If the coverage rate is less than 100%, the timing model is corrected according to the uncovered timing arcs in the timing library until the coverage rate is 100%. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a flow chart of the FPGA timing model verification method of the present invention;

[0034] Figure 2 Schematic diagram of a circuit netlist in some embodiments of the present invention;

[0035] Figure 3 A schematic diagram of a circuit network after marking timing nodes in some embodiments of the present invention;

[0036] Figure 4 is a schematic diagram of a timing diagram in some embodiments of the present invention;

[0037] Figure 5 A schematic diagram of a circuit network in a first working mode in some embodiments of the present invention;

[0038] Figure 6 A schematic diagram of a circuit network in a second working mode in some embodiments of the present invention;

[0039] Figure 7 A schematic diagram of a fully connected circuit network in some embodiments of the present invention;

[0040] Figure 8 A block diagram of the working modes of modules in some embodiments of the present invention;

[0041] Fig. 9 Schematic diagram of a fully connected circuit network in some other embodiments of the present invention. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0043] In view of the problems existing in the prior art, an embodiment of the present invention provides a method for verifying an FPGA timing model. Figure 1 , the FPGA timing model verification method comprises the following steps:

[0044] S1: Perform timing analysis on the timing model to generate a timing diagram;

[0045] S2: Checking the timing diagram, and modifying the timing model according to the checking result, until the checking result of the timing diagram is correct;

[0046] S3: marking the timing arcs in the corrected timing model, and matching the timing arcs in the corrected timing model with the timing arcs in the timing library; if the timing arcs in the corrected timing model do not match the timing arcs in the timing library, correcting the timing model according to the matching result until all the timing arcs in the corrected timing model match the timing arcs in the timing library;

[0047] S4: Calculate the ratio of the number of timing arcs in the modified timing model to the number of timing arcs in the timing library as the coverage rate, and if the coverage rate is less than 100%, modify the timing model according to the timing arcs not covered in the timing library until the coverage rate is 100%. Wherein, when the timing arcs in the timing model match multiple timing arcs in the timing library, it is determined that the timing arcs in the timing model do not match the timing arcs in the timing library, and the timing arcs not covered in the timing library, that is, the timing arcs existing in the timing library, do not appear in the timing model.

[0048] In some embodiments, the timing model in step S3 is the timing model of the correct timing diagram finally obtained after executing step S2; if the timing arcs in the timing model after correction do not match the timing arcs in the timing library, the unmatched timing arcs are output, and the corresponding parts of the timing model are corrected, and then steps S1 to S3 are re-executed; when executing step S4, if the coverage rate is less than 100%, the timing arcs that do not exist in the timing library, that is, the timing arcs that are not covered by the timing library, are output, and the corresponding parts of the timing model are corrected, and then steps S1 to S4 are re-executed.

[0049] In some embodiments, the timing diagram may be checked manually, or the timing diagram may be compared with a timing diagram generated from data in a timing library to achieve the check.

[0050] In some embodiments, performing timing analysis on the timing model to generate a timing diagram includes:

[0051] Obtaining a circuit netlist of the timing model;

[0052] Marking timing nodes in the circuit netlist;

[0053] The timing diagram is generated according to the interconnection relationship of the timing nodes and the timing arcs.

[0054] In some embodiments, the timing diagram is generated according to the interconnection relationship and timing arcs of the timing nodes during static analysis, and contains a large amount of timing information, so it can accurately reflect the structure and timing model of the circuit netlist.

[0055] Figure 2 Schematic diagram of a circuit netlist in some embodiments of the present invention. Figure 2 , the figure includes the top-level port in1, the data port dia, the top-level port clk1, the clock port clka, the top-level port out1, and the data output port qa.

[0056] Figure 3 This is a schematic diagram of a circuit network after marking timing nodes in some embodiments of the present invention. Figure 3 , the top-level port in1 is marked as timing node ①, the data port dia is marked as timing node ②, the top-level port clk1 is marked as timing node ③, the clock port clka is marked as timing node ④, the data output port aq is marked as timing node ⑤, and the top-level port out1 is marked as timing node ⑥.

[0057] Figure 4 Schematic diagram of a timing diagram in some embodiments of the present invention. Figure 4, timing node ① and timing node ② are a timing path, and timing node ③, timing node ④, timing node ⑤ and timing node ⑥ are a timing path.

[0058] In some embodiments, before performing timing analysis on the timing model to generate a timing diagram, the process includes: performing timing analysis on the timing model according to the working mode to generate a timing diagram.

[0059] Figure 5 FIG. 1 is a schematic diagram of a circuit network in a first working mode in some embodiments of the present invention. Figure 5 , port dia and port qa are related to port clka, and port dib and port qb are related to port clkb.

[0060] Figure 6 FIG. 1 is a schematic diagram of a circuit network in the second working mode in some embodiments of the present invention. Figure 6 , port dia, port dib and port clka are related, and port qa, port qb and port clkb are related.

[0061] In some embodiments, before performing timing analysis on the timing model to generate a timing diagram, the process includes: performing timing analysis on the timing model in a fully connected manner to generate a timing diagram.

[0062] Figure 7 This is a schematic diagram of a fully connected circuit network in some embodiments of the present invention. When some timing arcs in a module exist objectively but the functions are not yet open, the subsequent coverage cannot reach 100% when the timing model is analyzed according to the working mode to generate a timing diagram. In this case, the fully connected method can be used to test these timing arcs that have not yet been opened. Figure 7 The module has port dia, port clka and port qa. Port dia is connected to the top-level module port in1, port clka is connected to the top-level module port clk1, and port qa is connected to the top-level module port out1.

[0063] Figure 8 FIG. 1 is a block diagram of the working modes of modules in some embodiments of the present invention. Figure 8 ,Module HRIO includes BYPASS working mode, SDR working mode, DDRX1 working mode, DDRX1_PIPE working mode, DDRX2 working mode, and DDRX2L working mode. ,The timing model is analyzed according to BYPASS working mode, SDR working mode, DDRX1 working mode, DDRX1_PIPE working mode, DDRX2 working mode, and DDRX2L working mode to generate six timing diagrams.

[0064] Fig. 9This is a schematic diagram of a fully connected circuit network in some other embodiments of the present invention. Fig. 9 ,Module HRIO has a total of 13 ports, which are port ce, port ts, port ipad, port doq, port rst, port ipclk, port opclk, port isclk, port osclk, port opad, port bpad, port dip and port di. Port ce is connected to the upper-level port in1, port ts is connected to the upper-level port in2, port ipad is connected to the upper-level port in3, port doq is connected to the upper-level port in4, port rst is connected to the upper-level port in5, port ipclk is connected to the upper-level port clk1, port opclk is connected to the upper-level port clk2, port isclk is connected to the upper-level port clk3, port osclk is connected to the upper-level port clk4, port opad is connected to the upper-level port out1, port bpad is connected to the upper-level port out2, port dip is connected to the upper-level port out3, and port di is connected to the upper-level port out4.

[0065] In some embodiments, timing analysis is performed on the timing model according to the working mode to generate a timing diagram, or timing analysis is performed on the timing model in a fully connected manner to generate a timing diagram. Both methods can ensure the accuracy of the timing model of the module in each working mode, and combined with the fully connected method can effectively improve the coverage.

[0066] In some embodiments, calculating the ratio of the number of timing arcs in the timing model after correction to the number of timing arcs in the timing library as coverage includes:

[0067] Counting the number of timing arcs in the timing library as a complete set;

[0068] Marking the timing arcs in the timing model, and then counting the number of timing arcs in the timing model as a collection;

[0069] The ratio of the entire set to the collection is calculated to obtain the coverage rate, thereby ensuring that all the timing arcs in the timing library appear in the timing model.

[0070] In some embodiments, the FPGA timing model verification method further includes a step of obtaining a timing model, and the step of obtaining a timing model includes: reading a timing model from a fixed database.

[0071] In some embodiments, the FPGA timing model verification method further includes a fixed database generation step, wherein the fixed database generation step includes: saving data at any completed stage in the circuit implementation process as a fixed database. Preferably, the data after the wiring is completed in the circuit implementation process is saved as a fixed database.

[0072] In some embodiments, before executing the timing analysis of the timing model to generate the timing diagram, a module division step is also included, and the module division step includes: dividing the circuit to be tested into different functional modules according to the function, and performing timing tests on different functional modules respectively. The FPGA chip contains a variety of functional modules, and the timing models of each functional module in different working modes are different. The diversity of modules and working modes makes it difficult to cover the timing model. After dividing the modules, testing according to the modules can facilitate engineers to track the progress of the test, so as to achieve the purpose of full coverage of the timing model of each module. In addition, the method of testing by module is also helpful to quickly locate the problem of the timing model during the regression test. During the regression test, the regression problem of a module often affects the test of a module, while the timing information of other modules remains unchanged. Engineers can quickly infer the problem through the changes of the tested modules, thereby shortening the timing repair cycle of the module.

[0073] The present invention also discloses an FPGA timing model verification system, which is used to implement the FPGA timing model verification method. The timing test system includes a test module and a test evaluation module. The test module is used to perform timing analysis on the timing model to generate a timing diagram, then check the timing diagram, and correct the timing model according to the inspection result until the inspection result of the timing diagram is correct; the test evaluation module is used to mark the timing arcs in the corrected timing model, and match the timing arcs in the corrected timing model with the timing arcs in the timing library. If the timing arcs in the corrected timing model do not match the timing arcs in the timing library, the timing model is corrected according to the matching result until all the timing arcs in the corrected timing model match the timing arcs in the timing library, and the ratio of the number of timing arcs in the corrected timing model to the number of timing arcs in the timing library is calculated as the coverage rate. If the coverage rate is less than 100%, the timing model is corrected according to the uncovered timing arcs in the timing library until the coverage rate is 100%.

[0074] Although the embodiments of the present invention are described in detail above, it is obvious to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein may have other embodiments and may be implemented or realized in a variety of ways.

Claims

1. A FPGA timing model verification method, characterized in that: include: Performing timing analysis on the timing model to generate a timing diagram, including: obtaining a circuit netlist of the timing model; marking timing nodes in the circuit netlist; generating the timing diagram according to the interconnection relationship of the timing nodes and the timing arcs in the timing model; Checking the timing diagram, and correcting the timing model according to the checking result, until the checking result of the timing diagram is correct; Mark the timing arcs in the modified timing model, and match the timing arcs in the modified timing model with the timing arcs in the timing library. If the timing arcs in the modified timing model do not match the timing arcs in the timing library, modify the timing model according to the matching result until all the timing arcs in the modified timing model match the timing arcs in the timing library. The ratio of the number of timing arcs in the corrected timing model to the number of timing arcs in the timing library is calculated as the coverage rate. If the coverage rate is less than 100%, the timing model is corrected according to the uncovered timing arcs in the timing library until the coverage rate reaches 100%.

2. The FPGA timing model verification method according to claim 1, characterized in that: Before performing timing analysis on the timing model to generate a timing diagram, the following steps are included: Perform timing analysis on the timing model according to the working mode to generate a timing diagram.

3. The FPGA timing model verification method according to claim 1, characterized in that: Before performing timing analysis on the timing model to generate a timing diagram, the following steps are included: Perform timing analysis on the timing model in a fully connected manner to generate a timing diagram.

4. The FPGA timing model verification method according to claim 1, characterized in that: The calculating the ratio of the number of timing arcs in the timing model after correction to the number of timing arcs in the timing library as coverage includes: Counting the number of timing arcs in the timing library as a complete set; Marking the timing arcs in the timing model, and then counting the number of timing arcs in the timing model as a collection; The ratio of the entire set to the collection is calculated to obtain the coverage rate.

5. The FPGA timing model verification method according to claim 1, characterized in that: The step of obtaining a timing model is also included, and the step of obtaining a timing model includes: Read the time series model from a fixed database.

6. The FPGA timing model verification method according to claim 5, characterized in that: The fixed database generation step is also included, and the fixed database generation step includes: Save data at any completed stage in the circuit realization process as a fixed database.

7. The FPGA timing model verification method according to claim 6, characterized in that: The data of any completed stage in the circuit implementation process is saved as a fixed database, including: The data after the winding is completed in the circuit realization process is saved as a fixed database.

8. The FPGA timing model verification method according to claim 1, characterized in that: Before performing the timing analysis on the timing model to generate the timing diagram, a module division step is also included, and the module division step includes: The circuit to be tested is divided into different functional modules according to the functions, and timing tests are performed on different functional modules respectively.

9. An FPGA timing model verification system, characterized in that: The FPGA timing model verification system is used to implement the FPGA timing model verification method as described in any one of claims 1 to 8, wherein the FPGA timing model verification system includes a test module and a test evaluation module, wherein the test module is used to perform timing analysis on the timing model to generate a timing diagram, including: obtaining a circuit netlist of the timing model; marking timing nodes in the circuit netlist; generating the timing diagram according to the interconnection relationship of the timing nodes and the timing arcs in the timing model; then checking the timing diagram, and correcting the timing model according to the check result until the check result of the timing diagram is correct; and the test evaluation module is used to mark the corrected timing model. The timing arcs in the timing model are matched with the timing arcs in the timing library after correction. If the timing arcs in the timing model after correction do not match the timing arcs in the timing library, the timing model is corrected according to the matching result until all the timing arcs in the timing model after correction match the timing arcs in the timing library. The ratio of the number of timing arcs in the timing model after correction to the number of timing arcs in the timing library is calculated as the coverage rate. If the coverage rate is less than 100%, the timing model is corrected according to the uncovered timing arcs in the timing library until the coverage rate is 100%.

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