Adaptive frequency electronic tag data decoding method, system, device and medium

Abstract

The present invention discloses an adaptive frequency electronic tag data decoding method, system, computer device and computer readable storage medium, including the steps of obtaining a pulse signal sent by an electronic tag, determining the pulse width of each pulse in the pulse signal, obtaining a pulse width sequence, determining the intermediate frequency pulse width according to the pulse width sequence, performing multiple rounds of pulse width bit width conversion processes, performing multiple rounds of bit width byte conversion processes, converting the bit time data sequence into byte data, etc. The present invention can convert the pulse signal sent by the electronic tag into byte data by performing a pulse width bit width conversion process and a bit width byte conversion process on the pulse width sequence corresponding to the pulse signal, wherein the intermediate frequency pulse width corresponding to the pulse signal is determined, and the bit value corresponding to the pulse width sequence is judged according to the intermediate frequency pulse width in the pulse width bit width conversion process, so as to adapt to pulse signals of different frequencies, thereby realizing frequency adaptation of the reader / writer. The present invention is widely used in the field of near field communication technology.

Description

Technical Field

[0001] The present invention relates to the field of near field communication technology, and in particular to a method, system, computer device and computer-readable storage medium for decoding electronic tag data with an adaptive frequency. Background Art

[0002] Radio Frequency Identification (RFID) is an automatic identification technology and near field communication technology. It uses radio frequency to carry out non-contact two-way data communication and read and write recording media (electronic tags or radio frequency cards) to achieve target identification and data exchange. It is an information technology with development potential.

[0003] The working principle of radio frequency identification technology can be explained through half-duplex (HDX) technology. Half-duplex (HDX) technology is a communication method between tags and readers specified in ISO11784 / 11785. In HDX technology, the reader first turns on the RF field to charge the tag to activate the tag, and then turns off the magnetic field. The tag transmits data to the reader when the reader's magnetic field is turned off. Compared with full-duplex (FDX), HDX usually has stronger recognition capabilities because the RF field of the HDX reader is turned off during the HDX tag response period, so that the reader can focus on receiving signals from the tag, while also eliminating the interference of the reader's RF field on the tag signal. Reference Figure 1 HDX uses frequency shift keying (FSK) technology, using a frequency of 124.2KHz to send data "1" and a frequency of 134.2KHz to send data "0". The data transmission rate is about 8Kbps, which is basically twice that of FDX (Full Duplex). In actual operation, the reader keeps the RF field open for at least 50 milliseconds to activate the tag. Within 3 milliseconds after the reader turns off the RF field, the tag starts to send back identification data.

[0004] In the existing technical solutions, when identifying the data sent back by the tag, the working frequency of the HDX tag is usually pre-set in the program. During use, decoding is performed only according to the set frequency. This results in that if the tag frequency deviates, decoding will be completely impossible. For example, if the data representing the bit "1" sent by the HDX tag becomes 145KHz when it reaches the reader due to environmental interference or changes in the HDX tag process standards, the reader will not be able to identify the data sent by the HDX tag according to the original rule of "124.2KHz represents bit 1, 134.2KHz represents bit 0". Summary of the invention

[0005] In view of the technical problems in the current radio frequency identification technology such as poor adaptability to the frequency of signals sent by electronic tags, the purpose of the present invention is to provide a method, system, computer device and computer-readable storage medium for decoding electronic tag data with adaptive frequency.

[0006] On the one hand, an embodiment of the present invention includes a method for decoding electronic tag data with an adaptive frequency, comprising:

[0007] The method for decoding electronic tag data with adaptive frequency includes:

[0008] Obtain the pulse signal sent by the electronic tag;

[0009] Determine the pulse width of each pulse in the pulse signal to obtain a pulse width sequence; the pulse width sequence is for sequentially reading out two pulse widths each time;

[0010] According to the pulse width sequence, determining a high frequency pulse width, a low frequency pulse width and a medium frequency pulse width;

[0011] Perform multiple rounds of pulse width bit width conversion process until all pulse widths are read out from the pulse width sequence; in any round of the pulse width bit width conversion process, read out two pulse widths corresponding to this round of the pulse width bit width conversion process from the pulse width sequence, determine the current time count value according to the read two pulse widths and the time count value corresponding to the previous round of the pulse width bit width conversion process, the current time count value is the time count value corresponding to this round of the pulse width bit width conversion process, determine the bit value corresponding to the current time count value according to the size relationship between the current time count value and the intermediate frequency pulse width, and write the current time count value into the bit time A data sequence, wherein the bit time data sequence sequentially records the bit values ​​added in each round of the pulse width to bit width conversion process, and obtains a same-frequency count and a different-frequency count of the bit time data sequence, wherein the same-frequency count is a count of a time count value in the bit time data sequence having the same signal frequency as that corresponding to the current time count value, and the different-frequency count is a count of a time count value in the bit time data sequence having a signal frequency different from that corresponding to the current time count value, and when the same-frequency count is 0, the different-frequency count is overwritten and saved in the initial value of the compensation coefficient, the same-frequency count is increased, and the different-frequency count is cleared;

[0012] When there is no error in the bit-time data sequence, multiple rounds of bit-width byte conversion processes are performed; in any round of the bit-width byte conversion process, the compensation coefficient value is determined according to the initial value of the compensation coefficient, the bit value corresponding to the round of the bit-width byte conversion process is read from the bit-time data sequence, the number of bits is determined according to the read bit value, the compensation coefficient value and the high-frequency pulse width, and a shift operation is performed on the bit-time data sequence according to the bit number to convert the bit-time data sequence into byte data.

[0013] Furthermore, the adaptive frequency electronic tag data decoding method further includes:

[0014] Perform CRC check on the byte data.

[0015] Further, performing CRC check on the byte data includes:

[0016] Divide the byte data into a plurality of byte blocks; each of the byte blocks comprises 13 bytes;

[0017] Obtain a first CRC value and a second CRC value corresponding to the same byte block; the first CRC value is a CRC value of bytes 0-7 in the byte block, and the second CRC value is a CRC value of bytes 0-10 in the byte block;

[0018] Compare the first CRC value with the 8th to 9th bytes in the byte block, and compare the second CRC value with the 11th to 12th bytes in the byte block,

[0019] When the first CRC value is the same as the 8th-9th bytes in the byte block, and the second CRC value is the same as the 11th-12th bytes in the byte block, it is determined that the byte block is correct, otherwise, it is determined that the byte block is wrong. Further, the high-frequency pulse width, the low-frequency pulse width and the medium-frequency pulse width are determined according to the pulse width sequence, including:

[0020] averaging the 20th to 120th pulse widths in the pulse width sequence, and using the average value as the high-frequency pulse width;

[0021] Adding a fixed value to the high-frequency pulse width, and using the result as the low-frequency pulse width;

[0022] The arithmetic mean of the high-frequency pulse width and the low-frequency pulse width is determined, and the obtained result is used as the medium-frequency pulse width.

[0023] Furthermore, the adaptive frequency electronic tag data decoding method further includes:

[0024] In any round of the pulse width bit width conversion process, the same frequency count is modulo-calculated, and the bit value corresponding to the current time count value is maintained or jumped according to the modulo-calculated result.

[0025] Further, the modulo the same frequency count, and determining to maintain or jump the bit value corresponding to the current time count value according to the modulo result, includes:

[0026] Taking the same frequency count modulo 16;

[0027] When the modulo result is greater than 13, the bit value corresponding to the current time count value is jumped, otherwise, the bit value corresponding to the current time count value is maintained.

[0028] Further, when the bit time data sequence does not have an error, it includes:

[0029] Detecting the bit time data sequence;

[0030] When it is detected that there is a frame header in the bit time data sequence, it is determined that there is no error in the bit time data sequence, otherwise, it is determined that there is an error in the bit time data sequence.

[0031] On the other hand, an embodiment of the present invention further includes an adaptive frequency electronic tag data decoding system, the adaptive frequency electronic tag data decoding system includes a driving chip, a push-pull circuit, a resonant circuit, an antenna, an amplifying circuit, a frequency discriminator, a comparator and a single-chip microcomputer; the single-chip microcomputer is sequentially connected to the driving chip, the push-pull circuit, the resonant circuit and the antenna, and the antenna is sequentially connected to the frequency discriminator, the comparator and the single-chip microcomputer;

[0032] The single chip microcomputer is used to generate an activation signal, and output the activation signal to the antenna through the driving chip, the push-pull circuit and the resonant circuit in sequence;

[0033] The antenna is used to send the activation signal to the electronic tag, receive the pulse signal sent by the electronic tag, and send the pulse signal to the single-chip microcomputer through the frequency detector and the comparator in sequence;

[0034] The single chip microcomputer is used to execute the adaptive frequency electronic tag data decoding method in the embodiment and process the pulse signal.

[0035] On the other hand, an embodiment of the present invention also includes a computer device, including a memory and a processor, wherein the memory is used to store at least one program, and the processor is used to load the at least one program to execute the adaptive frequency electronic tag data decoding method in the embodiment.

[0036] On the other hand, an embodiment of the present invention further includes a computer-readable storage medium, in which a program executable by a processor is stored. When the program executable by the processor is executed by the processor, it is used to execute the adaptive frequency electronic tag data decoding method in the embodiment.

[0037] The beneficial effects of the present invention are as follows: the adaptive frequency electronic tag data decoding method in the embodiment can convert the pulse signal sent by the electronic tag into byte data by executing a pulse width-to-bit width conversion process and a bit width-to-byte conversion process on the pulse width sequence corresponding to the pulse signal, wherein the intermediate frequency pulse width corresponding to the pulse signal is determined, and the bit value corresponding to the pulse width sequence is judged according to the intermediate frequency pulse width during the pulse width-to-bit width conversion process, so that it can adapt to pulse signals of different frequencies, thereby realizing frequency adaptation of the reader / writer. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a schematic diagram of the HDX sending a signal through frequency shift keying in the embodiment;

[0039] Figure 2 It is a structural schematic diagram of the electronic tag data decoding system with adaptive frequency in the embodiment;

[0040] Figure 3 This is a flow chart of the steps of receiving and collecting tag data in the embodiment;

[0041] Figure 4 Flow chart of the initial data processing steps in the embodiment;

[0042] Figure 5 A flowchart of the steps of converting pulse width into bit width in an embodiment;

[0043] Figure 6 A schematic diagram of the principle of converting pulse width into bit width in an embodiment;

[0044] Figure 7 FIG. 4 is a flowchart of steps for converting bit width into bytes in an embodiment. DETAILED DESCRIPTION

[0045] In this embodiment, use Figure 2 The adaptive frequency electronic tag data decoding system shown in the figure performs the adaptive frequency electronic tag data decoding method. Figure 2 The frequency-adaptive electronic tag data decoding system shown can be used as a reader / writer in conjunction with electronic tags such as HDX tags.

[0046] Reference Figure 2, the adaptive frequency electronic tag data decoding system includes a driving chip, a push-pull circuit, a resonant circuit, an antenna, an amplifying circuit, a discriminator, a comparator and a single-chip microcomputer; the single-chip microcomputer is connected to the driving chip, the push-pull circuit, the resonant circuit and the antenna in sequence, and the antenna is connected to the discriminator, the comparator and the single-chip microcomputer in sequence. In this embodiment, the push-pull circuit is a half-bridge push-pull circuit, the resonant circuit is an LC resonant circuit, a common-mode suppression inductor is provided between the resonant circuit and the antenna, and a limiting circuit and an amplifying circuit are provided between the antenna and the discriminator. In this embodiment, the adaptive frequency electronic tag data decoding system is also provided with an antenna insertion detection circuit, which is used to detect the access of the antenna and convert the access and removal of the antenna into a switch signal that can be recognized by the single-chip microcomputer.

[0047] Figure 2 In the process, the single-chip microcomputer is used to generate an activation signal, which is then output to the antenna through the driver chip, push-pull circuit, and resonant circuit in sequence; the antenna is used to send an activation signal to the electronic tag, receive the pulse signal sent by the electronic tag, and send the pulse signal to the single-chip microcomputer through the discriminator and comparator in sequence. Specifically, a 134KHz square wave is output from the single-chip microcomputer, and the driving capability is enhanced by the driver chip and the half-bridge push-pull circuit. The signal is amplified to about 60V using an LC resonant circuit, and radiated through the antenna to activate the HDX tag. After activating the HDX tag, the single-chip microcomputer stops outputting the 134KHz square wave, reduces the antenna voltage to 0V, and receives the data signal returned by the HDX tag. The data signal returned by the HDX tag has Figure 1 The pulse form shown can be called a pulse signal. The pulse signal received by the antenna is amplified by the limiter circuit and the amplifier circuit. The pulse signal after secondary amplification is input into the frequency discrimination amplifier, and the clutter is filtered out and amplified again for output. Finally, the comparator is used to shape the signal into a square wave and input it into the single-chip microcomputer. The single-chip microcomputer executes the adaptive frequency electronic tag data decoding method to decode the pulse signal.

[0048] In this embodiment, the method for decoding electronic tag data with adaptive frequency includes the following steps:

[0049] S1. Obtain the pulse signal sent by the electronic tag;

[0050] S2. Determine the pulse width of each pulse in the pulse signal to obtain a pulse width sequence; the pulse width sequence is for reading out two pulse widths in sequence each time;

[0051] S3. Determine the high frequency pulse width, low frequency pulse width and medium frequency pulse width according to the pulse width sequence;

[0052] S4. Execute multiple rounds of pulse width bit width conversion process until all pulse widths are read out from the pulse width sequence; in any round of pulse width bit width conversion process, read out two pulse widths corresponding to this round of pulse width bit width conversion process from the pulse width sequence, determine the current time count value according to the two pulse widths read out and the time count value corresponding to the previous round of pulse width bit width conversion process, the current time count value is the time count value corresponding to this round of pulse width bit width conversion process, determine the bit value corresponding to the current time count value according to the size relationship between the current time count value and the intermediate frequency pulse width, and write the current time count value into the ratio The bit time data sequence records the bit values ​​added in each round of pulse width bit width conversion process in sequence, and obtains the same frequency count and different frequency count of the bit time data sequence. The same frequency count is the count of the time count value with the same signal frequency corresponding to the current time count value in the bit time data sequence, and the different frequency count is the count of the time count value with the same signal frequency corresponding to the current time count value in the bit time data sequence. When the same frequency count is 0, the different frequency count is overwritten and saved in the initial value of the compensation coefficient, the same frequency count is increased, and the different frequency count is cleared;

[0053] S5. When there is no error in the bit-time data sequence, perform multiple rounds of bit-width byte conversion processes; in any round of bit-width byte conversion processes, determine the compensation coefficient value according to the initial value of the compensation coefficient, read the bit value corresponding to the round of bit-width byte conversion process from the bit-time data sequence, determine the number of bits according to the read bit value, compensation coefficient value and high-frequency pulse width, perform a shift operation on the bit-time data sequence according to the number of bits, and convert the bit-time data sequence into byte data;

[0054] S6. Perform CRC check on the byte data.

[0055] In this embodiment, steps S1-S6 can be performed by Figure 2 The adaptive frequency electronic tag data decoding system shown is executed by a single chip microcomputer.

[0056] In this embodiment, step S1 is a tag data receiving and collecting step, and its specific process is as follows: Figure 3 First, the MCU sends a 134KHz carrier wave for 100ms through the antenna to activate the electronic tag. After the transmission is completed, the carrier wave transmission is turned off, and the external interrupt DMA is enabled. After 50ms of receiving, the receiving program is turned off, the data collection is stopped, and the tag data receiving and collection steps are ended.

[0057] In this embodiment, steps S2-S3 are the initial data processing steps, which can obtain the tag frequency. The specific process of steps S2-S3 is as follows: Figure 4 As shown, the process node "A" is Figure 3In step S2, when the single-chip microcomputer receives each pulse in the pulse signal through DMA, the time when the rising edge or falling edge of a pulse is received is recorded by the timer, so the pulse width of the pulse can be obtained by calculating the time difference between two adjacent rising edges or falling edges of a pulse. By determining the pulse width of each pulse in the pulse signal, a sequence consisting of multiple pulse widths, namely a pulse width sequence, can be obtained.

[0058] After the pulse width sequence is obtained, each pulse width in the pulse width sequence may be stored in the array InData[] in order.

[0059] Reference Figure 4 When executing step S3, that is, determining the high frequency pulse width, the low frequency pulse width and the medium frequency pulse width according to the pulse width sequence, the following steps may be specifically performed:

[0060] S301. Calculate the average value of the 20th to 120th pulse widths in the pulse width sequence, and use the result as the high-frequency pulse width;

[0061] S302. Add a fixed value to the high frequency pulse width, and use the result as the low frequency pulse width;

[0062] S303. Determine the arithmetic mean of the high-frequency pulse width and the low-frequency pulse width, and use the result as the medium-frequency pulse width.

[0063] Reference Figure 4 In step S301, the sum of the 20th to 120th pulse widths in the pulse width sequence can be divided by 50, and the result obtained is used as the high frequency pulse width. The 20th to 120th pulse widths in step S301 are where the start frame in the tag HDX protocol is 1, so the pulse width corresponding to the high frequency can be determined by the fixed value of the 20th to 120th pulse width in the pulse width sequence.

[0064] In step S302, the high frequency pulse width calculated in step S301 can be added to 12, and the result obtained is used as the low frequency pulse width. In step S303, the sum of the high frequency pulse width calculated in step S301 and the low frequency pulse width calculated in step S302 can be divided by 2, and the result obtained is used as the medium frequency pulse width.

[0065] In this embodiment, the high frequency pulse width obtained in step S301 can be stored in a variable HighFreq, the low frequency pulse width obtained in step S302 can be stored in a variable LowFreq, and the medium frequency pulse width obtained in step S303 can be stored in a variable MidFreq.

[0066] The high-frequency pulse width HighFreq calculated by steps S301-S303 can represent the pulse width of the signal with a higher frequency in the pulse signal, which generally represents the bit "0", and the low-frequency pulse width LowFreq can represent the pulse width of the signal with a lower frequency in the pulse signal, which generally represents the bit "1". The medium-frequency pulse width MidFreq, as the average value of the high-frequency pulse width HighFreq and the low-frequency pulse width LowFreq, can be used as a judgment criterion to judge whether the pulse belongs to the high-frequency pulse width HighFreq or the low-frequency pulse width LowFreq according to the size relationship between the pulse width of a pulse and the medium-frequency pulse width MidFreq.

[0067] In this embodiment, step S4 is a step of converting the pulse width into the bit width. The specific process of step S4 is as follows: Figure 5 As shown, the process node "B" is Figure 4 The process nodes shown by "B" are connected.

[0068] In step S4, multiple rounds of pulse width bit width conversion processes are performed, and in each round of pulse width bit width conversion process, two pulse widths are read out from the pulse width sequence InData[] for processing. Figure 5 The steps of the pulse width bit width conversion process are shown in FIG. Since the principles of each pulse width bit width conversion process are the same, they can all be Figure 6 As shown, the pulse width is converted into the bit width, so one round of pulse width to bit width conversion process can be described.

[0069] Reference Figure 5 In any round of pulse width bit width conversion process, two pulse widths corresponding to this round of pulse width bit width conversion process are read from the pulse width sequence InData[], namely, InData[i] and InData[i+1], where i is a counting variable, and after each round of pulse width bit width conversion process is executed, i=i+2, so that two different pulse widths are read in each round of pulse width bit width conversion process. According to the read two pulse widths InData[i] and InData[i+1] and the time count value Timesum corresponding to the previous round of pulse width bit width conversion process, the time count value corresponding to this round of pulse width bit width conversion process, namely, the current time count value, is determined, which is equivalent to executing the operation Timesum=(Timesum+InData[i]+InData[i+1]) / 2, and obtaining the updated time count value Timesum, which is the current time count value.

[0070] The current time count value Timesum corresponding to the current pulse width bit width conversion process is calculated according to the time count value Timesum corresponding to the previous pulse width bit width conversion process and the two pulse widths InData[i] and InData[i+1] read out in the current pulse width bit width conversion process, and the current time count value Timesum obtained is equivalent to the smoothed pulse width. When executing the first round of pulse width bit width conversion process, if there is no time count value Timesum corresponding to the previous round of pulse width bit width conversion process, the time count value Timesum can be set to the two pulse widths InData[0] or InData[1] read out in the first round of pulse width bit width conversion process.

[0071] Reference Figure 5 , in any round of pulse width bit width conversion process, according to the size relationship between the current time count value Timesum and the medium frequency pulse width MidFreq, determine the bit value corresponding to the current time count value Timesum. Specifically, if the current time count value Timesum is greater than the medium frequency pulse width MidFreq, it indicates that the pulse width of the pulse corresponding to the current time count value Timesum is close to the high frequency pulse width HighFreq, and the bit value "0" is usually represented by a high frequency pulse, so it can be determined that in this round of pulse width bit width conversion process, the pulse corresponding to the time count value Timesum to be identified represents the bit value "0"; if the current time count value Timesum is less than the medium frequency pulse width MidFreq, it indicates that the pulse width of the pulse corresponding to the current time count value Timesum is close to the low frequency pulse width LowFreq, and the bit value "1" is usually represented by a low frequency pulse, so it can be determined that in this round of pulse width bit width conversion process, the pulse corresponding to the time count value Timesum to be identified represents the bit value "1".

[0072] In this embodiment, refer to Figure 5 After executing a round of pulse width bit width conversion process and determining that the bit value is Bit=0 or Bit=1, the current time count value Timesum is written into the bit time data sequence BitTimeData. The bit time data sequence BitTimeData also records the time count value Timesum identified by the previous rounds of pulse width bit width conversion process.

[0073] In this embodiment, refer to Figure 5, obtain the same frequency count and different frequency count of the bit time data sequence BitTimeData. Among them, the same frequency count is the count of the time count value in the bit time data sequence with the same pulse frequency as the current time count value Timesum, and the different frequency count is the count of the bit value in the bit time data sequence with a different pulse frequency from the current time count value Timesum. For example, if the bit value corresponding to the current time count value Timesum is "1", then the pulse corresponding to this bit value is a low-frequency pulse, so the same frequency count is a low-frequency count, which can represent the count of the bit value of 1 in the bit time data sequence BitTimeData, and the different frequency count is a high-frequency count, which can represent the count of the bit value of 0 in the bit time data sequence BitTimeData.

[0074] In this embodiment, when the same frequency count is 0, the different frequency count is overwritten and saved in the compensation coefficient initial value TimeNumComp, the same frequency count is increased, and the different frequency count is cleared. Figure 5 After writing the current time count value Timesum (corresponding to the low-frequency pulse signal) representing the bit value 1 into the bit time data sequence BitTimeData[k], without jumping, when the low-frequency count is 0, the high-frequency count is overwritten and saved to the compensation coefficient initial value TimeNumComp, the low-frequency count is increased (low-frequency count + 1), and the high-frequency count is cleared; refer to Figure 5 After writing the current time count value Timesum representing the bit value 0 (corresponding to the high-frequency pulse signal) into the bit time data sequence BitTimeData[k], in the case of a jump, the current time count value Timesum becomes the bit value 1 (corresponding to the low-frequency pulse signal). When the low-frequency count is 0, the high-frequency count is overwritten and saved in the compensation coefficient initial value TimeNumComp, the low-frequency count is increased (low-frequency count + 1), and the high-frequency count is cleared.

[0075] In this embodiment, during any round of pulse width bit width conversion, the same frequency count is modulo, and the bit value corresponding to the current time count value is maintained or jumped according to the modulo result. Figure 5, if the current time count value Timesum represents a bit value of 1 (corresponding to a low-frequency pulse signal), the high-frequency count is modulo, specifically, the high-frequency count is modulo 16, and it is determined whether the modulo result is greater than 13. If the modulo result is greater than 13, the variable BitSta_H is set to 1, allowing the current time count value Timesum to represent a bit value that jumps from 1 to 0. By jumping, errors caused by phase offset mixed with one or two low-frequency waveforms in a bunch of high-frequency waveforms, or errors caused by phase offset mixed with one or two high-frequency waveforms in a bunch of low-frequency waveforms can be corrected.

[0076] In this embodiment, steps S5 and S6 are steps for converting the bit width into bytes. The specific process of steps S5 and S6 is as follows: Figure 7 As shown, the process node "C" is Figure 5 The process nodes shown by "C" are connected.

[0077] When executing step S5, the bit time data sequence BitTimeData[k] can be detected to determine whether there is a frame header in the bit time data sequence BitTimeData[k]. Generally speaking, the frame header is fixed to 01111110, so it can be determined whether there is an element (time count value Timesum) in the bit time data sequence BitTimeData[k] that is greater than 4 times the high frequency pulse width HighFreq and less than 7 times the high frequency pulse width HighFreq within the total length of 3ms. If it is determined from the beginning that the total length of the data is greater than 3ms, it is considered that there is no frame header and the bit time data sequence BitTimeData[k] has an error. Otherwise, it is considered that there is a frame header in the bit time data sequence BitTimeData[k] and there is no error in the bit time data sequence BitTimeData[k].

[0078] Reference Figure 7In step S5, during any round of bit width byte conversion, the compensation coefficient value TimeComp is determined according to the compensation coefficient initial value TimeNumComp. Specifically, if the bit value corresponding to a time count value Timesum in the bit time data sequence BitTimeData[k] is 0, the compensation coefficient value TimeComp is calculated by TimeComp=14-(TimeNumComp / 6.0 / 100); if the bit value corresponding to a time count value Timesum in the bit time data sequence BitTimeData[k] is 1, the compensation coefficient value TimeComp is calculated by TimeComp=TimeNumComp / 6.0 / 100. Next, according to the read bit value BitTimeData, the compensation coefficient value TimeComp and the high frequency pulse width HighFreq, the bit number BitNum is determined by the formula BitNum=(HighFreq+TimeComp) / BitTimeData.

[0079] After obtaining the bit number BitNum, a bit shift operation is performed on the bit time data sequence BitTimeData[k] according to the bit number BitNum to convert the bit time data sequence into byte data. Figure 7 , use the high frequency pulse width HighFreq plus the compensation coefficient value TimeComp and divide it with the Bit time data BitTimeData to get BitNum, which indicates how many bits the data corresponds to. Then take the remainder of BitNum to determine whether the remainder exceeds the high frequency pulse width HighFreq plus half of the compensation coefficient value TimeComp. If it exceeds, add 1 to BitNum, otherwise do not operate. After obtaining BitNum, convert Bit to byte through bit shift operation.

[0080] In step S6, a CRC check is performed on the byte data. Specifically, the following steps can be performed:

[0081] S601. Divide the byte data into multiple byte blocks; each byte block includes 13 bytes;

[0082] S602. Obtain the first CRC value and the second CRC value corresponding to the same byte block; the first CRC value is the CRC value of the 0th to 7th bytes in the byte block, and the second CRC value is the CRC value of the 0th to 10th bytes in the byte block;

[0083] S603. Compare the first CRC value with the 8th-9th bytes in the byte block, and compare the second CRC value with the 11th-12th bytes in the byte block.

[0084] S604. When the first CRC value is the same as the 8th-9th bytes in the byte block, and the second CRC value is the same as the 11th-12th bytes in the byte block, it is determined that the byte block is correct; otherwise, it is determined that the byte block is wrong.

[0085] In step S604, if a byte block is determined to be correct, then the byte block is returned; if a byte block is determined to be erroneous, then a corresponding error code is returned.

[0086] A computer program that executes the adaptive frequency electronic tag data decoding method in this embodiment can be written and written into a computer device or a computer-readable storage medium. When the computer program is read out and run, the adaptive frequency electronic tag data decoding method in this embodiment is executed, thereby achieving the same technical effect as the adaptive frequency electronic tag data decoding method in the embodiment.

[0087] It should be noted that, unless otherwise specified, when a feature is referred to as "fixed" or "connected" to another feature, it may be directly fixed or connected to another feature, or it may be indirectly fixed or connected to another feature. In addition, the descriptions of up, down, left, right, etc. used in this disclosure are only relative to the relative positional relationship of the components of the present disclosure in the accompanying drawings. The singular forms of "a", "said" and "the" used in this disclosure are also intended to include the plural forms, unless the context clearly indicates other meanings. In addition, unless otherwise defined, all technical and scientific terms used in this embodiment have the same meaning as those generally understood by technicians in this technical field. The terms used in the specification of this embodiment are only for describing specific embodiments, not for limiting the present invention. The term "and / or" used in this embodiment includes any combination of one or more related listed items.

[0088] It should be understood that, although the term first, second, third etc. may be adopted to describe various elements in the present disclosure, these elements should not be limited to these terms. These terms are only used to distinguish the same type of elements from each other. For example, without departing from the scope of the present disclosure, the first element may also be referred to as the second element, and similarly, the second element may also be referred to as the first element. The use of any and all examples or exemplary language ("for example", "such as" etc.) provided by the present embodiment is only intended to better illustrate embodiments of the present invention, and unless otherwise required, the scope of the present invention will not be limited.

[0089] It should be appreciated that embodiments of the present invention may be implemented or enforced by computer hardware, a combination of hardware and software, or by computer instructions stored in a non-transitory computer-readable memory. The method may be implemented in a computer program using standard programming techniques - including a non-transitory computer-readable storage medium configured with a computer program, wherein the computer-readable storage medium so configured causes the computer to operate in a specific and predefined manner - according to the methods and drawings described in the specific embodiments. Each program may be implemented in a high-level procedural or object-oriented programming language to communicate with a computer system. However, if desired, the program may be implemented in an assembly or machine language. In any case, the language may be a compiled or interpreted language. In addition, the program may be run on a programmed ASIC for this purpose.

[0090] In addition, the operations of the process described in this embodiment may be performed in any suitable order, unless otherwise indicated in this embodiment or otherwise clearly contradicted by the context. The process described in this embodiment (or variations and / or combinations thereof) may be performed under the control of one or more computer systems configured with executable instructions, and may be implemented as a code (e.g., executable instructions, one or more computer programs, or one or more applications) executed jointly on one or more processors, by hardware or a combination thereof. The computer program includes a plurality of instructions that may be executed by one or more processors.

[0091] Further, the method can be implemented in any type of computing platform that is operably connected to a suitable computer, including but not limited to a personal computer, a minicomputer, a mainframe, a workstation, a network or distributed computing environment, a separate or integrated computer platform, or in communication with a charged particle tool or other imaging device, etc. Various aspects of the present invention can be implemented in machine-readable code stored on a non-transitory computer-readable storage medium or device, whether removable or integrated into a computing platform, such as a hard disk, an optical read and / or write computer-readable storage medium, RAM, ROM, etc., so that it can be read by a programmable computer, and when the computer-readable storage medium or device is read by the computer, it can be used to configure and operate the computer to perform the process described herein. In addition, the machine-readable code, or portions thereof, can be transmitted via a wired or wireless network. When such media includes instructions or programs that implement the steps described above in conjunction with a microprocessor or other data processor, the invention described in this embodiment includes these and other different types of non-transitory computer-readable storage media. When programmed according to the methods and techniques of the present invention, the present invention also includes the computer itself.

[0092] The computer program can be applied to input data to perform the functions described in the present embodiment, thereby converting the input data to generate output data stored in a non-volatile memory. The output information can also be applied to one or more output devices such as a display. In a preferred embodiment of the present invention, the converted data represents a physical and tangible object, including a specific visual depiction of the physical and tangible object produced on the display.

[0093] The above is only a preferred embodiment of the present invention. The present invention is not limited to the above implementation. As long as the technical effect of the present invention is achieved by the same means, any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the scope of protection of the present invention. Within the scope of protection of the present invention, its technical scheme and / or implementation method may have various modifications and changes.

Claims

1. A frequency-adaptive electronic tag data decoding method, characterized in that: The method for decoding electronic tag data with adaptive frequency includes: Obtain the pulse signal sent by the electronic tag; Determine the pulse width of each pulse in the pulse signal to obtain a pulse width sequence; the pulse width sequence is for sequentially reading out two pulse widths each time; According to the pulse width sequence, determining a high frequency pulse width, a low frequency pulse width and a medium frequency pulse width; Perform multiple rounds of pulse width bit width conversion process until all pulse widths are read out from the pulse width sequence; in any round of the pulse width bit width conversion process, read out two pulse widths corresponding to this round of the pulse width bit width conversion process from the pulse width sequence, determine the current time count value according to the read two pulse widths and the time count value corresponding to the previous round of the pulse width bit width conversion process, the current time count value is the time count value corresponding to this round of the pulse width bit width conversion process, determine the bit value corresponding to the current time count value according to the size relationship between the current time count value and the intermediate frequency pulse width, and write the current time count value into the bit time A data sequence, wherein the bit time data sequence sequentially records the bit values ​​added in each round of the pulse width to bit width conversion process, and obtains a same-frequency count and a different-frequency count of the bit time data sequence, wherein the same-frequency count is a count of a time count value in the bit time data sequence having the same signal frequency as that corresponding to the current time count value, and the different-frequency count is a count of a time count value in the bit time data sequence having a signal frequency different from that corresponding to the current time count value, and when the same-frequency count is 0, the different-frequency count is overwritten and saved in the initial value of the compensation coefficient, the same-frequency count is increased, and the different-frequency count is cleared; When there is no error in the bit-time data sequence, multiple rounds of bit-width byte conversion processes are performed; in any round of the bit-width byte conversion process, the compensation coefficient value is determined according to the initial value of the compensation coefficient, the bit value corresponding to the round of the bit-width byte conversion process is read from the bit-time data sequence, the number of bits is determined according to the read bit value, the compensation coefficient value and the high-frequency pulse width, and a shift operation is performed on the bit-time data sequence according to the number of bits to convert the bit-time data sequence into byte data; Wherein, in any round of the pulse width bit width conversion process, determining the current time count value according to the read two pulse widths and the time count values ​​corresponding to the previous round of the pulse width bit width conversion process includes: According to the formula Timesum=(Timesum+InData[i]+InData[i+1]) / 2 Calculation is performed; wherein the previous Timesum is the current time count value, the next Timesum is the time count value corresponding to the previous round of the pulse width bit width conversion process, InData[i] and InData[i+1] are the two pulse widths read out of the current round of the pulse width bit width conversion process, i is a counting variable, and each round of pulse width bit width conversion process is completed, the calculation is performed according to i=i+2.

2. The method for decoding electronic tag data with adaptive frequency according to claim 1, characterized in that: The method for decoding electronic tag data with adaptive frequency also includes: Perform CRC check on the byte data.

3. The method for decoding electronic tag data with adaptive frequency according to claim 2, characterized in that: The step of performing CRC check on the byte data comprises: Divide the byte data into a plurality of byte blocks; each of the byte blocks comprises 13 bytes; Obtain a first CRC value and a second CRC value corresponding to the same byte block; the first CRC value is a CRC value of bytes 0-7 in the byte block, and the second CRC value is a CRC value of bytes 0-10 in the byte block; Compare the first CRC value with the 8th to 9th bytes in the byte block, and compare the second CRC value with the 11th to 12th bytes in the byte block, When the first CRC value is the same as the 8th-9th bytes in the byte block, and the second CRC value is the same as the 11th-12th bytes in the byte block, it is determined that the byte block is correct; otherwise, it is determined that the byte block is erroneous.

4. The method for decoding electronic tag data with adaptive frequency according to claim 1, characterized in that: Determining the high frequency pulse width, the low frequency pulse width and the medium frequency pulse width according to the pulse width sequence includes: averaging the 20th to 120th pulse widths in the pulse width sequence, and using the average value as the high-frequency pulse width; Adding a fixed value to the high-frequency pulse width, and using the result as the low-frequency pulse width; The arithmetic mean of the high-frequency pulse width and the low-frequency pulse width is determined, and the obtained result is used as the medium-frequency pulse width.

5. The method for decoding electronic tag data with adaptive frequency according to claim 1, characterized in that: The method for decoding electronic tag data with adaptive frequency also includes: In any round of the pulse width bit width conversion process, the same frequency count is modulo-calculated, and the bit value corresponding to the current time count value is maintained or jumped according to the modulo-calculated result.

6. The method for decoding electronic tag data with adaptive frequency according to claim 5, characterized in that: The modulo the same frequency count, and determining to maintain or jump the bit value corresponding to the current time count value according to the modulo result, includes: Taking the same frequency count modulo 16; When the modulo result is greater than 13, the bit value corresponding to the current time count value is jumped, otherwise, the bit value corresponding to the current time count value is maintained.

7. The method for decoding electronic tag data with adaptive frequency according to claim 1, characterized in that: When there is no error in the bit time data sequence, it includes: Detecting the bit time data sequence; When it is detected that there is a frame header in the bit time data sequence, it is determined that there is no error in the bit time data sequence, otherwise, it is determined that there is an error in the bit time data sequence.

8. An adaptive frequency electronic tag data decoding system, characterized in that: The adaptive frequency electronic tag data decoding system comprises a driving chip, a push-pull circuit, a resonant circuit, an antenna, an amplifying circuit, a frequency discriminator, a comparator and a single-chip microcomputer; the single-chip microcomputer is sequentially connected to the driving chip, the push-pull circuit, the resonant circuit and the antenna, and the antenna is sequentially connected to the frequency discriminator, the comparator and the single-chip microcomputer; The single chip microcomputer is used to generate an activation signal, and output the activation signal to the antenna through the driving chip, the push-pull circuit and the resonant circuit in sequence; The antenna is used to send the activation signal to the electronic tag, receive the pulse signal sent by the electronic tag, and send the pulse signal to the single-chip microcomputer through the frequency detector and the comparator in sequence; The single chip microcomputer is used to execute the adaptive frequency electronic tag data decoding method described in any one of claims 1 to 7 to process the pulse signal.

9. A computer device, characterized in that: The invention comprises a memory and a processor, wherein the memory is used to store at least one program, and the processor is used to load the at least one program to execute the adaptive frequency electronic tag data decoding method according to any one of claims 1 to 7.

10. A computer-readable storage medium storing a program executable by a processor, characterized in that: The processor-executable program is used to execute the adaptive frequency electronic tag data decoding method according to any one of claims 1 to 7 when executed by the processor.

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