Word line driving circuit and dynamic random access memory

Abstract

The present invention provides a word line driving circuit and a dynamic random access memory. The word line driving circuit includes a driving module and a control module. The control module includes: a control unit; a first switching unit having a control end, a first end and a second end, the control end being electrically connected to the control unit, the first end being electrically connected to a first power supply voltage, and the second end being electrically connected to a third input end of the driving module; a second switching unit having a control end, a first end and a second end, the control end being electrically connected to the control unit, the first end being electrically connected to a second power supply voltage, and the second end being electrically connected to the third input end of the driving module, wherein the second power supply voltage is greater than the ground voltage. The advantages of the present invention are that the static power consumption of the chip driving module is reduced in the standby mode, and the service life of the components in the circuit is prolonged.

Description

Technical Field

[0001] The present invention relates to the field of electronic circuits, and particularly to a word line driving circuit and a dynamic random access memory. Background Art

[0002] Att Figure 1 Shown is a word line driving circuit of a dynamic random access memory in the prior art. The word line driving circuit includes: a first inverter A1, a second inverter A2, a third inverter A3, a P-type driving transistor P, a first N-type driving transistor N, and a second N-type driving transistor N2. The gates of the P-type driving transistor P and the first N-type driving transistor N are electrically connected to an external control signal bMWL.

[0003] The input terminal of the first inverter A1 is electrically connected to an external circuit. The input terminal of the second inverter A2 is electrically connected to the output terminal of the first inverter A1. The input terminal of the third inverter A3 is electrically connected to an external circuit. The output terminal of the third inverter A3 is electrically connected to the gate of the second N-type driving transistor N2. The source of the P-type driving transistor P is electrically connected to the output terminal of the second inverter A2. The drains of the P-type driving transistor P and the first N-type driving transistor N are electrically connected to a signal output terminal WL. The drain of the second N-type driving transistor N2 is electrically connected to the signal output terminal WL. The sources of the first N-type driving transistor N and the second N-type driving transistor N2 are electrically connected to a ground voltage Vss.

[0004] An external signal is input through the input terminal of the first inverter A1, and a signal PXID is output through the output terminal of the second inverter A2. The source of the P-type driving transistor receives the signal PXID. Another external signal is input through the input terminal of the third inverter A3, and a signal PXIB is output through the output terminal of the third inverter A3. The gate of the second N-type driving transistor N2 receives the signal PXIB.

[0005] In the active mode, the external control signal bMWL electrically connected to the gates of the P-type driving transistor P and the first N-type driving transistor N is controlled to be at a low potential. An external signal controls the signal PXID to be at a high potential through the first inverter A1 and the second inverter A2. Another external signal controls the signal PXIB to be at a low potential through the third inverter A3. Then the P-type driving transistor P is turned on, the first N-type driving transistor N and the second N-type driving transistor N2 are turned off, and the signal output terminal WL outputs a high potential to turn on the corresponding word line.

[0006] However, when the circuit is in the standby mode, the external control signal bMWL electrically connected to the gates of the P-type driving transistor P and the first N-type driving transistor N is at a high potential. An external signal controls the signal PXID to be at a low potential through the first inverter A1 and the second inverter A2, and another external signal controls the signal PXIB to be at a high potential through the third inverter A3. Then, the first N-type driving transistor N and the second N-type driving transistor N2 are turned on, the P-type driving transistor P is turned off, and the signal output terminal WL outputs a low potential to turn off the corresponding word line. In this mode, the source and drain voltages of the P-type driving transistor P are the ground voltage Vss, and the gate voltage is the high potential required to turn on the word line. Then, a large voltage difference is formed between the gate and drain and between the gate and source of the P-type driving transistor P. In the overlapping region of the gate and drain of the CMOS field effect transistor, electron-hole pairs are generated in the depletion region due to the high electric field, and the channel between the bands on the drain surface is prone to form gate-induced drain leakage current (GIDL), which not only increases the power consumption of the chip but also affects the service life of the transistor.

[0007] Therefore, how to solve the leakage of the P-type driving transistor and thus reduce the static power consumption of the word line driving circuit is a problem that needs to be solved in the prior art. Summary of the Invention

[0008] The technical problem to be solved by the present invention is to provide a word line driving circuit and a dynamic random access memory that can reduce the power consumption of the dynamic random access memory.

[0009] To solve the above problems, the present invention provides a word line driving circuit, which includes:

[0010] A driving module having a first input terminal, a second input terminal, a third input terminal, and an output terminal. The first input terminal is used to receive a first external driving signal, the second input terminal is used to receive a second external driving signal, and the output terminal is used to output a word line driving signal;

[0011] A control module, including:

[0012] A control unit;

[0013] A first switch unit having a control terminal, a first terminal, and a second terminal. The control terminal is electrically connected to the control unit, the first terminal is electrically connected to a first power supply voltage, and the second terminal is electrically connected to the third input terminal of the driving module; a second switch unit having a control terminal, a first terminal, and a second terminal. The control terminal is electrically connected to the control unit, the first terminal is electrically connected to a second power supply voltage, and the second terminal is electrically connected to the third input terminal of the driving module, where the second power supply voltage is greater than the ground voltage.

[0014] Optionally, when the word line driving circuit is in the standby mode, the control unit controls the first switching unit to disconnect and the second switching unit to conduct, so that the third input terminal of the driving module receives the second power supply voltage.

[0015] Optionally, when the word line driving circuit is in the active mode, the control unit controls the first switching unit to conduct and the second switching unit to disconnect, so that the third input terminal of the driving module receives the first power supply voltage.

[0016] Optionally, the control unit is electrically connected to the first power supply voltage, and the first end of the first switching unit is electrically connected to the first power supply voltage through the control unit.

[0017] Optionally, the control unit further includes: a first inverter having an input terminal and an output terminal, the input terminal of the first inverter is configured to receive a third external driving signal, and the output terminal of the first inverter is electrically connected to the control terminals of the first switching unit and the second switching unit; a second inverter is electrically connected to the first power supply voltage, and the second inverter has an input terminal and an output terminal, the input terminal of the second inverter is electrically connected to the output terminal of the first inverter, and the output terminal of the second inverter is electrically connected to the first end of the first switching unit.

[0018] Optionally, when the word line driving circuit is in the standby mode, the third external driving signal provides a low potential, the first switching unit disconnects, and the second switching unit conducts, so that the third input terminal of the driving module receives the second power supply voltage.

[0019] Optionally, when the word line driving circuit is in the active mode, the third external driving signal provides a high potential, the first switching unit conducts, and the second switching unit disconnects, so that the third input terminal of the driving module receives the first power supply voltage.

[0020] Optionally, the first inverter is formed by connecting an odd number of sub-inverters in series, and / or the second inverter is formed by connecting an odd number of sub-inverters in series.

[0021] Optionally, the first switching unit is a first PMOS transistor, and the second switching unit is a first NMOS transistor.

[0022] Optionally, the first power supply voltage is greater than the second power supply voltage.

[0023] Optionally, the second power supply voltage is the chip power supply voltage.

[0024] Optionally, the second power supply voltage is the source power supply voltage; the value range of the second power supply voltage is 0.2 to 0.5V.

[0025] Optionally, the second supply voltage is less than the threshold voltage of the second switching unit.

[0026] Optionally, the driving module includes: a P-type driving transistor having a control terminal, a first terminal, and a second terminal, where the control terminal is electrically connected to the first input terminal of the driving module, the first terminal is electrically connected to the third input terminal of the driving module, and the second terminal is electrically connected to the output terminal of the driving module; an N-type driving transistor having a control terminal, a first terminal, and a second terminal, where the control terminal is electrically connected to the first input terminal of the driving module, the first terminal is electrically connected to the output terminal of the driving module, and the second terminal is electrically connected to the ground terminal; a second NMOS transistor having a control terminal, a first terminal, and a second terminal, where the control terminal is electrically connected to the second input terminal of the driving module, the first terminal is electrically connected to the output terminal of the driving module, and the second terminal is electrically connected to the ground terminal.

[0027] Optionally, when the word line driving circuit is in the standby mode, the first external driving signal provides a high potential, and the second external driving signal provides a high potential.

[0028] Optionally, when the word line driving circuit is in the active mode, the first external driving signal provides a low potential, and the second external driving signal provides a low potential.

[0029] Optionally, the driving module further includes a third inverter having an input terminal and an output terminal. The input terminal of the third inverter is electrically connected to the second input terminal of the driving module for receiving the second external driving signal, and the output terminal of the third inverter is electrically connected to the control terminal of the second NMOS transistor.

[0030] Optionally, when the word line driving circuit is in the standby mode, the first external driving signal provides a high potential, and the second external driving signal provides a low potential; when the word line driving circuit is in the active mode, the first external driving signal provides a low potential, and the second external driving signal provides a high potential.

[0031] Optionally, the third inverter is formed by connecting an odd number of sub-inverters in series.

[0032] The present invention also provides a dynamic random access memory including the above-mentioned word line driving circuit.

[0033] The advantages of the present invention are as follows. A control module including a first switch unit and a second switch unit is provided at the third input terminal of the driving module of the word line driving circuit. When the word line driving circuit is in the standby mode, the third input terminal of the driving module is electrically connected to the second power supply voltage, and the second power supply voltage is greater than the ground voltage. Thus, the voltage of the third input terminal of the driving module is pulled up, the voltage difference between the gate and the source of the P-type driving transistor is reduced, and accordingly, the gate-induced drain leakage current (GIDL) is reduced, achieving the purpose of reducing the chip power consumption of the driving module in the standby mode and prolonging the service life of the components in the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a circuit diagram of a word line driving circuit in the prior art.

[0035] Figure 2 is a circuit diagram of a word line driving circuit provided in the first embodiment of the present invention.

[0036] Figure 3 is a circuit diagram of a word line driving circuit provided in the second embodiment of the present invention.

[0037] Figure 4 is a circuit diagram of a word line driving circuit provided in the third embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0038] For ease of understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present application are shown in the drawings. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present application will be thorough and complete.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the specification of this application herein are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0040] It can be understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, the first input terminal may be referred to as the second input terminal, and similarly, the second input terminal may be referred to as the first input terminal. Both the first input terminal and the second input terminal are input terminals, but they are not the same input terminal.

[0041] It can be understood that in the following embodiments, "connection" means "electrical connection", "communication connection", etc. if there is transmission of electrical signals or data between the connected circuits, modules, units, etc.

[0042] It should be noted that the so-called high potential and low potential in the following embodiments are relative concepts (i.e., the voltage value of the high potential is higher than the voltage value of the corresponding low potential), without limiting the specific voltage value of the high potential, nor the specific voltage value of the low potential. And it is not limited that the high potentials applied on different signal lines in this specific embodiment are equal, nor that the high potential of a specific signal line is equal in different states. Those skilled in the art should understand that the values of the corresponding high potential and low potential can be set by themselves according to process nodes, speed requirements, reliability requirements, etc.

[0043] The following will describe in detail an embodiment of a word line driving circuit and a dynamic random access memory provided by the present invention with reference to the accompanying drawings. The electrical connection described in the present invention includes direct connection, connection through a transistor, and other equivalent connection methods.

[0044] Acc Figure 2 shown is a circuit diagram of a word line driving circuit provided by the first embodiment of the present invention. Please refer to Acc Figure 2 , the word line driving circuit includes a driving module and a control module.

[0045] The driving module has a first input terminal bMWL, a second input terminal PXIB, a third input terminal PXID, and an output terminal WL. The first input terminal bMWL is used to receive a first external driving signal, the second input terminal PXIB is used to receive a second external driving signal, and the output terminal WL is used to output a word line driving signal.

[0046] The control module includes a control unit C1, a first switching unit P1, and a second switching unit N1.

[0047] The control unit C1 can receive a third external driving signal.

[0048] The first switching unit P1 has a control terminal, a first terminal, and a second terminal. The control terminal is electrically connected to the control unit C1 at point A. The first terminal is electrically connected to a first supply voltage Vpp, and the second terminal is electrically connected to the third input terminal PXID of the driving module. In this embodiment, the control unit C1 is electrically connected to the first supply voltage Vpp, and the first terminal of the first switching unit P1 is electrically connected to the first supply voltage Vpp through the control unit C1. In other embodiments of the present invention, the first terminal of the first switching unit P1 can also be directly electrically connected to the first supply voltage Vpp.

[0049] The second switching unit N1 has a control terminal, a first terminal, and a second terminal. The control terminal is electrically connected to the control unit C1 at point A. The first terminal is electrically connected to the second supply voltage Vsl, and the second terminal is electrically connected to the third input terminal PXID of the driving module. Wherein, the second supply voltage Vsl is greater than the ground voltage Vss.

[0050] When the word line driving circuit is in the standby mode, the control unit C1 receives a third external driving signal and controls the first switching unit P1 to be turned off and the second switching unit N1 to be turned on according to the third external signal, so that the third input terminal PXID of the driving module receives the second supply voltage Vsl.

[0051] When the word line driving circuit is in the active mode, the control unit C1 receives a third external driving signal and controls the first switching unit P1 to be turned on and the second switching unit N1 to be turned off according to the third external signal, so that the third input terminal PXID of the driving module receives the first supply voltage Vpp.

[0052] In the word line driving circuit of the present invention, a control module including a first switching unit and a second switching unit is provided at the third input terminal of the driving module. When the word line driving circuit is in the standby mode, the third input terminal of the driving module is electrically connected to the second supply voltage, and the second supply voltage is greater than the ground voltage. Furthermore, the voltage of the third input terminal of the driving module is pulled up, and the voltage difference between the gate and the source of the P-type driving transistor P of the driving module is reduced, thereby reducing the gate-induced drain leakage current (GIDL), achieving the purpose of reducing the static power consumption of the driving module in the standby mode, and prolonging the service life of the components in the circuit.

[0053] Furthermore, the first switching unit P1 is a PMOS transistor, and the second switching unit N1 is an NMOS transistor. When the word line driving circuit is in the standby mode, the control unit C1 controls point A to be at a high potential, the first switching unit P1 is turned off, and the second switching unit N1 is turned on, so that the third input terminal PXID of the driving module receives the second supply voltage Vsl, and further pulls up the voltage of the third input terminal PXID of the driving module, reducing the voltage difference between the gate and the source of the P-type driving transistor P of the driving module, thereby reducing the gate-induced drain leakage current (GIDL), achieving the purpose of reducing the static power consumption of the driving module in the standby mode; when the word line driving circuit is in the active mode, the control unit C1 controls point A to be at a low potential, the first switching unit P1 is turned on, and the second switching unit N1 is turned off, so that the third input terminal PXID of the driving module receives the first supply voltage Vpp.

[0054] Furthermore, the second supply voltage Vsl is less than the threshold voltage of the second switching unit N1. In this embodiment, the second supply voltage Vsl is the source supply voltage, and its value range can be 0.2 to 0.5V.

[0055] Furthermore, the driving module includes a P-type driving transistor P, an N-type driving transistor N, and a second NMOS transistor N2.

[0056] The P-type driving transistor P has a control terminal, a first terminal, and a second terminal. The control terminal is electrically connected to the first input terminal bMWL of the driving module, the first terminal is electrically connected to the third input terminal PXID of the driving module, and the second terminal is electrically connected to the output terminal WL of the driving module.

[0057] The N-type driving transistor N has a control terminal, a first terminal, and a second terminal. The control terminal is electrically connected to the first input terminal bMWL of the driving module, the first terminal is electrically connected to the output terminal WL of the driving module, and the second terminal is electrically connected to the ground terminal Vss.

[0058] The second NMOS transistor N2 has a control terminal, a first terminal, and a second terminal. The control terminal is electrically connected to the second input terminal PXIB of the driving module, the first terminal is electrically connected to the output terminal WL of the driving module, and the second terminal is electrically connected to the ground terminal Vss.

[0059] When the word line driving circuit is in the standby mode, the first external driving signal provides a high potential, the P-type driving transistor P is turned off, and the N-type driving transistor N is turned on, so that the output terminal WL is electrically connected to the ground terminal Vss; the second external driving signal provides a high potential, and the second NMOS transistor N2 is turned on to further electrically connect the output terminal WL to the ground terminal Vss, so as to output a word line driving signal with a low potential and turn off the corresponding word line. At the same time, the control unit C1 receives the third external driving signal and controls the first switching unit P1 to be turned off and the second switching unit N1 to be turned on according to the third external driving signal, so that the first terminal of the P-type driving transistor P receives the second supply voltage Vsl, reducing the voltage difference between the gate and the source of the P-type driving transistor P, thereby reducing the gate-induced drain leakage current (GIDL) caused by the voltage difference between the gate and the source of the P-type driving transistor P in the word line driving circuit, achieving the purpose of reducing the static power consumption of the P-type driving transistor P in the standby mode and prolonging the service life of the components in the circuit.

[0060] When the word line driving circuit is in the active mode, the first external driving signal provides a low potential, the P-type driving transistor P is turned on, and the N-type driving transistor N is turned off, so that the output terminal WL is electrically connected to the first end of the P-type driving transistor P; the second external driving signal provides a low potential, and the second NMOS transistor N2 is turned off to prevent the output terminal WL from being electrically connected to the ground terminal Vss. At the same time, the control unit C1 receives the third external driving signal and controls the first switching unit P1 to be turned on and the second switching unit N1 to be turned off according to the third external signal. The first end of the P-type driving transistor P receives the first supply voltage VPP, so that the output terminal WL is electrically connected to the first supply voltage VPP, and a word line driving signal with a high potential is output to realize the driving of the word line.

[0061] The present invention also provides a second embodiment. The difference between the second embodiment and the first embodiment is that an implementation manner of the control unit is provided in the second embodiment. Please refer to Figure 3 which is the circuit diagram of the word line driving circuit provided by the second embodiment of the present invention.

[0062] The word line driving circuit includes a driving module and a control module.

[0063] The driving module has a first input terminal bMWL, a second input terminal PXIB, a third input terminal PXID, and an output terminal WL. The first input terminal bMWL is used to receive a first external driving signal, the second input terminal PXIB is used to receive a second external driving signal, and the output terminal WL is used to output a word line driving signal.

[0064] The control module includes a control unit C1, a first switching unit P1, and a second switching unit N1.

[0065] The first switching unit P1 has a control terminal, a first end, and a second end. The control terminal is electrically connected to the control unit at point A. The first end is electrically connected to the first supply voltage Vpp, and the second end is electrically connected to the third input terminal PXID of the driving module.

[0066] The second switching unit N1 has a control terminal, a first end, and a second end. The control terminal is electrically connected to the control unit at point A. The first end is electrically connected to the second supply voltage Vsl, and the second end is electrically connected to the third input terminal PXID of the driving module, where the second supply voltage is greater than the ground voltage Vss.

[0067] In this embodiment, the control unit C1 includes a first inverter A1 and a second inverter A2.

[0068] The first inverter A1 has an input terminal and an output terminal. The input terminal of the first inverter A1 is used to receive a third external driving signal, and the output terminal of the first inverter A1 is electrically connected to the control terminals of the first switching unit P1 and the second switching unit N1 at point A.

[0069] The second inverter A2 is electrically connected to the first supply voltage Vpp, and the second inverter A2 has an input terminal and an output terminal. The input terminal of the second inverter A2 is electrically connected to the output terminal of the first inverter A1, and the output terminal of the second inverter A2 is electrically connected to the first terminal of the first switching unit P1. In this embodiment, the first terminal of the first switching unit P1 is electrically connected to the first supply voltage Vpp through the second inverter A2.

[0070] When the word line driving circuit is in the standby mode, the third external driving signal provides a low potential. The input terminal of the first inverter A1 receives the third external driving signal and outputs a high potential at the output terminal, thereby controlling the first switching unit P1 to be turned off and the second switching unit N1 to be turned on, so that the third input terminal PXID of the driving module receives the second supply voltage Vsl.

[0071] When the word line driving circuit is in the active mode, the third external driving signal provides a high potential. The input terminal of the first inverter A1 receives the third external driving signal and outputs a low potential at the output terminal, thereby controlling the first switching unit P1 to be turned on and the second switching unit N1 to be turned off, so that the third input terminal PXID of the driving module receives the first supply voltage Vpp.

[0072] Furthermore, the first inverter A1 is formed by connecting an odd number of sub-inverters in series, and the second inverter A2 is formed by connecting an odd number of sub-inverters in series. For example, in this embodiment, the first inverter A1 is composed of one sub-inverter, and the second inverter A2 is composed of one sub-inverter. In another embodiment, the first inverter A1 is composed of three sub-inverters, and the second inverter A2 is composed of three sub-inverters. Among them, the number of sub-inverters constituting the first inverter A1 and the number of sub-inverters constituting the second inverter A2 may be the same or different, and the present application does not limit this.

[0073] Furthermore, the first switching unit P1 is a first PMOS transistor, and the second switching unit N1 is a first NMOS transistor.

[0074] Furthermore, the driving module includes a P-type driving transistor P, an N-type driving transistor N, and a second NMOS transistor N2.

[0075] The P-type driving transistor P has a control terminal, a first terminal, and a second terminal. The control terminal is electrically connected to the first input terminal bMWL of the driving module. The first terminal is electrically connected to the third input terminal PXID of the driving module. The second terminal is electrically connected to the output terminal WL of the driving module.

[0076] The N-type driving transistor N has a control terminal, a first terminal, and a second terminal. The control terminal is electrically connected to the first input terminal bMWL of the driving module. The first terminal is electrically connected to the output terminal WL of the driving module. The second terminal is electrically connected to the ground terminal Vss.

[0077] The second NMOS transistor N2 has a control terminal, a first terminal, and a second terminal. The first terminal is electrically connected to the output terminal WL of the driving module. The second terminal is electrically connected to the ground terminal Vss.

[0078] Furthermore, in this second embodiment, the driving module further includes a third inverter A3. The third inverter A3 is electrically connected to the first supply voltage VPP to achieve power supply. The third inverter A3 has an input terminal and an output terminal. The input terminal of the third inverter A3 is electrically connected to the second input terminal PXIB of the driving module for receiving the second external driving signal. The output terminal of the third inverter A3 is electrically connected to the control terminal of the second NMOS transistor N2.

[0079] Furthermore, the third inverter A3 is formed by connecting an odd number of sub-inverters in series. For example, in this embodiment, the third inverter A3 is formed by one sub-inverter. In another embodiment, the first inverter A3 is formed by three sub-inverters. The number of the sub-inverters forming the third inverter A3 can be set according to actual requirements, and this application does not limit it.

[0080] When the word line driving circuit is in the standby mode, the first external driving signal provides a high potential, the P-type driving transistor P is turned off, and the N-type driving transistor N is turned on, so that the output terminal WL is electrically connected to the ground terminal Vss; the second external driving signal provides a low potential, the third inverter A3 outputs a high potential, and the second NMOS transistor N2 is turned on to further electrically connect the output terminal WL to the ground terminal Vss, so as to output a word line driving signal with a low potential and turn off the corresponding word line. At the same time, the third external driving signal provides a low potential, the input terminal of the first inverter A1 receives the third external driving signal and outputs a high potential at the output terminal, thereby controlling the first switching unit P1 to be turned off and the second switching unit N1 to be turned on, so that the third input terminal PXID of the driving module receives the second supply voltage Vsl, and the second supply voltage Vsl is greater than the ground voltage Vss, thereby reducing the voltage difference between the gate and source of the P-type driving transistor P and reducing the gate-induced drain leakage current (GIDL) caused by the voltage difference between the gate and source of the P-type driving transistor P in the word line driving circuit, achieving the purpose of reducing the static power consumption of the P-type driving transistor P in the standby mode and extending the service life of the components in the circuit.

[0081] When the word line driving circuit is in the active mode, the first external driving signal provides a low potential, the P-type driving transistor P is turned on, and the N-type driving transistor N is turned off, so that the output terminal WL is electrically connected to the first terminal of the P-type driving transistor P; the second external driving signal provides a high potential, the third inverter A3 outputs a low potential, and the second NMOS transistor N2 is turned off to prevent the output terminal WL from being electrically connected to the ground terminal Vss. At the same time, the third external driving signal provides a high potential, the input terminal of the first inverter A1 receives the third external driving signal and outputs a low potential at the output terminal, thereby controlling the first switching unit P1 to be turned on and the second switching unit N1 to be turned off, so that the third input terminal PXID of the driving module receives the first supply voltage Vpp, and further electrically connects the output terminal WL to the first supply voltage VPP, outputs a word line driving signal with a high potential, and realizes the driving of the word line to ensure the normal operation of the word line driving circuit.

[0082] In this embodiment, in the standby mode, since the first PMOS transistor P1 and the first NMOS transistor N1 are directly electrically connected to the output terminal A of the first inverter, the point A is at a high potential at this time. The first PMOS transistor P1 is turned off, and the first NMOS transistor N1 is turned on, actually resulting in electrical isolation between the second inverter A2 and the P-type driving transistor P. The source voltage of the P-type driving transistor P is controlled by the first NMOS transistor N1, that is, the potential of PXID is controlled by the second supply voltage Vsl. Therefore, the source voltage of the P-type driving transistor P is Vsl. When the source voltage of the P-type driving transistor P is greater than the output voltage Vss of the second inverter, that is, when Vsl is greater than Vss, compared with the prior art solution, the gate-source voltage difference of the P-type driving transistor P in this solution is reduced, thereby reducing the gate-induced drain leakage current (GIDL) caused by the gate-source voltage difference of the P-type driving transistor P in the word line driving circuit of the dynamic random access memory, achieving the purpose of reducing the static power consumption of the P-type driving transistor P in the standby mode and extending the service life of the components in the circuit.

[0083] The third embodiment of the present invention further provides a word line driving circuit. The difference between the third embodiment and the second embodiment is that the second supply voltage is different. Please refer to Figure 4 which is a circuit diagram of a word line driving circuit provided by the third embodiment of the present invention.

[0084] The word line driving circuit includes a driving module and a control module.

[0085] The driving module has a first input terminal bMWL, a second input terminal PXIB, a third input terminal PXID, and an output terminal WL. The first input terminal bMWL is used to receive a first external driving signal, the second input terminal PXIB is used to receive a second external driving signal, and the output terminal WL is used to output a word line driving signal.

[0086] The control module includes a control unit C1, a first switching unit P1, and a second switching unit N1.

[0087] The first switching unit P1 has a control terminal, a first terminal, and a second terminal. The control terminal is electrically connected to the control unit at point A. The first terminal is electrically connected to the first supply voltage Vpp, and the second terminal is electrically connected to the third input terminal PXID of the driving module.

[0088] The second switching unit N1 has a control terminal, a first terminal, and a second terminal. The control terminal is electrically connected to the control unit at point A. The first terminal is electrically connected to the second supply voltage Vdd, and the second terminal is electrically connected to the third input terminal PXID of the driving module, where the second supply voltage Vdd is greater than the ground voltage Vss.

[0089] In the third embodiment, the second supply voltage Vdd is the chip power supply voltage. Further, in this embodiment, the first supply voltage Vpp is greater than the second supply voltage Vdd.

[0090] When the word line driving circuit is in the standby mode, the control unit C1 receives a third external driving signal, and controls the first switching unit P1 to disconnect and the second switching unit N1 to conduct according to the third external signal, so that the third input terminal PXID of the driving module receives the second supply voltage Vdd.

[0091] When the word line driving circuit is in the active mode, the control unit C1 receives a third external driving signal, and controls the first switching unit P1 to conduct and the second switching unit N1 to disconnect according to the third external signal, so that the third input terminal PXID of the driving module receives the first supply voltage Vpp.

[0092] In this embodiment, when the word line driving circuit is in the standby mode, the third input terminal of the driving module is electrically connected to the second supply voltage Vdd, and the second supply voltage Vdd is greater than the ground voltage Vss. Furthermore, the voltage of the third input terminal of the driving module is pulled up. Compared with the prior art solution, the gate-source voltage difference of the P-type driving transistor P in this solution is reduced, thereby reducing the gate-induced drain leakage current (GIDL) caused by the gate-source voltage difference of the P-type driving transistor P in the word line driving circuit of the dynamic random access memory, achieving the purpose of reducing the static power consumption of the P-type driving transistor P in the standby mode and extending the service life of the components in the circuit.

[0093] The present invention also provides a dynamic driving memory, which includes a word line and the above-mentioned word line driving circuit. The output terminal WL of the word line driving circuit is electrically connected to the word line to realize the driving of the word line. When the word line driving circuit is in the standby mode, the word line is not driven. When the word line driving circuit is in the active mode, the word line is driven and is in the working state.

[0094] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. A word line driving circuit, characterized in that, comprising: a driving module having a first input terminal, a second input terminal, a third input terminal and an output terminal, wherein the first input terminal is used for receiving a first external driving signal, the second input terminal is used for receiving a second external driving signal, and the output terminal is used for outputting a word line driving signal; a control module, comprising: a control unit; a first switching unit having a control terminal, a first terminal and a second terminal, wherein the control terminal is electrically connected to the control unit, the first terminal is electrically connected to a first supply voltage, and the second terminal is electrically connected to the third input terminal of the driving module; a second switching unit having a control terminal, a first terminal and a second terminal, wherein the control terminal is electrically connected to the control unit, the first terminal is electrically connected to a second supply voltage, and the second terminal is electrically connected to the third input terminal of the driving module, and wherein the second supply voltage is greater than the ground voltage; when the word line driving circuit is in a standby mode, the control unit controls the first switching unit to be turned off and the second switching unit to be turned on, so that the third input terminal of the driving module receives the second supply voltage.

2. The word line driving circuit according to claim 1, characterized in that, when the word line driving circuit is in an active mode, the control unit controls the first switching unit to be turned on and the second switching unit to be turned off, so that the third input terminal of the driving module receives the first supply voltage.

3. The word line driving circuit according to claim 1, characterized in that, the control unit is electrically connected to the first supply voltage, and the first terminal of the first switching unit is electrically connected to the first supply voltage through the control unit.

4. The word line driving circuit according to claim 3, characterized in that, the control unit comprises: a first inverter having an input terminal and an output terminal, wherein the input terminal of the first inverter is used for receiving a third external driving signal, and the output terminal of the first inverter is electrically connected to the control terminals of the first switching unit and the second switching unit; a second inverter electrically connected to the first supply voltage, and having an input terminal and an output terminal, wherein the input terminal of the second inverter is electrically connected to the output terminal of the first inverter, and the output terminal of the second inverter is electrically connected to the first terminal of the first switching unit.

5. The word line driving circuit according to claim 4, characterized in that, when the word line driving circuit is in a standby mode, the third external driving signal provides a low potential, the first switching unit is turned off, and the second switching unit is turned on, so that the third input terminal of the driving module receives the second supply voltage.

6. The word line driving circuit according to claim 4, characterized in that, when the word line driving circuit is in an active mode, the third external driving signal provides a high potential, the first switching unit is turned on, and the second switching unit is turned off, so that the third input terminal of the driving module receives the first supply voltage.

7. The word line driving circuit according to claim 4, characterized in that, The first inverter is formed by connecting an odd number of sub-inverters in series, and / or the second inverter is formed by connecting an odd number of sub-inverters in series.

8. The word line driving circuit according to claim 1, wherein, the first switching unit is a first PMOS transistor, and the second switching unit is a first NMOS transistor.

9. The word line driving circuit according to claim 1, wherein, the second supply voltage is the chip power supply voltage.

10. The word line driving circuit according to claim 1, wherein, the second supply voltage is the source power supply voltage.

11. The word line driving circuit according to claim 10, wherein, the value range of the second supply voltage is 0.2~0.5V.

12. The word line driving circuit according to claim 1, wherein, the second supply voltage is less than the threshold voltage of the second switching unit.

13. The word line driving circuit according to claim 1, wherein, the first supply voltage is greater than the second supply voltage.

14. The word line driving circuit according to claim 1, wherein, the driving module includes: a P-type driving transistor having a control terminal, a first terminal and a second terminal, the control terminal is electrically connected to the first input terminal of the driving module, the first terminal is electrically connected to the third input terminal of the driving module, and the second terminal is electrically connected to the output terminal of the driving module; an N-type driving transistor having a control terminal, a first terminal and a second terminal, the control terminal is electrically connected to the first input terminal of the driving module, the first terminal is electrically connected to the output terminal of the driving module, and the second terminal is electrically connected to the ground terminal; a second NMOS transistor having a control terminal, a first terminal and a second terminal, the control terminal is electrically connected to the second input terminal of the driving module, the first terminal is electrically connected to the output terminal of the driving module, and the second terminal is electrically connected to the ground terminal.

15. The word line driving circuit according to claim 14, wherein, when the word line driving circuit is in the standby mode, the first external driving signal provides a high potential, and the second external driving signal provides a high potential.

16. The word line driving circuit according to claim 14, wherein, when the word line driving circuit is in the active mode, the first external driving signal provides a low potential, and the second external driving signal provides a low potential.

17. The word line driving circuit according to claim 14, wherein, the driving module further includes a third inverter having an input terminal and an output terminal, the input terminal of the third inverter is electrically connected to the second input terminal of the driving module for receiving the second external driving signal, and the output terminal of the third inverter is electrically connected to the control terminal of the second NMOS transistor.

18. The word line driving circuit according to claim 17, wherein, when the word line driving circuit is in the standby mode, the first external driving signal provides a high potential, and the second external driving signal provides a low potential.

19. The word line driving circuit according to claim 17, wherein, When the word line driving circuit is in the active mode, the first external driving signal provides a low potential and the second external driving signal provides a high potential.

20. The word line driving circuit according to claim 17, characterized in that the third inverter is formed by connecting an odd number of sub-inverters in series.

21. A dynamic random access memory, characterized in that it includes the word line driving circuit according to any one of claims 1 to 20.

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