A method for forming a metal wire

Abstract

The present invention provides a method for forming a metal line, comprising: providing a semiconductor front-end device structure, forming an insulating dielectric stack on the front-end device structure, the insulating dielectric stack comprising a low dielectric constant material layer and a grinding stop layer stacked in sequence; etching the insulating dielectric stack to form a groove in the insulating dielectric stack; forming a metal layer, the metal layer filling the groove; and grinding the metal layer until the grinding stop layer is exposed to form a metal line. The method can conveniently and effectively improve the problem of unstable control of the height of the metal line in the traditional grinding process, and can accurately control the height of the metal line, thereby improving the stability and controllability of the metal line.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a method for forming a metal wire. Background Art

[0002] The resistance of the metal wires in the chip affects the heat generation and response speed of the chip, so controlling the resistance of the metal wires is important for ensuring the stability of the chip. Before processing, the length of the metal wires in the chip is usually designed, so from a process perspective, the resistance of the metal wires during chip processing is only affected by the metal wire width and metal wire height (the height difference between the upper and lower surfaces of the metal wire, hereinafter referred to as wire height).

[0003] The line height is affected by multiple processes during chip processing. How to ensure the stability of the line height has always been a difficult problem in chip processing.

[0004] The mainstream chip manufacturing process now controls the line height through chemical mechanical polishing (CMP). However, CMP itself has limitations such as a large variety of consumables, high replacement frequency, and limited process monitoring methods. The ability to control the line height is very limited, so the line height will fluctuate, which will lead to unstable chip performance. With the continuous improvement of technology nodes, the tolerance of chips to the fluctuation of the line height in the back end is getting lower and lower, and people are in urgent need of finding a more stable way to control the line height. Summary of the invention

[0005] In view of this, the present invention provides a method for forming a metal line, which can ensure the stability of the line height and can accurately control the line height.

[0006] In order to achieve the above object and other related objects, the present invention provides a method for forming a metal line, comprising:

[0007] A semiconductor front-end device structure is provided, and an insulating dielectric stack is formed on the front-end device structure, wherein the insulating dielectric stack includes a low dielectric constant material layer and a grinding stop layer stacked in sequence;

[0008] etching the insulating dielectric stack to form a trench in the insulating dielectric stack;

[0009] forming a metal layer, wherein the metal layer fills the groove;

[0010] The metal layer is ground until the grinding stop layer is exposed to form a metal line.

[0011] Optionally, an interlayer dielectric layer is formed on the surface of the semiconductor front-end device structure, and the insulating medium stack is located on the interlayer dielectric layer.

[0012] Optionally, the method for forming the trench includes: forming a hard mask layer having an opening on the insulating dielectric stack, the opening defining the shape and position of the trench; and etching the insulating dielectric stack using the hard mask layer as a mask to form the trench.

[0013] Optionally, before or after the step of etching the insulating dielectric stack to form the trench, the method for forming the metal line further includes: forming a through hole, one end of the through hole being connected to the bottom of the trench and the other end passing through the interlayer dielectric layer.

[0014] Optionally, in the step of filling the trench with the metal layer, the metal layer also fills the through hole to form a metal plug for interlayer interconnection in the through hole.

[0015] Optionally, the process of forming the trench and the via includes a dual damascene process.

[0016] Optionally, the bottom of the trench is flush with the lower surface of the low dielectric constant material layer.

[0017] Optionally, the thicknesses of the low dielectric constant material layer and the grinding stop layer are determined according to the height of the metal line to be formed, and the ratio of the thickness of the low dielectric constant material layer to the grinding stop layer is not less than 4.

[0018] Optionally, the thicknesses of the low dielectric constant material layer and the grinding stop layer are controlled by an advanced process control process.

[0019] Optionally, the insulating dielectric stack further includes a grinding buffer layer located above the grinding stop layer.

[0020] Optionally, the low dielectric constant material includes an ultra-low dielectric constant material, and the dielectric constant of the ultra-low dielectric constant material does not exceed 2.8.

[0021] Optionally, the ultra-low dielectric constant material includes porous SiO 2 .

[0022] Optionally, the material of the grinding stop layer includes silicon nitride.

[0023] Optionally, the metal layer comprises a copper metal layer.

[0024] Compared with the prior art, the present invention has the following advantages:

[0025] The present invention provides a method for forming a metal wire, by forming the insulating dielectric stack, the insulating dielectric stack includes a low dielectric constant material layer and a grinding stop layer stacked in sequence, forming a groove in the insulating dielectric stack, and filling the groove with a metal layer, during the subsequent grinding process, the grinding process is conveniently and controllably stopped at the grinding stop layer, no additional monitoring and control process for the grinding end point is required, and the requirements for the stability of the grinding process are reduced; the upper surface of the formed metal wire is flush with the upper surface of the grinding stop layer, so the line height of the metal wire can remain stable; further, the line height of the metal wire can be accurately controlled to be stable at an expected value; therefore, the method for forming a metal wire provided by the present invention can conveniently and effectively improve the stability and controllability of the metal wire. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a flow chart of a method for forming a metal line provided in one embodiment;

[0027] Figure 2 to Figure 5 is a schematic cross-sectional structural diagram of a semiconductor device at each step in a process of forming a metal line in an embodiment;

[0028] The reference numerals are described as follows:

[0029] 100 - semiconductor front-end device structure; 101 - interlayer dielectric layer; 102 - low dielectric constant material layer; 103 - grinding stop layer; 104 - hard mask layer; 105 - trench; 106 - through hole; 107 - metal layer; 108 - metal plug; 109 - metal line. DETAILED DESCRIPTION

[0030] In order to make the purpose, advantages and features of the present invention more clear, a method for forming a metal wire provided by the present invention is further described in detail below in conjunction with the accompanying drawings. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0031] Glossary: ​​The "low dielectric constant material" mentioned in this invention refers to a material with a dielectric constant k less than SiO 2 Dielectric material with a dielectric constant of (3.9).

[0032] See also Figure 1 The method for forming a metal wire provided by the present invention comprises the following steps:

[0033] Step S1: providing a semiconductor front-end device structure, forming an insulating dielectric stack on the front-end device structure, wherein the insulating dielectric stack includes a low dielectric constant material layer and a grinding stop layer stacked in sequence;

[0034] Step S2: etching the insulating dielectric stack to form a groove in the insulating dielectric stack;

[0035] Step S3: forming a metal layer, wherein the metal layer fills the groove;

[0036] Step S4: grinding the metal layer until the grinding stop layer is exposed to form a metal line.

[0037] See also Figure 2 , perform step S1, provide a semiconductor front-end device structure 100, form an insulating dielectric stack on the front-end device structure, and the insulating dielectric stack includes a low dielectric constant material layer 102 and a grinding stop layer 103 stacked in sequence.

[0038] In this embodiment, the semiconductor front-end device structure 100 includes a transistor, but is not limited thereto, and may also include other semiconductor devices; preferably, an interlayer dielectric layer 101 is formed on the surface of the semiconductor front-end device structure 100, and the interlayer dielectric layer 101 is preferably SiO 2 layer, but other suitable dielectric material layers can also be selected. The interlayer dielectric layer 101 can be a doped structural layer or an undoped structural layer. The formation process of the SiO2 layer is: using tetraethyl silicate (TEOS) as the raw material for chemical vapor deposition process, but is not limited to this, and other suitable processes can also be selected. An insulating dielectric stack is formed on the interlayer dielectric layer 101, and the insulating dielectric stack includes a low dielectric constant material layer 102 and a grinding stop layer 103 stacked in sequence. The material of the low dielectric constant material layer 102 is a low dielectric constant material. According to industry standards, the low dielectric constant material refers to a material with a dielectric constant k less than 3.9, and 3.9 is the dielectric constant of traditional dielectric materials SiO 2 By reducing the dielectric constant of the dielectric material used in the semiconductor device, the leakage current of the semiconductor device can be reduced, the capacitance effect between metal wires can be reduced, the heat generation of the semiconductor device can be reduced, etc. Preferably, the low dielectric constant material is an ultra-low dielectric constant material with k not exceeding 2.8. For example, in this embodiment, the material of the low dielectric constant material layer 102 is a porous SiO with k<2.8. 2 , the porous SiO 2 By using SiO 2 Introducing voids into the material can reduce the material density and thus reduce the k value. 2 The preparation method of the grinding stop layer 103 can refer to the prior art and will not be described in detail here. The material of the grinding stop layer 103 is preferably silicon nitride (Si 3 N 4), but other suitable materials may also be selected. The formation of the grinding stop layer 103 is preferably performed by physical vapor deposition process, but is not limited to this, and may also be other suitable processes.

[0039] In another embodiment, the insulating dielectric stack further includes a grinding buffer layer located above the grinding stop layer 103, and the material of the grinding buffer layer is preferably a low dielectric constant material, and more preferably a porous SiO2 with an ultra-low dielectric constant. 2 .

[0040] In this embodiment, when forming the grinding stop layer 103, the thickness of the grinding stop layer 103 is adjusted according to the thickness of the low dielectric constant material layer 102 thereunder through the existing advanced process control (APC) process, and the sum of the thicknesses of the two layers is controlled to be stable at an expected value, which can be set according to process requirements. The sum of the thicknesses is directly related to the height of the metal line finally formed. At the same time, the ratio of the thickness of the low dielectric constant material layer 102 to the grinding stop layer 103 is controlled to be not less than 4, so as to ensure that the metal line finally formed is generally in the low dielectric material medium, so that the metal lines have a lower distributed capacitance, and the device performance is improved.

[0041] In this embodiment, the average thickness h of the low dielectric constant material layer 102 is determined according to actual process requirements. 1 The average thickness h of the grinding stop layer 103 is 2 Preferably, h 1 With h 2 The ratio of is not less than 4, so as to ensure that the metal lines finally formed are generally in the low dielectric material medium, so that the metal lines have lower distributed capacitance, and the device performance is improved. The formation of the low dielectric constant material layer 102, the grinding stop layer 103 and the grinding buffer layer preferably adopts at least one of the chemical vapor deposition process, the physical vapor deposition process and the atomic layer deposition process, but is not limited thereto, and other suitable processes in the prior art may also be adopted.

[0042] See also Figure 3 , executing step S2, etching the insulating dielectric stack to form a trench 105 in the insulating dielectric stack.

[0043] In this embodiment, the process of forming the trench 105 can be briefly described as follows:

[0044] A hard mask layer 104 is formed on the insulating dielectric stack, and the hard mask layer 104 is patterned by photolithography and etching processes to form an opening thereon, wherein the opening defines the shape and position of the groove 105; the insulating dielectric stack is etched using the hard mask layer 104 as a mask to form the groove 105.

[0045] The number of the grooves 105 may be one or more, and the number of metal lines subsequently formed in the grooves 105 corresponds to one or more. Figure 4 The material of the hard mask layer 104 is preferably titanium nitride (TiN), and other suitable materials may also be selected. In addition to being able to serve as a hard mask, the suitable material must also ensure that it can be removed by grinding in the subsequent grinding process.

[0046] The process for forming the grooves 105 is a mature process in the industry. By controlling the process parameters, it can be ensured that the bottoms of the formed grooves are at the same height, that is, the depths of the grooves are equal. In this embodiment, further, the bottoms of the grooves can be controlled to extend downward to the upper surface of the interlayer dielectric layer 101. Figure 3 As shown in the figure, the height of the finally formed metal line can be increased, the resistance of the metal line can be reduced, and the depth of the finally formed groove can be accurately controlled to reach the expected value. As mentioned above, the expected value is equal to the sum of the thicknesses of the low dielectric constant material layer 102 and the grinding stop layer 103.

[0047] In this embodiment, a dual damascene process is used to form a through hole 106 before or after the step of etching the insulating dielectric stack to form the trench 105. One end of the through hole 106 is connected to a partial area at the bottom of the trench 105, and the other end passes through the interlayer dielectric layer 101. The number of through holes 106 connected to each trench 105 can be one or more. The specific process of the dual damascene process can refer to the prior art and will not be described in detail here.

[0048] See also Figure 4 , perform step S3 to form a metal layer 107, and the metal layer 107 fills the groove 105. In this embodiment, the metal layer 107 fills the groove 105 and also fills the through hole 106 to form a metal plug 108 for interlayer interconnection in the through hole 106. The formation of the metal layer 107 can be completed by a metal electroplating process, but is not limited to this, and other suitable processes can also be used. Since metal copper has excellent electrical properties, in this embodiment, the metal layer 107 is preferably a copper metal layer, but is not limited to this, and can also be other suitable metal layers, such as an aluminum metal layer.

[0049] The metal layer 107 will cover the insulating dielectric stack, so a grinding process is required to remove unnecessary film layers and form a flat surface.

[0050] See also Figure 5, performing step S4 to grind the metal layer 107 until the grinding stop layer 103 is exposed to form a metal line 109 .

[0051] In this embodiment, the grinding process adopts a chemical mechanical polishing (CMP) process. After the grinding process is completed, the portion above the grinding stop layer 103 is removed. In this embodiment, the portion above the grinding stop layer 103 includes the hard mask layer 104 and a portion of the metal layer 107. In another embodiment, it also includes the grinding buffer layer.

[0052] Due to the limitations of the level of thin film preparation technology and other subjective and objective factors, in actual applications, there may be uneven concave areas on the upper surface of the grinding stop layer 103. If the metal layer 107 is directly formed on the grinding stop layer 103, a small amount of metal layer will remain in these concave areas after the grinding process. These residual metal layers will affect the insulation and dielectric properties of the insulating medium stack, thereby reducing the quality of the metal wire 109.

[0053] To solve the above problem, in another embodiment, a grinding buffer layer is formed between the grinding stop layer 103 and the metal layer 107. The material of the grinding buffer layer is preferably a low dielectric constant material, and further preferably a porous SiO2 with an ultra-low dielectric constant. 2 Due to the existence of the grinding buffer layer, when depressions are formed on the surface of the grinding stop layer 103, after the grinding process is completed, what remains in these depressions is the grinding buffer layer material, which will not adversely affect the quality of the metal wire 109 subsequently formed in the insulating dielectric stack.

[0054] Due to the existence of the grinding stop layer 103, the grinding process can be conveniently and controllably stopped at the grinding stop layer 103, and no additional monitoring and control process for the grinding end point is required, which can reduce the requirements for the stability of the grinding process. In addition, the upper surface of the metal line 109 is flush with the upper surface of the grinding stop layer 103, and the lower surface of the metal line 109 is also at the same height. Furthermore, in this embodiment, the lower surface of the metal line 109 is flush with the lower surface of the low dielectric constant material layer 102, so the line height of the metal line 109 can remain stable; in particular, in this embodiment, the line height of the metal line 109 is equal to the sum of the thickness of the low dielectric constant material layer 102 and the grinding stop layer 103, and this sum of thicknesses can be accurately controlled by the aforementioned APC process at an expected value, thereby improving the controllability of the line height of the metal line 109.

[0055] In summary, the present invention provides a method for forming a metal line, by forming the insulating dielectric stack, the insulating dielectric stack includes a low dielectric constant material layer 102 and a grinding stop layer 103 stacked in sequence, and a groove 105 is formed in the insulating dielectric stack, and a metal layer 107 is deposited in the groove 105. In the subsequent grinding process, the grinding process is conveniently and controllably stopped at the grinding stop layer 103, and no additional monitoring and control process for the grinding end point is required, thereby reducing the requirements for the stability of the grinding process; the formed metal line The upper surface of the wire 109 is flush with the upper surface of the grinding stop layer 103, so the line height of the metal wire 109 can be kept stable; further, in the process of forming the groove, the bottom of the groove 105 is controlled to be flush with the lower surface of the low dielectric constant material layer 102, so that the line height of the metal wire 109 can be equal to the sum of the thickness of the low dielectric constant material layer 102 and the grinding stop layer 103. The sum of the thickness of these two layers is controlled to be an expected value by using advanced process control technology, and the line height of the metal wire 109 can be precisely controlled. The method for forming the metal wire provided by the present invention can conveniently and effectively ensure the stability of the line height of the metal wire; further, the line height of the metal wire can be precisely controlled to be stable at an expected value, thereby improving the controllability of the metal wire.

[0056] It is understood that the "layer" described in the present invention refers to a thin film layer, which is formed by an existing suitable thin film preparation process. It is also understood that when a "layer" is referred to as being above or below another "layer", it can be directly located above or below another "layer", or there can also be an intermediate layer, unless the context clearly expresses that there is no intermediate layer between the two layers. In addition, it is understood that although the present invention has been disclosed as above with preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or to modify it into an equivalent embodiment of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention, still belongs to the scope of protection of the technical solution of the present invention. It should also be understood that the present invention is not limited to the specific methods, compounds, materials, manufacturing techniques, usages and applications described herein, which can be changed. It should also be understood that the terms described herein are only used to describe specific embodiments, not to limit the scope of the present invention. It must be noted that as used herein and in the appended claims, the singular forms "a", "an", and "the" include plural references unless the context clearly indicates otherwise. Thus, for example, a reference to "a step" means a reference to one or more steps, and may include secondary steps. All conjunctions used should be understood in the broadest sense. Thus, the word "or" should be understood to have a logical "or" definition, rather than a logical "exclusive or" definition, unless the context clearly indicates otherwise. Structures described herein are to be understood to also refer to functional equivalents of the structures. Language that can be interpreted as approximating should be interpreted as such unless the context clearly indicates otherwise.

Claims

1. A method for forming a metal wire, characterized in that: include: A semiconductor front-end device structure is provided, and an insulating dielectric stack is formed on the front-end device structure, wherein the insulating dielectric stack comprises a low dielectric constant material layer and a grinding stop layer stacked in sequence, and the insulating dielectric stack further comprises a grinding buffer layer located on the grinding stop layer; Etching the insulating dielectric stack to form a groove in the insulating dielectric stack; forming a metal layer, the metal layer filling the groove, the bottom of the groove being flush with the lower surface of the low dielectric constant material layer, the thickness of the low dielectric constant material layer and the grinding stop layer being determined according to the height of the metal line to be formed, and the ratio of the thickness of the low dielectric constant material layer to the grinding stop layer being not less than 4; The metal layer is ground until the grinding stop layer is exposed to form a metal line.

2. The method for forming a metal wire according to claim 1, wherein: An interlayer dielectric layer is formed on the surface of the semiconductor front-end device structure, and the insulating medium stack is located on the interlayer dielectric layer.

3. The method for forming a metal wire according to claim 1, wherein: The method for forming the groove comprises: forming a hard mask layer having an opening on the insulating dielectric stack, wherein the opening defines a shape and a position of a trench; The insulating dielectric stack is etched using the hard mask layer as a mask to form the trench.

4. The method for forming a metal wire according to claim 2, wherein: Before or after the step of forming the trench, the method for forming the metal line further includes: forming a through hole, one end of which is connected to the bottom of the trench and the other end of which passes through the interlayer dielectric layer.

5. The method for forming a metal wire according to claim 4, wherein: In the step of filling the trench with the metal layer, the metal layer also fills the through hole to form a metal plug for interlayer interconnection in the through hole.

6. The method for forming a metal wire according to claim 4, wherein: The process of forming the trench and the via includes a dual damascene process.

7. The method for forming a metal wire according to claim 1, wherein: The thicknesses of the low dielectric constant material layer and the grinding stop layer are controlled by an advanced process control technique.

8. The method for forming a metal wire according to claim 1, wherein: The low dielectric constant material layer includes an ultra-low dielectric constant material, and the dielectric constant of the ultra-low dielectric constant material is no more than 2.

8.

9. The method for forming a metal wire according to claim 8, wherein: The ultra-low dielectric constant material includes porous SiO2.

10. The method for forming a metal wire according to claim 1, wherein: The material of the grinding stop layer includes silicon nitride.

11. The method for forming a metal wire according to claim 1, wherein: The metal layer includes a copper metal layer.

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