Semiconductor device and method of manufacturing the same

Abstract

Embodiments of the invention relate to semiconductor devices and methods of manufacturing the same. A semiconductor device includes first and second core regions; first and second input / output (I / O) regions coupled to each other and to the first and second core regions; the first and second I / O regions are interposed between a consumable region and the corresponding first and second core regions; a seal ring surrounding the core regions and the I / O regions; a metallization layer and an interconnect layer; an inter-com segment extending between the I / O regions; first and second spacers extending from a first side to a third side of the seal ring or from a first location on the corresponding third and fourth spacers to a second location, the latter extending from the first side to the third side of the seal ring; the first spacer is interposed between the first core region and the first I / O region; and the second spacer is interposed between the second core region and the second I / O region.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices and methods for manufacturing the same. Background Technology

[0002] An integrated circuit (“IC”) package (“IC package”) comprises one or more semiconductor devices. Each semiconductor device comprises one or more integrated circuits. Each integrated circuit comprises active devices (e.g., transistors, etc.) and passive devices (e.g., resistors, capacitors, etc.). These active and passive devices are coupled in different ways to provide the functionality of the corresponding integrated circuit. Typical interconnect structures include lateral interconnects (e.g., conductive segments corresponding to metallization layers) and vertical interconnects (e.g., via structures corresponding to interconnect layers and contact structures in “transistor layers”).

[0003] The typical manufacturing process of an IC package is as follows: A substrate with a flat, circular shape is cut from an ingot of semiconductor material (e.g., silicon) and referred to as a wafer. Multiple semiconductor devices are formed on the wafer. The surface of the wafer is divided into small rectangular regions. A semiconductor device is formed on each rectangular region. At some point in the manufacturing process, the semiconductor devices are separated by dicing (also known as scribing, sawing, or slicing) the wafer. To prevent the dicing process from damaging the semiconductor devices, consumable (or sacrificial) areas are reserved between the rectangular regions that are at least partially consumed by the dicing process.

[0004] In the early stages of manufacturing, one way to represent semiconductor devices is by referring to a planar diagram as a layout. The layout is generated within the context of design rules that impose constraints on the placement of corresponding patterns within the layout, such as geographic / spatial constraints, connectivity constraints, etc. Typically, the set of design rules is specific to a process node through which the semiconductor device will be manufactured based on the resulting layout. The set of design rules compensates for the variability of the corresponding process node. This compensation increases the likelihood that the actual semiconductor device generated from the layout will become an acceptable counterpart to the virtual device on which the layout is based. Summary of the Invention

[0005] According to one aspect of the present invention, a semiconductor device is provided, comprising: a first core region and a second core region of a core circuit; a first input / output (I / O) region and a second I / O region of an interface circuit, coupled to each other and correspondingly coupled to the first core region and the second core region; a consumable region; relative to a first direction: the consumable region is located between the first I / O region and the second I / O region; the first I / O region is located between the consumable region and the first core region; and the second I / O region is located between the consumable region and the second core region; a sealing ring having a first side, a second side, a third side, and a fourth side, the sealing ring surrounding the first core region and the second core region, as well as the first I / O region and the second I / O region; a metallization layer; and an interconnect layer, which is disposed above the metallization layer. Interleaved; inter-com segments, located in a subset of the metallization layer, each inter-com segment extending between and thereby coupling the first I / O region and the second I / O region; a first guard wall and a second guard wall, each extending from a first side of the sealing ring to a third side or from a first position on a corresponding third guard wall and a fourth guard wall to a second position, each of the third guard wall and the fourth guard wall extending from a first side of the sealing ring to a third side; the first guard wall being between the first core region and the first I / O region and isolating it from each of the first core region and the first I / O region; and the second guard wall being between the second core region and the second I / O region and isolating it from each of the second core region and the second I / O region.

[0006] According to another aspect of the present invention, a semiconductor device is also provided, comprising: a core region of a core circuit; an input / output (I / O) region of an interface circuit coupled to the core region; a sealing ring having a first side, a second side, and a third side relative to a vertical first direction and a second direction, the sealing ring surrounding the core region and the I / O region and isolating the core region and the I / O region; and a first protective wall extending from the first side of the sealing ring to the third side or from a first position on a corresponding third protective wall and a fourth protective wall to a second position, each of the third protective wall and the fourth protective wall extending from the first side of the sealing ring to the third side, the first protective wall being located between the core region and the I / O region and isolating each of the core region and the I / O region.

[0007] According to one aspect of the present invention, a method for manufacturing a semiconductor device is provided, the method comprising: incrementally forming a structure using corresponding photolithography processes, the structure comprising: a first core region and a second core region of a core circuit; a first input / output (I / O) region and a second I / O region of an interface circuit, coupled to each other and correspondingly coupled to the first core region and the second core region; a consumable region; a sealing ring having a first side, a second side, a third side, and a fourth side; metallization layers and interconnect layers, the interconnect layers being interleaved between the metallization layers; an inter-com segment located in a subset of the metallization layers; and a first guard wall and a second guard wall; and wherein the forming step comprises: relative to a first direction: positioning the consumable region between the first I / O region and the second I / O region; positioning the first I / O region between the consumable region and the first core region; and positioning the second I / O region between the consumable region and the first core region. Between the two core regions; a sealing ring is arranged to surround the first core region and the second core region, as well as the first I / O region and the second I / O region; correspondingly, each mutual communication segment is arranged to extend between corresponding portions of the first I / O region and the second I / O region and thereby couple the corresponding portions of the first I / O region and the second I / O region, the mutual communication segment extending through the consumable region; each of the first and second protective walls is arranged to extend from a first side to a third side of the sealing ring or from a first position to a second position on the corresponding third and fourth protective walls, each of the third and fourth protective walls extending from a first side to a third side of the sealing ring; the first protective wall is positioned between the first core region and the first I / O region and isolated from each of the first core region and the first I / O region; and the second protective wall is positioned between the second core region and the second I / O region and isolated from each of the second core region and the second I / O region. Attached Figure Description

[0008] One or more embodiments are shown in the accompanying drawings by way of example (not limitation), wherein elements having the same reference numerals throughout the description denote similar elements. The drawings are not to scale unless otherwise disclosed.

[0009] Figure 1 This is a block diagram of a semiconductor device according to at least one embodiment of the present disclosure.

[0010] Figures 2A-2B These are cross-sectional views of corresponding semiconductor devices according to some embodiments.

[0011] Figure 2A 'Based on some embodiments Figure 2A A less detailed version.

[0012] Figures 3A-3FThis is a top view (plan view) of a corresponding layer of a semiconductor device according to some embodiments.

[0013] Figure 4 This is a top view (plan view) of a wafer according to some embodiments.

[0014] Figures 5A-5G This is a corresponding flowchart of a method for manufacturing a semiconductor device according to some embodiments.

[0015] Figure 6 This is a flowchart of a method for manufacturing a semiconductor device according to some embodiments.

[0016] Figure 7 This is a block diagram of an electronic design automation (EDA) system according to some embodiments.

[0017] Figure 8 This is a block diagram of a semiconductor device manufacturing system and an associated IC manufacturing process according to some embodiments.

[0018] Figures 9A-9B This is a top view (plan view) of a corresponding layer of a semiconductor device according to some embodiments.

[0019] Figures 10A-10B Correspondingly, there are cross-sectional views and three-quarter perspective views of semiconductor devices according to some embodiments. Detailed Implementation

[0020] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components, materials, values, steps, operations, arrangements, etc., are described below to simplify this disclosure. These are merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, etc., are contemplated. For example, in the following description, forming a first component on or above a second component can include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout the various embodiments of the invention. Such repetition is for brevity and clarity only and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0021] Furthermore, for ease of description, spatial relation terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spatial relation terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relation descriptors used herein can be interpreted accordingly.

[0022] In some embodiments, an integrated circuit (IC) package (IC package) includes one or more dual-chip semiconductor devices and / or one or more single-chip semiconductor devices. A dual-chip semiconductor device includes first and second single chips. Therefore, the dual-chip semiconductor device is separated (or diced) to obtain two single-chip semiconductor devices. In some embodiments, the dual-chip semiconductor device includes a cumulative sealing structure to protect the core region and I / O region from mechanical stress and / or moisture intrusion.

[0023] The first and second single chips of the dual-chip semiconductor device correspondingly include: first and second core regions of core circuitry; and first and second input / output (I / O) regions of interface circuitry. The first and second I / O regions are coupled to each other and correspondingly coupled to the first and second core regions. The first core region and the first I / O region are separated from the second core region and the second I / O region by consumable regions. When the dual-chip semiconductor device is diced, a cut is made through the consumable regions, which consumes at least a portion of the consumable regions.

[0024] The dual-chip semiconductor device also includes metallization layers and interconnect layers interleaved between the metallization layers. A first I / O region is coupled to a first core region via a first intra-com stack, which includes first intra-com segments from a first subset of the metallization layers. Each first intra-com segment extends between and is coupled to the first core region and the first I / O region. Similarly, a second I / O region is coupled to a second core region via a second intra-com stack, which includes second intra-com segments from a first subset of the metallization layers. The first and second I / O regions are coupled via an inter-com stack, which includes inter-com segments from a second subset of the metallization layers. Each inter-com segment extends between and is coupled to the first and second I / O regions. Each inter-com segment extends through a consumable region.

[0025] In some embodiments, the cumulative sealing structure includes a sealing ring and first, second, third, and fourth parapets. The sealing ring surrounds and isolates from first and second core regions and first and second I / O regions. Each of the first to fourth parapets extends from a first side to a third side of the sealing ring. The first parapet is located on a first internal communication stack and is situated between and isolated from the first core region and the first I / O region. Thus, the first parapet seals the first core region relative to the first I / O region. The second parapet is located on a second internal communication stack and is situated between and isolated from the second core region and the second I / O region. Thus, the second parapet seals the second core region relative to the second I / O region. The third parapet is located between the first I / O region and the consumable region. The fourth parapet is located between the second I / O region and the consumable region. Each of the third and fourth parapets is formed between the mutual communication stack and the substrate, relative to the direction of the metallization layer stack (“stack direction”). Therefore, relative to the stacking direction, and for the lower portion of the first I / O region located below the interconnected stack, the third shield seals the lower portion of the first I / O region relative to the consumable region. Since the first shield directly seals the first core region and the third shield indirectly seals the first core region, the first and third shields are described as cumulative. Furthermore, therefore, relative to the stacking direction, and for the lower portion of the second I / O region located below the interconnected stack, the fourth shield seals the lower portion of the second I / O region relative to the consumable region. Since the second shield directly seals the second core region and the fourth shield indirectly seals the second core region, the second and fourth shields are described as cumulative. In some embodiments, the first and second shields extend correspondingly from a first position to a second position on the third and fourth shields.

[0026] According to another method, a dual-chip semiconductor device lacking a sealing structure is provided, whereby the sealing structure would otherwise correspond to the first and second protective walls in at least some embodiments. When the dual-chip semiconductor device according to the other method is diced, the core region of each of the two resulting single-chip semiconductor devices is susceptible to moisture intrusion through the corresponding I / O regions. Moisture enters the single chip through the remaining portions of the interconnect stack after the dicing process. The remaining portions of the interconnect stack include not only the remaining portions of the interconnect segments in a first subset of the metallization layers, but also the remaining portions of the corresponding interconnect layers. More specifically, moisture propagates through the dielectric material in the remaining portions of the interconnect layers, through the corresponding portions of the interconnect layers in the I / O stack, and forward to a portion of the interconnect layers in the core region. In contrast, according to some embodiments, the first and second protective walls, even if they cannot prevent moisture intrusion, reduce the moisture intrusion suffered according to the other method, thereby improving the reliability of the corresponding first and second single-chip semiconductor devices.

[0027] In some embodiments, the cumulative sealing structure further includes fifth and sixth protective walls, corresponding to the first and second wall pads on the fifth and sixth protective walls. Each of the fifth and sixth protective walls is located on the intercom stack. The fifth protective wall is aligned with the third protective wall and is therefore located between the first I / O region and the consumable region. The sixth protective wall is aligned with the fourth protective wall and is therefore located between the second I / O region and the consumable region. Relative to the stacking direction, and for the upper portion of the first I / O region located above the intercom stack, the fifth protective wall seals the upper portion of the first I / O region relative to the consumable region. Relative to the stacking direction, and for the upper portion of the second I / O region located above the intercom stack, the sixth protective wall seals the upper portion of the second I / O region relative to the consumable region. According to another approach, a dual-chip semiconductor device lacking both a sealing structure and a padding structure is provided; otherwise, the sealing structure would correspond to the fifth and sixth protective walls of at least some embodiments, and the padding structure would correspond to the first and second wall pads of at least some embodiments. During the dicing process, the intercom stack is subjected to mechanical stress, but the other approach lacks a structure to mitigate this mechanical stress. In contrast, according to some embodiments, the first and second wall pads correspondingly stacked on the fifth and sixth walls reduce the mechanical stress borne by the interconnecting stacks during the dicing process, which improves the reliability of the corresponding first and second single-chip semiconductor devices.

[0028] Figure 1 This is a block diagram of an integrated circuit (IC) package (IC package) according to at least one embodiment of the present disclosure.

[0029] exist Figure 1 In the IC package 100, a dual-chip semiconductor device 102A and a single-chip semiconductor device 102B are included. The dual-chip semiconductor device includes first and second single chips. Therefore, the dual-chip semiconductor device is separated (or cut) to obtain two single-chip semiconductor devices. The dual-chip semiconductor device includes a cumulative sealing structure to prevent mechanical stress and / or moisture intrusion. The single-chip semiconductor device includes a cumulative sealing structure to prevent mechanical stress and / or moisture intrusion.

[0030] Figure 2A This is a cross-sectional view of a semiconductor device 202A according to some embodiments.

[0031] Figure 2A 'Based on some embodiments Figure 2A A less detailed version.

[0032] For example, relative to Figure 2A The purpose of the comparison Figure 2A 'Emphasized' Figure 2A The larger structure, the result is Figure 2A 'why not Figure 2AIn detail. For example, Figure 2A The diagram shows many components included in the retaining wall 252(1), while Figure 2A The protective wall 252(1) is shown, but the components included in the protective wall 252(1) are not shown. For simplicity, reference is made below. Figure 2A Nevertheless, it should be understood that Figure 2A Most of the discussion also applies to Figure 2A '.

[0033] Semiconductor device 202A is a dual-chip semiconductor device, such as dual-chip semiconductor device 102A ( Figure 1 Semiconductor device 202A includes chips 203(1) and 203(2). Chips 203(1) and 203(2) are discussed in more detail below.

[0034] Semiconductor device 202A is a dual-chip semiconductor device including a substrate 204. In some embodiments, the substrate 204 is a semiconductor material. In some embodiments, the substrate 204 includes silicon. In some embodiments, the substrate is a doped semiconductor material.

[0035] exist Figure 2A In the semiconductor device 202A, a metallization layer, a contact layer, and an interconnect layer are also included, wherein the interconnect layers are staggered correspondingly among the metallization layers. The contact layer CNTK is located above the substrate 204. A first metallization layer (layer M_1st) is located above the contact CNTK layer. A first interconnect layer (layer V_1st) is located above the M_1st layer. Figure 2A Assuming a numbering convention, the M_1st layer and V_1st layer are referred to as M1 and VIA1 respectively. In some embodiments, the numbering convention assumes that the M_1st layer and V_1st layer are referred to as M0 and VIA0 respectively.

[0036] The metallization layer and interconnect layer also include the following: a second metallization layer (layer M2) above layer VIA1; a second interconnect layer (layer VIA2) above layer M2; a third metallization layer (layer M3) above layer VIA2; a third interconnect layer (layer VIA3) above layer M3; a fourth metallization layer (layer M4) above layer VIA3; a fourth interconnect layer (layer VIA4) above layer M4; a fifth metallization layer (layer M5) above layer VIA4; a fifth interconnect layer (layer VIA5) above layer M5; a sixth metallization layer (layer M6) above layer VIA5; a sixth interconnect layer (layer VIA6) above layer M6; a seventh metallization layer (layer M7) above layer VIA6; a seventh interconnect layer (layer VIA7) above layer M7; and an eighth metallization layer (layer M8) above layer VIA7. Figure 2A In the text, layer M8 represents the top metallization layer (layer M_top). Although Figure 2AEight metallization layers are shown, but in some embodiments, the number of metallization layers is less than eight or more than eight.

[0037] for Figure 2A For simplicity, and except as indicated below, each conductive segment in a given metallization layer is considered to be labeled with the same reference numerals as follows: segment 212 in layer M1; segment 215 in layer M2; segment 218 in layer M3; segment 221 in layer M4; segment 224s in layer M5; segment 227 in layer M6; segment 230 in layer M7; and segment 233 in layer M8. As described below, each of layers M1-M3 also includes conductive segments 238(1) and 238(2). As discussed below, each of layers M5-M6 also includes conductive segment 248.

[0038] Similarly, in order to Figure 2A For simplicity, it is assumed that each interconnect layer of VIA1-VIA7 has two types of interconnect structures: via strips and discrete vias, as described below. For visual distinction purposes, relative to... Figure 2A The X-axis marked above shows the through-hole strip as always wider than the discrete through-hole. Furthermore, in order to... Figure 2A For simplicity, each via strip in a given interconnect layer is assumed to be labeled with the same first reference numeral, and each discrete via in a given interconnect layer is assumed to be labeled with the same second reference numeral, as follows: via strip 213 and discrete via 214 in layer VIA1; via strip 216 and discrete via 217 in layer VIA2; via strip 219 and discrete via 220 in VIA3; via strip 222 and discrete via 223 in VIA4; via strip 225 and discrete via 226 in VIA5; via strip 228 and discrete via 229 in VIA6; and via strip 231 and discrete via 232 in VIA7.

[0039] The gaps in each of layers M1-M8 are spaces that are not filled with the corresponding conductive segments, and are filled with the corresponding interlayer dielectric (ILD) material. The gaps in each of layers VIA1-VIA7 are spaces that are not filled with the corresponding via structures, and are filled with the corresponding interlayer dielectric (ILD) material.

[0040] In terms of layers, the semiconductor device 202A also includes a passivation layer PSVT1 located above the M8 layer and a second passivation layer PSVT2 located above the PSVT1 layer.

[0041] exist Figure 2AIn this configuration, each of the substrate 204, contact layer CNTK, metallization layers M1-M8, interconnect layers VIA1-VIA7, and passivation layers PSVT1-PSVT2 extends along a first and a second direction, which are perpendicular to each other. In some embodiments, the first and second directions correspond to the X-axis and the Y-axis, respectively. The contact layer CNTK, metallization layers M1-M8, interconnect layers VIA1-VIA7, and passivation layers PSVT1-PSVT2 are stacked along a third direction (“stack direction”), which is perpendicular to each of the first and second directions. In some embodiments where the first and second directions correspond to the X-axis and the Y-axis, the third direction is the Z-axis.

[0042] Semiconductor device 202A also includes core regions 206(1) and 206(2), input / output (I / O) regions 208(1) and 208(2), and consumable region 209. Each of the core regions 206(1) and 206(2) includes a corresponding core circuit.

[0043] The core circuitry of each of the core regions 206(1) and 206(2) includes a corresponding segment in one or more of layers M1-M8 and a corresponding via structure in the corresponding layers VIA1-VIA7. The I / O circuitry of each of the I / O regions 208(1) and 208(2) includes a corresponding segment in one or more of layers M1-M8 and a corresponding via structure in the corresponding layers VIA1-VIA7. In addition, a contact structure 211 is formed in the CNTK layer, thereby coupling the corresponding segments of the core regions 206(1) and 206(2) in layer M1 to the corresponding doped region 210 in the substrate 204.

[0044] Each of I / O regions 208(1) and 208(2) includes interface circuitry. In some embodiments, the interface circuitry facilitates communication between core regions 206(1) and 206(2). Figure 2A In the middle, relative to the X-axis: consumable region 209 lies between I / O regions 208(1) and 208(2); I / O region 208(1) lies between consumable region 209 and core region 206(1); and I / O region 208(2) lies between consumable region 209 and core region 206(2). Each of core regions 206(1) and 206(2), I / O regions 208(1) and 208(2), and consumable region 209 has a corresponding occupied area representing the area relative to the X-axis and Y-axis (see See Figures 3B-3F ).

[0045] exist Figure 2A In the semiconductor device 202A, a sealing ring 254 is also included, which surrounds (see...) Figures 3B-3F(Top view) Core regions 206(1) and 206(2), I / O regions 208(1) and 208(2) and consumable region 209 are isolated therefrom. Sealing ring 204 is isolated from core regions 206(1) and 206(2) and I / O regions 208(1) and 208(2).

[0046] The sealing ring 254 has a left side 256 (L), a right side 256 (R), and a distal side 256 (D) (see...) Figures 3B-3F Where the descriptor far side is relative to the containing Figures 3A-3B (at the bottom of the page) and near side 256 (P) (see again) Figures 3B-3F The descriptor proximal to the containing Figures 3B-3F (At the bottom of the page). The left side 256(L) of the sealing ring 254 is located between the core region 206(1) and the dicing edge 274(1). The dicing edge 274(1) is where the semiconductor device 274 is attached to the wafer (see bottom of page). Figure 4 The result of separating (or cutting) other semiconductor devices on the core. The right side 256(R) of the sealing ring 254 is located between the core region 206(2) and the cut edge 274(2).

[0047] The sealing ring 254 includes an inner wall 260 and a consumable outer wall 258. Each of walls 258 and 260 is arranged as a stack, including segments in each of layers M1-M8 and through-hole structures in each of layers VIA1-VIA7. Two types of through-hole structures are present in the sealing ring 254: discrete through-holes and through-hole strips. Further details regarding a sealing ring including an inner wall, a consumable outer wall, through-hole strips, and discrete through-holes are disclosed in U.S. Patent No. 8,334,582, issued December 18, 2012, the entire contents of which are incorporated herein by reference. For example, an integrated circuit structure includes a semiconductor chip. The semiconductor chip includes: a semiconductor substrate; a plurality of low-k dielectric layers above the semiconductor substrate; a first passivation layer above the plurality of low-k dielectric layers; a second passivation layer above the first passivation layer; and a first sealing ring adjacent to an edge of the semiconductor chip, wherein the first sealing ring has an upper surface substantially flush with the bottom surface of the first passivation layer. The trench ring includes at least a portion directly above the first sealing ring. The trench ring extends downward from the top surface of the second passivation layer to at least the interface between the first and second passivation layers. In each of the plurality of low-k dielectric layers, the first sealing ring includes a metal wire ring and a via ring beneath the metal wire ring. In each of the plurality of low-k dielectric layers, the first sealing ring also includes a discrete via beneath and adjacent to the metal wire ring, wherein the discrete via is aligned with a wire having a ring shape. The sealing ring includes via strips and discrete vias. The discrete vias can be formed in an array, and the array extends along the edges of each semiconductor chip to form a ring-like structure. In one embodiment, one via strip is located inside the discrete vias, while other via strips are formed outside the discrete vias (close to the edge of each semiconductor chip). Advantageously, by forming discrete through-holes and fine through-hole strips, the etching difficulties caused by corrosion of the large dielectric area used for the through-hole openings are reduced.

[0048] More specifically, each of walls 258 and 260 includes: segment 212 in layer M1; one or more through-hole strips 213 and one or more discrete through-holes 214 in layer VIA1; segment 215 in layer M2; one or more through-hole strips 216 and one or more discrete through-holes 217 in layer VIA2; segment 218 in layer M3; one or more through-hole strips 219 and one or more discrete through-holes 220 in layer VIA3; segment 221 in layer M4; one or more through-hole strips 222 and one or more discrete through-holes 223 in layer VIA4; segment 224 in layer M5; one or more through-hole strips 225 and one or more discrete through-holes 226 in layer VIA5; segment 227 in layer M6; one or more through-hole strips 228 and one or more discrete through-holes 229 in layer VIA6; segment 230 in layer M7; one or more through-hole strips 231 and one or more discrete through-holes 232 in layer VIA7; and segment 233 in layer M8. In some embodiments, contact structure 211 is formed in the CNTK layer, thereby coupling the inner wall 260 of the sides 256(L), 256(R), 256(D) and 256(P) of the sealing ring 254 and the corresponding segment 212 in the consumable outer wall 258 to the substrate 204.

[0049] In some embodiments, the area occupied by a discrete through-hole has an approximately square proportion relative to the distance along the X-axis and the distance along the Y-axis. In some embodiments, the area occupied by the discrete through-hole is rectangular and has a major axis-to-minor axis ratio of less than about 2. A through-hole strip is an extended version of the discrete through-hole. In some embodiments, the area occupied by the through-hole strip has a rectangular proportion, and the minor axis of the through-hole strip is approximately twice the major axis of the discrete through-hole, and the major axis of the through-hole strip is substantially larger than the minor axis of the through-hole strip.

[0050] In some embodiments, for the left side 256(L) of the sealing ring 254: the length of the major axis of each of the through-hole strips 213, 216, 219, 222, 225, 228 and 231 in the outer wall 258 is equal to the length of the major axis of the outer wall 258 in the left side 256(L); and the length of the major axis of each of the through-hole strips 213, 216, 219, 222, 225, 228 and 231 in the inner wall 260 is equal to the length of the major axis of the inner wall 260 in the left side 256(L). In some embodiments, for the right side 256(R) of the sealing ring 254: the dimension of the major axis of each of the through-hole strips 213, 216, 219, 222, 225, 228, and 231 in the consumable outer wall 258 is equal to the dimension of the major axis of the outer wall 258 in the right side 256(R); and the dimension of the major axis of each of the through-hole strips 213, 216, 219, 222, 225, 228, and 231 in the inner wall 260 is equal to the dimension of the major axis of the inner wall 260 in the right side 256(R). In some embodiments, for the distal side 256(D) of the sealing ring 254 (see... Figures 3B-3F The major axis dimension of each of the through-hole strips 213, 216, 219, 222, 225, 228, and 231 in the outer wall 258 is equal to the major axis dimension of the outer wall 258 in the distal 256(D); and the major axis dimension of each of the through-hole strips 213, 216, 219, 222, 225, 228, and 231 in the inner wall 260 is equal to the major axis dimension of the inner wall 260 in the distal 256(D). In some embodiments, for the proximal 256(P) of the sealing ring 254 (see... Figures 3B-3F The major axis of each of the through-hole strips 213, 216, 219, 222, 225, 228 and 231 in the outer wall 258 is equal to the major axis of the outer wall 258 in the proximal side 256(P); and the major axis of each of the through-hole strips 213, 216, 219, 222, 225, 228 and 231 in the inner wall 260 is equal to the major axis of the inner wall 260 in the proximal side 256(P).

[0051] In some embodiments (not shown), the minor axis of each of the through-hole strips 213, 216, 219, 222, 225, 228, and 231 in the outer wall 258 is substantially equal to the minor axis of the outer wall 258 in the left side 256(L), resulting in wall 258 excluding the corresponding discrete through holes 214, 217, 220, 223, 226, 229, and 232; and the minor axis of each of the through-hole strips 213, 216, 219, 222, 225, 228, and 231 in the inner wall 260 is substantially equal to the minor axis of the inner wall 260 in the left side 256(L), resulting in wall 260 excluding the corresponding discrete through holes 214, 217, 220, 223, 226, 229, and 232.

[0052] Semiconductor device 202A also includes a first intra-com stack 236(1) and a second intra-com stack 236(2). The intra-com stack 236(1) includes intra-com segments 238(1) in each of the (i)th layers (layer M_i) from layers M1 to M2-M8, where i is a positive integer. Figure 2A In this context, i = 3 and layer M_i is layer M3. In some embodiments, i is a value other than 3. The internal communication stack 236(2) includes internal communication segments 238(2) in each of layers M1 to M_i, wherein in Figure 2A In the middle, (again) layer M_i is M3. Each internal communication segment 238(1) extends and is coupled between the corresponding portion of the core region 206(1) and the corresponding portion of the I / O region 208(1). Each internal communication segment 238(2) extends and is coupled between the corresponding portion of the core region 206(2) and the corresponding portion of the I / O region 208(2).

[0053] exist Figure 2A In the semiconductor device 202A, there are also guard walls (or lower walls) 252(1) and 252(2). Guard walls 252(1) and 252(2) are correspondingly aligned above internal communication stacks 236(1) and 236(2). Each of guard walls 252(1) and 252(2) extends from the distal side 256(D) of sealing ring 254 (see See Figures 3B-3F ) extends to proximal 256(P) (see Figures 3B-3F A protective wall 252(1) is located between and isolated from the core region 206(1) and the I / O region 208(1). A protective wall 252(2) is located between and isolated from the core region 206(2) and the I / O region 208(2).

[0054] Each of the retaining walls 252(1) and 252(2) includes segments in each of the (i + 1)-th metallization layer (layer M_i+1) to the (k)-th metallization layer (layer M_k) of layers M2 - M8, where k is a positive integer and i < k. No metallization layer is located between layer M_i and layer M_i+1. Again, in Figure 2A i = 3, so layer M_i+1 is layer M4. Additionally, in Figure 2A k = 7, so layer M_k is M7. In some embodiments, k = 8 such that M_k is M8, which is reflected in Figure 2A by showing segments 233, via bars 231, and discrete vias 232 in each of the retaining walls 252(1) and 252(2) using dashed lines.

[0055] More specifically, each of the retaining walls 252(1) and 252(2) includes: segment 221 in layer M4; one or more via bars 222 and one or more discrete vias 223 in VIA4; segment 224 in layer M5; one or more via bars 225 and one or more discrete vias 226 in VIA5; segment 227 in layer M6; one or more via bars 228 and one or more discrete vias 229 in VIA6; segment 230 in layer M7; one or more via bars 231 and one or more discrete vias 232 in VIA7; and segment 233 in layer M8.

[0056] In some embodiments, the proportion of the occupied area of the via bars 222, 225, 228, and 231 in each of the retaining walls 252(1) and 252(2) corresponds to the proportion of the occupied area of the via bars 222, 225, 228, and 231 in the inner walls 260 of the left side 256(L) and the right side 256(R) of the sealing wall 254. In some embodiments, the proportion of the occupied area of the discrete vias 223, 226, 229, and 232 in each of the retaining walls 252(1) and 252(2) corresponds to the proportion of the occupied area of the via bars 223, 226, 229, and 232 in the inner walls 260 of the left side 256(L) and the right side 256(R) of the sealing wall 254.

[0057] In Figure 2A the semiconductor device 202A further includes retaining walls (or lower walls) 240(1) and 240(2). Each of the retaining walls 240(1) and 240(2) extends from the distal side 256(D) of the sealing ring 254 (see Figures 3B-3F ) to the proximal side 256(P) (see Figures 3B-3FA protective wall 240(1) is located between and isolated from the I / O area 208(1). A protective wall 252(2) is located between and isolated from the I / O area 208(2).

[0058] Wall 240(1) includes an inner wall 244(1) and a consumable outer wall 242(1). Wall 240(2) includes an inner wall 244(2) and a consumable outer wall 242(2). Each of walls 242(1), 242(2), 244(1), and 244(2) is arranged as a stack, comprising: a segment in each of the (p)th metallization layers (layer M_p) of layers M1 to M2-M8, where p is a positive integer and 2≤p; and at least one through-hole strip and at least one discrete through-hole in each of layers VIA2-VIA7 corresponding to layers M2 to M_p. Figure 2A In this case, p = 4, such that layer M_p is M4. In some embodiments, p is a positive integer other than p = 4, and it is also 2 ≤ p.

[0059] More specifically, each of the retaining walls 240(1) and 240(2) includes: a segment 212 in layer M1; one or more via strips 213 and one or more discrete vias 214 in layer VIA1; a segment 215 in layer M2; one or more via strips 216 and one or more discrete vias 217 in layer VIA2; a segment 218 in layer M3; one or more via strips 219 and one or more discrete vias 220 in VIA3; and a segment 221 in layer M4. In some embodiments, a contact structure 211 is formed in the CNTK layer, whereby the corresponding segments 212 in the inner walls 244(1) and 244(2) and the consumable outer walls 242(1) and 242(2) of the corresponding retaining walls 240(1) and 240(2) are coupled to the substrate 204.

[0060] In some embodiments, the proportion of the occupied area of the through-hole strips 213, 216, and 219 in each of the inner walls 244(1) and 244(2) corresponding to the retaining walls 240(1) and 240(2) corresponds to the proportion of the occupied area of the through-hole strips 213, 216, and 219 in the inner wall 260 of the left side 256(L) and the right side 256(R) of the sealing wall 254. In some embodiments, the proportion of the occupied area of the discrete through-holes 214, 217, and 220 in each of the inner walls 244(1) and 244(2) corresponding to the retaining walls 240(1) and 240(2) corresponds to the proportion of the occupied area of the discrete through-holes 217, 220, and 223 in the inner wall 260 of the left side 256(L) and the right side 256(R) of the sealing wall 254. In some embodiments, the proportion of the occupied area of the through-hole strips 213, 216, and 219 in each of the consumable outer walls 242(1) and 242(2) corresponding to the retaining walls 240(1) and 240(2) corresponds to the proportion of the occupied area of the through-hole strips 213, 216, and 219 in the consumable outer wall 258 of the left side 256(L) and the right side 256(R) of the sealing wall 254. In some embodiments, the proportion of the occupied area of the discrete through-holes 214, 217, and 220 in each of the consumable outer walls 244(1) and 244(2) corresponding to the retaining walls 240(1) and 240(2) corresponds to the proportion of the occupied area of the discrete through-holes 217, 220, and 22~ in the consumable outer wall 258 of the left side 256(L) and the right side 256(R) of the sealing wall 254.

[0061] The semiconductor device 202A further includes an inter-com stack 246. The inter-com stack 246 includes inter-com segments 248 in each of the (p + 1)-th metalization layer (layer M_p+1) to the (q)-th metalization layer (layer M_q) of layers M2 - M8, where q is a positive integer and p < q. In Figure 2A , p = 4, q = 6, layer M_p+1 is M5, and layer M_q is layer M6. In some embodiments, q is a value other than i = 6. The inter-com stack 246 includes inter-com segments 248 in each layer from layer M_p+1 to M_i, where in Figure 2A , (again) layer M_i is M3. Each internal communication segment 246 extends between and thereby couples corresponding portions of the I / O region 208(1) and the I / O region 208(2).

[0062] In Figure 2A , the semiconductor device 202A further includes retaining walls (or lower walls) 262(1) and 262(2). Each of the retaining walls 262(1) and 262(2) extends from the distal side 256(D) of the sealing ring 254 (see Figures 3B-3F ) to the proximal side 256(P) (see Figures 3B-3F A protective wall 262(1) is located between I / O area 208(1) and consumable area 209, and is isolated from each of them. A protective wall 262(2) is located between I / O area 208(2) and consumable area 209, and is isolated from each of them.

[0063] Wall 262(1) includes an inner wall 266(1) and a consumable outer wall 264(1). Wall 266(2) includes an inner wall 266(2) and a consumable outer wall 264(2). Each of walls 264(1), 264(2), 266(1) and 266(2) is arranged as a stack, comprising a segment in each of the (q+1)th metallized layer (layer M_q+1) to the top metallized layer (layer M_top) of layers M3-M8; and at least one through-hole strip and at least one discrete through-hole in each of layers VIA3-VIA7 corresponding to layers M_q+1 to M_top. No metallized layer is located between layers M_q and M_q+1. Again, in Figure 2A In this case, i = 6, therefore layer M_q+1 is layer M7. Furthermore, in... Figure 2A In the middle, layer M_top is M8. More specifically, each of the wall retainers 240(1) and 240(2) includes: segment 230 in layer M7; one or more through-hole strips 231 and one or more discrete through-holes 232 in VIA7; and segment 233 in layer M8.

[0064] In some embodiments, the proportion of the area occupied by the through-hole strip 231 in each of the inner walls 266(1) and 266(2) of the corresponding protective walls 262(1) and 262(2) corresponds to the proportion of the area occupied by the through-hole strip 231 in the inner walls 260 of the left side 256(L) and right side 256(R) of the sealing wall 254. In some embodiments, the proportion of the area occupied by the discrete through-hole 232 in each of the inner walls 266(1) and 266(2) of the corresponding protective walls 262(1) and 262(2) corresponds to the proportion of the area occupied by the discrete through-hole 232 in the inner walls 260 of the left side 256(L) and right side 256(R) of the sealing wall 254. In some embodiments, the proportion of the area occupied by the through-hole strip 231 in each of the consumable outer walls 264(1) and 264(2) corresponding to the protective walls 262(1) and 262(2) corresponds to the proportion of the area occupied by the through-hole strip 231 in the consumable outer walls 258 of the left side 256(L) and right side 256(R) of the sealing wall 254. In some embodiments, the proportion of the area occupied by the discrete through-hole 232 in each of the consumable outer walls 264(1) and 264(2) corresponding to the protective walls 262(1) and 262(2) corresponds to the proportion of the area occupied by the discrete through-hole 232 in the consumable outer walls 258 of the left side 256(L) and right side 256(R) of the sealing wall 254.

[0065] exist Figure 2A In the semiconductor device 202A, a wall gasket 268 is also located on the sealing ring 254.

[0066] Wall pad 268 has a left side 270 (L), a right side 270 (R), and a distal side 270 (D) (see...) Figure 3A Where the descriptor far side is relative to the containing Figure 3A (at the bottom of the page) and near side 270 (P) (see again) Figure 3A The descriptor proximal to the containing Figure 3A (At the bottom of the page). Sides 270(L), 270(R), 270(D), and 270(P) of the wall gasket 268 correspond to sides 256(L), 256(R), 256(D), and 256(P) of the sealing ring 254. The first and second portions of the wall gasket 268 are respectively located in the passivation layers PVST1 and PVST2.

[0067] The sides 270(L), 270(R), 270(D), and 270(P) of the wall pad 268 have a Y-shape relative to their long axes. In some embodiments, the material forming the wall pad 268 includes aluminum. In some embodiments, the benefit of the wall pad 268 is that it helps the sealing ring 254 reduce mechanical stress associated with the cutting process. Further details regarding the wall pad are disclosed in U.S. Patent No. 8,334,582, issued December 18, 2012, the entire contents of which are (again) incorporated herein by reference. For example, a semiconductor chip includes: a semiconductor substrate; a plurality of low-k dielectric layers above the semiconductor substrate; a first passivation layer above the plurality of low-k dielectric layers; and a second passivation layer above the first passivation layer. A first sealing ring is adjacent to an edge of the semiconductor chip, wherein the first sealing ring has an upper surface substantially flush with the bottom surface of the first passivation layer. The second sealing ring is adjacent to the first sealing ring and is located on the inner side of the semiconductor chip compared to the first sealing ring. The second sealing ring includes wall pads in the first passivation layer and the second passivation layer.

[0068] Furthermore, the semiconductor device 202A includes chips 203(1) and 203(2). Chip 203(1) includes: a core region 206(1); an I / O region 208(1); a portion of the left side 256(L), the distal side 256(D), and the proximal side 256(P) of a sealing ring 254; a portion of the left side 270(L), the distal side 270(D), and the proximal side 270(P) of a wall pad 268; an internal communication stack 236(1); a protective wall 252(1); a protective wall 240(1); a portion of an interconnected communication stack 246; a protective wall 262(1); a protective wall 272(1); and a consumable area and a portion of 209. Chip 203(2) includes: a core region 206(2); an I / O region 208(2); a portion of the right side 256(R), the distal side 256(D), and the proximal side 256(P) of a sealing ring 254; a portion of the right side 270(R), the distal side 270(D), and the proximal side 270(P) of a wall pad 268; an internal communication stack 236(2); a protective wall 252(2); a protective wall 240(2); a portion of an intercommunication stack 246; a protective wall 262(2); a protective wall 272(2); and a consumable area and a portion of 209.

[0069] According to another method, a dual-chip semiconductor device lacking a sealing structure is provided, which would otherwise correspond to the guards 252(1) and 252(2) in at least some embodiments. When the dual-chip semiconductor device according to the other method is diced, the core region of each of the two resulting single-chip semiconductor devices is susceptible to moisture intrusion through the corresponding I / O region. Moisture enters the single chip through the remaining portion of the interconnect stack after the dicing process. The remaining portion of the interconnect stack includes not only the remaining portion of the interconnect segments in the first subset of the metallization layer, but also the remaining portion of the corresponding interconnect layer. More specifically, moisture propagates through the dielectric material in the remaining portion of the interconnect layer, through the corresponding portion of the interconnect layer in the I / O stack, and forward to a portion of the interconnect layer in the core region. In contrast, according to some embodiments, guards 252(1) and 252(2) reduce moisture intrusion according to the other method, even if they do not prevent moisture intrusion, which improves the corresponding single-chip semiconductor device including chip 203(1) (see Figure 2B The reliability of the single-chip semiconductor device 202B and the corresponding single-chip semiconductor device (not shown) including chip 203 (2).

[0070] exist Figure 2A In the semiconductor device 202A, there are also wall pads 272(1) and 272(2) located on the corresponding protective walls 262(1) and 262(2).

[0071] Each of wall pads 272(1) and 272(2) is located from the distal side 270(D) of wall pad 268 (see also...) Figure 3A ) extends to the proximal 270 (P) (see Figure 3A The first and second portions of each of wall pads 272(1) and 272(2) are respectively located in passivation layers PVST1 and PVST2. The long axis of wall pad 272(1) is substantially parallel to the long axis of wall 266(1). The long axis of wall pad 272(2) is substantially parallel to the long axis of wall 266(2).

[0072] Each of the wall pads 272(1) and 272(2) has a Y-shaped vertical cross-section relative to the major axis of each of the wall pads 272(1) and 272(2). In some embodiments, the material forming each of the wall pads 272(1) and 272(2) includes aluminum. In some embodiments, the benefit of each of the wall pads 272(1) and 272(2) is that the wall pads 272(1) and 272(2) help reduce the mechanical stress associated with the cutting process in each of the corresponding guard walls 262(1) and 262(2). Further details regarding the wall pads are disclosed in U.S. Patent No. 8,334,582, granted December 18, 2012, the entire contents of which are (again) incorporated herein by reference.

[0073] According to another approach, a dual-chip semiconductor device lacking both a sealing structure and a gasket structure is provided; otherwise, the sealing structure would correspond to the guard walls 262(1) and 262(2) in at least some embodiments, and the gasket structure would correspond to the wall pads 272(1) and 272(2) in at least some embodiments. During the dicing process, the interconnected stack is subjected to mechanical stress, and the other approach lacks a structure to mitigate this mechanical stress. In contrast, according to some embodiments, the wall pads 272(1) and 272(2) are correspondingly stacked on the guard walls 262(1) and 262(2), reducing the mechanical stress experienced by the interconnected stack 246 during the dicing process. This improves the performance of the corresponding single-chip semiconductor device including chip 203(1) (see [link to documentation]). Figure 2B The reliability of the single-chip semiconductor device 202B and the corresponding single-chip semiconductor device (not shown) including chip 203 (2).

[0074] Figure 2B This is a cross-sectional view of a semiconductor device 202B according to some embodiments.

[0075] Semiconductor device 202B is a single-chip semiconductor device including chip 203(1). Semiconductor device 202B has a cut edge 274(3) because semiconductor device 202A is cut in half by cutting through consumable region 209 of semiconductor device 202A.

[0076] Chip 203(1) includes: a core region 206(1); an I / O region 208(1); a portion of the left side 256(L), the distal side 256(D), and the proximal side 256(P) of a sealing ring 254; a portion of the left side 270(L), the distal side 270(D), and the proximal side 270(P) of a wall pad 268; an internal communication stack 236(1); a protective wall 252(1); a protective wall 240(1); the remaining portion 246' of an intercommunication stack 246; a protective wall 262(1); a protective wall 272(1); and the remaining portion 209' of a consumable area 209. The remaining portion 246' of the intercommunication stack 246 includes the remaining portion 248' of segment 248.

[0077] Figures 3A-3F This is a top view of a corresponding layer of a semiconductor device according to some embodiments.

[0078] More in detail, Figures 3A-3F yes Figure 2A A top view of the corresponding layer of semiconductor device 202A. Although named using the 3 series numbering, Figures 3A-3F use Figure 2A The 2 series number annotation.

[0079] More specifically, Figure 3A yes Figure 2A A top view of the passivation layer PVST1 of the semiconductor device 202A. For simplicity, Figure 3A ILD material is not shown. For the context, Figure 3A The structure in layer M8 below is shown using dashed lines.

[0080] More specifically, Figure 3B yes Figure 2A A top view of layer M8 of semiconductor device 202A. Figure 3C yes Figure 2A A top view of layer M7 of semiconductor device 202A. Figure 3D yes Figure 2A A top view of each of layers M5 and M6 of the semiconductor device 202A. Figure 3E yes Figure 2A A top view of layer M4 of semiconductor device 202A. Figure 3F yes Figure 2A A top view of each of layers M1, M2 and M3 of the semiconductor device 202A.

[0081] Figure 4 This is a top view of wafer 376 according to some embodiments.

[0082] Wafer 376 includes multiple semiconductor devices 302A', where an apostrophe indicates a pre-diced state. To prevent damage to the semiconductor devices 302A' during the dicing process, consumable (or sacrificial) regions 384 are reserved between the semiconductor devices 302A'. The consumable regions 384 are at least partially consumed by the dicing process. Wafer 376 is organized into columns 781(1)-378(3) and rows 379(1)-379(7) of the semiconductor devices 302A'. Wafer 376 also includes regions 380 that are insufficient to accommodate instances of semiconductor devices 302A'.

[0083] If reference Figure 4 Assume that testing has been performed to determine which of chips 303(1) and 303(2) in each semiconductor device 302A (if any) is defective. The reference number of the defective chip is appended with parentheses "(D)", for example, see the defective chip 303(1)(D) at the intersection of column 378(1) and row 379(5). The defect-free chip is appended with parentheses "(N)", for example, the defect-free chip 303(3)(N) at the intersection of column 378(2) and row 379(3). If one of the two chips in a given instance of semiconductor 302A is defective, the given instance of semiconductor 302A is separated, and the remaining defect-free chip represents semiconductor device 302B', where the apostrophe indicates a pre-cut state.

[0084] Boundary 382' indicates two adjacent instances of semiconductor device 302A, which are designated not to be separated by a dicing process. Each semiconductor device 302A within boundary 382' has two defect-free chips.

[0085] Figure 5A A flowchart of a method 500A for manufacturing a semiconductor device according to some embodiments.

[0086] Method 500A includes block 502. Block 502 itself includes blocks 508, 510, 512, 514, 517, 519, 520, and 521. At block 502, first and second core regions, first and second I / O regions, consumable regions, and sealing rings are formed with metallization layers (including inter-com segments) and interconnect layers, and first and second protective walls are incrementally formed using corresponding photolithography processes (see [link to relevant documentation]). Figure 8 Examples of the first and second core regions are corresponding core regions 206(1) and 206(2). Examples of the first and second I / O regions are corresponding I / O regions 208(1) and 208(2). An example of a consumable region is consumable region 509. An example of a sealing ring is sealing ring 254. Examples of metallization layers include... Figure 2A Layers M1-M8. Examples of a subset of metallization layers are M5-M6, and an example of an interconnect segment is interconnect segment 248. Examples of interconnect layers include... Figure 2A Layers VIA1-VIA7. Examples of the first and second protective walls are the corresponding protective walls 252(1) and 252(2).

[0087] During the formation of the structure in box 502, spatial relationships between the structures are also established. Boxes 508, 510, 512, 514, 517, 519, 520, and 521 included in box 502 represent how spatial relationships are established. For the purposes of discussion, the boxes in box 502 are discussed in the order of 508, 510, 512, 514, 517, 519, 520, and 521. However, in some embodiments, other orders of boxes 508, 510, 512, 514, 517, 519, 520, and 521 are considered. Therefore, the order 508, 510, 512, 514, 517, 519, 520, and 521 is not intended to be limiting. In some embodiments, box 502 is completed with one or more boxes (not described) in addition to boxes 508, 510, 512, 514, 517, 519, 520, and 521.

[0088] At box 508, a consumable region is located between the first and second I / O regions. An example of a consumable region located between the first and second I / O regions is consumable region 209, which is located between I / O regions 208(1) and 208(2). The process proceeds from box 508 to box 510.

[0089] At box 510, the first I / O region is located between the first core region and the consumable region. An example of the first I / O region located between the first core region and the consumable region is I / O region 208(1), which is located between core region 206(1) and consumable region 209. The process proceeds from box 510 to box 512.

[0090] At box 512, the second I / O region is located between the second core region and the consumable region. An example of a second I / O region located between the second core region and the consumable region is I / O region 208(2), which is located between core region 206(2) and consumable region 209. The process proceeds from box 512 to box 514.

[0091] At box 514, a sealing ring is arranged to surround and isolate from the first and second core regions and the first and second I / O regions. An example of a sealing ring arranged to surround and isolate from the first and second core regions, the first and second I / O regions, and the consumable regions is sealing ring 254, which has a left side 256 (L), a right side 256 (R), a distal side 256 (D), and a proximal side 256 (P) surrounding core regions 206 (1) and 206 (2) and I / O regions 208 (1) and 208 (2). The process proceeds from box 514 to box 517.

[0092] At block 517, a mutual communication segment is arranged to extend and thereby couple between corresponding portions of the first and second I / O regions. An example of a mutual communication segment arranged to extend between the first and second I / O regions is mutual communication segment 248, which extends between corresponding portions of I / O regions 208(1) and 208(2). The flow proceeds from block 517 to block 519.

[0093] At frame 519, first and second protective walls are arranged to extend between the first and third walls of the sealing ring. Examples of first and second protective walls arranged to extend between the first and third walls of the sealing ring include corresponding protective walls 252(1) and 252(2), each extending from the distal side 256(D) to the proximal side 256(P) of the sealing ring 254. The process proceeds from frame 519 to frame 520.

[0094] At box 520, a first protective wall is positioned between and isolated from the first core region and the first I / O region. An example of a first protective wall positioned between and isolated from the first core region and the first I / O region is protective wall 262(1). Protective wall 262(1) is located between and isolated from the core region 206(1) and the I / O region 208(1). The process proceeds from box 520 to box 521.

[0095] At frame 521, a second protective wall is positioned between and isolated from the second core region and the second I / O region. An example of a second protective wall positioned between and isolated from the second core region and the second I / O region is protective wall 262(2). Protective wall 262(2) is located between and isolated from the core region 206(2) and the I / O region 208(2).

[0096] Figure 5B A flowchart of a method 500B for manufacturing a semiconductor device according to some embodiments.

[0097] In some embodiments, method 500B is Figure 5A The method is an extension of 500A.

[0098] exist Figure 5B In method 500B, block 522 is included. At block 522, a portion of the consumable region and corresponding portions of the first and third sides of the sealing ring are removed, thereby dividing the dual-chip semiconductor device into first and second single-chip semiconductor devices. An example of dividing the dual-chip semiconductor device into first and second single-chip semiconductor devices by removing corresponding portions of the consumable region and the first and third sides of the sealing ring is that a portion of the consumable region 209 and corresponding distal side 256(D) and proximal side 256(P) of the sealing ring 254 are removed, thereby dividing the device. Figure 2A The dual-chip semiconductor device 202A. An example of the first single-chip semiconductor device obtained is... Figure 2B Single-chip semiconductor device 202B.

[0099] Figure 5C A flowchart of a method 500C for manufacturing a semiconductor device according to some embodiments.

[0100] In some embodiments, method 500C is Figure 5A The method is an extension of 500A.

[0101] exist Figure 5C In method 500C, blocks 524-526 are included. At block 524, a semiconductor substrate is formed. An example of a semiconductor substrate is substrate 204. The process proceeds from block 524 to block 526.

[0102] At box 526, a corresponding doped region is formed in the semiconductor substrate for each of the first and second core regions and for each of the first and second I / O regions. An example of a corresponding doped region formed in the substrate for each of the first and second core regions and for each of the first and second I / O regions is doped region 210.

[0103] Figure 5D A flowchart of a method 500D for manufacturing a semiconductor device according to some embodiments.

[0104] In some embodiments, method 500D is Figure 5A Method 500D is an extension of method 500A. Method 500D includes box 502', which is... Figure 5A Version 502 of the box. In Figure 5D In the middle, at frame 502', the corresponding photolithography process is used (see...). Figure 8 The structure is formed incrementally. More specifically, at frame 502', a structure is formed comprising... Figure 5A The structure formed by frame 502 includes: first and second stacks corresponding to the first and second core regions, third and fourth stacks corresponding to the first and second I / O regions, and first and second intra-com stacks.

[0105] Each of the first to fourth stacks includes a corresponding segment in one or more metallization layers and a corresponding via structure in one or more interconnect layers. Examples of the first and second internal communication stacks are internal communication stack 236(1) having internal communication segment 238(1) and internal communication stack 236(2) having internal communication segment 238(2).

[0106] exist Figure 5DIn this context, box 502' includes boxes 528, 530, 534, 536, 538, and 540. During the formation of the structure by box 502', spatial relationships between the structures are also established. Again, boxes 528, 530, 534, 536, 538, and 540 included in box 502' indicate how spatial relationships are established. For the purposes of discussion, the boxes in box 502' are discussed in the order of 528, 530, 534, 536, 538, and 540. However, in some embodiments, other orders of boxes 528, 530, 534, 536, 538, and 540 are considered. Therefore, the order 528, 530, 534, 536, 538, and 540 is not intended to be limiting. In some embodiments, in addition to boxes 528, 530, 534, 536, 538, and 540, box 502 is also completed using one or more boxes (not described).

[0107] At box 528, the first to fourth sides of the sealing ring are isolated from the first and second core regions and the first and second I / O regions. Examples of the isolation of the first to fourth sides of the sealing ring from the first and second core regions and the first and second I / O regions include the left side 256(L), right side 256(R), distal side 256(D), and proximal side 256(P) of the sealing ring 254 surrounding the core regions 206(1) and 206(2), and the I / O regions 208(1) and 208(2). The process proceeds from box 528 to box 530.

[0108] At frame 530, the sealing ring is arranged as a stack comprising a conductive segment in each metallization layer and a via structure in each interconnect layer. An example of a sealing ring arranged as a stack comprising a conductive segment in each metallization layer and a via structure in each interconnect layer is sealing ring 254. More specifically, each of the inner wall 258 and the consumable outer wall 260 of sealing ring 254 comprises: a segment 212 in layer M1; one or more via strips 213 and one or more discrete vias 214 in layer VIA1; a segment 215 in layer M2; one or more via strips 216 and one or more discrete vias 217 in layer VIA2; a segment 218 in layer M3; one or more via strips 219 and one or more discrete vias 220 in layer VIA3; and a segment 220 in layer M4. 1; one or more through-hole strips 222 and one or more discrete through-holes 223 in VIA4; segment 224 in layer M5; one or more through-hole strips 225 and one or more discrete through-holes 226 in VIA5; segment 227 in layer M6; one or more through-hole strips 228 and one or more discrete through-holes 229 in VIA6; segment 230 in layer M7; one or more through-hole strips 231 and one or more discrete through-holes 232 in VIA7; and segment 233 in layer M8. The process proceeds from block 530 to block 534.

[0109] At block 534, a first internal communication segment is arranged to extend and thereby couple between corresponding portions of the first core region and the first I / O region. An example of a first internal communication segment arranged to extend and thereby couple between corresponding portions of the first core region and the first I / O region is internal communication segment 238(1). Internal communication segment 238(1) extends and thereby couples between corresponding portions of core region 216(1) and I / O region 208(1). The flow proceeds from block 534 to block 536.

[0110] At box 536, a second internal communication segment is arranged to extend and thereby couple between corresponding portions of the second core region and the second I / O region. An example of a second internal communication segment arranged to extend and thereby couple between corresponding portions of the second core region and the second I / O region is internal communication segment 238(2). Internal communication segment 238(2) extends and thereby couples between corresponding portions of core region 216(2) and I / O region 208(2). The flow proceeds from box 536 to box 538.

[0111] At block 538, a first sheath is arranged as a stack comprising a conductive segment in each of layers M_i+1 to M_k and a via structure in each corresponding interconnect structure. An example of a first sheath arranged as a stack comprising a conductive segment in each of layers M_i+1 to M_k and a via structure in each corresponding interconnect structure is sheath 252(1). More specifically, sheath 252(1) comprises: segment 221 in layer M4; one or more via strips 222 and one or more discrete vias 223 in layer VIA4; segment 224 in layer M5; one or more via strips 225 and one or more discrete vias 226 in layer VIA5; segment 227 in layer M6; one or more via strips 228 and one or more discrete vias 229 in layer VIA6; segment 230 in layer M7; one or more via strips 231 and one or more discrete vias 232 in layer VIA7; and segment 233 in layer M8. The flow proceeds from block 538 to block 540.

[0112] At frame 540, a second sheath is arranged as a stack comprising conductive segments in each of layers M_i+1 to M_k and via structures in each corresponding interconnect structure. An example of a second sheath arranged as a stack comprising conductive segments in each of layers M_i+1 to M_k and via structures in each corresponding interconnect structure is sheath 252(2). More specifically, sheath 252(2) comprises: segment 221 in layer M4; one or more via strips 222 and one or more discrete vias 223 in layer VIA4; segment 224 in layer M5; one or more via strips 225 and one or more discrete vias 226 in layer VIA5; segment 227 in layer M6; one or more via strips 228 and one or more discrete vias 229 in layer VIA6; segment 230 in layer M7; one or more via strips 231 and one or more discrete vias 232 in layer VIA7; and segment 233 in layer M8.

[0113] Figure 5E A flowchart of a method 500E for manufacturing a semiconductor device according to some embodiments.

[0114] In some embodiments, method 500E is Figure 5A Method 500E is an extension of method 500A. Method 500E includes box 502, which is... Figure 5A Version 502 of the box. In Figure 5E In the middle, at frame 502", the corresponding photolithography manufacturing process is used (see...). Figure 8 The structure is formed incrementally. More specifically, at frame 502, a structure is formed comprising... Figure 5A The structure formed by frame 502 includes a third and fourth retaining wall and a fifth and sixth retaining wall. Examples of the third and fourth retaining walls are corresponding retaining walls 240(1) and 240(2). Examples of the fifth and sixth retaining walls are corresponding retaining walls 262(1) and 262(2).

[0115] exist Figure 5E In the middle, box 502 includes boxes 544, 546, 550, 552, 554, 556, 560, 562, 563, 564, 656, 566 and 568.

[0116] exist Figure 5EIn this context, box 502" includes boxes 544, 546, 550, 552, 554, 556, 560, 562, 563, 564, 656, 566, and 568. During the formation of the structure in box 502", spatial relationships between the structures are also established. (Again) boxes 544, 546, 550, 552, 554, 556, 560, 562, 563, 564, 656, 566, and 568 included in box 502" indicate how spatial relationships are established. For discussion purposes, the boxes in box 502' are discussed in the order of 544, 546, 550, 552, 554, 556, 560, 562, 563, 564, 656, 566, and 568. However, in some embodiments, boxes 544, 546, 550, 552, 554, 556, 560, 562, 563, 564, 656, 566, and 568 are considered. Other orders of 556, 560, 562, 563, 564, 656, 566, and 568. Therefore, the orders 544, 546, 550, 552, 554, 556, 560, 562, 563, 564, 656, 566, and 568 are not intended to be limiting. In some embodiments, in addition to boxes 544, 546, 550, 552, 554, 556, 560, 562, 563, 564, 656, 566, and 568, box 502” is also completed with one or more boxes (not described).

[0117] At frame 544, third and fourth retaining walls are arranged to extend between the first and third walls of the sealing ring. Examples of third and fourth retaining walls arranged to extend between the first and third walls of the sealing ring include corresponding retaining walls 240(1) and 240(2), each retaining wall extending from the distal side 256(D) to the proximal side 256(P) of the sealing ring 254. The process proceeds from frame 544 to frame 546.

[0118] At box 546, a third conduit is positioned between and isolated from the first core region and the first I / O region. An example of a third conduit positioned between and isolated from the first core region and the first I / O region is conduit 240(1). Conduit 240(1) is located between and isolated from the core region 206(1) and the I / O region 208(1). The flow proceeds from box 546 to box 550.

[0119] At box 550, a fourth conduit is positioned and isolated between and from the second core region and the second I / O region. An example of a fourth conduit positioned and isolated between and from the second core region and the second I / O region is conduit 240(2). Conduit 240(2) is located between and isolated from the core region 206(2) and the I / O region 208(2). The flow proceeds from box 550 to box 552.

[0120] At frame 552, a third sheath is arranged as a stack comprising a conductive segment in each of layers M_1 to M_p and a via structure in each corresponding interconnect structure. An example of a third sheath arranged as a stack comprising a conductive segment in each of layers M_1 to M_p and a via structure in each corresponding interconnect structure is sheath 240(1). More specifically, sheath 240(1) comprises: a segment in each of layers M1 to M4; and at least one via strip and at least one discrete via in each of layers VIA1-VIA3. More specifically, the wall retainer 240(1) includes: segment 212 in layer M1; one or more through-hole strips 213 and one or more discrete through-holes 214 in layer VIA1; segment 215 in layer M2; one or more through-hole strips 216 and one or more discrete through-holes 217 in layer VIA2; segment 218 in layer M3; one or more through-hole strips 219 and one or more discrete through-holes 220 in VIA3; and segment 221 in layer M4. The process proceeds from block 552 to block 554.

[0121] At frame 554, a fourth sheath is arranged as a stack comprising a conductive segment in each of layers M_1 to M_p and a via structure in each corresponding interconnect structure. An example of a fourth sheath arranged as a stack comprising a conductive segment in each of layers M_1 to M_p and a via structure in each corresponding interconnect structure is sheath 240(2). More specifically, sheath 240(2) comprises: a segment in each of layers M1 to M4; and at least one via strip and at least one discrete via in each of layers VIA1 to VIA3. More specifically, sheath 240(2) comprises: a segment 212 in layer M1; one or more via strips 213 and one or more discrete vias 214 in layer VIA1; a segment 215 in layer M2; one or more via strips 216 and one or more vias 217 in layer VIA2; a segment 218 in layer M3; one or more via strips 219 and one or more discrete vias 220 in layer VIA3; and a segment 221 in layer M4. The process proceeds from box 554 to box 556.

[0122] At block 556, the internal communication segments are arranged as a stack comprising conductive segments in each of layers M_p+1 to M_q and via structures in each corresponding interconnect layer. An example of an inter-communication segment arranged as a stack comprising conductive segments in each of layers M_p+1 to M_q and via structures in each corresponding interconnect layer is inter-communication segment 248 in inter-communication stack 246. The flow proceeds from block 556 to block 560.

[0123] At frame 560, fifth and sixth retaining walls are arranged to extend between the first and third walls of the sealing ring. Examples of fifth and sixth retaining walls arranged to extend between the first and third walls of the sealing ring include corresponding retaining walls 262(1) and 262(2), each retaining wall extending from the distal side 256(D) to the proximal side 256(P) of the sealing ring 254. The process proceeds from frame 560 to frame 562.

[0124] At box 562, a fifth conduit is positioned between and isolated from the first core region and the first I / O region. An example of a fifth conduit positioned between and isolated from the first core region and the first I / O region is conduit 262(1). Conduit 262(1) is located between and isolated from the core region 206(1) and the I / O region 208(1). The process proceeds from box 562 to box 563.

[0125] At box 563, the fifth guard wall is aligned above the third guard wall. An example of a fifth guard wall aligned above the third guard wall is guard wall 262(1), which is aligned above guard wall 240(1). The process proceeds from box 563 to box 564.

[0126] At box 564, a sixth conduit is positioned and isolated between and from the second core region and the second I / O region. An example of a sixth conduit positioned and isolated between and from the second core region and the second I / O region is conduit 262(2). Conduit 262(2) is located between and isolated from the core region 206(2) and the I / O region 208(2). The process proceeds from box 564 to box 565.

[0127] At box 565, the sixth guard wall is aligned above the fourth guard wall. An example of a sixth guard wall aligned above the fourth guard wall is guard wall 262(2), which is aligned above guard wall 240(2). The process proceeds from box 565 to box 566.

[0128] At block 566, a fifth sheath is arranged as a stack comprising a conductive segment in each of layers M_q+1 to M_top and a via structure in each corresponding interconnect structure. An example of a fifth sheath arranged as a stack comprising a conductive segment in each of layers M_q+1 to M_top and a via structure in each corresponding interconnect structure is sheath 262(1). More specifically, sheath 262(1) comprises: a segment 230 in layer M7; one or more via strips 231 and one or more discrete vias 232 in layer VIA7; and a segment 233 in layer M8. The flow proceeds from block 566 to block 568.

[0129] At frame 568, a sixth sheath is arranged as a stack comprising a conductive segment in each of layers M_q+1 to M_top and a via structure in each corresponding interconnect structure. An example of a sixth sheath arranged as a stack comprising a conductive segment in each of layers M_q+1 to M_top and a via structure in each corresponding interconnect structure is sheath 262(2). More specifically, sheath 262(2) comprises: a segment 230 in layer M7; one or more via strips 231 and one or more discrete vias 232 in layer VIA7; and a segment 233 in layer M8.

[0130] Figure 5F A flowchart of a method 500F for manufacturing a semiconductor device according to some embodiments.

[0131] In some embodiments, method 500F is Figure 5A Method 500F is an extension of method 500A. Method 500F includes box 502", which is... Figure 5A Version 502 of the box. In Figure 5F In the middle, at frame 502", the corresponding photolithography process is used (see...). Figure 8 The structure is formed incrementally. More specifically, at frame 502", a structure is formed including... Figure 5A The structure formed by frame 502 includes first and second wall pads. Examples of the first and second wall pads are corresponding wall pads 271(1) and 272(2).

[0132] exist Figure 5F In this context, box 502”' includes boxes 572, 574, and 576. During the formation of the structure by box 502”', spatial relationships between the structures are also established. (Again) boxes 572, 574, and 576 included in box 502”' indicate how spatial relationships are established. For the purposes of discussion, the boxes in box 502”' are discussed in the order of 572, 574, and 576. However, in some embodiments, other orders of boxes 572, 574, and 576 are considered. Therefore, the order 572, 574, and 576 is not intended to be limiting. In some embodiments, box 502”' is completed with one or more boxes (not described) in addition to boxes 572, 574, and 576.

[0133] At frame 572, the major axis of the first wall pad is substantially parallel to the major axis of the fifth wall. An example of the major axis of the first wall pad that is substantially parallel to the major axis of the fifth wall is the major axis of wall pad 272(1), which is substantially parallel to the major axis of wall 266(1). The process proceeds from frame 572 to frame 574.

[0134] At frame 574, the major axis of the second wall pad is substantially parallel to the major axis of the sixth protective wall. An example of a second wall pad whose major axis is substantially parallel to the major axis of the sixth protective wall is the major axis of wall pad 272(2), which is substantially parallel to the major axis of wall 266(2). The flow proceeds from frame 574 to frame 576.

[0135] At frame 576, the vertical cross-section of each of the first and second wall pads is configured to have a Y-shape relative to the major axis of each of the first and second wall pads. Examples of the cross-sections of the first and second wall pads configured to have a Y-shape are wall pads 272(1) and 272(2), each of which has a Y-shaped cross-section.

[0136] Figure 5G A flowchart of a method 500G for manufacturing a semiconductor device according to some embodiments.

[0137] In some embodiments, method 500G is Figure 5A Method 500G is an extension of method 500A. Method 500G includes box 502”, which is Figure 5A Version 502 of the box. In Figure 5F In the middle, at frame 502", the corresponding photolithography process is used (see...). Figure 8 The structure is formed incrementally. More specifically, at frame 502", a structure is formed including... Figure 5A The structure formed by frame 502 includes a wall pad. An example of a wall pad is wall pad 268.

[0138] Box 502"" includes boxes 580-582. During the formation of the structure in box 502"" the spatial relationships between the structures are also established. Boxes 580-582 included in box 502"" again indicate how the spatial relationships are established. For the purposes of discussion, the boxes in box 502"" are discussed in the order of 580-582. However, in some embodiments, the order of box 582 followed by box 580 is considered. Therefore, the order 580-582 is not intended to be limiting. In some embodiments, in addition to boxes 580-582, box 502"" is also completed with one or more boxes (not described).

[0139] At frame 580, the wall gasket is arranged to have first, second, third, and fourth portions corresponding to the first, second, third, and fourth sides of the sealing ring. An example of such a wall gasket is wall gasket 268, which has sides 270(L), 270(R), 270(D), and 270(P) corresponding to sides 256(L), 256(R), 256(D), and 256(P) of the sealing ring 254. The process proceeds from frame 580 to frame 582.

[0140] At frame 582, the vertical cross-section of each of the first to fourth portions of the wall pad is configured to have a Y-shape relative to the major axis of the first to fourth portions. Examples of the cross-sections of the first to fourth portions of the wall pad configured to have a Y-shape are the cross-sections of sides 270(L), 270(R), 270(D), and 270(P) of the wall pad 268, each having a Y-shape.

[0141] Figure 6 This is a flowchart of a method 600 for manufacturing a semiconductor device according to some embodiments, the method including generating a layout diagram.

[0142] According to some embodiments, method 600 may, for example, use EDA system 700 (discussed below). Figure 7 ) and Integrated Circuit (IC) Manufacturing System 800 (discussed below) Figure 8 To implement this.

[0143] exist Figure 6 In method 600, blocks 602-604 are included. At block 602, a layout diagram is generated according to one or more embodiments disclosed herein. Examples of IC packages including semiconductor devices corresponding to the layout generated by method 600 include... Figure 1 IC package 100. According to some embodiments, block 602 is achievable, for example, using EDA system 700 ( Figure 7 (This will be discussed below). Regarding box 602, examples of layout diagrams generated according to box 602 include layout diagrams corresponding to semiconductor devices disclosed herein, layout diagrams corresponding to methods disclosed herein, etc.

[0144] At box 604, based on the layout diagram, at least one of the following is performed: (A) one or more photolithographic exposures are conducted; (B) one or more semiconductor masks are fabricated; or (C) one or more components in a semiconductor device layer are fabricated. See below. Figure 8 The discussion.

[0145] Figure 7 This is a block diagram of an electronic design automation (EDA) EDA system 700 according to some embodiments.

[0146] In some embodiments, EDA system 700 includes an APR system. According to some embodiments, the EDA system 700 can be used, for example, to implement the design layout methods described herein, which represent semiconductor devices disclosed herein (the latter also according to one or more embodiments).

[0147] In some embodiments, the EDA system 700 is a general-purpose computing device that includes a hardware processor 702 and a non-transitory computer-readable storage medium 704. Among other things, the storage medium 704 is encoded, i.e., stores, computer program code 706, i.e., a set of computer-executable instructions. The instructions 706, executed by the hardware processor 702, represent (at least partially represent) an EDA tool that implements some or all of the methods described herein according to one or more embodiments (hereinafter, the process and / or method).

[0148] Processor 702 is electrically coupled to computer-readable storage medium 704 via bus 708. Processor 702 is also electrically coupled to I / O interface 710 via bus 708. Network interface 712 is also electrically coupled to processor 702 via bus 708. Network interface 712 is connected to network 714, thereby enabling processor 702 and computer-readable storage medium 704 to be connected to external components via network 714. Processor 702 is configured to execute computer program code 706 encoded in computer-readable storage medium 704 to make system 700 available for performing part or all of the process and / or method. In one or more embodiments, processor 702 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0149] In one or more embodiments, the computer-readable storage medium 704 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 704 includes semiconductor or solid-state memory, magnetic tape, portable computer floppy disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable storage medium 704 includes read-only optical disk storage (CD-ROM), optical disk read / write (CD-R / W), and / or digital video optical disk (DVD).

[0150] In one or more embodiments, storage medium 704 stores computer program code 706 configured to enable EDA system 700 (where such execution (at least partially) represents EDA tools) to perform part or all of the process and / or method. In one or more embodiments, storage medium 704 also stores information that facilitates the execution of part or all of the process and / or method. In one or more embodiments, storage medium 704 stores a standard cell library 707, including such standard cells disclosed herein.

[0151] EDA system 700 includes an I / O interface 710. The I / O interface 710 is coupled to external circuitry. In one or more embodiments, the I / O interface 710 includes a keyboard, a numeric keypad, a mouse, a trackball, a touchpad, a touchscreen, and / or cursor arrow keys that transmit information and commands to processor 702.

[0152] EDA system 700 also includes a network interface 712 coupled to processor 702. Network interface 712 allows EDA system 700 to communicate with network 714, through which one or more other computer systems are connected. Network interface 712 includes a wireless network interface such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, some or all of the described process and / or method are implemented in two or more systems 700.

[0153] EDA system 700 is configured to receive information via I / O interface 710. The information received via I / O interface 710 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters for processing by processor 702. The information is transferred to processor 702 via bus 708. EDA system 700 is also configured to receive UI-related information via I / O interface 710. This information is stored as a user interface (UI) 742 on computer-readable medium 704.

[0154] In some embodiments, part or all of the process and / or method is implemented as a standalone software application executed by a processor. In some embodiments, part or all of the process and / or method is implemented as a software application as part of an additional software application. In some embodiments, part or all of the process and / or method is implemented as a plug-in to a software application. In some embodiments, at least one of the process and / or method is implemented as a software application as part of an EDA tool. In some embodiments, part or all of the process and / or method is implemented as a software application used by an EDA system 700. In some embodiments, a software application such as those available from CADENCE DESIGNSYSTEMS is used. Alternatively, use other suitable layout generation tools to generate layout diagrams that include standard cells.

[0155] In some embodiments, the process is implemented as the function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / in-system storage or storage units, such as one or more of optical discs (such as DVDs), magnetic disks (such as hard disks), and semiconductor memories (such as ROM, RAM, memory cards, etc.).

[0156] Figure 8 This is a block diagram of an integrated circuit (IC) manufacturing system 800 and its associated IC manufacturing process according to some embodiments.

[0157] In some embodiments, based on a layout diagram, for example, a manufacturing system 800 is used to manufacture at least one of (A) one or more semiconductor masks or (B) at least one component of a layer of a semiconductor integrated circuit.

[0158] exist Figure 8 In this IC manufacturing system 800, entities such as design rooms 820, mask rooms 830, and IC manufacturers / fabs (“fabs”) 850 interact with each other in the design, development, and manufacturing cycles and / or services related to the manufacture of IC devices 860. The entities in system 800 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as intranets and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design rooms 820, mask rooms 830, and IC fabs 850 are owned by a single, larger company. In some embodiments, two or more of the design rooms 820, mask rooms 830, and IC fabs 850 coexist in a shared facility and use shared resources.

[0159] Design room (or design team) 820 generates IC design layout 822. IC design layout 822 includes various geometric patterns designed for IC device 860. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that form various components of the IC device 860 to be manufactured. The various layers combine to form various IC functions. For example, a portion of IC design layout 822 includes various IC components such as active regions, gate electrodes, source and drain electrodes, metal lines or discrete vias for interlayer interconnects, and openings for bonding pads formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Design room 820 implements appropriate design processes to form IC design layout 822. The design process includes one or more of logic design, physical design, or placement and routing. IC design layout 822 is presented in one or more data files containing geometric pattern information. For example, IC design layout 822 may be expressed in GDSII file format or DFII file format.

[0160] Mask chamber 830 includes data preparation 832 and mask fabrication 844. Mask chamber 830 uses an IC design layout 822 to fabricate one or more masks 845 for fabricating various layers of an IC device 860 according to the IC design layout 822. Mask chamber 830 performs mask data preparation 832, where the IC design layout 822 is translated into a representative data file (RDF). Mask data preparation 832 provides the RDF to mask fabrication 844. Mask fabrication 844 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (mask) 845 or a semiconductor wafer 853. Mask layout data preparation 832 processes the design layout 822 to conform to the specific characteristics of the mask writer and / or the requirements of the IC fab 850. Figure 8 In this embodiment, mask data preparation 832 and mask manufacturing 844 are shown as separate elements. In some embodiments, mask data preparation 832 and mask manufacturing 844 may be collectively referred to as mask data preparation.

[0161] In some embodiments, mask data preparation 832 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, or other processing effects. OPC adjusts the IC design layout diagram 822. In some embodiments, mask data preparation 832 includes other resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assistance, phase-shift masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography (ILT) is also used, which treats OPC as an inverse imaging problem.

[0162] In some embodiments, mask data preparation 832 includes a mask rule checker (MRC) that uses a set of mask creation rules to check the IC design layout 822, which has already been processed in the OPC, to ensure sufficient margin to address variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 822 to compensate for lithography effects during mask fabrication 844, which can undo a portion of the modifications performed by the OPC to satisfy the mask creation rules.

[0163] In some embodiments, mask data preparation 832 includes a lithography process check (LPC), which simulates the process to be implemented by an IC fab 850 to manufacture an IC device 860. The LPC simulates the process based on an IC design layout 822 to create a simulated manufactured device, such as IC device 860. Processing parameters in the LPC simulation may include parameters related to various processes in the IC manufacturing cycle, parameters related to the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and combinations thereof. In some embodiments, after a simulated manufactured device has been created via LPC, if the simulated device is not close enough in shape to meet design rules, OPC and / or MRC are repeated to further refine the IC design layout 822.

[0164] It should be understood that, for clarity, the above description of mask data preparation 832 has been simplified. In some embodiments, data preparation 832 includes additional features such as logic operations (LOPs) to modify the IC design layout 822 according to manufacturing rules. Additionally, the processes applied to the IC design layout 822 during data preparation 832 may be performed in various different sequences.

[0165] Following mask data preparation 832 and during mask fabrication 844, a mask 845 or a set of masks 845 is fabricated based on a modified IC design layout 822. In some embodiments, mask fabrication 844 includes performing one or more photolithographic exposures based on the IC design layout 822. In some embodiments, an electron beam (e-beam) or multi-electron beam mechanism is used to form a pattern on the mask (photomask or mask stencil) 845 based on the modified IC design layout 822. The mask 845 can be formed using various techniques. In some embodiments, the mask 845 is formed using a binary technique. In some embodiments, the mask pattern includes opaque regions and transparent regions. Radiation beams, such as ultraviolet (UV) beams, used to expose an image-sensitive material layer (e.g., photoresist) already coated on the wafer are blocked by the opaque regions and pass through the transparent regions. In one example, a binary mask version of the mask 845 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, a phase-shifting technique is used to form mask 845. In the phase-shifting mask (PSM) version of mask 845, various features in the pattern formed on the phase-shifting mask are configured to have appropriate phase difference to enhance resolution and imaging quality. In various examples, the phase-shifting mask can be a decaying PSM or an alternating PSM. The mask generated by mask fabrication 844 is used in a variety of processes. For example, such a mask is used in ion implantation processes to form various doped regions in semiconductor wafer 853, in etching processes to form various etched regions in semiconductor wafer 853, and / or in other suitable processes.

[0166] IC Fab 850 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various IC products. In some embodiments, IC Fab 850 is a semiconductor manufacturing plant. For example, there may be a manufacturing plant for front-end manufacturing (FEOL) of multiple IC products, a second manufacturing plant for providing back-end manufacturing (BEOL) for the interconnection and packaging of IC products, and a third manufacturing plant for providing other services for the manufacturing operations.

[0167] IC fab 850 includes manufacturing tool 852 configured to perform various manufacturing operations on semiconductor wafer 853 to fabricate IC device 860 according to a mask (e.g., mask 845). In various embodiments, manufacturing tool 852 includes one or more of the following: wafer stepper, ion implanter, photoresist coating machine, processing chamber (e.g., CVD chamber or LPCVD furnace), CMP system, plasma etching system, wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes as discussed herein.

[0168] IC fab 850 uses mask 845, manufactured by mask chamber 830, to fabricate IC device 860. Therefore, IC fab 850 uses IC design layout 822 at least indirectly to fabricate IC device 860. In some embodiments, semiconductor wafer 853 is fabricated from IC fab 850 using mask 845 to form IC device 860. In some embodiments, IC fabrication includes one or more photolithographic exposures based at least indirectly on IC design layout 822. Semiconductor wafer 853 includes a silicon substrate or other suitable substrate having material layers formed thereon. Semiconductor wafer 853 also includes one or more of various doped regions, dielectric components, multilayer interconnects, etc. (formed in subsequent fabrication steps).

[0169] Regarding integrated circuit (IC) manufacturing systems (e.g., Figure 8 Details of the system 800 and the associated IC manufacturing process can be found, for example, in U.S. Patent No. 9,256,709, granted February 9, 2016; U.S. Pre-Publication No. 20150278429, published October 1, 2015; U.S. Pre-Publication No. 20140040838, published February 6, 2014; and U.S. Patent No. 7,260,442, granted August 21, 2007, the entire contents of which are incorporated herein by reference.

[0170] For example, in U.S. Patent No. 9,256,709, an IC design layout is generated in a design room (or design team). The IC design layout includes various geometric patterns designed for an IC device. These geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute the various components of the IC device to be manufactured. The various layers combine to form various IC functions. For example, portions of the IC design layout include various IC components such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for forming pads in the semiconductor. These openings will be formed on a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate. The design room performs appropriate design processes to form the IC design layout. These design processes may include logic design, physical design, and / or placement and routing. The IC design layout is presented in one or more data files containing geometric pattern information. A mask room uses the IC design layout to fabricate one or more masks, which are used to fabricate the various layers of the IC device according to the IC design layout. The mask room performs mask data preparation, in which the IC design layout is converted into a form that can be physically written by a mask writer. The design layout prepared by mask data preparation is modified to conform to a specific mask manufacturer and / or mask vendor before fabrication. In this embodiment, mask data preparation and mask fabrication are illustrated as separate elements; however, they can be collectively referred to as mask data preparation. Mask data preparation typically includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, or other processing effects. Mask data preparation may include other resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary features, phase-shift masks, other suitable techniques, or combinations thereof. Mask data preparation 132 also includes a mask rule checker (MRC), which uses a set of mask creation rules to check the IC design layout that has already been processed in the OPC. These mask creation rules may include some geometric and connectivity constraints to ensure sufficient margin.

[0171] For example, in U.S. Patent Publication No. 20150278429, in one embodiment, the IC manufacturing system may employ maskless lithography techniques, such as electron beam lithography or optical maskless lithography. In such a system, mask fabrication is bypassed, and the IC design layout is modified through data preparation suitable for wafer processing using a specific maskless lithography technique. The data preparation modifies the design layout to suit subsequent operations within the IC manufacturing system. The result of the data preparation is represented by one or more data files, such as files in GDSII or DFII file formats. The one or more data files include information on geometric patterns, such as polygons representing the primary design pattern and / or auxiliary components. In this embodiment, the one or more data files also include auxiliary data generated by the data preparation. This auxiliary data will be used to enhance various operations of the IC manufacturing system, such as mask fabrication performed in the mask chamber and wafer exposure performed by the IC manufacturer.

[0172] For example, in Pre-License No. 20140040838, the IC design layout is presented in one or more data files containing geometric pattern information. In one example, the IC design layout is represented in the “GDS” format known in the art. In alternative embodiments, the IC design layout may be transferred between components in an IC manufacturing system in alternative file formats such as DFII, CIF, OASIS, or any other suitable file type. The IC design layout 300 includes various geometric patterns representing components of an integrated circuit. For example, the IC design layout may include primary IC components such as active regions, gate electrodes, source and drain electrodes, metal lines, interlayer interconnect vias, and openings for forming pads in the semiconductor, which will be formed on a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate. The IC design layout may also include auxiliary components, such as those for imaging effects, processing enhancement and / or mask recognition information.

[0173] For example, in U.S. Patent No. 7,260,442, a mask manufacturing system includes: a processing tool for processing a mask; a metrology tool connected to the processing tool for inspecting the mask and obtaining inspection results; and a controller coupled to the processing tool and the metrology tool for generating a manufacturing model of the processing tool and calibrating the manufacturing model based on equipment data, material data, and the mask inspection results. The mask manufacturing system may include at least one processing tool, a metrology tool, a controller, a database, and a manufacturing execution system. The processing tool may be an exposure tool, a developer, an etcher, or a photoresist stripper. The metrology tool performs post-etch or post-stripping inspections and obtains post-etch or post-stripping inspection results, respectively. The controller provides operation-to-operation control for the processing tool, including feedforward and feedback control. The controller receives post-etch or post-stripping inspection results from the metrology tool and retrieves device and material data from the database. The controller, connected to the manufacturing execution system, generates a manufacturing model of the processing tool and calibrates the manufacturing model based on equipment data, material data, and the mask inspection results. The controller also monitors the operating conditions of the processing tool and adjusts the manufacturing model of the processing tool during processing.

[0174] Figures 9A-9B This is a top view (plan view) of a corresponding layer of a semiconductor device according to some embodiments.

[0175] Figures 9A-9B Follow and Figures 3A-3F The numbering scheme is similar to the one described above, which uses a 2-series numbering system. While they correspond, some components differ. To help identify corresponding but still differing components, the numbering convention is designed for... Figures 9A-9B Uses the 9 series numbering, and the numbering convention is for... Figures 3A-3F Use the 2-series numbering system. For example, Figure 9B Project 908(1) is the I / O area. Figure 3A The corresponding item 208(1) is the I / O area. For the sake of brevity, the discussion will focus more on the similarities than on the similarities. Figures 9A-9B and Figures 3A-3F The differences between them.

[0176] In fact, Figure 9A yes Figures 3A-3B In conclusion. Therefore, Figure 9A Helps to observe relative to Figure 9B The differences are as follows.

[0177] Figure 9AThe semiconductor devices include: chips 903A(1) and 903A(2); a sealing ring 954 having sides 956(L), 956(R), 956(D) and 956(P); a consumable region 909 therebetween; and an interconnected communication stack 946 having interconnected segments 948. Chip 903A(1) includes: a core region 906(1); an I / O region 908(1); an internal communication stack 936(1) having an internal communication segment 938(1); a guard wall 940(1); a guard wall 952A(1); and a guard wall 962(1). Chip 903A(2) includes: a core region 906(2); an I / O region 908(2); an internal communication stack 936(2) having an internal communication segment 938(2); a guard wall 940(2); a guard wall 952A(2); and a guard wall 962(2).

[0178] exist Figure 9A In the middle, each of the retaining walls 940(1) and 940(2) extends from side 956(D) of the sealing ring 954 to side 956(P). Similarly, each of the retaining walls 952A(1) and 952A(2) extends from side 956(D) of the sealing ring 954 to side 956(P). Each of the retaining walls 952A(1) and 952A(2) is essentially a straight line. Therefore, each of the retaining walls 952A(1) and 952A(2) has a segment.

[0179] exist Figure 9B In the middle, the retaining wall 952B(1) extends from the first position 941(1)(1) on the retaining wall 940(1) to the second position 941(1)(2) on the retaining wall 940(1). The retaining wall 952B(1) is a segmented continuous line, including segments 953(1)(1), 953(1)(2) and 953(1)(3).

[0180] Segments 953(1)(1) and 953(1)(3) are substantially parallel to the corresponding sides 956(D) and 956(P) of the sealing ring 954. Segment 953(1)(2) is substantially parallel to side 956(L) of the sealing ring 954. Segment 953(1)(1) intersects with the retaining wall 940(1) at the first position 941(1)(1). Segment 953(1)(3) intersects with the retaining wall 940(1) at the second position 941(1)(2). Segment 953(1)(1) extends between segments 953(1)(1) and 953(1)(2).

[0181] exist Figure 9BIn [the figure], the retaining wall 952B(2) extends from the first position 941(1)(2) on the retaining wall 940(2) to the second position 941(2)(2) on the retaining wall 940(2). The retaining wall 952B(2) is a piecewise continuous line, including segments 953(2)(1), 953(2)(2), and 953(2)(3).

[0182] Segments 953(2)(1) and 953(2)(3) are substantially parallel to the corresponding sides 956(D) and 956(P) of the sealing ring 954. Segment 953(2)(2) is substantially parallel to the side 956(R) of the sealing ring 954. Segment 953(2)(1) intersects the retaining wall 940(1) at the first position 941(2)(2). Segment 953(2)(3) intersects the retaining wall 940(2) at the second position 941(2)(2). Segment 953(2)(1) extends between segments 953(2)(1) and 953(2)(2).

[0183] In Figure 9A and Figure 9B each of [the figures], the number of internal communication segments 938(1) is represented by the variable A, the number of mutual communication segments 948 is represented by the variable C, and the number of internal communication segments 938(1) is represented by the variable B. In Figure 9A and Figure 9B [the figures], A = C, and B = C, that is, A = C = B.

[0184] In some embodiments (not shown), A > C and B > C and A = B. In some embodiments (not shown), A > C and B > C and A > B. In some embodiments (not shown), A > C and B > C and A < B.

[0185] In some embodiments (not shown), A < C and B < C and A = B. In some embodiments (not shown), A < C and B < C and A > B. In some embodiments (not shown), A < C and B < C and A < B.

[0186] In some embodiments (not shown), A > C, B < C and A > B. In some embodiments (not shown), A < C, B > C and A < B.

[0187] Figures 10A-10B [The figure] is a cross-sectional view and a three-quarter perspective view of a semiconductor device according to some embodiments.

[0188] Figures 10A-10B Follows a numbering scheme similar to that of Figure 2A-Figure 2A '. Although corresponding, some components are also different. To help identify the corresponding but still different components, the numbering convention uses a 10-series numbering for Figures 10A-10B while the numbering convention uses Figure 2A-Figure 2AUse the 2-series numbering. For example, Figure 10A Item 1072(1) is a wall pad. Figure 2A The corresponding item 272(1) is the wall mat. For the sake of brevity, the discussion will focus more on the similarities than on the similarities. Figures 10A-10B and Figure 2A-Figure 2A The difference between '.

[0189] Specifically, Figure 10A The details of the cross-sectional diagram will be understood in the context of... Figure 10B The discussion will proceed with cases showing essentially the same details (albeit in a three-quarter view). Note that... Figure 10B yes Figure 10A The simplification is not Figure 10B The middle shows Figure 10A All elements.

[0190] Figure 10A The semiconductor device includes: chips 1003(1) and 1003(2); a consumable region 1009 therebetween; and an interconnected communication stack 1046 having one or more interconnected segments 1048. Chip 1003(1) includes: a core region 1006(1); an I / O region 1008(1); an internal communication stack 1036(1); a wall shield 1040(1); a wall shield 1052(1); and a wall pad 1072(1). Chip 1003(2) includes: a core region 1006(2); an I / O region 1008(2); an internal communication stack 1036(2); a wall shield 1040(2); a wall shield 1052(2); and a wall pad 1072(2).

[0191] exist Figure 10A In the middle, wall pads 1072(1) and 1072(2) correspond to Figure 2A and Figure 2A Wall pads 272(1) and 272(2). Wall pads 272(1) and 272(2) are located above the corresponding protective walls 240(1) and 240(2), and wall pads 1072(1) and 1072(2) are located above the corresponding protective walls 1052(1) and 1052(2).

[0192] It will be apparent to those skilled in the art that the disclosed one or more embodiments achieve one or more of the advantages described above. After reading the foregoing specification, those skilled in the art will be able to conceive of various variations, equivalent substitutions, and numerous other embodiments as broadly disclosed herein.

[0193] In an embodiment, a semiconductor device includes: first and second core regions of core circuitry; first and second input / output (I / O) regions of interface circuitry coupled to each other and correspondingly coupled to the first and second core regions and a consumable region; the consumable region being located between the first and second I / O regions relative to a first direction; the first I / O region being located between the consumable region and the first core region; the second I / O region being located between the consumable region and the second core region; a sealing ring having first, second, third, and fourth sides, the sealing ring surrounding and isolating the first and second core regions and the first and second I / O regions; a metallization layer; and an interconnect layer. Interleaved between metallization layers; inter-com segments, located in subsets of the metallization layers, each inter-com segment extending and thus coupled between the first I / O region and the second I / O region; first and second sheaths, each extending from a first side to a third side of the sealing ring, or from a first position to a second position on the corresponding third and fourth sheaths, each of the third and fourth sheaths extending from the first side to the third side of the sealing ring; the first sheath is located between and isolated from the first I / O region; the second sheath is located between and isolated from the second core region and the second I / O region.

[0194] In an embodiment, the semiconductor device further includes: a semiconductor substrate extending along first and second directions, the first and second directions being perpendicular; and each of the first and second core regions and each of the first and second I / O regions including a corresponding doped region formed in the semiconductor substrate. In an embodiment, each metallization layer and each interconnect layer extending along the first and second directions, the first and second directions being perpendicular; and each of the first and second core regions, the first and second I / O regions, and the consumable region having: a corresponding occupied area representing an area relative to the first and second directions; and a height extending along a third direction perpendicular to each of the first and second directions; the first and second core regions, the first and second I / O regions, and the consumable region including: corresponding first, second, third, fourth, and fifth stacks, each of the first to fifth stacks extending along a third direction, each of the first to fifth stacks including a corresponding conductive segment located in one or more metallization layers and a via structure located in one or more interconnect layers; the first to fourth sides of a sealing ring correspondingly isolated from the first and second core regions, the first and second I / O regions, and the consumable region; the sealing ring being arranged as a stack, the stack including: a conductive segment in each metallization layer and a via structure in each interconnect layer. In an embodiment, relative to a third direction, the metallization layer includes: a first metallization layer (layer M_1st) closest to the semiconductor substrate in the metallization layer; a top metallization layer (layer M_top) furthest from the semiconductor substrate in the metallization layer relative to a third direction; and a (i)th metallization layer (layer M_i) between the M_1st layer and the M_top layer; the semiconductor device further includes: a first intra-com stack including a first intra-com segment in each of the M_1st to M_i layers, each first intra-com segment correspondingly extending and thus coupled between a first core region and a first I / O region; and a second intra-com stack including a second intra-com segment in each of the M_1st to M_i layers, each second intra-com segment correspondingly extending and thus coupled between a second core region and a second I / O region. In this embodiment, relative to the third direction, the metallization layer further includes: a (i+1)th metallization layer (layer M_i+1), located between the M_i layer and the M_top layer, with no metallization layer between the M_i and M_i+1 layers; a (k)th metallization layer (layer M_k), located between the M_i layer and the M_top layer; a first sheath is arranged as a stack, the stack including: a conductive segment in each of the M_i+1 to M_k layers; and a via structure in each corresponding interconnect layer; and a second sheath is arranged as a stack, including: a conductive segment in each of the M_i+1 to M_top layers; and a via structure located in each of the corresponding interconnect layers. In this embodiment, the M_k layer and the M_top layer are the same layer.In an embodiment, the semiconductor device further includes: a third and a fourth protective wall; the third protective wall is located between and isolated from the first I / O region and the consumable region; the fourth protective wall is located between and isolated from the second I / O region and the consumable region; and wherein each metallization layer and each interconnect layer extends along a first and a second direction, the first and second directions being perpendicular; relative to a third direction perpendicular to each of the first and second directions, the metallization layer includes: a first metallization layer (layer M_1st), which is closest to the semiconductor substrate in the metallization layer; a top metallization layer (layer M_top), which is furthest from the semiconductor substrate in the metallization layer relative to the third direction; and a (p)th metallization layer (layer M_p), which is located between and isolated from the first I / O region and the consumable region; and a third metallization layer (layer M_p), which is located between and isolated from the second I / O region and the second interconnect region; and a fourth metallization layer (layer M_p), which is located between and isolated from the second interconnect region. Between the M_1st layer and the M_top layer; a (p+1)th metallization layer (layer M_p+1), between the M_p layer and the M_top layer, and no metallization layer between the M_p layer and the M_p+1 layer; and a (q)th metallization layer (layer M_q), between the M_p+1 layer and the M_top layer; a third guard is arranged as a stack, the stack comprising: conductive segments in each of the M_1st to M_p layers; and via structures in each corresponding interconnect layer; and a fourth guard is arranged as a stack, the stack comprising: conductive segments in each of the M_1st to M_j layers; and via structures in each corresponding interconnect layer; a subset of metallization layers in which they communicate with each other. The segments extend from layer M_p+1 to layer M_q; the interconnecting segments are arranged in a stack, including: corresponding interconnecting segments in each of layers M_p+1 to M_q; the semiconductor device also includes: fifth and sixth guards, each extending from a first side of the sealing ring to a third side; the fifth guard is located between and isolated from each of the first I / O region and the consumable region, and aligned above the third guard; the sixth guard is located between and isolated from each of the second I / O region and the consumable region, and aligned above the fourth guard; relative to the third direction, the metallization layer also includes: a (q+1)th metallization layer (layer M_q+1), located between layer M_q and layer M_top, and without a metallization layer in M_ Between the q layer and the M_top layer; a fifth sheath is arranged as a stack, including: conductive segments in each of the M_q+1 to M_top layers; and via structures in each corresponding interconnect layer; and a sixth sheath is arranged as a stack, including: conductive segments in each of the M_q+1 to M_top layers; and via structures in each corresponding interconnect layer; the semiconductor device further includes: first and second wall pads, correspondingly located on the fifth and sixth sheaths; and the long axis of the first wall pad is substantially aligned with the long axis of the fifth sheath; the long axis of the second wall pad is substantially aligned with the long axis of the sixth sheath; and the vertical cross-section of each of the first and second wall pads has a Y shape relative to the corresponding long axis of each of the first and second wall pads. In an embodiment, the material forming each of the first and second wall pads includes aluminum.In one embodiment, the semiconductor device further includes: a wall pad located on a sealing ring, the wall pad having first, second, third, and fourth portions corresponding to first, second, third, and fourth sides of the sealing ring; and wherein, relative to the major axis of each of the first to fourth portions of the wall pad, the vertical cross-section of each of the first to fourth portions of the wall pad has a Y-shape. In one embodiment, the material forming each wall pad includes aluminum.

[0195] In one embodiment, a semiconductor device includes: a core region of core circuitry; an input / output (I / O) region of interface circuitry coupled to the core region; a sealing ring having a first side, a second side, and a third side relative to a first and a second perpendicular direction, the sealing ring surrounding and isolating the core region and the I / O region; and a first protective wall extending from the first side of the sealing ring to the third side or from a first position on a corresponding third and fourth protective wall to a second position, each of the third and fourth protective walls extending from the first side of the sealing ring to the third side; the first protective wall being located between and isolating the core region and the I / O region from each of them.

[0196] In an embodiment, the semiconductor device further includes a second sheath, with the I / O region located between the second sheath and the first sheath, the second sheath being isolated from the I / O region. In another embodiment, the semiconductor device further includes: metallization layers; and interconnect layers interleaved between the metallization layers; wherein each metallization layer and each interconnect layer extends along first and second directions, the first and second directions being perpendicular; and each of the core region and the I / O region has: a corresponding occupied area representing an area relative to the first and second directions; and a height extending along a third direction perpendicular to each of the first and second directions; each of the core region and the I / O region includes: corresponding first and second stacks located on a semiconductor substrate, each of the first and second stacks extending along a third direction, each of the first and second stacks including a corresponding conductive segment located in one or more metallization layers and a via structure located in one or more interconnect layers; first to third sides of a sealing ring are correspondingly isolated from the core region and the I / O region; the sealing ring is arranged as a stack, including: a conductive segment in each metallization layer and a via structure in each interconnect layer. In an embodiment, relative to a third direction, the metallization layer includes: a first metallization layer (layer M_1st) closest to the semiconductor substrate; a top metallization layer (layer M_top) furthest from the semiconductor substrate relative to a third direction; and a (i)th metallization layer (layer M_i) between the M_1st layer and the M_top layer; the semiconductor device further includes: an intra-com stack including intra-com segments in each of the M_1st to M_i layers, each of the intra-com segments correspondingly extending between the core region and the first input / output region and thereby coupling the core region and the first input / output region. In this embodiment, relative to the third direction, the metallization layer further includes: a (i+1)th metallization layer (layer M_i+1), located between the M_i layer and the M_top layer, with no metallization layer between the M_i and M_i+1 layers; a (k)th metallization layer (layer M_k), located between the M_i layer and the M_top layer; the first guard wall is arranged as a stack, the stack including: conductive segments in each of the M_i+1 to M_k layers; and via structures in each corresponding interconnect layer. In this embodiment, the M_k layer and the M_top layer are the same layer.In an embodiment, the semiconductor device further includes: a metallization layer; and interconnect layers interleaved between the metallization layers; wherein each metallization layer and each interconnect layer extends along a first and a second direction, the first and second directions being perpendicular; and relative to a third direction perpendicular to each of the first and second directions, the metallization layer includes: a first metallization layer (layer M_1st) closest to the semiconductor substrate in the metallization layer; a top metallization layer (layer M_top) furthest from the semiconductor substrate in the metallization layer relative to the third direction; and a (p)th metallization layer (layer M_p) between the M_1st layer and the M_top layer; and a second guard is arranged as a stack, including: a conductive segment in each of the M_1st to M_p layers; and a via structure in each corresponding interconnect layer; relative to the third direction, the metallization layer further includes: a (p+1)th metallization layer (layer M_p+1) between the M_p layer and the M_top layer, and no metallization layer between the M_p layer and the M_p+1 layer; a (q)th layer A metallization layer (layer M_q) is located between layers M_p+1 and M_top; a (q+1)th metallization layer (layer M_q+1) is located between layers M_q and M_top, and there is no metallization layer between layers M_q and M_q+1; the semiconductor device also includes: the remaining portion of the mutual communication segment in each of layers M_p+1 to M_q, each remaining portion of the mutual communication segment being correspondingly coupled to an I / O region at a first end and open at a second end, the second end being close to a cleavage of the semiconductor device. The semiconductor device includes: an edge; a third retaining wall extending from a first side of the sealing ring to a third side, an I / O region situated between the third retaining wall and the first retaining wall, and the third retaining wall being isolated from the I / O region; the third retaining wall being arranged as a stack, including: conductive segments in each of layers M_q+1 to M_top; and via structures in each corresponding interconnect layer; the semiconductor device further includes: a wall pad located on the third retaining wall; the long axis of the wall pad being substantially aligned with the long axis of the third retaining wall; and the vertical cross-section of the wall pad having a Y-shape relative to the long axis of the wall pad. In an embodiment, the material forming the wall pad includes aluminum. In an embodiment, the semiconductor device further includes: a wall pad located on the sealing ring, the wall pad having first, second, and third portions corresponding to the first, second, and third sides of the sealing ring; and wherein, relative to the long axis of each of the first to third portions of the wall pad, the vertical cross-section of each of the first to third portions of the wall pad has a Y-shape. In an embodiment, the material forming the wall pad includes aluminum.

[0197] In an embodiment, a method of manufacturing a semiconductor device includes: progressively forming, using a corresponding photolithography process, a consumable region comprising first and second core regions of core circuitry, first and second input / output (I / O) regions of interface circuitry (coupled to each other and correspondingly coupled to the first and second core regions), a sealing ring having first, second, third, and fourth sides, a metallization layer and an interconnect layer (interconnect layers interleaved between metallization layers), inter-com segments in a subset of the metallization layers, and first and second sheaths; and wherein the forming includes: positioning the consumable region between the first and second I / O regions relative to a first direction; positioning the first I / O region between the consumable region and the first core region; and positioning the second I / O region between the first and second core regions. The O region is positioned between the consumable region and the second core region; a sealing ring is arranged to surround the first and second core regions and the first and second I / O regions; each mutual communication segment is correspondingly arranged to extend and thereby couple between corresponding portions of the first I / O region and the second I / O region, the mutual communication segment extending through the consumable region; each of the first and second protective walls is arranged to extend from a first side to a third side of the sealing ring or from a first position to a second position on corresponding third and fourth protective walls, each of the third and fourth protective walls extending from a first side to a third side of the sealing ring; a first protective wall is positioned between and isolated from the first core region and the first I / O region; and a second protective wall is positioned between and isolated from the second core region and the second I / O region.

[0198] In an embodiment, the method further includes: removing a portion of a consumable region extending from a first side to a third side of the sealing ring, as well as corresponding portions of the first and third sides of the sealing ring, thereby dividing the semiconductor device into first and second chips; wherein the first chip includes: a first core region; a first I / O region; a first remaining portion of a subset of metallization layers corresponding to mutually communicating segments; a second side of the sealing ring and corresponding portions of the first and third sides; and a first protective wall; and the second chip includes: a second core region; a second I / O region; a second remaining portion of a subset of metallization layers corresponding to mutually communicating segments; a fourth side of the sealing ring and corresponding portions of the first and third sides; and a second protective wall. In an embodiment, each of the metallization layers and each of the interconnect layers extends along a first direction and a second direction, the first direction and the second direction being perpendicular; and each of the first core region and the second core region, the first input / output region and the second input / output region, and the consumable region has: a corresponding occupied area representing the area relative to the first direction and the second direction; and a height extending along a third direction perpendicular to each of the first direction and the second direction; the forming step further includes: arranging the first core region and the second core region, the first input / output region and the second input / output region, and the consumable region to... The device includes corresponding first, second, third, and fourth stacks, each of which extends along the third direction, and each of which includes a corresponding conductive segment in one or more of the metallization layers and a via structure in one or more of the interconnect layers; and isolates the first to fourth sides of the sealing ring from the first core region and the second core region, as well as the first input / output region and the second input / output region; the sealing ring is arranged in a stack, the stack including a conductive segment in each of the metallization layers and a via structure in each of the interconnect layers. In an embodiment, relative to a third direction, the metallization layer includes: a first metallization layer (layer M_1st) closest to the semiconductor substrate in the metallization layer; a top metallization layer (layer M_top) furthest from the semiconductor substrate in the metallization layer relative to a third direction; and a (i)th metallization layer (layer M_i) between the M_1st layer and the M_top layer; the structure formed by this formation method further includes: a first intra-com stack comprising a first intra-com segment located in each of the M_1st to M_i layers; and a second intra-com stack comprising a second intra-com segment located in each of the M_1st to M_i layers; each first intra-com segment is correspondingly arranged to extend and thereby couple between corresponding portions of the first core region and the first I / O region;The formation further includes: correspondingly arranging each second internal communication segment to extend and thereby couple between corresponding portions of the second core region and the second I / O region. In an embodiment, relative to a third direction, the metallization layer further includes: a (i+1)th metallization layer (layer M_i+1), located between the M_i layer and the M_top layer, with no metallization layer between the M_i and M_i+1 layers; a (k)th metallization layer (layer M_k), located between the M_i layer and the M_top layer; the formation further includes: arranging a first sheath as a stack comprising: conductive segments in each of the M_i+1 to M_k layers; and via structures in each corresponding interconnect layer; and arranging a second sheath as a stack comprising: conductive segments in each of the M_i+1 to M_k layers; and via structures in each corresponding interconnect layer. In an embodiment, the structure formed by the forming method further includes: third and fourth protective walls; fifth and sixth protective walls; first and second wall pads correspondingly located on the fifth and sixth protective walls; and the forming further includes: positioning the third protective wall between and isolated from the first I / O region and the consumable region; positioning the fourth protective wall between and isolated from the second I / O region and the consumable region; and wherein each metallization layer and each interconnect layer extends along the first and second directions, which are perpendicular to each other; relative to a third direction perpendicular to each of the first and second directions, the metallization layer includes: a first metallization layer (layer M_1st) closest to the semiconductor substrate in the metallization layer; a top metallization layer (layer M_top) furthest from the semiconductor substrate in the metallization layer relative to the third direction; a (p)th metallization layer (layer M_p) between the M_1st layer and the M_top layer; a (p+1)th metallization layer (layer M_p+1) between the M_p layer and the M_top layer, and no metallization layer in M_p+1. Between layer _p and layer M_p+1; and the (q)th metallization layer (layer M_q), between layer M_p+1 and layer M_top; the third guard is arranged as a stack, comprising: conductive segments in each of layers M_1st to M_p; and via structures in each corresponding interconnect layer; and the fourth guard is arranged as a stack, comprising: conductive segments in each of layers M_1st to M_p; and via structures in each corresponding interconnect layer; a subset of metallization layers, wherein the interconnecting segments extend from M_p+1 Layers M_p+1 to M_q; The mutual communication segments are arranged in a stack, comprising: corresponding mutual communication segments in each layer from M_p+1 to M_q; each of the fifth and sixth protective walls is arranged to extend from a first side of the sealing ring to a third side; the fifth protective wall is positioned between and isolated from the first I / O area and the consumable area; the fifth protective wall is aligned above the third protective wall; the sixth protective wall is arranged between and isolated from the second I / O area and the consumable area; the sixth protective wall is aligned above the fourth protective wall;Relative to the third direction, the metallization layer further includes: a (q+1)th metallization layer (layer M_q+1), located between layer M_q and layer M_top, with no metallization layer between layer M_q and layer M_top; a fifth sheath arranged as a stack, comprising: conductive segments in each layer from M_q+1 to M_top; and via structures in each corresponding interconnect layer; and a sixth sheath arranged as a stack, comprising: conductive segments in each layer from M_q+1 to M_top; and via structures in each corresponding interconnect layer; first and second wall pads correspondingly formed on the fifth and sixth sheaths; the long axis of the first wall pad aligned substantially parallel to the long axis of the fifth sheath; the long axis of the second wall pad aligned substantially parallel to the long axis of the sixth sheath; and the vertical cross-section of each of the first and second wall pads configured to have a Y-shape relative to the corresponding long axis of each of the first and second wall pads.

[0199] In an embodiment, the method further includes: forming a semiconductor substrate extending along first and second directions, the first and second directions being perpendicular; and forming a corresponding doped region in the semiconductor substrate for each of the first and second core regions and each of the first and second I / O regions. In an embodiment, each metallization layer and each interconnect layer extends along the first and second directions, the first and second directions being perpendicular; and each of the first and second core regions, the first and second I / O regions, and the consumable region has: a corresponding occupied area representing an area relative to the first and second directions; and a height extending along a third direction perpendicular to each of the first and second directions; the formation further includes: arranging the first and second core regions, the first and second I / O regions, and the consumable region to include: corresponding first, second, third, and fourth stacks, each of the first to fourth stacks extending along a third direction, each of the first to fourth stacks including a corresponding conductive segment located in one or more metallization layers and a via structure located in one or more interconnect layers; correspondingly isolating the first to fourth sides of a sealing ring from the first and second core regions and the first and second I / O regions; and arranging the sealing ring as a stack, which includes: a conductive segment in each metallization layer and a via structure in each interconnect layer. In an embodiment, the M_k layer and the M_top layer are the same layer. In an embodiment, the material forming each of the first and second wall pads includes aluminum. In an embodiment, the structure formed by this forming method further includes: a wall pad located on a sealing ring; and the forming further includes: arranging the wall pad to have first, second, third, and fourth portions corresponding to the first, second, third, and fourth sides of the sealing ring; and configuring the vertical cross-section of each of the first to fourth portions of the wall pad to have a Y-shape relative to the major axis of each of the first to fourth portions of the wall pad. In an embodiment, the material forming the wall pad includes aluminum.

[0200] In one embodiment, a method of manufacturing a semiconductor device, for a layout diagram stored on a non-transitory computer-readable medium, includes generating the layout diagram by generating a pattern corresponding to the structure of one or more semiconductor devices disclosed herein. In another embodiment, the method further includes: based on the layout diagram, at least one of the following: (A) performing one or more photolithographic exposures; (B) fabricating one or more semiconductor masks; or (C) fabricating at least one component in a layer of a semiconductor integrated circuit.

[0201] In one embodiment, a system for manufacturing a semiconductor device includes: at least one processor; and at least one memory including computer program code for one or more programs; wherein the at least one memory, the computer program code, and the at least one processor are configured to cause the system to perform a layout drawing generation operation on a layout drawing stored on a non-transitory computer-readable medium, including generating a pattern corresponding to the structure of one or more semiconductor devices disclosed herein. In another embodiment, the system further includes at least one of: a masking facility configured to manufacture one or more semiconductor masks based on the layout drawing; or a manufacturing facility configured to manufacture at least one component of a layer of a semiconductor integrated circuit based on the layout drawing.

[0202] The foregoing has described components of several embodiments, enabling those skilled in the art to better understand the various embodiments of the present invention. Those skilled in the art should understand that other processes and structures can be readily designed or modified based on the present invention to achieve the same objectives and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, comprising: The first and second core regions of the core circuit; The first input / output region and the second input / output region of the interface circuit are coupled to each other and correspondingly coupled to the first core region and the second core region. Consumable area; Relative to the first direction: the consumable area is located between the first input / output area and the second input / output area; the first input / output area is located between the consumable area and the first core area; and the second input / output area is located between the consumable area and the second core area; A sealing ring having a first side, a second side, a third side, and a fourth side, the sealing ring surrounding the first core region and the second core region, as well as the first input / output region and the second input / output region; Metallization layer; Interconnect layers are interleaved between the metallization layers; Intercommunication segments, located in a subset of the metallization layer, each of the intercommunication segments correspondingly extends between the first input / output region and the second input / output region and thereby couples the first input / output region and the second input / output region; The first protective wall and the second protective wall each extend from the first side of the sealing ring to the third side or from the first position on the corresponding third protective wall and the fourth protective wall to the second position, and each of the third protective wall and the fourth protective wall extends from the first side of the sealing ring to the third side; The first protective wall is located between the first core region and the first input / output region and is isolated from each of the first core region and the first input / output region; and The second protective wall is located between the second core region and the second input / output region and is isolated from each of the second core region and the second input / output region.

2. The semiconductor device according to claim 1, wherein, The semiconductor device further includes: A semiconductor substrate extends along a first direction and a second direction, wherein the first direction and the second direction are perpendicular; and Each of the first core region and the second core region, as well as each of the first input / output region and the second input / output region, includes a corresponding doped region formed in the semiconductor substrate.

3. The semiconductor device according to claim 1, wherein: Each of the metallization layers and each of the interconnect layers extends along a first direction and a second direction, wherein the first direction and the second direction are perpendicular to each other. and Each of the first core region and the second core region, the first input / output region and the second input / output region, and the consumable region has: a corresponding occupied area representing the area relative to the first direction and the second direction; And the height extending along a third direction perpendicular to each of the first and second directions; The first core region and the second core region, the first input / output region and the second input / output region, and the consumable region include: corresponding first stack, second stack, third stack, fourth stack, and fifth stack, each of the first to fifth stacks extending along the third direction, and each of the first to fifth stacks including a corresponding conductive segment located in one or more of the metallization layers and a via structure located in one or more of the interconnect layers; and The first to fourth sides of the sealing ring are correspondingly isolated from the first core region and the second core region, the first input / output region and the second input / output region, and the consumable region; The sealing rings are arranged as a stack, which includes conductive segments in each of the metallization layers and via structures in each of the interconnect layers.

4. The semiconductor device according to claim 3, wherein: Relative to the third direction, the metallization layer includes: The first metallization layer is closest to the semiconductor substrate in the metallization layer; Top metallization layer, in which the metallization layer is furthest from the semiconductor substrate in a third direction relative to the third direction; and The (i)th metallization layer is located between the first metallization layer and the top metallization layer; The semiconductor device further includes: A first internal communication stack includes a first internal communication segment located in each of the first metallization layer to the (i)th metallization layer, each of the first internal communication segments correspondingly extending between and thereby coupling the first core region and the first input / output region; and The second internal communication stack includes a second internal communication segment located in each of the first metallization layer to the (i)th metallization layer, each of the second internal communication segments correspondingly extending between the second core region and the second input / output region and thereby coupling the second core region and the second input / output region.

5. The semiconductor device according to claim 4, wherein: Relative to the third direction, the metallization layer further includes: The (i+1)th metallization layer is located between the (i)th metallization layer and the top metallization layer, and there is no metallization layer between the (i)th metallization layer and the (i+1)th metallization layer; The (k)th metallization layer is located between the (i)th metallization layer and the top metallization layer; The first protective wall is arranged as a stack, the stack comprising: a conductive segment located in each of the (i+1)th to (k)th metallization layers; and a via structure located in each of the corresponding interconnect layers; and The second protective wall is arranged as a stack, which includes: a conductive segment in each of the (i+1)th metallization layer to the top metallization layer; and a via structure in each of the corresponding interconnect layers.

6. The semiconductor device according to claim 1, further comprising: The third protective wall and the fourth protective wall; The third protective wall is located between the first input / output area and the consumable area and is isolated from each of the first input / output area and the consumable area; Furthermore, the fourth protective wall is located between the second input / output area and the consumable area and is isolated from each of the second input / output area and the consumable area; and in: Each of the metallization layers and each of the interconnect layers extends along a first direction and a second direction, wherein the first direction and the second direction are perpendicular to each other. The metallization layer comprises, relative to a third direction perpendicular to each of the first and second directions: a first metallization layer, closest to the semiconductor substrate; a top metallization layer, furthest from the semiconductor substrate relative to the third direction; a p-th metallization layer, located between the first metallization layer and the top metallization layer; a p+1-th metallization layer, located between the p-th metallization layer and the top metallization layer, and having no metallization layer between the p-th metallization layer and the p+1-th metallization layer; and a q-th metallization layer, located between the p+1-th metallization layer and the top metallization layer. The third protective wall is arranged as a stack, which includes: a conductive segment located in each of the first metallization layer to the (p)th metallization layer; and a via structure located in each of the corresponding interconnect layers; The fourth protective wall is arranged as a stack, which includes: a conductive segment located in each of the first metallization layer to the M_j layer; and a via structure located in each of the corresponding interconnect layers; The mutual communication segments are subsets of the metallization layers from the (p+1)th metallization layer to the (q)th metallization layer; The mutual communication segments are arranged as a stack, which includes corresponding mutual communication segments located in each of the (p+1)th to (q)th metallization layers; The semiconductor device further includes: a fifth protective wall and a sixth protective wall, each extending from a first side of the sealing ring to a third side; the fifth protective wall is located between the first input / output region and the consumable region, and is isolated from each of the first input / output region and the consumable region, and is aligned above the third protective wall; and the sixth protective wall is located between the second input / output region and the consumable region, and is isolated from each of the second input / output region and the consumable region, and is aligned above the fourth protective wall; and Relative to the third direction, the metallization layer further includes: a (q+1)th metallization layer, located between the (q)th metallization layer and the top metallization layer, and without a metallization layer between the (q)th metallization layer and the (q+1)th metallization layer; and The fifth protective wall is arranged as a stack, the stack comprising: conductive segments in each of the (q+1)th metallization layer to the top metallization layer; and via structures in each of the corresponding interconnect layers; and The sixth protective wall is arranged as a stack, which includes: a conductive segment in each of the (q+1)th metallization layer to the top metallization layer; and a via structure in each of the corresponding interconnect layers; The semiconductor device further includes: a first wall pad and a second wall pad, correspondingly located on the fifth and sixth protective walls; and the major axis of the first wall pad is substantially aligned with the major axis of the fifth protective wall; the major axis of the second wall pad is substantially aligned with the major axis of the sixth protective wall; and the vertical cross-section of each of the first and second wall pads has a Y shape relative to the corresponding major axis of each of the first and second wall pads.

7. The semiconductor device according to claim 6, wherein: The material forming each of the first and second wall pads includes aluminum.

8. A semiconductor device, comprising: The core area of ​​the core circuit; The input / output area of ​​the interface circuit is coupled to the core area; The sealing ring has a first side, a second side, and a third side relative to the vertical first and second directions, and the sealing ring surrounds and isolates the core region and the input / output region from the core region and the input / output region; and A first protective wall extends from a first side of the sealing ring to a third side or from a first position on a corresponding third and fourth protective wall to a second position, each of the third and fourth protective walls extending from the first side of the sealing ring to the third side, the first protective wall being located between the core region and the input / output region and is isolated from each of the core region and the input / output region.

9. The semiconductor device according to claim 8, wherein, The semiconductor device further includes: The second protective wall is located between the input / output area and the first protective wall, and the second protective wall is isolated from the input / output area.

10. The semiconductor device according to claim 8, wherein, The semiconductor device further includes: a metallization layer; and interconnect layers interleaved between the metallization layers; Wherein: each of the metallization layers and each of the interconnect layers extends along a first direction and a second direction, the first direction and the second direction being perpendicular; and each of the core region and the input / output region has: a corresponding occupied area representing the area relative to the first direction and the second direction; and a height extending along a third direction perpendicular to each of the first direction and the second direction; Each of the core region and the input / output region includes: corresponding first and second stacks located on the semiconductor substrate, each of the first and second stacks extending along the third direction, each of the first and second stacks including a corresponding conductive segment located in one or more of the metallization layers and a via structure located in one or more of the interconnect layers; and The first to third sides of the sealing ring are correspondingly isolated from the core region and the input / output region; The sealing rings are arranged as a stack, which includes conductive segments in each of the metallization layers and via structures in each of the interconnect layers.

11. The semiconductor device according to claim 10, wherein: Relative to the third direction, the metallization layer includes: a first metallization layer, which is closest to the semiconductor substrate in the metallization layer; a top metallization layer, which is furthest from the semiconductor substrate in the metallization layer relative to the third direction; and a (i)th metallization layer, which is located between the first metallization layer and the top metallization layer; The semiconductor device further includes an internal communication stack comprising an internal communication segment located in each of the first metallization layer to the (i)th metallization layer, each of the internal communication segments extending correspondingly between the core region and the input / output region and thereby coupling the core region and the input / output region.

12. The semiconductor device according to claim 11, wherein: Relative to the third direction, the metallization layer further includes: a (i+1)th metallization layer, located between the (i)th metallization layer and the top metallization layer, and having no metallization layer between the (i)th metallization layer and the (i+1)th metallization layer; and a (k)th metallization layer, located between the (i)th metallization layer and the top metallization layer; The first protective wall is arranged as a stack, which includes: a conductive segment in each of the (i+1)th to (k)th metallization layers; and a via structure in each of the corresponding interconnect layers.

13. The semiconductor device according to claim 9, further comprising: Metallization layer; Interconnect layers are interleaved between the metallization layers; in: Each of the metallization layers and each of the interconnect layers extends along a first direction and a second direction, the first direction and the second direction being perpendicular to each other; and The metallization layer comprises, relative to a third direction perpendicular to each of the first and second directions: a first metallization layer, closest to the semiconductor substrate; a top metallization layer, furthest from the semiconductor substrate relative to the third direction; and a (p)th metallization layer, situated between the first metallization layer and the top metallization layer; and The second protective wall is arranged as a stack, the stack comprising: a conductive segment in each of the first metallization layer to the (p)th metallization layer; and a via structure in each of the corresponding interconnect layers; Relative to the third direction, the metallization layer further includes: a (p+1)th metallization layer, located between the (p)th metallization layer and the top metallization layer, and having no metallization layer between the (p)th metallization layer and the (p+1)th metallization layer; a (q)th metallization layer, located between the (p+1)th metallization layer and the top metallization layer; and a (q+1)th metallization layer, located between the (q)th metallization layer and the top metallization layer, and having no metallization layer between the (q)th metallization layer and the (q+1)th metallization layer; The semiconductor device further includes: a remaining portion of an interconnecting segment, located in each of the (p+1)th to (q)th metallization layers, each remaining portion of the interconnecting segment being correspondingly coupled to the input / output region at a first end and open at a second end near a dicing edge of the semiconductor device; and a third protective wall extending from a first side to a third side of the sealing ring, the input / output region being located between the third protective wall and the first protective wall, and the third protective wall being isolated from the input / output region. The third protective wall is arranged as a stack, which includes: a conductive segment in each of the (q+1)th metallization layer to the top metallization layer; and a via structure in each of the corresponding interconnect layers; The semiconductor device further includes: a wall pad located on the third protective wall; the long axis of the wall pad is substantially aligned with the long axis of the third protective wall; and the vertical cross-section of the wall pad has a Y shape relative to the long axis of the wall pad.

14. The semiconductor device according to claim 13, wherein: The material forming the wall pad includes aluminum.

15. A method of manufacturing a semiconductor device, the method comprising incrementally forming a structure using a corresponding photolithography process, the structure comprising: The first and second core regions of the core circuit; The first input / output region and the second input / output region of the interface circuit are coupled to each other and correspondingly coupled to the first core region and the second core region; consumable region; A sealing ring having a first side, a second side, a third side, and a fourth side; a metallization layer and an interconnect layer, the interconnect layer being interleaved between the metallization layers; Mutual communication segments are located in a subset of the metallization layer; and the first and second retaining walls; and The formation steps include: Relative to the first direction: the consumable area is positioned between the first input / output area and the second input / output area; the first input / output area is positioned between the consumable area and the first core area; and the second input / output area is positioned between the consumable area and the second core area; The sealing ring is arranged to surround the first core region and the second core region, as well as the first input / output region and the second input / output region; Correspondingly, each of the inter-communication segments is arranged to extend between corresponding portions of the first input / output region and the second input / output region and thereby couple the corresponding portions of the first input / output region and the second input / output region, the inter-communication segment extending through the consumable region; Each of the first and second protective walls is arranged to extend from a first side of the sealing ring to a third side or from a first position on the corresponding third and fourth protective walls to a second position, wherein each of the third and fourth protective walls extends from the first side of the sealing ring to the third side; The first protective wall is positioned between the first core region and the first input / output region, and is isolated from each of the first core region and the first input / output region; and The second protective wall is positioned between the second core region and the second input / output region and is isolated from each of the second core region and the second input / output region.

16. The method of claim 15, further comprising: A portion of the consumable area extending from the first side to the third side of the sealing ring, as well as corresponding portions of the first and third sides of the sealing ring, are removed, thereby dividing the semiconductor device into a first chip and a second chip. and in: The first chip includes: a first core region; a first input / output region; a first remaining portion of corresponding mutually communicating segments located in a subset of the metallization layer; a second side of the sealing ring and corresponding portions of the first and third sides; and a first protective wall; and The second chip includes: the second core region; the second input / output region; a second remaining portion of corresponding mutual communication segments located in a subset of the metallization layer; a fourth side of the sealing ring and corresponding portions of the first and third sides; and the second protective wall.

17. The method of claim 15, wherein: Each of the metallization layers and each of the interconnect layers extends along a first direction and a second direction, wherein the first direction and the second direction are perpendicular to each other. and Each of the first core region and the second core region, the first input / output region and the second input / output region, and the consumable region has: a corresponding occupied area representing the area relative to the first direction and the second direction; And the height extending along a third direction perpendicular to each of the first and second directions; The forming step further includes: arranging the first core region and the second core region, the first input / output region and the second input / output region, and the consumable region to include corresponding first stack, second stack, third stack, and fourth stack, each of the first stack to the fourth stack extending along the third direction, each of the first stack to the fourth stack including a corresponding conductive segment located in one or more of the metallization layers and a via structure located in one or more of the interconnect layers; and correspondingly isolating the first to fourth sides of the sealing ring from the first core region and the second core region, and the first input / output region and the second input / output region; The sealing rings are arranged in a stack, the stack including conductive segments in each of the metallization layers and via structures in each of the interconnect layers.

18. The method of claim 17, wherein: Relative to the third direction, the metallization layer includes: a first metallization layer, which is closest to the semiconductor substrate in the metallization layer; a top metallization layer, which is furthest from the semiconductor substrate in the metallization layer relative to the third direction; and a (i)th metallization layer, which is located between the first metallization layer and the top metallization layer; The structure formed by the forming step further includes: a first internal communication stack, comprising a first internal communication segment located in each of the first metallization layer to the (i)th metallization layer; a second internal communication stack, comprising a second internal communication segment located in each of the first metallization layer to the (i)th metallization layer; and The forming step further includes: correspondingly arranging each of the first internal communication segments to extend between corresponding portions of the first core region and the first input / output region and thereby coupling the corresponding portions of the first core region and the first input / output region; and correspondingly arranging each of the second internal communication segments to extend between corresponding portions of the second core region and the second input / output region and thereby coupling the corresponding portions of the second core region and the second input / output region.

19. The method of claim 18, wherein: Relative to the third direction, the metallization layer further includes: a (i+1)th metallization layer, located between the (i)th metallization layer and the top metallization layer, and having no metallization layer between the (i)th metallization layer and the (i+1)th metallization layer; and a (k)th metallization layer, located between the (i)th metallization layer and the top metallization layer; The forming step further includes arranging the first protective wall as a stack, the stack comprising: conductive segments in each of the (i+1)th to (k)th metallization layers; and via structures in each of the corresponding interconnect layers; and The second protective wall is arranged as a stack, which includes: a conductive segment in each of the (i+1)th to (k)th metallization layers; and a via structure in each of the corresponding interconnect layers.

20. The method of claim 15, further comprising: in: The structure formed by the forming step further includes: the third protective wall and the fourth protective wall; the fifth protective wall and the sixth protective wall; and the first wall pad and the second wall pad, correspondingly located on the fifth protective wall and the sixth protective wall; and The forming step further includes: positioning the third protective wall between the first input / output region and the consumable region and isolating it from each of the first input / output region and the consumable region; and positioning the fourth protective wall between the second input / output region and the consumable region and isolating it from each of the second input / output region and the consumable region; and each of the metallization layers and each of the interconnect layers extends along a first direction and a second direction, the first direction and the second direction being perpendicular; relative to a third direction perpendicular to each of the first direction and the second direction, The metallization layer comprises: a first metallization layer, which is closest to the semiconductor substrate in the metallization layer; a top metallization layer, which is furthest from the semiconductor substrate in the metallization layer relative to the third direction; a (p)th metallization layer, which is located between the first metallization layer and the top metallization layer; a (p+1)th metallization layer, which is located between the (p)th metallization layer and the top metallization layer, and there is no metallization layer between the (p)th metallization layer and the (p+1)th metallization layer; and a (q)th metallization layer, which is located between the (p+1)th metallization layer and the top metallization layer. The forming step also includes arranging the third protective wall as a stack, the stack comprising: a conductive segment in each of the first metallization layer to the (p)th metallization layer; and a via structure in each of the corresponding interconnect layers; The fourth protective wall is arranged as a stack, the stack comprising: a conductive segment in each of the first metallization layer to the (p)th metallization layer; and a via structure in each of the corresponding interconnect layers; wherein the interconnecting segments are a subset of the metallization layers from the (p+1)th metallization layer to the (q)th metallization layer; The interconnecting segments are arranged in a stack, the stack comprising: corresponding interconnecting segments located in each of the (p+1)th to (q)th metallization layers; each of the fifth and sixth protective walls is arranged to extend from a first side to a third side of the sealing ring; the fifth protective wall is positioned between the first input / output region and the consumable region and isolated from each of the first input / output region and the consumable region; the fifth protective wall is aligned above the third protective wall; the sixth protective wall is positioned between the second input / output region and the consumable region and isolated from each of the second input / output region and the consumable region; and the sixth protective wall is aligned above the fourth protective wall; Relative to the third direction, the metallization layer further includes: a (q+1)th metallization layer, located between the (q)th metallization layer and the top metallization layer, and there is no metallization layer between the (q)th metallization layer and the (q+1)th metallization layer; The fifth protective wall is arranged as a stack, the stack comprising: conductive segments in each of the (q+1)th metallization layer to the top metallization layer; and via structures in each of the corresponding interconnect layers; and The sixth retaining wall is arranged as a stack, the stack comprising: a conductive segment in each of the (q+1)th metallization layer to the top metallization layer; and a via structure in each of the corresponding interconnect layers; a first wall pad and a second wall pad are formed correspondingly on the fifth retaining wall and the sixth retaining wall; the long axis of the first wall pad is aligned substantially parallel to the long axis of the fifth retaining wall; the long axis of the second wall pad is aligned substantially parallel to the long axis of the sixth retaining wall; and the vertical cross section of each of the first wall pad and the second wall pad is configured to have a Y shape relative to the corresponding long axis of each of the first wall pad and the second wall pad.

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