Array substrate, preparation method of array substrate and display panel

Abstract

The application provides an array substrate, a preparation method of the array substrate and a display panel. The array substrate comprises an array layer, a first conductive line and a first electrode are arranged on the array layer, the first electrode is electrically connected to the array layer through the first conductive line, and the first conductive line covers at least part of the surface of the first electrode. The first electrode is an annealed electrode. The first conductive line covers at least part of the surface of the first electrode, the first electrode is formed on the array layer first, the first electrode can be an annealed electrode, that is, the first electrode can be formed after annealing treatment, and then the first conductive line is formed. The first electrode subjected to the annealing treatment has relatively strong corrosion resistance to etching solvents, so that excessive etching of the first electrode in the process of etching the first conductive line is alleviated. Therefore, the array substrate, the preparation method of the array substrate and the display panel provided by the application can reduce the phenomenon of excessive etching of the anode in the light transmission area in the preparation process, so that the display effect of the display panel is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display panels, and in particular to an array substrate, a preparation method of the array substrate, and a display panel. BACKGROUND

[0002] With the development of display technology, the market demand for display panels with high screen-to-body ratio is increasingly urgent, and display panels are developing towards full-screen.

[0003] In the related art, a display panel includes a light-transmitting area. A backlight surface of the display panel at the light-transmitting area is integrated with an under-screen functional device. Light can pass through the display panel at the light-transmitting area to reach the under-screen functional device, thereby realizing the function of the under-screen functional device. On the other hand, the display panel at the light-transmitting area can also normally emit light to realize a display function, thereby ensuring that the display panel has a high screen-to-body ratio.

[0004] However, the anode in the light-transmitting area is prone to being excessively etched in the preparation process, thereby affecting the display effect of the display panel. SUMMARY

[0005] In view of at least one of the above technical problems, the embodiments of the present application provide an array substrate, a preparation method of the array substrate, and a display panel, which can reduce the phenomenon of excessive etching of the anode in the light-transmitting area in the preparation process, thereby improving the display effect of the display panel.

[0006] To achieve the above-mentioned purpose, the embodiments of the present application provide the following technical solutions:

[0007] The first aspect of the embodiments of the present application provides an array substrate, which includes an array layer, the array layer being provided with a first conductive line and a first electrode, the first electrode being electrically connected to the array layer through the first conductive line, and the first conductive line covering at least part of the surface of the first electrode connected thereto.

[0008] The array substrate provided by the embodiments of the present application can include an array layer, the array layer being provided with a first conductive line and a first electrode, the first electrode being electrically connected to the array layer through the first conductive line, so that the array layer transmits signals to the first electrode through the first conductive line. The first conductive line covers at least part of the surface of the first electrode connected thereto, the first electrode can be formed on the array layer first, and then the first conductive line is formed. Since the first electrode can be an annealed electrode, that is, the first electrode can be formed by annealing. In this way, the first electrode has strong corrosion resistance to etching solvents, thereby alleviating the excessive etching of the first electrode in the process of etching the first conductive line, so as to improve the display effect of the display panel.

[0009] It can be achieved that the first electrode includes a first transparent electrode layer, a metal electrode layer, and a second transparent electrode layer which are sequentially stacked.

[0010] It can be implemented that the first conductive line is a transparent conductive line.

[0011] It can be implemented that the shape of the first conductive line is a curve.

[0012] In this way, the first conductive line and the first electrode can be implemented in many ways and are suitable for many scenarios.

[0013] In a possible implementation, in a direction from the array layer to the first electrode, a cross-sectional area of the first electrode parallel to the array layer gradually decreases.

[0014] In this way, the side wall area of the first electrode is large, and the connection stability of the first electrode and the structure layer attached to the first electrode is high.

[0015] In a possible implementation, the first conductive line has a conductive part at one end close to the first electrode, the conductive part is located on a side of the first electrode away from the array layer, and a projection of the conductive part on the array layer at least partially overlaps a projection of the first electrode on the array layer.

[0016] In this way, the conductive part can reduce the contact resistance between the first conductive line and the first electrode.

[0017] In a possible implementation, the extension length of the end of the first conductive line covering the first electrode relative to the edge of the first electrode ranges from 0.5 μm to 5 μm.

[0018] In this way, the connection between the first electrode and the first conductive line is stable, and in addition, the surface flatness of the first electrode can be avoided from being excessively affected by the first conductive line.

[0019] The second aspect of the embodiment of the present application provides a preparation method of an array substrate, comprising:

[0020] providing an array layer; forming a first electrode on the array layer; performing annealing treatment on the first electrode; forming a first conductive line on the array layer, the first conductive line covering at least part of the surface of the first electrode after the annealing treatment; and electrically connecting the first electrode and the array layer through the first conductive line.

[0021] The preparation method of the array substrate provided by the embodiment of the present application comprises providing an array layer, first forming a first electrode on the array layer, and then forming a first conductive line. The first electrode can be an annealed electrode, that is, the first electrode can be formed after annealing treatment. In this way, the first electrode has strong corrosion resistance to etching solvents, thereby relieving excessive etching of the first electrode in the process of etching the first conductive line, to improve the display effect of the display panel. The first conductive line covers at least part of the surface of the first electrode after the annealing treatment. The first electrode and the array layer are electrically connected through the first conductive line.

[0022] In a possible implementation, the step of annealing the first electrode includes:

[0023] The first electrode is annealed in an inert gas environment at an annealing temperature of 200-300 DEG C for 40-100 minutes.

[0024] In a possible implementation, the inert gas includes at least one of helium, neon, krypton, argon, xenon, and nitrogen.

[0025] In a possible implementation, the step of forming the first conductive line on the array layer includes: forming a conductive layer on the first electrode and the array layer; and patterning the conductive layer to form the first conductive line, the first conductive line covering at least part of the sidewall surface of the first electrode.

[0026] In a possible implementation, the first conductive line covers part of the surface of the first electrode away from the array layer.

[0027] In this way, the first conductive line can be connected to the first electrode in various ways, and can be applied in various scenarios.

[0028] A third aspect of the embodiments of the present application provides a display panel, including the array substrate in the first aspect.

[0029] The display panel provided by the embodiments of the present application includes an array substrate, which can include an array layer, the array layer being provided with a first conductive line and a first electrode, the first electrode being electrically connected to the array layer through the first conductive line, so that the array layer transmits signals to the first electrode through the first conductive line. The first conductive line covers at least part of the surface of the first electrode to which it is connected, and the first electrode can be formed on the array layer first, and then the first conductive line is formed. Since the first electrode can be an annealed electrode, that is, the first electrode can be formed by annealing. In this way, the first electrode has strong corrosion resistance to etching solvents, thereby relieving excessive etching of the first electrode in the process of etching the first conductive line, so as to improve the display effect of the display panel.

[0030] In a possible implementation, the display panel includes a plurality of light emitting structures arranged on the array layer of the array substrate, and at least two light emitting structures of the same color are connected by the same first conductive line of the array substrate.

[0031] In a possible implementation, the display panel includes a light transmission area, a display area, and a transition area between the light transmission area and the display area, and the array layer in the transition area includes a plurality of pixel driving circuits.

[0032] One pixel driving circuit in the transition area is electrically connected to a plurality of light emitting structures in the light transmission area through the first conductive line.

[0033] The array layer can be provided with a second conductive line in the array layer, the second conductive line being transparent in the transparent region and the transition region, the second conductive line being electrically connected with the first conductive line, and one pixel driving circuit in the transition region being electrically connected with the plurality of light emitting structures in the transparent region through the first conductive line and the second conductive line.

[0034] In this way, the influence of the pixel driving circuit on the light transmittance of the transparent region can be avoided.

[0035] The structure of the present application and other inventive purposes and benefits will be more apparent and easy to understand through the description of the preferred embodiments in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0037] Figure 1 A cross-sectional view of the array layer and the light emitting structure provided by the embodiments of the present application;

[0038] Figure 2 A structure schematic diagram of the first conductive line covering the first electrode provided by the embodiments of the present application;

[0039] Figure 3a A structure schematic diagram of the conductive part provided by the embodiments of the present application;

[0040] Figure 3b Another structure schematic diagram of the conductive part provided by the embodiments of the present application;

[0041] Figure 4 A top view of the first conductive line and the first electrode provided by the embodiments of the present application;

[0042] Figure 5 A top view of the first conductive line provided by the embodiments of the present application;

[0043] Figure 6 A flowchart of the preparation method of the array substrate provided by the embodiments of the present application;

[0044] Figure 7 A structure schematic diagram of the array layer provided by the embodiments of the present application;

[0045] Figure 8 A structure schematic diagram of the first electrode provided by the embodiments of the present application;

[0046] Figure 9A structure schematic diagram for forming the first conductive line is provided for the embodiments of the present application.

[0047] Label explanation:

[0048] 100a: light transmission area; 100b: transition area; 100c: display area;

[0049] 200: array layer; 201: substrate; 211: active layer;

[0050] 212: gate layer; 213: source-drain trace layer; 221: first capacitor electrode;

[0051] 222: second capacitor electrode; 231: first insulating layer; 232: second insulating layer;

[0052] 233: third insulating layer; 234: fourth insulating layer; 240: dielectric layer;

[0053] 241: via hole; 250: second conductive line; 261: first buffer layer;

[0054] 262: second buffer layer; 270: light reflection layer; 300: light emitting structure;

[0055] 310: first conductive line; 320: light emitting layer; 330: first electrode;

[0056] 340: pixel; 350: pixel defining layer; 360: second electrode;

[0057] 370: conductive part. DETAILED DESCRIPTION

[0058] In the related art, a display panel includes an array substrate, and the array substrate includes an array layer and a plurality of anodes located on the array layer. The display panel includes a light transmission area, and the anodes in the light transmission area are provided with conductive pieces on the side facing the array layer. The array layer can be electrically connected to the anodes through the conductive pieces to transmit signals to the anodes.

[0059] Before the anodes are prepared, the conductive pieces are formed on the array layer, and then an anode material layer is formed on the side of the conductive pieces away from the array layer. The anode material layer is subjected to wet etching (for example, etching with an acid solvent) to form a plurality of anodes spaced apart. The conductive pieces are in a sheet structure, the orthographic projection of the anodes on the array layer is located within the orthographic projection of the conductive pieces on the array layer, the size of the conductive pieces is greater than the size of the anodes, and the area of the conductive pieces exposed near the outer periphery of the anodes is relatively large.

[0060] However, in the wet etching process of the anode, the acid etching solvent is formed by polar molecules, and the conductive member is also formed by polar molecules. Due to the fact that the orthogonal projection of the anode on the array layer is located within the orthogonal projection of the conductive member on the array layer, the size of the conductive member is large, the area of the conductive member exposed near the periphery of the anode is large, and the conductive member is easy to adsorb more etching solvent, so that the concentration of the etching solvent near the anode is high, which is easy to cause over-etching of the anode, resulting in that the size of the finally formed anode is too small, the hole transport capability of the light-emitting structure is reduced, the brightness of the light-emitting structure is affected, and thus the display effect of the display panel is affected. In addition, if the anode is over-etched and the size is too small, the edge of the anode cannot be covered by the pixel limiting layer. When the anode is a composite layer of ITO / Ag / ITO (indium tin oxide / silver / indium tin oxide), Ag will overflow in the subsequent high-temperature process, resulting in short circuit between the anode and the cathode, and thus dark spots will appear on the display panel.

[0061] Based on the at least one technical problem described above, the embodiments of the present application provide an array substrate, a preparation method of the array substrate, and a display panel. The array substrate can include an array layer, the array layer is provided with a first conductive line and a first electrode, and the first electrode is electrically connected to the array layer through the first conductive line, so that the array layer transmits signals to the first electrode through the first conductive line. The first conductive line covers part of the surface of the first electrode. The first electrode can be formed on the array layer first, and then the first conductive line is formed. The first electrode can be an annealed electrode, that is, the first electrode can be formed by annealing. In this way, the first electrode has strong corrosion resistance to the etching solvent, thereby relieving the over-etching of the first electrode in the process of etching the first conductive line, and improving the display effect of the display panel.

[0062] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0063] The following will be described in conjunction with the accompanying drawings Figures 1-9 The display panel provided by the embodiments of the present application will be described.

[0064] The display panel provided by the embodiments of the present application can be used in mobile or fixed terminals such as electronic paper, mobile phones, tablet computers, televisions, displays, notebook computers, digital photo frames, super personal computers, navigation devices, etc.

[0065] The display panel can be an organic light-emitting diode (OLED) display panel, a micro light-emitting diode (Micro LED or μLED) display panel, or a liquid crystal display (LCD) display panel.

[0066] Embodiments of the present application are described by taking an OLED display panel as an example.

[0067] The display panel can include an outlight surface and a backlight surface arranged oppositely. The outlight surface is used for displaying a picture, and the backlight surface is an opposite surface of the outlight surface along the thickness direction of the display panel.

[0068] As shown in Figure 1 The display panel can include a light-transmitting area 100a. The backlight surface side of the display panel of the light-transmitting area 100a can be provided with an under-screen functional device. The under-screen functional device can include any one or more of a camera, a fingerprint identifier, an iris identifier, and a distance sensor.

[0069] Embodiments of the present application are described by taking an under-screen functional device as a camera.

[0070] The camera is arranged on the backlight surface side of the display panel of the light-transmitting area 100a. On the one hand, the display panel of the light-transmitting area 100a can normally display a picture to ensure that the display panel has a high screen ratio. On the other hand, the light-transmitting area 100a has good light-transmitting properties to enable light to reach the camera.

[0071] In some examples, the display panel can further include a transition area 100b. The transition area 100b is adjacent to the light-transmitting area 100a, and the transition area 100b can normally display a picture. The display panel of the transition area 100b has a light-transmitting property less than that of the display panel of the light-transmitting area 100a. For example, the transition area 100b can be arranged outside the light-transmitting area 100a.

[0072] In other examples, the display panel can further include a display area 100c. The display area 100c can normally display a picture. For example, the display area 100c can be an area other than the light-transmitting area 100a and the transition area 100b. The light-transmitting area 100a, the transition area 100b, and the display area 100c can be arranged adjacently in sequence, i.e., the transition area 100b can be located between the light-transmitting area 100a and the display area 100c. For example, the display area 100c can be arranged outside the transition area 100b. The display panel of the display area 100c can have a light-transmitting property less than or equal to that of the display panel of the transition area 100b.

[0073] AsFigure 1 As shown, the display panel includes an array substrate, which may include an array layer 200. A light-emitting structure 300 is disposed on the array layer 200. Multiple pixel driving circuits are disposed in the array layer 200. The multiple pixel driving circuits can be arranged in an array, and the pixel driving circuits are electrically connected to the light-emitting structure 300. The pixel driving circuits are used to drive the light-emitting structure 300 to emit light.

[0074] To avoid the pixel driving circuit affecting the light transmittance of the display panel in the light-transmitting area 100a, a pixel driving circuit may not be provided in the display panel of the light-transmitting area 100a (the pixel driving circuit has multiple metal traces, which have poor light transmittance). Instead, pixel driving circuits can be provided in the transition area 100b and the display area 100c, with the pixel driving circuit in the transition area 100b driving the light-emitting structure 300 in the light-transmitting area 100a to emit light. Furthermore, the pixel driving circuit in the transition area 100b can also drive the light-emitting structure 300 in the transition area 100b to emit light.

[0075] like Figure 1 As shown, the array substrate may include an array layer 200, which includes a substrate 201 and a pixel driving circuit located on the substrate 201, between the light-emitting structure 300 and the substrate 201. The substrate 201 can provide support for other structural film layers fabricated on the substrate 201, wherein the substrate 201 may be a single-layer structure or a multi-layer structure.

[0076] Substrate 201 can be a rigid substrate, for example, the material of substrate 201 can be glass. In other examples, substrate 201 can be a flexible substrate, and the material of substrate 201 can include at least one of polyimide (PI), polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyarylate, and polyethersulfone.

[0077] The pixel driving circuit provided in the embodiments of this application will be described in detail below.

[0078] The pixel driving circuit includes a thin film transistor (TFT) and a capacitor structure. The thin film transistor can be a low temperature polysilicon (LTPS) thin film transistor or a metal oxide thin film transistor, etc.

[0079] like Figure 1As shown, the thin film transistor can include, in sequence, an active layer 211, a first insulating layer 231, a gate layer 212, a second insulating layer 232, a third insulating layer 233, a source-drain wiring layer 213, and a fourth insulating layer 234 formed on the substrate 201, wherein the active layer 211 is located on the side of the first insulating layer 231 facing the substrate 201, the gate layer 212 is located on the side of the first insulating layer 231 away from the substrate 201, the second insulating layer 232 is located on the side of the gate layer 212 away from the substrate 201, the third insulating layer 233 is located on the side of the second insulating layer 232 away from the substrate 201, the source-drain wiring layer 213 is located on the side of the third insulating layer 233 away from the substrate 201, and the fourth insulating layer 234 is located on the side of the source-drain wiring layer 213 away from the substrate 201.

[0080] The buffer layer is arranged between the substrate 201 and the active layer 211, and is used to isolate the substrate 201 and the structural film layer above the substrate 201, so as to avoid impurities in the substrate 201 from entering the structural film layer above the substrate 201, thereby affecting the performance of the array substrate. In addition, the influence of high temperature on the substrate 201 in subsequent high-temperature processes can be reduced.

[0081] The buffer layer can include, for example, a first buffer layer 261 and a second buffer layer 262 arranged in layers, and the first buffer layer 261 is located on the side of the second buffer layer 262 close to the substrate 201.

[0082] The capacitor structure can include a first capacitor electrode 221 and a second capacitor electrode 222, and the gate layer 212 and the first capacitor electrode 221 can be of the same layer and the same material, so as to simplify the preparation process. The second insulating layer 232 is located between the first capacitor electrode 221 and the second capacitor electrode 222 to form a capacitor insulating layer of the capacitor structure. The orthographic projection of the first capacitor electrode 221 on the substrate 201 at least partially overlaps the orthographic projection of the second capacitor electrode 222 on the substrate 201.

[0083] The array layer 200 can further include a light-reflecting layer 270, which can be of the same layer and the same material as any one of the first capacitor electrode 221, the second capacitor electrode 222, the gate layer 212, and the source-drain wiring layer 213, so as to simplify the preparation process. The light-reflecting layer 270 is located in the light-transmitting region 100a. For example, as shown in the drawings, Figure 1 The light-reflecting layer 270 is located between the third insulating layer 233 and the fourth insulating layer 234 and is of the same layer and the same material as the source-drain wiring layer 213 in the present application.

[0084] The side of the light-reflecting layer 270 away from the substrate 201 is provided with a second conductive line 250. The second conductive line 250 is formed on the side of the fourth insulating layer 234 away from the substrate 201, and the second conductive line 250 is light-transmitting, so as to avoid the second conductive line 250 affecting the light transmittance of the display panel of the light-transmitting region 100a.

[0085] The second conductive lines 250 can be located in the light-transmitting region 100a, and at least part of the second conductive lines 250 extend into the transition region 100b and are electrically connected to the pixel driving circuit in the transition region 100b, so as to drive the light-emitting structure 300 in the light-transmitting region 100a to emit light through the pixel driving circuit in the transition region 100b.

[0086] The second conductive lines 250 can also be located in the display region 100c. The second conductive lines 250 located in the display region 100c can be electrically connected to the pixel driving circuit and the light-emitting structure 300 in the display region 100c. In addition, part of the second conductive lines 250 located in the transition region 100b can also be electrically connected to the pixel driving circuit and the light-emitting structure 300 in the transition region 100b. Therefore, the second conductive lines 250 in the light-transmitting region 100a, the transition region 100b and the display region 100c can be of the same layer and the same material, and there is no need to separately prepare a trace for electrically connecting the pixel driving circuit and the light-emitting structure 300 in the transition region 100b and the display region 100c, which can simplify the preparation process.

[0087] The side of the second conductive lines 250 away from the substrate 201 is provided with a dielectric layer 240 having a via hole 241. The dielectric layer 240 can have a planarization effect to provide good planar support for subsequent formation of a structure film layer. The material of the dielectric layer 240 can be an inorganic material such as silicon oxide, silicon nitride, etc., or an organic material such as polyethylene (PE), polypropylene, polystyrene, polyethylene terephthalate, polyethylene naphthalate or polyimide, etc. For example, the dielectric layer 240 can be a planarization layer. The via hole 241 can be provided in the dielectric layer 240 to enable the second conductive lines 250 to be electrically connected to the light-emitting structure 300 through the via hole 241. There can be a plurality of via holes 241, which can be located in the light-transmitting region 100a, the transition region 100b and the display region 100c. The via hole 241 penetrates the dielectric layer 240 along the thickness direction of the dielectric layer 240.

[0088] During the formation of via 241, photolithography can be used. The photoresist after exposure is removed during development, exposing the via 241 region of the dielectric layer 240. Etching is then performed on the region containing via 241 to form it on the dielectric layer 240. The transition region 100b and display region 100c contain pixel driving circuits, which include numerous reflective metal traces. By providing a reflective layer 270, the light-transmitting region 100a, transition region 100b, and display region 100c can all reflect the exposed light during the exposure process for forming via 241, ensuring consistent exposure across these regions. Specifically, in the light-transmitting region 100a, the orthogonal projection of via 241 onto the reflective layer 270 is located inside the reflective layer 270, resulting in better light reflection from the reflective layer 270.

[0089] It is understandable that the gate layer 212, the source / drain line layer 213, the first capacitor electrode 221 and the second capacitor electrode 222 can be made of metals or alloys such as silver, copper, aluminum, and molybdenum, or a multilayer structure formed by metals and transparent conductive oxides.

[0090] The dielectric layer 240 can be formed of organic material, which is formed of non-polar molecules. There is no mutual attraction between non-polar molecules and polar etching solvent, so it is not easy to cause over-etching of the first electrode 330.

[0091] The first buffer layer 261, the second buffer layer 262, the first insulating layer 231, the second insulating layer 232, the third insulating layer 233, and the fourth insulating layer 234 can be silicon nitride, silicon oxynitride, silicon oxide, or various novel organic insulating materials, or metal oxides with high dielectric constants such as aluminum oxide, tantalum oxide, etc.

[0092] like Figure 1 As shown, the array substrate may include a first electrode 330 and a first conductive line 310, both of which are located on the array layer 200. The first electrode 330 is electrically connected to the array layer 200 through the first conductive line 310. Multiple first electrodes 330 and first conductive lines 310 may be used. The first electrode 330 and first conductive line 310 may be located on the side of the dielectric layer 240 away from the substrate 201. The material, shape, size, and other parameters of the first electrode 330 in the light-transmitting region 100a, transition region 100b, and display region 100c may be the same or different.

[0093] like Figure 1As shown, the array layer 200 is sequentially stacked with the first electrode 330, the light-emitting layer 320 and the second electrode 360, which can be used to form the light-emitting structure 300. The second electrode 360 is located on the side of the first electrode 330 away from the substrate 201. The light-emitting layer 320 is located between the first electrode 330 and the second electrode 360. In this embodiment, the first electrode 330 can be an anode, and the second electrode 360 can be a cathode. There can be multiple light-emitting structures 300, and the first conductive line 310 is electrically connected to the light-emitting structure 300 by being electrically connected to the first electrode 330.

[0094] Specifically, the first electrode 330 can be a single-layer structure or a multi-layer structure. Taking the multi-layer structure as an example, the first electrode 330 can include a metal electrode layer and transparent electrode layers located on both sides of the metal electrode layer in the thickness direction. The transparent electrode layers can include a first transparent electrode layer and a second transparent electrode layer. The first transparent electrode layer is located on the side of the metal electrode layer away from the substrate 201, and the second transparent electrode layer is located on the side of the metal electrode layer facing the substrate 201. Alternatively, the first electrode 330 includes a metal electrode layer and a first transparent electrode layer located on the side of the metal electrode layer away from the substrate 201.

[0095] For example, the materials of the first transparent electrode layer and the second transparent electrode layer can include indium tin oxide (ITO) or indium zinc oxide (IZO), and the material of the metal electrode layer can include magnesium (Mg), silver (Ag) or aluminum (Al), etc. For example, the first electrode 330 can be a multi-layer structure of an ITO layer / silver layer / ITO layer. The metal electrode layer can reflect light, so that the light generated by the light-emitting structure 300 can be reflected and emitted out of the display panel, thereby improving the brightness of the display panel in the light-transmitting area 100a.

[0096] The embodiments of the present application take the first electrode 330 as an example of an ITO layer / silver layer / ITO layer.

[0097] The first electrode 330 can be an annealed electrode, that is, the structure layer forming the first electrode 330 is subjected to high-temperature annealing treatment, so as to change the arrangement rule of ITO molecules therein, so that the ITO material becomes dense, and then the etching solvent is not easy to corrode the ITO material, so as to improve the corrosion resistance of the first electrode 330 to the etching solvent, thereby reducing the corrosion of the etching solvent used in the subsequent process to the first electrode 330, relieving the excessive etching of the first electrode 330 in the subsequent etching process, and ensuring the display effect of the display panel.

[0098] The ITO layer on the side of the silver layer away from the substrate 201 protects the silver layer, and the ITO layer on the side of the silver layer facing the substrate 201 has a stronger connection force between the silver layer and the dielectric layer 240 than the silver layer, which can increase the connection force between the first electrode 330 and the dielectric layer 240 and reduce the possibility of peeling between the first electrode 330 and the dielectric layer 240. In addition, the silver in the first electrode 330 has a low resistivity and excellent conductivity, which can greatly reduce the overall energy consumption of the display panel.

[0099] As shown in Figure 1 The array substrate can include a plurality of first conductive lines 310, and the first conductive lines 310 are on the array layer 200, and the first electrode 330 is electrically connected to the array layer 200 through the first conductive lines 310. Specifically, a conductive material layer is formed on the side of the first electrode 330 away from the substrate 201, and the conductive material layer is patterned to form the first conductive lines 310. If the first conductive lines 310 are formed first and then the first electrode 330 is formed, the first conductive lines 310 will absorb more etching solvents and cause excessive etching of the first electrode 330. In the embodiment of the present application, the first electrode 330 is formed first and then the first conductive lines 310 are formed, and because the first electrode 330 after annealing has stronger corrosion resistance to etching solvents, the etching solvents used in the process of forming the first conductive lines 310 are less corrosive to the first electrode 330, the excessive etching of the first electrode 330 by the etching process of the first conductive lines 310 is alleviated, and the display effect of the display panel is ensured.

[0100] The first conductive lines 310 are transparent, which can avoid the influence of the first conductive lines 310 on the light transmittance of the display panel in the light transmission area 100a. Optionally, the material of the first conductive lines 310 is ITO.

[0101] The first conductive lines 310 and the second conductive lines 250 are electrically connected through the via holes 241, and the pixel driving circuit in the transition area 100b is electrically connected to the first electrode 330 in the light transmission area 100a through the second conductive lines 250 and the first conductive lines 310.

[0102] In the embodiment, as shown in Figure 2 The first conductive lines 310 cover at least part of the surface of the first electrode 330 to which they are connected. The first electrode 330 can include a first surface and a second surface arranged opposite and spaced apart along the thickness direction, and a side wall surface connecting the first surface and the second surface, the first surface facing the array layer 200, and the second surface arranged opposite the array layer 200. The surface of the first electrode 330 covered by the first conductive lines 310 can include the side wall surface of the first electrode 330; in addition, it can also include the surface of the first electrode 330 on the side away from the array layer 200, i.e. the second surface.

[0103] The first conductive wire 310 is formed on the array layer 200 between two adjacent first electrodes 330 and on the surface of the first electrode 330 away from the array layer 200, and the first conductive wire 310 is connected to the partial side wall surface of the first electrode 330 and the partial surface away from the array layer 200, so that the connection area between the first electrode 330 and the first conductive wire 310 is large, and the connection stability between the first electrode 330 and the first conductive wire 310 is high.

[0104] For example, the extension length of the end of the first conductive wire 310 covering the first electrode 330 relative to the edge of the first electrode 330 can be 0.5-5 μm, and a part of the first conductive wire 310 overlaps the first electrode 330, and the length of the overlapping part can be 0.5-5 μm. In other words, the orthographic projection of the first electrode 330 on the array layer 200 partially overlaps the orthographic projection of the first conductive wire 310 on the array layer 200, and the extension length of the overlapping part can be 0.5-5 μm. The extension length of the end of the first conductive wire 310 covering the first electrode 330 relative to the edge of the first electrode 330 can be 0.5 μm, 1 μm, 1.5 μm, 2 μm, 3 μm, 4 μm, 5 μm, or any length between 0.5-5 μm. In this way, the connection stability between the first conductive wire 310 and the first electrode 330 can be improved, and the influence of the first conductive wire 310 on the surface flatness of the first electrode 330 can be reduced.

[0105] For example, in the direction from the array layer 200 to the first electrode 330, the cross-sectional area of the first electrode 330 parallel to the array layer 200 gradually decreases. The side wall surface of the first electrode 330 is an inclined surface, so that the area of the side surface of the first electrode 330 can be increased, which is beneficial to the stable connection between the first conductive wire 310 attached to the side surface of the first electrode 330 and the first electrode 330, and the two are not prone to have pores.

[0106] In some embodiments, as shown in Figure 3a and Figure 3b The end of the first conductive wire 310 close to the first electrode 330 has a conductive part 370, the conductive part 370 is located on the side of the first electrode 330 away from the array layer 200, and the orthographic projection of the conductive part 370 on the array layer 200 at least partially overlaps the orthographic projection of the first electrode 330 on the array layer 200.

[0107] In some examples, as shown in Figure 3aAs shown, the orthographic projection of the conductive part 370 on the array layer 200 covers part of the orthographic projection of the first electrode 330 on the array layer 200, the contact area between the conductive part 370 and the first electrode 330 is large, and the contact resistance between the first conductive line 310 and the first electrode 330 can be reduced by arranging the conductive part 370. In some other examples, as shown in FIG. 3B, the orthographic projection of the first electrode 330 on the array layer 200 is located within the orthographic projection of the conductive part 370 on the array layer 200, and the first electrode 330 is completely covered by the conductive part 370. The pixel 340 is arranged on the side of the conductive part 370 away from the substrate 201, and the conductive part 370 can be used as a pixel electrode to provide driving current for the pixel 340. The first electrode 330 does not need to be used as a pixel electrode, and the area of the first electrode 330 can be set to be small, so that the influence of the first electrode 330 on the light transmittance of the display panel can be reduced. Figure 3b As shown, the orthographic projection of the conductive part 370 on the array layer 200 covers part of the orthographic projection of the first electrode 330 on the array layer 200, the contact area between the conductive part 370 and the first electrode 330 is large, and the contact resistance between the first conductive line 310 and the first electrode 330 can be reduced by arranging the conductive part 370. In some other examples, as shown in FIG. 3B, the orthographic projection of the first electrode 330 on the array layer 200 is located within the orthographic projection of the conductive part 370 on the array layer 200, and the first electrode 330 is completely covered by the conductive part 370. The pixel 340 is arranged on the side of the conductive part 370 away from the substrate 201, and the conductive part 370 can be used as a pixel electrode to provide driving current for the pixel 340. The first electrode 330 does not need to be used as a pixel electrode, and the area of the first electrode 330 can be set to be small, so that the influence of the first electrode 330 on the light transmittance of the display panel can be reduced.

[0108] In some embodiments of the present application, two first conductive lines 310 electrically connected to the same first electrode 330 can be electrically connected through the conductive part 370, and the two first conductive lines 310 and the conductive part 370 can be an integral part, that is, the first electrode 330 can be electrically connected to one first conductive line 310. When a plurality of first conductive lines 310 are connected through the conductive part 370 and form an integral part, and a plurality of first electrodes 330 are electrically connected through the integral plurality of first conductive lines 310, the plurality of first electrodes 330 can be electrically connected through one first conductive line 310.

[0109] With reference to FIG. 3A and FIG. 3B, Figure 1 The array substrate further includes a pixel defining layer 350, the pixel defining layer 350 is arranged on the side of the first electrode 330 and the first conductive line 310 away from the array layer 200, and the pixel defining layer 350 is located between the first electrode 330 and the second electrode 360. The light-emitting layer 320 includes a plurality of pixels 340 arranged at intervals, the plurality of pixels 340 can be arranged in an array, and the plurality of pixels 340 can be at least two colors, and the plurality of pixels 340 can include but are not limited to red pixels, green pixels, and blue pixels. In some other examples, the plurality of pixels 340 can further include white pixels. Among them, the pixel defining layer 350 is located between two adjacent pixels 340, the pixel defining layer 350 has a pixel opening therein, and the pixel 340 is located in the pixel opening. The pixel defining layer 350 can be arranged around the periphery of the pixel 340. The first electrode 330 is connected to the pixel 340 one by one.

[0110] For example, the pixel defining layer 350 covers the edge position of the first electrode 330 to avoid the edge of the first electrode 330 being exposed outside the pixel defining layer 350, and the pixel defining layer 350 can prevent Ag in the first electrode 330 from overflowing in subsequent high-temperature processes.

[0111] Specifically, the pixel defining layer 350 covers the edge of the surface of the first electrode 330 away from the substrate 201, and the orthogonal projection of the pixel defining layer 350 on the array layer 200 covers the edge of the orthogonal projection of the first electrode 330 on the array layer 200. Figure 4 The inner edge A shows the edge of the pixel opening, Figure 4 The outer edge B shows the edge of the first electrode 330, and the area between AB shows the area where the first electrode 330 is covered by the pixel defining layer 350. The distance between the inner edge A and the outer edge B can range from 1 μm to 4 μm. Specifically, the distance can range from 1.5 μm to 3.5 μm. For example, the distance can be 1 μm, 2 μm, 2.5 μm, 2.7 μm, 3 μm, 3.4 μm, 4 μm, or any value within the range from 1 μm to 4 μm. In this way, it can be avoided that the pixel defining layer 350 covers too little of the first electrode 330, which can result in that the edge of the first electrode 330 is easily exposed outside the pixel defining layer 350, and thus the display panel is prone to dark spots. It can also be avoided that the pixel defining layer 350 covers too much of the first electrode 330, which can result in that the first electrode 330 is too large and has a greater impact on the light transmittance of the light transmission area 100a.

[0112] The following describes the connection mode of the pixel driving circuit located in the transition area 100b and the first electrode 330 located in the light transmission area 100a.

[0113] One pixel driving circuit in the transition area 100b is electrically connected to at least two first electrodes 330 in the light transmission area 100a through the second conductive line 250 and the first conductive line 310. The at least two first electrodes 330 can form a first electrode unit, and the plurality of first electrodes 330 in the first electrode unit are electrically connected through the first conductive line 310, for example, adjacent two first electrodes 330 can be electrically connected through the first conductive line 310. The first electrode unit is electrically connected to the array layer 200 through the first conductive line 310. For example, in the first electrode unit, the plurality of first electrodes 330 can be electrically connected through the same first conductive line 310, and of course, can also be electrically connected through a plurality of first conductive lines 310.

[0114] The colors of the plurality of pixels 340 corresponding to the plurality of first electrodes 330 in the same first electrode unit can be the same.

[0115] The four first electrodes 330 are electrically connected to one pixel driving circuit. Taking an example of four red pixels corresponding to the four first electrodes 330, one pixel driving circuit in the transition area 100b can be electrically connected to the four first electrodes 330 in the light-transmitting area 100a. Adjacent two of the four first electrodes 330 are electrically connected by the first conductive lines 310. The four first electrodes 330 are electrically connected to the pixel driving circuit by the second conductive lines 250 and the first conductive lines 310. Of course, the number of the first electrodes 330 electrically connected to one pixel driving circuit in the transition area 100b can also be two, three or other numbers greater than three, so as to realize that one pixel driving circuit drives multiple pixels 340 to emit light. Thus, one pixel driving circuit in the transition area 100b can be electrically connected to multiple light-emitting structures 300 in the light-transmitting area 100a by the first conductive lines 310 and the second conductive lines 250.

[0116] As shown in FIG. 1, the four first electrodes 330 can be electrically connected by the first conductive lines 310 and form a first electrode unit. The first electrode unit is electrically connected to the array layer 200 by the first conductive lines 310. The colors of the multiple pixels 340 corresponding to the multiple first electrodes 330 in the same first electrode unit can be the same. Alternatively, the four first electrodes 330 can be electrically connected by the first conductive lines 310 to form a ring and be electrically connected to the array layer 200 by the first conductive lines 310. Figure 4

[0117] It should be noted that when light passes through the display panel of the light-transmitting area 100a to reach the camera, the light will diffract when passing through the first conductive lines 310 and the first electrodes 330. Diffraction refers to the phenomenon that light bends and spreads to different degrees when passing through obstacles such as slits, pinholes or discs, thereby deviating from the original straight-line propagation. In the diffraction process, the light interferes with each other to form alternating bright and dark diffraction fringes, which will affect the function of the camera. The diffraction fringes are affected by the size of the obstacle, such as the width of the slit, the size of the pinhole, etc. The positions of the diffraction fringes generated at positions with the same width are consistent, so that the diffraction effect is more obvious.

[0118] As shown in FIG. 1, the four first electrodes 330 can be electrically connected by the first conductive lines 310 and form a first electrode unit. The first electrode unit is electrically connected to the array layer 200 by the first conductive lines 310. The colors of the multiple pixels 340 corresponding to the multiple first electrodes 330 in the same first electrode unit can be the same. Alternatively, the four first electrodes 330 can be electrically connected by the first conductive lines 310 to form a ring and be electrically connected to the array layer 200 by the first conductive lines 310. Figure 4 and Figure 5 ​As shown, the shape of the first conductive lines 310 can be a curve, so that the gap widths at different positions between adjacent first conductive lines 310 are different, the positions of the diffraction fringes generated at different gap widths are different, and the diffraction effects at different positions cancel each other out, so that the diffraction effect can be effectively weakened to ensure normal operation of the camera. For example, the shape of the first conductive lines 310 is a circular arc line, which is relatively regular in shape and relatively easy to manufacture.

[0119] In addition, the shape of the first electrode 330 can be circular, elliptical, or other irregular shapes to ensure that light passing through the first electrode 330 can generate diffraction fringes with different positions and directions at different width positions of the first electrode 330, and the diffraction fringes with different positions and directions cancel each other out to weaken the diffraction effect. Of course, the first electrode 330 can also be a strip or other regular shape. The shape of the conductive part can also be circular, elliptical, or other irregular shapes.

[0120] The embodiment of the present application also provides a preparation method of an array substrate, which can be used to prepare the array substrate in the above embodiments.

[0121] As shown in the figure, the preparation method of the array substrate includes: Figure 6 As shown in the figure, the preparation method of the array substrate includes:

[0122] S100: providing an array layer.

[0123] As shown in the figure, the preparation method of the array substrate includes: Figure 7 As shown in the figure, the preparation method of the array substrate includes:

[0124] S200: forming a first electrode on the array layer.

[0125] A first conductive layer is deposited on the array layer 200, and the first conductive layer is patterned to form a plurality of first electrodes 330 arranged at intervals.

[0126] Specifically, the first electrode 330 can be a single-layer structure or a multi-layer structure. For example, the first electrode 330 can include a metal electrode layer and transparent electrode layers located on both sides of the metal electrode layer along the thickness direction, and the transparent electrode layers can include a first transparent electrode layer and a second transparent electrode layer. The first transparent electrode layer is located on the side of the metal electrode layer away from the substrate, and the second transparent electrode layer is located on the side of the metal electrode layer facing the substrate. Alternatively, the first electrode 330 includes a metal electrode layer and a first transparent electrode layer located on the side of the metal electrode layer away from the substrate.

[0127] For example, the materials of the first and second transparent electrode layers may include indium tin oxide (ITO) or indium zinc oxide (IZO), and the materials of the metal electrode layers may include magnesium (Mg), silver (Ag), or aluminum (Al), etc. For example, the first electrode 330 may be a multilayer structure of ITO layer / silver layer / ITO layer. The metal electrode layer is reflective, so that the light generated by the pixel 340 can be reflected and emitted from the display panel to improve the brightness of the display panel in the light-transmitting area.

[0128] This application uses an example where the first electrode 330 is an ITO layer / silver layer / ITO layer.

[0129] S300: Anneal the first electrode.

[0130] like Figure 8 As shown, the first electrode 330 is annealed to form an annealed electrode. This alters the arrangement of ITO molecules, making the ITO material denser and less susceptible to corrosion by etching solvents. This improves the corrosion resistance of the first electrode 330 to etching solvents, thereby reducing the corrosion of the first electrode 330 by etching solvents used in subsequent processes. This alleviates over-etching of the first electrode 330 by subsequent etching processes and ensures the display effect of the display panel.

[0131] It is possible to anneal the first electrode 330 in an inert gas environment. The inert gas can be any one or more of helium, neon, krypton, argon, xenon, and nitrogen.

[0132] The annealing temperature range can be 200℃-300℃, specifically 220℃-280℃. For example, the annealing temperature can be any value within the range of 200℃, 220℃, 250℃, 270℃, 300℃, or 200℃-300℃. This avoids annealing temperatures that are too low, which would fail to adequately improve the corrosion resistance of the first electrode 330, while also avoiding annealing temperatures that are too high, which could significantly impact other structural film layers.

[0133] The annealing time can range from 40 to 100 minutes. Specifically, the annealing time can range from 50 to 80 minutes. For example, the annealing time can be any value within the range of 40, 60, 80, 100 minutes, or 40-100 minutes. This avoids the situation where the annealing time is too short, which would fail to adequately improve the corrosion resistance of the first electrode 330, while also avoiding the situation where the annealing time is too long, which would have a significant impact on other structural film layers.

[0134] S400: A first conductive line is formed on the array layer, and the first conductive line covers a portion of the surface of the annealed first electrode.

[0135] As shown in FIG. 3, the first conductive line 310 is formed on the array layer 200, and covers part of the surface of the first electrode 330, and the first electrode 330 is electrically connected to the pixel driving circuit in the array layer 200 through the first conductive line 310. Figure 9

[0136] Specifically, a conductive layer is formed on the first electrode 330 and the array layer 200, which can be a second conductive layer, and then the second conductive layer is patterned to form the first conductive line 310. The first conductive line 310 can be located on the array layer 200 between two adjacent first electrodes 330, and the first conductive line 310 can also be located on the surface of at least one first electrode 330. For example, the surface of the first electrode 330 covered by the first conductive line 310 can include the sidewall surface of the first electrode 330; in addition, it can also include the surface of the first electrode 330 away from the array layer 200, i.e. the second surface.

[0137] It should be noted that the numerical values and numerical ranges involved in the embodiments of the present application are approximate values, and there can be a certain range of error due to the influence of the manufacturing process, which can be considered negligible by those skilled in the art.

[0138] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the above embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.​

Claims

1. An array substrate, characterized by, The array substrate comprises an array layer, a first conductive line and a first electrode, the first electrode is electrically connected to the array layer through the first conductive line, the first conductive line covers at least part of the surface of the first electrode, and the first electrode is an annealed electrode. An end of the first conductive line close to the first electrode has a conductive part, the conductive part is located on the side of the first electrode away from the array layer, the orthographic projection of the first electrode on the array layer is located within the orthographic projection of the conductive part on the array layer, and a pixel covers the side of the conductive part away from the array layer. Two first conductive lines electrically connected to the same first electrode are electrically connected through the conductive part.

2. The array substrate of claim 1, wherein, The length of the part of the first conductive line overlapped with the first electrode is 0.5-5 μm.

3. The array substrate of claim 2, wherein, The first electrode comprises a first transparent electrode layer, a metal electrode layer and a second transparent electrode layer arranged in sequence.

4. The array substrate of claim 3, wherein, The first conductive line is a transparent conductive line.

5. The array substrate of claim 4, wherein, The shape of the first conductive line is a curve.

6. The array substrate according to any one of claims 1 to 5, wherein, In the direction from the array layer to the first electrode, the cross-sectional area of the first electrode parallel to the array layer gradually decreases.

7. A method for fabricating an array substrate, characterized in that, The array substrate of any one of claims 1-6 is prepared by the following steps comprising: providing an array layer; forming a first electrode on the array layer; annealing the first electrode; forming a first conductive line on the array layer, the first conductive line covering part of the surface of the annealed first electrode; wherein the first electrode is electrically connected to the array layer through the first conductive line.

8. The method of manufacturing an array substrate according to claim 7, wherein The step of annealing the first electrode comprises: annealing the first electrode in an inert gas environment at an annealing temperature of 200-300 ℃ for 40-100 min.

9. The method of manufacturing an array substrate according to claim 8, wherein The inert gas comprises at least one of helium, neon, krypton, argon, xenon and nitrogen.

10. The method of manufacturing an array substrate according to claim 7, wherein The step of forming the first conductive line on the array layer comprises: forming a conductive layer on the first electrode and the array layer; patterning the conductive layer to form the first conductive line, the first conductive line covering part of the sidewall surface of the first electrode.

11. The method of manufacturing an array substrate according to claim 7, wherein The first conductive line covers part of the surface of the first electrode away from the array layer.

12. A display panel, characterized by, The array substrate of any one of claims 1-6.

13. The display panel of claim 12, wherein, The display panel comprises a light-transmitting area, a display area and a transition area between the light-transmitting area and the display area, the array layer in the transition area comprises a plurality of pixel driving circuits; 14. The display panel of claim 13, wherein, one of the pixel driving circuits in the transition area is electrically connected to a plurality of the light-emitting structures in the light-transmitting area through the first conductive line. ​ 15. The display panel of claim 14, wherein, The array layer is provided with a second conductive line in the light-transmitting region and the transition region, the second conductive line is electrically connected with the first conductive line, and one of the pixel drive circuits in the transition region is electrically connected with the plurality of light-emitting structures in the light-transmitting region through the first conductive line and the second conductive line.

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