Transistor, gate driving circuit and display device

Abstract

The application provides a transistor, a gate driving circuit and a display device. The transistor comprises a first insulating layer and at least one switching region, a first functional layer and a second functional layer are arranged on two sides of the first insulating layer along an x direction; a first source is arranged in a source region of a first semiconductor layer, and a first drain is arranged in a drain region of the first semiconductor layer; a second source is arranged in a source region of a second semiconductor layer, the second source is connected with the first source through a first connecting line penetrating the first insulating layer, a second drain is arranged in a drain region of the second semiconductor layer, and the second drain is connected with the first drain through a second connecting line penetrating the first insulating layer; a gate structure is arranged to be insulated from the first semiconductor layer and the second semiconductor layer respectively, and is arranged to be opposite to channel regions of the first semiconductor layer and the second semiconductor layer. The technical scheme of the application can reduce the area occupied by the driving circuit, narrow the frame of the display panel, and improve the size of the display picture.

Description

Technical Field

[0001] This application relates to the field of display driving technology, and in particular to a transistor, a gate driving circuit, and a display device. Background Technology

[0002] In the display field, display products typically incorporate driving circuits, which control the display by turning TFT (Thin Film Transistor) switches on and off. Therefore, a large number of TFT switches are embedded in the display panel. Due to the large number of TFT switches, they occupy a significant area, widening the bezel of the display panel and reducing the area available for image display.

[0003] The information disclosed in the background section is intended only to enhance understanding of the background of this application and may therefore include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] One object of this application is to provide a transistor, a gate driving circuit, and a display device that can reduce the area occupied by the driving circuit, narrow the bezel of the display panel, and increase the size of the displayed image.

[0005] According to one aspect of this application, this application provides a transistor, the transistor including a first insulating layer, the transistor further including at least one switching region, the switching region including a gate structure, a first functional layer and a second functional layer, the thickness direction of the first insulating layer being the x-direction, and the first functional layer and the second functional layer being disposed on both sides of the first insulating layer along the x-direction;

[0006] The first functional layer includes a first semiconductor layer, a first source, and a first drain. The first source is disposed in the source region of the first semiconductor layer, and the first drain is disposed in the drain region of the first semiconductor layer.

[0007] The second functional layer includes a second semiconductor layer, a second source, and a second drain. The second source is disposed in the source region of the second semiconductor layer and is connected to the first source through a first connecting line passing through the first insulating layer. The second drain is disposed in the drain region of the second semiconductor layer and is connected to the first drain through a second connecting line passing through the first insulating layer.

[0008] In one aspect, the gate structure is disposed insulated from the first semiconductor layer and the second semiconductor layer respectively, and is disposed opposite to the channel regions of the first semiconductor layer and the second semiconductor layer.

[0009] A direction perpendicular to the x direction is defined as a y direction, and a plurality of switch regions are arranged along the y direction.

[0010] In one aspect, a direction perpendicular to both the x direction and the y direction is defined as a z direction, and a plurality of switch regions are arranged along the z direction. A plurality of gate structures are arranged along the z direction, and the switch regions arranged along the z direction are correspondingly arranged with the gate structures arranged independently.

[0011] In one aspect, the transistor further comprises two gate layers, one of the gate layers is arranged on a side of the first semiconductor layer away from the first insulating layer, the first semiconductor layer is arranged on a side of the first source and the first drain away from the first insulating layer, and the other gate layer is arranged on a side of the second semiconductor layer away from the first insulating layer, the second semiconductor layer is arranged on a side of the second source and the second drain away from the first insulating layer.

[0012] In one aspect, the transistor further comprises a metal shielding layer, the metal shielding layer is arranged in the first insulating layer and covers a position of the gate layer in the first insulating layer.

[0013] In one aspect, a plurality of switch regions are arranged, and the metal shielding layer comprises a plurality of shielding segments, each of the switch regions is correspondingly arranged with one of the shielding segments.

[0014] In one aspect, the gate structure further comprises a single-layer gate layer, the gate layer is arranged between the first semiconductor layer and the second semiconductor layer, the gate layer is arranged in the first insulating layer, and a distance between the gate layer and the first semiconductor layer and the second semiconductor layer is equal.

[0015] In one aspect, the first semiconductor layer and the second semiconductor layer are made of indium gallium zinc oxide.

[0016] To solve the above problems, according to one aspect of the present application, the present application further provides a driving circuit, the gate driving circuit comprises a plurality of cascaded shift registers, and the shift register comprises the transistor as described above.

[0017] To solve the above problems, according to one aspect of the present application, the present application further provides a display device, the display device comprises a display panel and a gate driving circuit as described above, the display panel comprises a display area and a non-display area, and the gate driving circuit is arranged in the non-display area.

[0018] In the technical solution of the present application, the first functional layer and the second functional layer are arranged on the upper and lower surfaces of the first insulating layer respectively, so that the first functional layer and the second functional layer are overlapped, the thickness space of the display device is fully utilized, and the two lower layers are arranged under the original arrangement of the transistor. In the case of arranging the same number of transistors, the area of the transistor is directly reduced to half of the original area. In this way, the area occupied by the gate drive circuit is reduced, the frame of the display panel is narrowed, the size of the display area is increased, and the size of the display picture is increased.

[0019] It should be understood that the above general description and the following detailed description are only exemplary and cannot limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0020] The above and other objects, features and advantages of the present application will become more apparent from the following detailed description of example embodiments thereof by referring to the accompanying drawings.

[0021] Figure 1 is a structure diagram of a single-layer gate layer in a transistor in the first embodiment in the present application.

[0022] Figure 2 is a structure diagram of a double-layer gate layer in a transistor in the first embodiment in the present application.

[0023] Figure 3 is a structure diagram of the distribution of the switching area of the transistor in the y direction in the first embodiment in the present application.

[0024] Figure 4 is a structure diagram of the distribution of the switching area of the transistor in the z direction in the first embodiment in the present application.

[0025] Figure 5 is a structure diagram of the width-length ratio of the transistor in the first embodiment in the present application. Figure 4

[0026] Figure 6 is a structure diagram of the overlap of a plurality of extension lines in the x direction in the first embodiment in the present application.

[0027] Figure 7 is a connection diagram of the gate drive circuit in the second embodiment in the present application.

[0028] Figure 8 is a structure diagram of the display device in the third embodiment in the present application.

[0029] The reference signs are explained as follows:

[0030] ​1, switch region; 20, first functional layer; 30, second functional layer; 40, first connection line; 50, second connection line; 60, gate layer; 70, metal shielding layer; 90, display panel;

[0031] 110, first insulating layer; 120, second insulating layer; 130, third insulating layer; 210, first semiconductor layer; 220, first source electrode; 230, first drain electrode; 310, second semiconductor layer; 320, second source electrode; 330, second drain electrode; 610, main control line; 620, complementary control line; 621, first complementary line; 622, second complementary line; 623, third complementary line; 710, shielding segment; 810, first extension line; 820, second extension line; 830, third extension line; 840, fourth extension line; 910, display region; 920, non-display region; T1, first transistor switch; T2, second transistor switch; T3, third transistor switch; T4, fourth transistor switch; C, capacitor. DETAILED DESCRIPTION

[0032] While the application can be susceptible to various modifications and alternative forms, only some specific embodiments have been shown by way of example in the drawings and will be described in detail herein. It should be understood that the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the application. The following detailed description is therefore not restrictive, but given on the basis of practical representative embodiments to convey the substance thereof to the skilled in the art.

[0033] As such, a feature recited in this description as being indicative of an embodiment of the application will not necessarily be indicative of the entire inventive concept of the application, but can instead be indicative of a single feature of an embodiment of the application. Furthermore, it is to be noted that the description describes numerous features. Although certain features can be combined together to show possible system designs, these features can also be used in other combinations not explicitly described. As such, the described combinations are not intended to be limiting, unless otherwise specified.

[0034] In the embodiments shown in the drawings, the indications of direction, such as up, down, left, right, front, and back, are used to explain the structure and movement of the various elements of the application and are not absolute but relative. These indications are appropriate when the elements are in the position shown in the drawings. If the position of the elements is changed, the indications of direction are changed accordingly.

[0035] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided to make the description of this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art. The drawings are merely illustrative of this application and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0036] The preferred embodiments of this application will be further described in detail below with reference to the accompanying drawings.

[0037] Example 1

[0038] See Figure 1 and Figure 2 As shown, this application provides a transistor, in this embodiment the transistor refers to a TFT switching transistor. TFT transistors have the advantages of high responsivity, high brightness, and high contrast. In this embodiment, the first functional layer 20 and the second functional layer 30 are stacked in the thickness direction of the display panel, thereby reducing the amount of material laid on the same plane and saving area.

[0039] The transistor in this embodiment includes a first insulating layer 110 and at least one switching region 1. The switching region 1 includes a gate structure, a first functional layer 20, and a second functional layer 30. The thickness direction of the first insulating layer 110 is the x-direction. The first functional layer 20 and the second functional layer 30 are disposed on opposite sides of the first insulating layer 110 in the x-direction. The first insulating layer 110 can be understood as a substrate, which is the basis for the first functional layer 20 and the second functional layer 30. The first functional layer 20 and the second functional layer 30 are attached to the first insulating layer 110. The first insulating layer 110 can reduce the influence of external factors on the current of the first functional layer 20 or the second functional layer 30, and can also reduce the diffusion of metal ions in the first functional layer 20 and the second functional layer 30. Generally, the first insulating layer 110 is made of silicon dioxide.

[0040] The first functional layer 20 includes a first semiconductor layer 210, a first source 220, and a first drain 230. The first source 220 is disposed in the source region of the first semiconductor layer 210, and the first drain 230 is disposed in the drain region of the first semiconductor layer 210. The first semiconductor layer 210 can be turned on or off at the corresponding gate line. When the first semiconductor layer 210 is turned on, the first source 220 and the first drain 230 are turned on; when the first semiconductor layer 210 is turned off, the first source 220 and the first drain 230 are turned off.

[0041] The second functional layer 30 comprises a second semiconductor layer 310, a second source electrode 320 and a second drain electrode 330, the second source electrode 320 is arranged at a source region of the second semiconductor layer 310, and the second drain electrode 330 is arranged at a drain region of the second semiconductor layer 310; the second semiconductor layer 310 can be turned on or turned off under the action of the corresponding gate. When the second semiconductor layer 310 is turned on, the second source electrode 320 and the second drain electrode 330 are turned on, and when the second semiconductor layer 310 is turned off, the second source electrode 320 and the first drain electrode 230 are turned off. Turning on means that there is an electric signal passing through, and turning off means that there is no electric signal passing through.

[0042] The switch region 1 further comprises a first connecting line 40 and a second connecting line 50, the second source electrode 320 is connected with the first source electrode 210 through the first connecting line 40 penetrating the first insulating layer 110, and the second drain electrode 330 is connected with the first drain electrode 230 through the second connecting line 50 penetrating the first insulating layer 110.

[0043] Specifically, the first connecting line 40 and the second connecting line 50 penetrate the first insulating layer 110, one end of the first connecting line 40 is connected with the first source electrode 220, and the other end is connected with the second source electrode 320, one end of the second connecting line 50 is connected with the first drain electrode 230, and the other end is connected with the second drain electrode 330. A through hole can be arranged on the first insulating layer 110, one through hole corresponds to the first source electrode 220 and the second source electrode 320, and the other through hole corresponds to the first drain electrode 230 and the second drain electrode 330, the first connecting line 40 is arranged in the through hole corresponding to the first source electrode 220 and the second source electrode 320, and the second connecting line 50 is arranged in the through hole corresponding to the first drain electrode 230 and the second drain electrode 330.

[0044] Among them, the first source electrode 220 and the second source electrode 320 overlap in the orthographic projection on the first insulating layer 110, and the first drain electrode 230 and the second drain electrode 330 overlap in the orthographic projection on the first insulating layer 110, and the center axes of the corresponding through holes are perpendicular to the first insulating layer 110.

[0045] The gate structure is arranged to be mutually insulated from the first semiconductor layer 210 and the second semiconductor layer 310, and is arranged opposite to the channel regions of the first semiconductor layer 210 and the second semiconductor layer 310. By covering the corresponding channel regions through the gate structure, a magnetic field is formed, thereby realizing the turn-on or turn-off of the switch region 1.

[0046] In the technical solution of the embodiment, the first functional layer 20 and the second functional layer 30 are respectively arranged on the upper and lower surfaces of the first insulating layer 110, so that the first functional layer 20 and the second functional layer 30 are overlapped and stacked, and the two lower layers can be laid under the original arrangement of the one lower layer of transistors. In the case of laying the same number of transistors, the area is directly reduced to half of the original area. In this way, the area occupied by the gate drive circuit is reduced, the frame of the display panel is narrowed, the size of the display area is increased, and the size of the display picture is increased.

[0047] Referring to Figure 3 As shown in the figure, the direction perpendicular to the x direction is defined as the y direction, and the switch area 1 is provided with a plurality of switch areas 1 distributed along the y direction. The same gate structure is provided corresponding to the plurality of switch areas 1 distributed along the y direction. It can be seen that the gate structure also extends in the y direction, thereby overlapping with more switch areas 1. In this way, the same gate structure controls the conduction or disconnection of the plurality of switch areas 1. The structure is simplified, and the control switching efficiency is improved.

[0048] Referring to Figure 4 As shown in the figure, the direction perpendicular to the x direction and the y direction is defined as the z direction, and the switch area 1 is provided with a plurality of switch areas 1 distributed along the z direction. The gate structure is provided with a plurality of gate structures distributed along the z direction, and the switch area 1 distributed along the z direction is provided with an independently controlled gate structure.

[0049] In the display field, display products usually face a working environment with a large temperature change range. Especially the transistor, when the working environment temperature changes, the voltage threshold of the transistor often drifts. The voltage threshold drift is easy to cause display abnormalities. In order to make the transistor well adapt to different temperatures and flexibly adjust the electrical characteristics of the transistor, the gate structure is provided with a plurality of gate layers 60, one gate layer 60 corresponds to one switch area 1, and one gate layer 60 corresponds to another switch area 1.

[0050] At different temperatures, the on-off number of the gate layer 60 is changed to change the width-length ratio of the transistor. Generally, the lower the temperature, the more the on-off number of the gate layer 60. The gate drive circuit improves the low-temperature driving ability in a low-temperature environment. In a high-temperature and high-humidity environment, the on-off number of the gate layer 60 is reduced, and then the width-length ratio of the transistor is reduced to reduce the high-temperature heating of the TFT switch and improve the display abnormalities caused by the threshold voltage drift of the TFT switch.

[0051] Specifically, referring to Figure 5 As shown in the figure, the gate layer 60 is provided with four control lines, which are a main control line 610 and three compensation control lines 620. The three compensation control lines 620 are a first compensation line 621, a second compensation line 622, and a third compensation line 623.

[0052] detecting an ambient temperature of the transistor, generating a compensation signal according to the ambient temperature; when the ambient temperature is a first preset temperature, outputting the first compensation signal to the first compensation line 621, and the source line and the drain line corresponding to the first compensation line 621 are turned on; only when the main control line 610 is turned on, the width-length ratio of the transistor is W0 / L. After the first compensation line 621 is turned on, the width-length ratio of the transistor is W0 / L+W1 / L.

[0053] When the ambient temperature is a second preset temperature, the first compensation signal is output to the first compensation line 621, and the second compensation signal is output to the second compensation line 622, and the source line and the drain line corresponding to the first compensation line 621 and the source line and the drain line corresponding to the second compensation line 622 are turned on; the width-length ratio of the transistor is increased. At this time, the width-length ratio of the transistor is W0 / L+W1 / L+W2 / L.

[0054] When the ambient temperature is a third preset temperature, the first compensation signal is output to the first compensation line 621, the second compensation signal is output to the second compensation line 622, and the third compensation signal is output to the third compensation line 623, and the source line and the drain line corresponding to the first compensation line 621, the source line and the drain line corresponding to the second compensation line 622, and the source line and the drain line corresponding to the third compensation line 623 are turned on, and at this time, the width-length ratio of the transistor is W0 / L+W1 / L+W2 / L+W3 / L. Among them, the first preset temperature is greater than the second preset temperature, and the second preset temperature is greater than the third preset temperature. For example, the first preset temperature is greater than 40℃, the second preset temperature is between 0℃-40℃, and the third preset temperature is less than 0℃. Thus, the width-length ratio of the transistor is continuously increased to improve the low-temperature characteristics.

[0055] In order to more flexibly control the switching of the transistor, the transistor further includes two gate layers 60, one of which is arranged on the side of the first semiconductor layer 210 away from the first insulating layer 110, the first semiconductor layer 210 is arranged on the side of the first source 220 and the first drain 230 away from the first insulating layer 110, and the other gate layer 60 is arranged on the side of the second semiconductor layer 310 away from the first insulating layer 110, and the second semiconductor layer 310 is arranged on the side of the second source 320 and the second drain 330 away from the first insulating layer 110. In addition, a second insulating layer 120 is arranged between the gate layer 60 and the first semiconductor layer 210. A third insulating layer 130 is arranged between the other gate layer 60 and the second semiconductor layer 310. The materials of the first insulating layer 110, the second insulating layer 120 and the third insulating layer 130 can be the same.

[0056] Thus, the upper gate layer 60 can control the first functional layer 20. When the upper gate layer 60 is powered, a magnetic field is formed to affect the first semiconductor layer 210, and then the first source 220 and the first drain 230 are turned on. Similarly, the lower gate layer 60 can control the second functional layer 30. When the lower gate layer 60 is powered, a magnetic field is formed to affect the second semiconductor layer 310, and then the second source 320 and the second drain 330 are turned on.

[0057] The upper and lower gate layers 60 can be powered at the same time or only one of them can be powered. Thus, the first functional layer 20 and the second functional layer 30 can function independently, and the control is more flexible.

[0058] The gate layer 60 is a metal layer that generates a magnetic field when powered. The magnetic field has a certain effective range. If the upper gate layer 60 is powered and the lower gate layer 60 is not powered, the magnetic field of the upper gate layer 60 can affect the second functional layer 30. Thus, the second source 320 and the second drain 330 can be turned on, which is unnecessary. To reduce the mutual interference between the upper and lower gate layers 60 and avoid generating noise signals, the transistor further includes a metal shielding layer 70 located in the first insulating layer 110 and covering the orthographic projection position of the gate layer 60 in the first insulating layer 110. The magnetic field is further avoided, and the orthographic projection position of the gate layer 60 in the first insulating layer is covered. The metal shielding layer 70 is located in the first insulating layer 110, and the distance between the metal shielding layer 70 and the first functional layer 20 and the second functional layer 30 is usually equal. The material of the metal shielding layer 70 can be nickel, gold, silver, aluminum, or copper.

[0059] Further, the switch area 1 is provided with a plurality of metal shielding layers, and each switch area 1 is provided with a shielding segment. Each switch area 1 is provided with a gate line. To reduce the mutual interference between each group of gate lines, the metal shielding layer 70 includes a plurality of shielding segments 710, and the first connection line 40 and the second connection line 50 are provided with a plurality of shielding segments 710. The first connection line 40 and the second connection line 50 form a switch area 1, and each first connection line 40 and second connection line 50 is provided with a shielding segment 710.

[0060] To better improve the shielding effect, the coverage area of the shielding segment 710 and the coverage area of each gate line are the same in size and position, or the coverage area of the shielding layer can be larger than the coverage area of the gate layer 60.

[0061] In order to improve the control efficiency, the gate structure further comprises a single-layer gate layer 60, which is arranged between the first semiconductor layer 210 and the second semiconductor layer 310, and is arranged in the first insulating layer 110, and the distance between the single-layer gate layer 60 and the first semiconductor layer 210 and the second semiconductor layer 310 is equal. By energizing the single-layer gate layer 60, the first functional layer 20 and the second functional layer 30 can be simultaneously acted on by the magnetic field. That is, under the action of the single-layer gate layer 60, the first semiconductor layer 210, the first source electrode 220 and the first drain electrode 230 are turned on, and under the action of the single-layer gate layer 60, the second semiconductor layer 310, the second source electrode 320 and the second drain electrode 330 are turned on.

[0062] In this way, not only can the control of the upper and lower TFT switches be realized by one gate layer 60, but also the space of the first insulating layer 110 can be fully utilized, so that the thickness of the transistor is reduced.

[0063] Referring to Figure 6 As shown in the figure, the transistor further comprises a first extension line 810 and a second extension line 820, the first extension line 810 and the first source electrode 220 are arranged in the same layer, the second extension line 820 and the second source electrode 320 are arranged in the same layer, the first extension line 810 is connected to the first source electrode 220, the second extension line 820 is connected to the second source electrode 320, and the extension paths of the first extension line 810 and the second extension line 820 are the same in the orthographic projection of the first insulating layer 110. Generally, the source electrode is the signal input end, and the source electrode needs to be connected to some voltage source and the like. Through the connection of the first extension line 810 and the second extension line 820, the signal transmission of the voltage source can be facilitated. Moreover, by arranging the extension paths of the first extension line 810 and the second extension line 820 to be the same in the orthographic projection of the first insulating layer 110, the thickness of the transistor can be fully utilized, and the extension lines in the same plane can be reduced, which is further beneficial to the realization of narrow frame. Further, the transistor further comprises a third extension line 830 and a fourth extension line 840, the first extension line 810 and the second extension line 820 and the third extension line 830 and the fourth extension line 840 are arranged in the thickness direction of the display panel in turn.

[0064] In order to improve the response speed, the material of the first semiconductor layer 210 and the second semiconductor layer 310 is indium gallium zinc oxide (IGZO), which is an amorphous oxide containing indium, gallium and zinc, and the carrier mobility is 20-30 times that of amorphous silicon, which can greatly improve the charging and discharging rate of the TFT to the pixel electrode, improve the response speed of the pixel, realize faster refresh rate, and faster response also greatly improves the line scanning speed of the pixel.

[0065] Embodiment two

[0066] Referring to Figure 7As shown, the application also provides a gate drive circuit, which includes a plurality of cascaded shift registers, and the shift register includes a transistor.

[0067] In one gate drive circuit, the width-length ratio of the transistors of the first transistor switch T1 and the third transistor switch T3 is large, such as greater than 100. The first transistor switch T1 and the third transistor switch T3 are easily affected by temperature to cause threshold voltage shift. Through the embodiment, the first transistor switch T1 and the third transistor switch T3 can be replaced by the transistor with the adjustable width-length ratio mentioned above.

[0068] The signal input end input inputs a high level, the first transistor switch T1 is opened, the capacitor C is charged, and the third transistor switch T3 is turned on under the action of the high level. The clock signal CK is loaded on the capacitor C, and the control signal is output through the output end Gn. After the control signal is output, the reset end Reset outputs a high level, the second transistor switch T2 and the fourth transistor switch T4 are opened, and the capacitor C is reset to the reset voltage Vgl.

[0069] The transistor includes a first insulating layer 110 and at least one switching area 1, the switching area 1 includes a gate structure, a first functional layer 20 and a second functional layer 30, and the thickness direction of the first insulating layer is the x direction. The first functional layer 20 and the second functional layer 30 are arranged on both sides of the x direction of the first insulating layer 110; the first insulating layer 110 can be understood as a substrate, which is the basis for arranging the first functional layer 20 and the second functional layer 30. The first functional layer 20 and the second functional layer 30 are attached to the first insulating layer 110. The first insulating layer 110 can reduce the influence of external factors on the current of the first functional layer 20 or the second functional layer 30, and can also reduce the diffusion of metal ions of the first functional layer 20 and the second functional layer 30. Generally, the first insulating layer 110 is made of silicon dioxide.

[0070] The first functional layer 20 includes a first semiconductor layer 210, a first source 220 and a first drain 230, the first source 220 is arranged in the source region of the first semiconductor layer 210, and the first drain 230 is arranged in the drain region of the first semiconductor layer 210; the first semiconductor layer 210 can realize conduction or cutoff under the action of the corresponding gate. When the first semiconductor layer 210 is turned on, the first source 220 and the first drain 230 are turned on, and when the first semiconductor layer 210 is cut off, the first source 220 and the first drain 230 are disconnected.

[0071] The second functional layer 30 comprises a second semiconductor layer 310, a second source electrode 320 and a second drain electrode 330, the second source electrode 320 is arranged at a source region of the second semiconductor layer 310, and the second drain electrode 330 is arranged at a drain region of the second semiconductor layer 310; the second semiconductor layer 310 can be turned on or turned off under the action of the corresponding gate electrode. When the second semiconductor layer 310 is turned on, the second source electrode 320 and the second drain electrode 330 are turned on, and when the second semiconductor layer 310 is turned off, the second source electrode 320 and the first drain electrode 230 are disconnected.

[0072] The switch region 1 further comprises a first connecting line 40 and a second connecting line 50, the second source electrode is connected with the first source electrode through the first connecting line penetrating the first insulating layer, the second drain electrode is arranged at a drain region of the second semiconductor layer, and the second drain electrode is connected with the first drain electrode through the second connecting line penetrating the first insulating layer.

[0073] Specifically, the first connecting line 40 and the second connecting line 50 penetrate the first insulating layer 110, one end of the first connecting line 40 is connected with the first source electrode 220, and the other end is connected with the second source electrode 320, one end of the second connecting line 50 is connected with the first drain electrode 230, and the other end is connected with the second drain electrode 330. A through hole can be arranged on the first insulating layer 110, one through hole corresponds to the first source electrode 220 and the second source electrode 320, and the other through hole corresponds to the first drain electrode 230 and the second drain electrode 330, the first connecting line 40 is arranged in the through hole corresponding to the first source electrode 220 and the second source electrode 320, and the second connecting line 50 is arranged in the through hole corresponding to the first drain electrode 230 and the second drain electrode 330.

[0074] The first source electrode 220 and the second source electrode 320 are overlapped in the orthographic projection on the first insulating layer 110, the first drain electrode 230 and the second drain electrode 330 are overlapped in the orthographic projection on the first insulating layer 110, and the center axes of the corresponding through holes are perpendicular to the first insulating layer 110.

[0075] The gate electrode structure is arranged to be mutually insulated from the first semiconductor layer 210 and the second semiconductor layer 310, and is arranged opposite to the channel regions of the first semiconductor layer 210 and the second semiconductor layer 310. Through the coverage of the gate electrode structure on the corresponding channel region, a magnetic field is formed, and then the switch region 1 is turned on or turned off.

[0076] In the technical scheme of the embodiment, through the up-down stacking of multiple transistors, the area occupied by the gate driving circuit is further reduced, and the area of the non-display region 920 occupied by the gate driving circuit is reduced. In addition, the controller can realize the individual control of each transistor.

[0077] The embodiments of the gate driving circuit of the present application include all the technical schemes of all the embodiments of the transistors, and the technical effects achieved are also completely the same, which will not be repeated here.

[0078] Embodiment Three

[0079] Referring to Figure 8 As shown in the figure, the application also provides a display device. The display device comprises a display panel 90, the display panel 90 comprises a display area 910 and a non-display area 920, and a gate drive circuit is arranged in the non-display area 920. The display area 910 is used for light to pass through the display screen, and the non-display area 920 is usually arranged around the display area 910. Arranging the gate drive circuit in the non-display area 920 can avoid blocking the light of the display area 910.

[0080] The transistor comprises a first insulating layer 110 and at least one switching area 1, the switching area 1 comprises a gate structure, a first functional layer 20 and a second functional layer 30, and the thickness direction of the first insulating layer is the x direction. The first functional layer 20 and the second functional layer 30 are arranged on both sides of the x direction of the first insulating layer 110; the first insulating layer 110 can be understood as a substrate, and is the basis for arranging the first functional layer 20 and the second functional layer 30. The first functional layer 20 and the second functional layer 30 are attached to the first insulating layer 110. The first insulating layer 110 can reduce the influence of the external environment on the current of the first functional layer 20 or the second functional layer 30, and can also reduce the diffusion of metal ions of the first functional layer 20 and the second functional layer 30. Generally, the first insulating layer 110 is made of silicon dioxide.

[0081] The first functional layer 20 comprises a first semiconductor layer 210, a first source 220 and a first drain 230, the first source 220 is arranged in the source area of the first semiconductor layer 210, and the first drain 230 is arranged in the drain area of the first semiconductor layer 210; the first semiconductor layer 210 can realize conduction or cutoff under the action line corresponding to the gate. When the first semiconductor layer 210 is turned on, the first source 220 and the first drain 230 are turned on, and when the first semiconductor layer 210 is cut off, the first source 220 and the first drain 230 are disconnected.

[0082] The second functional layer 30 comprises a second semiconductor layer 310, a second source 320 and a second drain 330, the second source 320 is arranged in the source area of the second semiconductor layer 310, and the second drain 330 is arranged in the drain area of the second semiconductor layer 310; the second semiconductor layer 310 can realize conduction or cutoff under the action line corresponding to the gate. When the second semiconductor layer 310 is turned on, the second source 320 and the second drain 330 are turned on, and when the second semiconductor layer 310 is cut off, the second source 320 and the first drain 230 are disconnected.

[0083] The switching area 1 further comprises a first connecting line 40 and a second connecting line 50, the second source is connected with the first source through the first connecting line penetrating the first insulating layer, the second drain is arranged in the drain area of the second semiconductor layer, and the second drain is connected with the first drain through the second connecting line penetrating the first insulating layer.

[0084] Specifically, the first connecting line 40 and the second connecting line 50 are arranged through the first insulating layer 110, one end of the first connecting line 40 is connected to the first source electrode 220 and the other end is connected to the second source electrode 320, one end of the second connecting line 50 is connected to the first drain electrode 230 and the other end is connected to the second drain electrode 330. A via hole can be arranged on the first insulating layer 110, one via hole corresponds to the first source electrode 220 and the second source electrode 320, and the other via hole corresponds to the first drain electrode 230 and the second drain electrode 330, the first connecting line 40 is arranged in the via hole corresponding to the first source electrode 220 and the second source electrode 320, and the second connecting line 50 is arranged in the via hole corresponding to the first drain electrode 230 and the second drain electrode 330.

[0085] The first source electrode 220 and the second source electrode 320 are overlapped in the orthographic projection on the first insulating layer 110, and the first drain electrode 230 and the second drain electrode 330 are overlapped in the orthographic projection on the first insulating layer 110, and the center axis of the corresponding via hole is perpendicular to the first insulating layer 110.

[0086] The gate structure is arranged to be insulated from the first semiconductor layer and the second semiconductor layer, and is arranged opposite to the channel region of the first semiconductor layer and the second semiconductor layer. By covering the corresponding channel region through the gate structure, a magnetic field is formed, and the conduction or disconnection of the switching region 1 is realized.

[0087] In the technical solution of the embodiment, the non-display areas 920 of the display panel 90 can be stacked up and down, the general frame is arranged in the non-display area 920, and the area of the non-display area 920 occupied by the gate drive circuit is reduced, so that the frame is narrowed and the size of the display area 910 is increased.

[0088] The embodiments of the display device of the application include all the technical solutions of all the embodiments of the transistor, and the technical effects achieved are also completely the same, and will not be described here.

[0089] Although the application has been described with reference to several exemplary embodiments, it will be understood that the terms used are intended to be illustrative and not limiting. Since the application can be embodied in many different forms without departing from the spirit or essential characteristics thereof, it will be understood that the above-described embodiments are not limited to any of the details of the foregoing description, but are to be afforded a broad scope consistent with the principles and novel features disclosed. Thus, all changes and modifications that come within the spirit and broad scope of the following claims are desired to be protected.

Claims

1. A transistor, the transistor comprising a first insulating layer, characterized in that, The transistor further includes at least one switching region, which includes a gate structure, a first functional layer and a second functional layer. The thickness direction of the first insulating layer is the x-direction, and the first functional layer and the second functional layer are disposed on both sides of the first insulating layer along the x-direction. The first functional layer includes a first semiconductor layer, a first source, and a first drain. The first source is disposed in the source region of the first semiconductor layer, and the first drain is disposed in the drain region of the first semiconductor layer. The second functional layer includes a second semiconductor layer, a second source, and a second drain. The second source is disposed in the source region of the second semiconductor layer and is connected to the first source through a first connecting line passing through the first insulating layer. The second drain is disposed in the drain region of the second semiconductor layer and is connected to the first drain through a second connecting line passing through the first insulating layer. The gate structure is insulated from the first semiconductor layer and the second semiconductor layer respectively, and is disposed opposite to the channel regions of the first semiconductor layer and the second semiconductor layer; The gate structure further includes two gate layers. One gate layer is disposed on the side of the first semiconductor layer away from the first insulating layer, and the first semiconductor layer is disposed on the side of the first source and the first drain away from the first insulating layer. The other gate layer is disposed on the side of the second semiconductor layer away from the first insulating layer, and the second semiconductor layer is disposed on the side of the second source and the second drain away from the first insulating layer. The transistor further includes a metal shielding layer located within the first insulating layer and covering the position of the gate layer projected onto the first insulating layer. The switching area is provided in multiple ways, and the metal shielding layer includes multiple shielding segments, with each switching area corresponding to one shielding segment. With the center of the metal shielding layer passing through the z-direction as the line of symmetry, the first functional layer and the second functional layer are symmetrically arranged; wherein, the direction perpendicular to the x-direction is defined as the y-direction, and the direction perpendicular to both the x-direction and the y-direction is defined as the z-direction.

2. The transistor according to claim 1, characterized in that, The switching region is provided in multiple ways, and the multiple switching regions are distributed along the y-direction. The multiple switching regions distributed along the y-direction are respectively provided with the same gate structure.

3. The transistor according to claim 2, characterized in that, Multiple switching regions are distributed along the z-direction, and multiple gate structures are provided. The multiple gate structures are distributed along the z-direction, and each switching region distributed along the z-direction is provided with an independently controlled gate structure.

4. The transistor according to claim 1, characterized in that, The gate structure further includes a single gate layer, which is disposed between the first semiconductor layer and the second semiconductor layer. The gate layer is disposed within the first insulating layer, and the distance between the gate layer and the first semiconductor layer and the second semiconductor layer is equal.

5. The transistor according to claim 1, characterized in that, The first semiconductor layer and the second semiconductor layer are made of indium gallium zinc oxide.

6. A gate driving circuit, characterized in that, The gate drive circuit includes a plurality of cascaded shift registers, each shift register including a transistor as described in any one of claims 1 to 5.

7. A display device, characterized in that, The display device includes a display panel and a gate driving circuit as described in claim 6, wherein the display panel includes a display area and a non-display area, and the gate driving circuit is disposed in the non-display area.

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