semiconductor structure

Abstract

An embodiment of the present application provides a semiconductor structure comprising: a substrate, a channel layer, a barrier layer, a gate electrode, a source electrode, a drain electrode, and a plurality of island structures. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer, the gate electrode is disposed on the barrier layer, the source electrode and the drain electrode are disposed on opposite sides of the gate electrode and in contact with the barrier layer, respectively. The plurality of island structures are disposed between the gate electrode and the drain electrode, and the two-dimensional electron gas on the upper surface of the channel layer corresponding to the plurality of island structures is discontinuous.

Description

Technical Field

[0001] The present application relates to a semiconductor structure, and more particularly to a semiconductor structure including an island structure in which a two-dimensional electron gas on an upper surface of a channel layer is discontinuous. Background Art

[0002] Gallium nitride (GaN) is widely used due to its excellent properties, including a wide bandgap, high thermal resistance, high electron saturation velocity, and strong polarization effect. For example, GaN semiconductors are currently widely used in high electron mobility transistors (HEMTs) with heterojunction structures.

[0003] However, high electron mobility semiconductors (HEMS) often suffer from insufficient breakdown voltage, excessive on-resistance, and / or uneven electric field distribution, leading to reduced electrical performance. Consequently, while existing semiconductor structures have gradually met their intended uses, they still fall short of fully meeting all requirements. Consequently, further processing of these semiconductor structures to produce HEMS still requires tackling several challenges. Summary of the Invention

[0004] In view of the above problems, the present application further arranges multiple island structures on the barrier layer, in the channel layer, or through the channel layer and the barrier layer, so that the two-dimensional electron gas on the upper surface of the channel layer corresponding to the aforementioned multiple island structures is discontinuous, thereby increasing the breakdown voltage of the semiconductor structure, reducing the on-resistance and / or making the electric field distribution more uniform, thereby improving the electrical performance of the overall semiconductor structure.

[0005] According to some embodiments, a semiconductor structure is provided. The semiconductor structure includes: a substrate, a channel layer, a barrier layer, a gate electrode, a source electrode, a drain electrode, and a plurality of island structures. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The gate electrode is disposed on the barrier layer. The source electrode and the drain electrode are respectively disposed on opposite sides of the gate electrode and respectively contact the barrier layer. The plurality of island structures are disposed between the gate electrode and the drain electrode, and a two-dimensional electron gas (2DEG) on an upper surface of the channel layer corresponding to the plurality of island structures is discontinuous.

[0006] The semiconductor structure of the present application can be applied to various types of semiconductor devices. To make the features and advantages of the present application more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Through the following detailed description and the accompanying drawings, we can better understand the concepts of the embodiments of the present application. It is worth noting that according to standard industry practices, some components (features) may not be drawn to scale. In fact, the dimensions of different components may be increased or decreased for clarity of discussion.

[0008] Figures 1 to 3 1 is a schematic cross-sectional view illustrating a semiconductor structure formed at various stages according to some embodiments of the present application;

[0009] Figures 4 to 6 1 is a schematic cross-sectional view illustrating a semiconductor structure formed at various stages according to some embodiments of the present application;

[0010] Figures 7 to 9 is a schematic cross-sectional view illustrating a semiconductor structure formed at various stages according to some embodiments of the present application; and

[0011] Figures 10 to 13 FIG2 is a schematic top view of a semiconductor structure according to some embodiments of the present application.

[0012] [Explanation of symbols]

[0013] 1,2,3: Semiconductor structure

[0014] 100:Substrate

[0015] 200: buffer layer

[0016] 300: Channel layer

[0017] 310: Two-dimensional electron gas

[0018] 400: Barrier layer

[0019] 500: Compound semiconductor layer

[0020] 510: Gate electrode

[0021] 600: Island structure

[0022] 610: Part 1

[0023] 620: Part 2

[0024] 630: Part 3

[0025] 700: Source electrode

[0026] 800: Drain electrode

[0027] d 12 ,d 23 ,d D ,d G :distance

[0028] P: Path

[0029] R1: Active area

[0030] R2: Inactive area

[0031] R3: Region

[0032] s1: first spacing

[0033] s2: second spacing

[0034] s3: third spacing

[0035] t1: first thickness

[0036] t2: second thickness

[0037] t3: third thickness

[0038] w1: first width

[0039] w2: second width

[0040] w3: third width DETAILED DESCRIPTION

[0041] The following disclosure provides many different embodiments or examples for implementing different elements of the provided semiconductor structure. Specific examples of each element and its configuration are described below to simplify the embodiments of the present application. Of course, these are merely examples and are not intended to limit the present application. For example, if the description refers to a first element formed on a second element, it may include an embodiment in which the first and second elements are in direct contact, and it may also include an embodiment in which an additional element is formed between the first and second elements so that they are not in direct contact. In addition, the embodiments of the present application may repeat reference numbers and / or letters in different examples. Such repetition is for simplicity and clarity, and is not intended to indicate the relationship between the different embodiments and / or forms discussed.

[0042] The following describes some variations of the embodiments. Like reference numerals are used to designate like elements throughout the various figures and illustrated embodiments. It is understood that additional operations may be provided before, during, or after the method, and that some of the described operations may be replaced or deleted for other embodiments of the method.

[0043] Furthermore, spatially relative terms, such as "upper", "lower", "above", "below" and similar terms, include not only the orientations shown in the drawings, but also different orientations of the device in use or operation. When the device is turned to other orientations (rotated 90 degrees or other orientations), the spatially relative descriptions used herein can also be interpreted according to the rotated orientation. Here, the terms "about", "approximately", and "substantially" generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, in the absence of specific descriptions of "about", "approximately", and "substantially", the meanings of "about", "approximately", and "substantially" can still be implied.

[0044] Figures 1 to 3 1 is a schematic cross-sectional view illustrating a semiconductor structure at various stages according to some embodiments of the present application.

[0045] Reference Figure 1 A substrate 100 is provided, on which a buffer layer 200, a channel layer 300, and a barrier layer 400 are formed. The buffer layer 200 may be disposed on the substrate 100. The channel layer 300 may be disposed on the buffer layer 200, that is, the buffer layer 200 may be disposed between the substrate 100 and the channel layer 300. The barrier layer 400 may be disposed on the channel layer 300.

[0046] In one embodiment, the substrate 100 may be a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or a similar substrate. Generally speaking, a semiconductor-on-insulator substrate includes a film layer of semiconductor material formed on an insulator. For example, the insulating layer may be a silicon oxide layer, a silicon nitride layer, a polysilicon layer, or a stacked combination of the above film layers. The above insulating layer is provided on a substrate, typically a silicon or aluminum nitride (AlN) substrate. The substrate 100 may be a doped (for example, using p-type or n-type dopants) or undoped substrate. The substrate 100 may also be other types of substrates, such as a multi-layered substrate or a gradient substrate. In some embodiments, the substrate 100 may be a semiconductor substrate or a ceramic substrate, such as a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, an aluminum nitride substrate, or a sapphire substrate. In some embodiments, the substrate 100 may be a silicon substrate or a silicon carbide substrate.

[0047] In one embodiment, the lattice dislocation and / or lattice difference between the channel layer 300 and the substrate 100 may cause defects and / or strain. However, the buffer layer 200 can reduce or prevent the above-mentioned defects and / or strain. In one embodiment, the material of the buffer layer 200 may include a III-V compound semiconductor material, such as a III-nitride. For example, the material of the buffer layer 200 may be or include gallium nitride, aluminum nitride, aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), a single layer or multilayer combination of the foregoing, or any other suitable material. In some embodiments, the buffer layer 200 can be formed by a deposition process. The deposition process for forming the buffer layer 200 may be metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), combinations thereof, or similar processes, but is not limited thereto.

[0048] In one embodiment, a nucleation layer may be further disposed between the substrate 100 and the buffer layer 200. The material of the nucleation layer may be or include aluminum nitride, aluminum gallium nitride, a combination thereof, or any other suitable material. The nucleation layer may be formed by a deposition process. The deposition process for forming the nucleation layer may be, but is not limited to, metal organic chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, a combination thereof, or a similar process. The nucleation layer can reduce and / or prevent lattice differences between the substrate 100 and other layers disposed thereon, thereby improving crystal quality.

[0049] In one embodiment, the material of the channel layer 300 may include one or more III-V compound semiconductor materials, such as, but not limited to, Group III nitrides. For example, the material of the channel layer 300 may be or may include, but not limited to, gallium nitride, aluminum gallium nitride, aluminum indium nitride, indium gallium nitride (InGaN), indium aluminum gallium nitride (InAlGaN), combinations thereof, or any other suitable material. The channel layer 300 may be formed by a deposition process. The deposition process for forming the channel layer 300 may be, but not limited to, metal organic chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, combinations thereof, or similar processes. In one embodiment, the channel layer 300 may include gallium nitride.

[0050] In one embodiment, the barrier layer 400 may be made of a III-V compound semiconductor material, such as a Group III nitride. For example, the barrier layer 400 may be made of or include aluminum nitride, aluminum gallium nitride, aluminum indium nitride, indium aluminum gallium nitride, combinations thereof, or any other suitable material, but is not limited thereto. The barrier layer 400 may comprise a single layer or a multilayer structure. The barrier layer 400 may be formed by a deposition process, such as, but not limited to, metal organic chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, combinations thereof, or the like. In one embodiment, the barrier layer 400 may comprise aluminum gallium nitride. In some embodiments, the channel layer 300 and the barrier layer 400 are not doped with dopants. In some other embodiments, the channel layer 300 and the barrier layer 400 may use n-type dopants.

[0051] Due to the lattice constant difference caused by the heterojunction between gallium nitride (GaN) serving as the channel layer 300 and aluminum gallium nitride (AlGaN) serving as the barrier layer 400, a two-dimensional electron gas (2DEG) 310 is formed near the upper surface of the channel layer 300. In one embodiment, the 2DEG 310 is formed in the channel layer 300 and adjacent to the barrier layer 400. In some embodiments, the 2DEG channel can provide conductive carriers for a subsequently formed high electron mobility semiconductor, thereby serving as a current path.

[0052] Reference Figure 2 The compound semiconductor layer 500 is formed on the barrier layer 400. In one embodiment, the compound semiconductor layer 500 may be p-type doped. In one embodiment, the compound semiconductor layer 500 may include p-type doped gallium nitride. The compound semiconductor layer 500 may suppress the formation of a two-dimensional electron gas below the compound semiconductor layer 500. In other words, the two-dimensional electron gas corresponding to the bottom of the compound semiconductor layer 500 may be discontinuous, that is, the two-dimensional electron gas is a depleted region. Therefore, by disposing the compound semiconductor layer 500 between the gate electrode and the barrier layer 400 to be formed later, the high electron mobility semiconductor formed later has a normally-off state, thereby overcoming the concern that conventional high electron mobility semiconductors have a normally-on state.

[0053] In one embodiment, the compound semiconductor layer 500 can be formed by the aforementioned deposition process. For example, a compound semiconductor material layer can be formed on the barrier layer 400 through a deposition process; a mask layer is then formed on the compound semiconductor material layer; a photoresist is formed on the mask layer to expose a portion of the mask layer; the mask layer is then patterned to form a patterned mask; a portion of the compound semiconductor material layer is exposed through the patterned mask; and the aforementioned compound semiconductor material layer is then patterned, i.e., the portion of the compound semiconductor material layer not covered by the patterned mask is etched to form the compound semiconductor layer 500. In one embodiment, the compound semiconductor layer 500 has a first thickness t1.

[0054] It should be noted that, in one embodiment, in addition to forming the compound semiconductor layer 500 on the barrier layer 400, a plurality of island structures 600 are formed on the barrier layer 400 and between the subsequently formed gate and drain electrodes. Because the plurality of island structures 600 formed on the barrier layer 400 may comprise a material similar to or identical to that of the compound semiconductor layer 500, the plurality of island structures 600 can also have the effect of transmitting through the barrier layer 400 and suppressing the formation of the two-dimensional electron gas 310. For example, in one embodiment, the plurality of island structures 600 comprise p-type doped gallium nitride (GaN) or p-type doped aluminum gallium nitride (AlGaN). Consequently, the two-dimensional electron gas 310 corresponding to the plurality of island structures 600 on the upper surface of the channel layer 300 is discontinuous, and thus the two-dimensional electron gas between the subsequently formed gate and drain electrodes is discontinuous. In other words, the two-dimensional electron gas 310 corresponding to the plurality of island structures 600 is canceled out. Specifically, in one embodiment, the two-dimensional electron gas 310 beneath the multiple island structures 600 is discontinuous, that is, a depletion region. The term "discontinuous" herein refers to the significant variation in conductivity within the two-dimensional electron gas. In one embodiment, because the length of the conductive path between the gate and drain electrodes is a major factor affecting the breakdown voltage of a high-voltage device, the multiple island structures 600 can be formed only between the subsequently formed gate and drain electrodes, rather than between the subsequently formed gate and source electrodes, to reduce manufacturing costs.

[0055] In one embodiment, forming the compound semiconductor layer 500 on the barrier layer 400 and forming the plurality of island structures 600 on the barrier layer 400 are performed in separate processes. In one embodiment, the plurality of island structures 600 are simultaneously formed on the barrier layer 400 during the process of forming the compound semiconductor layer 500 on the barrier layer 400. In other words, the compound semiconductor layer 500 and the plurality of island structures 600 are formed in the same process, and thus, are formed from the same material and have the same thickness. Forming the compound semiconductor layer 500 and the plurality of island structures 600 in the same process can reduce the cost of the manufacturing process. In one embodiment, the compound semiconductor layer 500 has a first thickness t1; the plurality of island structures 600 have a second thickness t2; and both the compound semiconductor layer 500 and the plurality of island structures 600 are formed of p-type doped gallium nitride (p-GaN), and the first thickness t1 is substantially equal to the second thickness t2. However, this is not limiting, and the first thickness t1 may be different from the second thickness t2. In one embodiment, the number of island structures 600 can be adjusted based on the electrical performance requirements of the semiconductor structure. For example, the island structures 600 can include a first portion 610, a second portion 620, and a third portion 630. However, the arrangement of the island structures 600 will be described in detail later.

[0056] Reference Figure 3 In one embodiment, a gate electrode 510 is subsequently formed on the compound semiconductor layer 500. In some embodiments, the material of the gate electrode 510 may be a conductive material. For example, the conductive material may include a metal, a metal nitride, a semiconductor material, a combination thereof, or any other suitable conductive material, but is not limited thereto. In some embodiments, the metal may be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), the like, or a combination thereof, but is not limited thereto. The semiconductor material may be polycrystalline silicon or polycrystalline germanium. The above-mentioned conductive materials may be deposited by, for example, chemical vapor deposition (CVD), sputtering, resistance heating evaporation, electron beam evaporation, a combination thereof, or the like. Similarly, a conductive material layer may be first formed on the compound semiconductor layer 500, and then the gate electrode 510 may be formed through a patterning process.

[0057] Furthermore, in one embodiment, a contact via (not shown) is formed that penetrates the barrier layer 400 and exposes a portion of the channel layer 300. The aforementioned contact vias can be provided on both sides of the gate electrode 510, and the lateral distance between the aforementioned contact vias and the gate electrode 510 can be adjusted according to the electrical properties of the desired high electron mobility semiconductor. Then, a conductive material is deposited in the contact vias. In one embodiment, the conductive material can be the same as or different from the conductive material used to form the gate electrode 510, and can be deposited using the same or different process as the deposition process used to form the gate electrode 510. The deposited conductive material is then patterned to form a source electrode 700 provided on one side of the gate electrode 510 and in contact with the channel layer 300, and a drain electrode 800 provided on the other side of the gate electrode 510 and in contact with the channel layer 300, thereby obtaining the semiconductor structure 1 of the present application. Among them, the semiconductor structure 1 can be further processed to form a high electron mobility semiconductor.

[0058] Figures 4 to 6 1 is a schematic cross-sectional view of a semiconductor structure formed at various stages according to some embodiments of the present application. Details identical or similar to the above contents are not repeated here.

[0059] Reference Figure 4 In one embodiment, a substrate 100 is provided; a buffer layer 200 is formed on the substrate 100; and a plurality of island structures 600 are formed on the buffer layer 200. That is, the plurality of island structures 600 may be located in the channel layer 300 formed subsequently. In one embodiment, the plurality of island structures 600 may be formed by the aforementioned deposition process. For example, an island structure material layer may be formed on the buffer layer 200 by a deposition process; a patterned mask may then be formed on the island structure material layer; a portion of the island structure material layer may be exposed through the patterned mask; and the island structure material layer may then be patterned to form the plurality of island structures 600. Since the plurality of island structures 600 are formed at the interface between the buffer layer 200 and the channel layer 300, the formation process is simple and the channel layer 300 is not easily damaged, thereby avoiding the problem of reduced reliability of the channel layer 300. In one embodiment, the plurality of island structures 600 include p-type GaN. In one embodiment, the plurality of island structures 600 may include a first portion 610 , a second portion 620 , and a third portion 630 , and may have a third thickness t3 .

[0060] In another embodiment, the plurality of island structures 600 are not limited to being formed on the upper surface of the buffer layer 200. The plurality of island structures 600 may also be formed in the channel layer 300 but not in contact with the buffer layer 200. For example, a portion of the channel layer may be first formed on the buffer layer 200, followed by forming the plurality of island structures 600 on the portion of the channel layer, and then forming another portion of the channel layer on the plurality of island structures 600, so that the plurality of island structures 600 are disposed in the channel layer 300.

[0061] Reference Figure 5 Next, a channel layer 300 is formed on the buffer layer 200 and the plurality of island structures 600 using an epitaxial process such as MOCVD, and a barrier layer 400 is formed on the buffer layer. In one embodiment, the plurality of island structures 600 are all formed of p-type GaN. As previously described, a compound semiconductor layer 500 is then formed on the barrier layer 400, and a gate electrode 510 is formed on the compound semiconductor layer 500.

[0062] Reference Figure 6 , forming a source electrode 700 and a drain electrode 800 on opposite sides of the gate electrode 510, thereby obtaining the semiconductor structure 2 of the present application, wherein the source electrode 700 and the drain electrode 800 are respectively in contact with the channel layer 300. The semiconductor structure 2 can be further processed to form a high electron mobility semiconductor. In some embodiments, the source electrode 700 and the drain electrode 800 are respectively in contact with the barrier layer 400, that is, the depth of the source electrode 700 and the drain electrode 800 does not reach the channel layer 300 (not shown).

[0063] It should be noted that the multiple island structures 600 can penetrate the channel layer 300 and upwardly influence the two-dimensional electron gas 310 on the upper surface of the channel layer 300, causing the corresponding two-dimensional electron gas 310 to be discontinuous. Specifically, in one embodiment, the two-dimensional electron gas 310 located above the multiple island structures 600 is discontinuous, that is, it forms a depletion region. Furthermore, the vertical depth of the multiple island structures 600 within the channel layer 300, the third thickness t3 of the multiple island structures 600, and / or the number of the multiple island structures 600 can all be adjusted based on the desired electrical performance of the semiconductor structure. In one embodiment, compared to forming the plurality of island structures 600 on the barrier layer 400, forming the plurality of island structures 600 in the channel layer 300 allows the plurality of island structures 600 to be closer to the two-dimensional electron gas 310 located on the upper surface of the channel layer 300. Therefore, the plurality of island structures 600 can be thinner. For example, the plurality of island structures 600 can have a third thickness t3 that is smaller than the first thickness t1 and / or the second thickness t2. This also allows the corresponding two-dimensional electron gas 310 to be discontinuous.

[0064] Therefore, by forming multiple island structures 600 in the channel layer 300, the margin of the formation process for forming the multiple island structures 600 can be improved and the process cost can be reduced. In detail, since the thickness of the multiple island structures 600 formed in the channel layer 300 can be adjusted according to the required electrical properties of the semiconductor structure, multiple island structures 600 with various appropriate thicknesses can be provided, thereby improving the process margin. In addition, since multiple thinner island structures 600 can be provided, the formation time of the formation process of the multiple island structures 600, such as the deposition time, can be reduced, and the deposition material required can be reduced, thereby reducing the cost of the formation process.

[0065] Figures 7 to 9 1 is a schematic cross-sectional view of a semiconductor structure formed at various stages according to some embodiments of the present application. Details identical or similar to the above contents are not repeated here.

[0066] Reference Figure 7 , similar to Figure 1 , providing a substrate 100, and sequentially forming a buffer layer 200, a channel layer 300, and a barrier layer 400.

[0067] Reference Figure 8 A plurality of island structures 600 are formed on the buffer layer 200, penetrating the channel layer 300 and the barrier layer 400. A compound semiconductor layer 500 and a gate electrode 510 are sequentially formed on the barrier layer 400. In one embodiment, a patterned mask can be formed on the barrier layer 400 to expose a portion of the barrier layer 400. The barrier layer 400 and the channel layer 300 are then patterned, and the unmasked portions of the barrier layer 400 and the channel layer 300 are removed through an etching process to form a plurality of island structure locations (not shown) penetrating the barrier layer 400 and the channel layer 300. The island structure locations are then filled with an island structure material to form the plurality of island structures 600. The island structure material may include or be an insulating material such as silicon oxide, silicon nitride, a combination thereof, or the like. In another embodiment, the plurality of island structures 600 can be formed by an implantation process. For example, the plurality of island structures 600 may be formed by implanting N 2 , Ar, Br, the like, or a combination thereof.

[0068] In one embodiment, the plurality of island structures 600 may penetrate the barrier layer 400 but not the channel layer 300. Specifically, the plurality of island structures 600 may penetrate the barrier layer 400 and the two-dimensional electron gas on the upper surface of the channel layer 300, but not the channel layer 300. The bottom surfaces of the plurality of island structures 600 may not contact the bottom surface of the channel layer 300, that is, the bottom surfaces of the plurality of island structures 600 may not contact the top surface of the buffer layer 200 and may be spaced apart. Because the plurality of island structures 600 penetrate the two-dimensional electron gas on the upper surface of the channel layer 300, the two-dimensional electron gas corresponding to the plurality of island structures 600 can be discontinuous. In other words, because the plurality of island structures 600 penetrate the two-dimensional electron gas, substantially no two-dimensional electron gas is present between adjacent island structures in the plurality of island structures 600.

[0069] Therefore, forming multiple island structures 600 through an implantation process not only discontinuously creates a two-dimensional electron gas (2DEG), but also simplifies the process for forming multiple island structures 600 and makes the process for forming multiple island structures 600 more compatible with existing processes, thereby improving process margins and reducing process costs. For example, parameters such as the implantation mask, implantation concentration, implanted dopant type, and implantation depth can be adjusted based on the desired electrical performance of the semiconductor structure to flexibly form multiple island structures 600.

[0070] Reference Figure 9 The source electrode 700 and the drain electrode 800 are formed on opposite sides of the gate electrode 510 to obtain the semiconductor structure 3 of the present application. The semiconductor structure 3 can be further processed to form a high electron mobility semiconductor.

[0071] It should be noted that, since the plurality of island structures 600 penetrate the barrier layer 400 and the channel layer 300 , no two-dimensional electron gas 310 is generated at the plurality of island structures 600 , making the corresponding two-dimensional electron gas 310 discontinuous, thereby increasing the breakdown voltage of the semiconductor structure and reducing the on-resistance.

[0072] Continuing from the above, Figures 10 to 13 1 is a schematic top view of a semiconductor structure 1 , 2 or 3 according to some embodiments of the present application. Figure 3 、 Figure 6 and Figure 9 Can be along Figure 10 Schematic cross-sectional view taken along section line AA'.

[0073] Reference Figure 10 For ease of illustration, only the barrier layer 400, the gate electrode 500, the plurality of island structures 600, the source electrode 700, and the drain electrode 800 are shown, and other components are omitted. Figure 10In the embodiment, the plurality of island structures 600 may be shown as an embodiment disposed on the barrier layer 400, or as an embodiment penetrating the barrier layer 400 and the channel layer 300. However, Figure 10 The multiple island structures 600 shown are also applicable to the embodiment of being disposed in the channel layer.

[0074] like Figure 10 As shown, when viewed from above, the multiple island-like structures 600 include multiple columns of island-like portions arranged along an extension direction parallel to the gate electrode 510. For example, each column of the multiple columns of island-like portions is arranged along a lateral direction, and the length direction of each island-like portion in the multiple columns of island-like portions is parallel to the aforementioned lateral direction. The number of columns of island-like portions included in the multiple island-like structures 600 can be adjusted according to the required electrical performance. For example, it can be any integer between 1 and 50. For ease of explanation, the following description only uses island-like portions including 3 columns, but the present application is not limited to this.

[0075] Continuing from the above, in one embodiment, the plurality of island-shaped portions include a plurality of first portions 610, a plurality of second portions 620, and a plurality of third portions 630. Among the plurality of third portions 630, the first portion 610 is closest to the gate electrode 510; the third portion 630 is farthest from the gate electrode; and the second portion 620 is disposed between the first portion 610 and the third portion 630.

[0076] like Figure 10 As shown, in one embodiment, the first portion 610, the second portion 620, and the third portion 630 are arranged in an alternating pattern. By staggering the first portion 610, the second portion 620, and the third portion 630, the two-dimensional electron gas corresponding to the first portion 610, the second portion 620, and the third portion 630 is discontinuous, allowing the conductive path P to extend along the portion not corresponding to the first portion 610, the second portion 620, and the third portion 630, thereby forming a non-linear conductive path P. For example, the conductive path P may be zigzag-shaped, but the present application is not limited thereto. The conductive path P may also be zipper-shaped, Z-shaped, or similar shapes. Therefore, compared to a linear conductive path P, the total path length of the conductive path P in the semiconductor structure of the present application is greater, thereby increasing the distance between the source electrode 700 and the drain electrode 800, thereby increasing the breakdown voltage.

[0077] also, Figure 10The active region R1 and inactive region R2 of the high electron mobility semiconductor formed by subsequent processing of the semiconductor structure 1, 2, or 3 are shown. The active region R1 and the inactive region R2 can be defined via a mesa (MESA) process. For example, after forming the barrier layer 400, a dry etching process is performed to etch the barrier layer 400, the channel layer 300, and the buffer layer 200 to form an isolation mesa on the substrate 100. This isolates the semiconductor structures on the substrate 100 and defines the isolation mesa as the active region R1.

[0078] In some embodiments, at least a portion of the multiple island structures 600 spans the active region R1 and the inactive region R2. For example, the second portion 620 spans the active region R1 and the inactive region R2 to further ensure that the conduction path is non-linear, thereby increasing the breakdown voltage. Furthermore, in one embodiment, in the region R3 between the gate electrode 510 and the drain electrode 800 in the active region R1, the ratio of the area of the multiple island structures 600 to the total area of the region R3 is 0.05 to 0.9. When the ratio is less than 0.05, there will be no significant difference from the existing semiconductor structure, and therefore the breakdown voltage of the semiconductor structure cannot be increased and the on-resistance cannot be reduced. When the ratio is greater than 0.9, it will lead to the negative effect of too little current. In one embodiment, the ratio of the area of the multiple island structures 600 to the total area of the region R3 is 0.2 to 0.6.

[0079] like Figure 10 As shown, the first portion 610 has a first width w1, and adjacent first portions 610 have a first spacing s1; the second portion 620 has a second width w2, and adjacent second portions 620 have a second spacing s2; and the third portion 630 has a third width w3, and adjacent third portions 630 have a third spacing s3. There is a distance d between the gate electrode 510 and the first portion 610. G The first portion 610 and the second portion 620 closest to the first portion 610 have a distance d between them 12 The second portion 620 and the third portion 630 closest to the second portion 620 have a distance d between them 23 ; and a distance d between the third portion 630 and the drain electrode D .

[0080] It should be noted that, taking the first portion 610 of the multiple island structures 600 as an example, when the size of region R3 is fixed, if the first width w1 is constant, increasing the first spacing s1 will increase the current; whereas, if the first width w1 is constant, shortening the first spacing s1 will improve the uniformity of the electric field distribution. Furthermore, in one embodiment, the thickness of the multiple island structures 600 is adjusted to discontinuously distribute the corresponding two-dimensional electron gas 310; and the spacing between the multiple island structures 600 is adjusted to optimize the electric field distribution.

[0081] exist Figure 10 , the first width w1, the second width w2 and the third width w3 are substantially the same; the first spacing s1, the second spacing s2 and the third spacing s3 are substantially the same; and the distance d G , distance d 12 , distance d 23 and distance d D Therefore, the semiconductor substrate of the present application has the beneficial effect of being simple and easy to design.

[0082] Reference Figure 11 , the first width w1 is greater than the second width w2, and the second width w2 is greater than the third width w3; the first spacing s1, the second spacing s2 and the third spacing s3 are substantially the same; and the distance d G , distance d 12 , distance d 23 and distance d D Therefore, the semiconductor substrate of the present application can have the effect of reducing the electric field near the gate electrode 510 .

[0083] Reference Figure 12 , the first width w1, the second width w2 and the third width w3 are substantially the same; the first spacing s1 is smaller than the second spacing s2, and the second spacing s2 is smaller than the third spacing s3; and the distance d G , distance d 12 , distance d 23 and distance d D Therefore, the semiconductor substrate of the present application can have the effect of balancing the electric fields near the gate electrode 510 and near the drain electrode 800 .

[0084] Reference Figure 13 , the first width w1, the second width w2 and the third width w3 are substantially the same; the first spacing s1, the second spacing s2 and the third spacing s3 are substantially the same; and at a distance d G and distance d D When the distance d is substantially the same, 12 Less than distance d 23 Therefore, the semiconductor substrate of the present application can have the effect of balancing the electric field and current.

[0085] In addition, the semiconductor structure of the present application can also be applied to metal-insulator-semiconductor high electron mobility semiconductors (MIS-HEMT).

[0086] In summary, according to some embodiments of the present application, the present application provides a plurality of island structures in the channel layer, on the barrier layer and / or on the buffer layer and at positions that penetrate the channel layer and the barrier layer, so that the two-dimensional electron gas between the gate electrode and the drain electrode is a depletion region, thereby increasing the breakdown voltage of the semiconductor structure and reducing the on-resistance, thereby improving the performance of the subsequently formed high electron mobility semiconductor. In addition, the thickness, width, spacing and staggered arrangement of the plurality of island structures can be adjusted according to the required electrical performance. Therefore, the present application can make the conduction path between the gate electrode and the drain electrode a non-straight path when observed from a top view, thereby increasing the total length of the conduction path and thereby increasing the breakdown voltage. Furthermore, since the present application includes a plurality of island structures, it is possible to improve the uniformity of the electric field distribution.

[0087] Although the embodiments of the present application and their advantages have been disclosed as above, it should be understood that anyone with ordinary knowledge in the art can make changes, substitutions and modifications without departing from the scope of protection of the present application. In addition, the scope of protection of the present application is not limited to the processes, machines, manufacturing, material compositions, devices, methods and steps in the specific embodiments described in the specification. Anyone with ordinary knowledge in the art can understand the current or future developed processes, machines, manufacturing, material compositions, devices, methods and steps from the disclosure of some embodiments of the present application. As long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described herein, they can all be used according to some embodiments of the present application. Therefore, the scope of protection of the present application includes the above-mentioned processes, machines, manufacturing, material compositions, devices, methods and steps. In addition, each patent application constitutes an individual embodiment, and the scope of protection of the present application also includes the combination of each patent application and embodiment.

Claims

1. A semiconductor structure, characterized in that Include: a substrate; a channel layer, disposed on the substrate; a barrier layer disposed on the channel layer; a gate electrode disposed on the barrier layer; a source electrode and a drain electrode, respectively disposed on opposite sides of the gate electrode and respectively contacting the barrier layer; as well as A plurality of island structures are disposed between the gate electrode and the drain electrode, and the two-dimensional electron gas corresponding to the plurality of island structures on the upper surface of the channel layer is discontinuous. Wherein, when viewed from above, the plurality of island-shaped structures include a plurality of columns of island-shaped portions arranged along an extension direction parallel to the gate electrode, and the plurality of columns of island-shaped portions include a plurality of first portions, a plurality of second portions, and a plurality of third portions; The first portions are closest to the gate electrode; the third portions are farthest from the gate electrode; and the first portions, the second portions, and the third portions are staggered. A first spacing between adjacent first portions in the plurality of first portions is less than or equal to a second spacing between adjacent second portions in the plurality of second portions; and the second spacing is less than or equal to a third spacing between adjacent third portions in the plurality of third portions; or A distance between a first portion of the plurality of first portions and a most adjacent second portion of the plurality of second portions is less than or equal to a distance between the second portion of the plurality of second portions and a most adjacent third portion of the plurality of third portions.

2. The semiconductor structure according to claim 1, wherein: The source electrode and the drain electrode are in contact with the channel layer respectively.

3. The semiconductor structure according to claim 1, wherein: Also includes: a buffer layer disposed between the substrate and the channel layer; and A compound semiconductor layer is disposed between the barrier layer and the gate electrode.

4. The semiconductor structure according to claim 1, wherein: The plurality of island structures are disposed in the channel layer.

5. The semiconductor structure according to claim 1, wherein: The plurality of island structures are disposed on the barrier layer.

6. The semiconductor structure according to claim 4 or 5, characterized in that: The plurality of island structures include p-type doped gallium nitride or p-type doped aluminum gallium nitride.

7. The semiconductor structure according to claim 1, wherein: The plurality of island structures are disposed on the substrate and penetrate the channel layer and the barrier layer.

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