Semiconductor structure and method for forming semiconductor structure

Abstract

A semiconductor structure and a method for forming the same include: a substrate having a plurality of parallel fin structures; a gate structure located on the substrate; source / drain doped regions located within the fin structures on either side of the gate structure; and a second insulating layer, wherein the source / drain doped regions contain first ions. The gate structure spans the fin structure and is located within the second insulating layer. A metal layer located within the second insulating layer, extending in the same direction as the fin structures and located on the source / drain doped regions. A first isolation structure located within the second insulating layer and within the fin structures, extending in the same direction as the fin structures, and located between adjacent metal layers. A second isolation structure located within the second insulating layer, extending in the same direction as the fin structures, located on the first isolation structure, and located between adjacent metal layers. The performance of the structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the semiconductor structure Background Art

[0002] With the continuous development of semiconductor technology, the improvement of integrated circuit performance is mainly achieved by continuously reducing the size of integrated circuit devices to increase their speed. Currently, due to the demand for high device density, high performance and low cost, the semiconductor industry has advanced to nanotechnology process nodes, and the production of semiconductor devices is restricted by various physical limits.

[0003] As CMOS device sizes continue to shrink, manufacturing and design challenges have led to the development of three-dimensional designs such as fin field-effect transistors (FinFETs). Compared to existing planar transistors, FinFETs are advanced semiconductor devices used in process nodes of 20nm and below. They can effectively control the short-channel effect, which is difficult to overcome when devices are scaled down, and can also effectively increase the density of transistor arrays formed on the substrate. At the same time, the gate in FinFETs is set around the fin (fin-shaped channel), so static electricity can be controlled from three sides, and the performance in static control is also more outstanding.

[0004] In order to further increase the device density in the FinFET process, many single diffusion breaks (SDBs) can be designed to form more and narrower shallow trench isolations to save the area of the gate array.

[0005] However, the process and performance of the existing design of shallow trench isolation formed by cutting off a single diffusion region still need to be improved. Summary of the Invention

[0006] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the semiconductor structure, so as to improve the performance of the semiconductor structure.

[0007] To solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, comprising: a substrate, wherein the substrate has a plurality of parallel fin structures and a first insulating layer, the first insulating layer is located on the side wall of the fin structure and the top plane of the first insulating layer is lower than the top surface of the fin structure; a gate structure located on the substrate and source-drain doped regions in the fin structure on both sides of the gate structure, the source-drain doped regions have first ions, and the gate structure spans the fin structure; a second insulating layer located on the substrate, the gate structure is located in the second insulating layer, and the top plane of the second insulating layer is higher than the top plane of the gate structure; a metal layer located in the second insulating layer, the extension direction of the metal layer is the same as the arrangement direction of the fin structure, the metal layer is located on the source-drain doped regions and is electrically connected to the source-drain doped regions; a first isolation structure located in the second insulating layer and in the fin structure, the extension direction of the first isolation structure is the same as the arrangement direction of the fin structure, and the first isolation structure is located between adjacent metal layers. A second isolation structure is located in the substrate, wherein the extension direction of the second isolation structure is the same as the arrangement direction of the fin structure, the second isolation structure is located on the first isolation structure, and the first isolation structure and the second isolation structure are located between adjacent metal layers.

[0008] Optionally, the first isolation structure is located on the substrate and isolates the fin structure.

[0009] Optionally, the method further includes: a second isolation structure located in the fin structure, the first isolation structure is located on the second isolation structure, the second isolation structure has second ions therein, and the conductivity type of the second ions is opposite to that of the first ions.

[0010] Optionally, the material of the second isolation structure is a fin structure material having second ions.

[0011] Optionally, the first ions include N-type ions or P-type ions; the second ions include N-type ions or P-type ions.

[0012] Optionally, the method further includes: a blocking structure located in the second insulating layer, wherein the extending direction of the blocking structure is the same as the extending direction of the fin structure, and the blocking structure is located between adjacent metal layers.

[0013] Optionally, the material of the blocking structure includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0014] Optionally, the material of the first isolation structure includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0015] Optionally, the method further includes: an etch stop layer located within the second insulating layer, wherein a bottom surface of the etch stop layer is coplanar with a top surface of the gate structure.

[0016] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate having a plurality of parallel fin structures thereon; forming a gate structure, source-drain doped regions located in the fin structures on both sides of the gate structure, and a second insulating layer on the substrate, wherein the source-drain doped regions have first ions, the gate structure spans the fin structure, and the gate structure is located in the second insulating layer; forming an initial metal layer in the second insulating layer, wherein the extension direction of the initial metal layer is the same as the arrangement direction of the fin structure, the initial metal layer is located on the source-drain doped regions and is electrically connected to the source-drain doped regions; forming a mask structure on the substrate, wherein the mask structure has a plurality of first openings therein, the extension direction of the first openings is the same as the arrangement direction of the fin structure, and the first openings expose a portion of the surface of the initial metal layer; using the mask structure as a mask, removing the initial metal layer exposed by the first openings, forming a first groove in the second insulating layer, wherein the first groove exposes the surface of the source-drain doped region; removing the source-drain doped region exposed by the first groove until the surface of the fin structure is exposed, and forming a second groove in the fin structure; and forming a first isolation structure in the first groove and the second groove.

[0017] Optionally, the mask structure further has a plurality of second openings, the extension direction of the second openings is the same as the extension direction of the fin structure, and the second openings expose a portion of the second insulation layer surface and the initial metal layer surface between adjacent fin structures.

[0018] Optionally, using the mask structure as a mask to remove the initial metal layer exposed by the first opening also includes: removing the initial metal layer exposed by the second opening to form a third groove in the second insulating layer.

[0019] Optionally, while forming the first isolation structure in the first groove and the second groove, the method further includes: forming a blocking structure in the third groove.

[0020] Optionally, the material of the blocking structure includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0021] Optionally, after forming the second groove in the fin structure and before forming the first isolation structure in the first groove and the second groove, it also includes: removing the fin structure exposed by the second groove until the substrate surface is exposed, and forming a fourth groove in the fin structure; the first isolation structure is also located in the fourth groove.

[0022] Optionally, the material of the first isolation structure includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0023] Optionally, the process for removing the fin structure exposed by the second groove includes a pulse plasma etching process, wherein the parameter range of the pulse plasma etching process is: power of 400 watts to 1400 watts; bias voltage of 100 volts to 1000 volts; duty cycle of 5% to 60%; gas of halogen-containing gas, C x H y O z and one or more of hydrogen, and one or more of helium or argon, the halogen-containing gas includes chlorine-containing gas or bromine-containing gas, the x is a natural number greater than or equal to 1, the value of the y is a natural number greater than or equal to 1, and the z is a natural number greater than or equal to 0.

[0024] Optionally, after forming the second groove in the fin structure and before forming the first isolation structure in the first groove and the second groove, it also includes: ion implantation of second ions into the fin structure exposed by the second groove, wherein the conductivity type of the second ions is opposite to the conductivity type of the first ions in the source and drain doping regions, thereby forming a second isolation structure in the fin structure.

[0025] Optionally, the first ions include N-type ions or P-type ions; the second ions include N-type ions or P-type ions.

[0026] Optionally, the process for removing the source / drain doped region exposed by the first groove includes a pulsed plasma etching process, wherein the parameter range of the pulsed plasma etching process is: power of 400W to 1400W; bias voltage of 100V to 1000V; duty cycle of 5% to 60%; gas of halogen-containing gas, C x H y O z and one or more of hydrogen, and one or more of helium or argon, the halogen-containing gas includes chlorine-containing gas or bromine-containing gas, the x is a natural number greater than or equal to 1, the value of the y is a natural number greater than or equal to 1, and the z is a natural number greater than or equal to 0.

[0027] Optionally, the process of removing the initial metal layer exposed by the first opening includes a wet etching process or a dry etching process; the gas of the dry etching process includes carbon fluorine gas, and one or more of oxygen and hydrogen; the etching solution of the wet etching process includes an acidic solution, and the acidic solution includes sulfuric acid, hydrochloric acid or hydrofluoric acid.

[0028] Optionally, the mask structure includes: a liner layer, an anti-reflection layer located on the liner layer, and a photoresist layer located on the anti-reflection layer.

[0029] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0030] The formation method of the present invention first forms an initial metal layer located on the source and drain doped regions, then forms a mask structure having a plurality of first openings extending in the same direction as the arrangement of the fin structures. A portion of the initial metal layer is removed to form a first groove, and then the source and drain doped regions are removed to form a second groove. A first isolation structure is then formed within the first and second grooves. By first forming the initial metal layer and then removing a portion of the initial metal layer to form the first isolation structure, the process of forming the first isolation structure does not damage the gate structure, thereby improving the performance of the semiconductor structure.

[0031] Furthermore, the mask structure also includes a plurality of second openings extending in the same direction as the fin structures. The second openings expose portions of the second insulating layer surface and the initial metal layer surface between adjacent fin structures. The second openings in the mask structure are openings for cutting through the initial metal layer. Integrating the openings for cutting through the initial metal layer and forming the first isolation structure into a single mask reduces costs and simplifies the process.

[0032] Furthermore, the first isolation structure and the barrier structure are formed simultaneously, thereby saving process flow.

[0033] Furthermore, the first isolation structure is also located in the fourth groove, and the first isolation structure has a good isolation capability for the fin structure.

[0034] Furthermore, the second isolation structure is formed by ion implantation of second ions into the fin structure. The conductivity type of the second ions is opposite to that of the first ions in the source and drain doping regions. During operation, the second ions have an opposite conductivity type to that of the ions in the fin structure, thereby acting as an inversion barrier. This provides improved isolation between the first and second isolation structures. Furthermore, the implantation of the second ions can repair lattice defects in the fin structure caused by removing the source and drain doping regions, thereby improving the performance of the fin structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figures 1 to 3 is a schematic cross-sectional structural diagram of a semiconductor structure forming process in one embodiment;

[0036] Figures 4 to 18 is a schematic cross-sectional view of a semiconductor structure forming process according to an embodiment of the present invention;

[0037] Figure 19 and Figure 20 It is a schematic cross-sectional structural diagram of a semiconductor structure forming process in another embodiment of the present invention. DETAILED DESCRIPTION

[0038] As described in the background art, the existing process and performance of shallow trench isolation formed by cutting a single diffusion region still need to be improved.

[0039] Figures 1 to 3 It is a schematic cross-sectional structural diagram of a semiconductor structure forming process in one embodiment.

[0040] Please refer to Figure 1 , providing a substrate 100; the substrate 100 has a fin 101; the substrate 100 has a plurality of gate structures 103, the gate structures 103 spanning the fin 101; the substrate 100 has a second insulating layer 102, the gate structures 103 are located in the second insulating layer 102.

[0041] Please refer to Figure 2 , a mask structure 104 is formed on the substrate 100, wherein the mask structure 104 exposes a portion of the top surface of the gate structure 103; using the mask structure 104 as a mask, a portion of the gate structure 103 and the fin 101 is removed to form an opening 105 in the second insulating layer 102 and the fin 101.

[0042] Please refer to Figure 3 , an isolation structure 106 is formed in the opening 105 .

[0043] During the formation of the semiconductor structure, after the gate structure 103 is formed, portions of the gate structure 103 and the fin 101 are removed, and then the isolation structure 106 is formed. On the one hand, the gate structure 103 is formed first, and then portions of the gate structure 103 are removed to form the isolation structure 106. During the process of forming the opening 105, the plasma of the etching process is likely to damage other gate structures 103 that do not need to be removed, resulting in differences in the operating voltages of the gate structures 103. On the other hand, the gate structure 103 is a metal gate, and includes a second gate insulating layer, a work function layer located on the second gate insulating layer, and a gate layer located on the work function layer. During the process of removing the gate structure 103, the work function layer is composed of multiple layers of different materials. Therefore, the removal process results in poor uniformity in the removal of the gate structure 103, resulting in differences in the isolation structure 106 formed subsequently. Furthermore, a separate mask is required to form the isolation structure 106, which is also costly.

[0044] To address the aforementioned issues, the present invention provides a semiconductor structure and a method for forming the same. The method involves first forming an initial metal layer on the source and drain doped regions, then forming a mask structure having a plurality of first openings extending in the same direction as the arrangement of the fin structures. A portion of the initial metal layer is removed to form a first groove, and then the source and drain doped regions are removed to form a second groove. Finally, a first isolation structure is formed within the first groove and the second groove. By first forming the initial metal layer and then removing a portion of the initial metal layer to form the first isolation structure, the process of forming the first isolation structure does not damage the gate structure, thereby improving the performance of the semiconductor structure.

[0045] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0046] Figures 4 to 18 It is a schematic cross-sectional structural diagram of a semiconductor structure forming process in one embodiment of the present invention.

[0047] Please refer to Figure 4 and Figure 5 , Figure 5 for Figure 4 A top view of Figure 4 for Figure 5 A schematic structural diagram along the section line AA1 shows a substrate 200 having a plurality of fin structures 201 arranged in parallel.

[0048] In this embodiment, a first insulating layer (not shown) is further formed on the substrate. The first insulating layer is located on the sidewall of the fin structure 201 , and a top plane of the first insulating layer is lower than the top surface of the fin structure 201 .

[0049] The material of the first insulating layer includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride, and silicon carbon nitride oxynitride. In this embodiment, the material of the first insulating layer includes silicon oxide.

[0050] In this embodiment, the substrate 200 is made of silicon. The fin structure 201 is made of silicon.

[0051] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon on insulator (SOI), or germanium on insulator (GOI). Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP. The material of the fin structure includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon on insulator (SOI), or germanium on insulator (GOI). Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0052] Please refer to Figure 6 , Figure 6 For Figure 4 Based on the schematic diagram, a gate structure 204, a source-drain doped region 203 located in the fin structure 201 on both sides of the gate structure 204, and a second insulating layer 205 are formed on the substrate 200, the source-drain doped region 203 has a first ion, the gate structure 204 spans the fin structure 201, the gate structure 204 is located in the second insulating layer 205, and the top plane of the second insulating layer 205 is higher than the top plane of the gate structure 204.

[0053] In this embodiment, the present invention further includes an etch stop layer (not shown) located in the second insulating layer 205 , wherein the bottom surface of the etch stop layer is coplanar with the top surface of the gate structure 204 .

[0054] The etching stop layer is used to ensure that the pattern transfer process of the first opening in the mask structure is accurate when the first groove is subsequently formed in the second insulating layer, and the size accuracy of the formed first groove is good.

[0055] The material of the etching stop layer is different from that of the second insulating layer 205 .

[0056] The material of the etch stop layer includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride, and silicon carbon nitride oxynitride. In this embodiment, the material of the etch stop layer includes silicon nitride.

[0057] The gate structure 204 includes a gate dielectric layer (not shown) and a gate layer (not shown) located on the gate dielectric layer.

[0058] In this embodiment, the material of the gate dielectric layer includes a high dielectric constant material having a dielectric constant greater than 3.9, and the high dielectric constant material includes hafnium oxide or aluminum oxide; the material of the gate layer includes a metal, and the metal includes tungsten.

[0059] In other embodiments, the material of the gate dielectric layer includes silicon oxide or a low-K (K less than 3.9) material; and the material of the gate layer includes polysilicon.

[0060] In this embodiment, the gate structure 204 also includes a work function layer (not marked), which is located between the gate dielectric layer and the gate layer; the material of the work function layer includes an N-type work function material or a P-type work function material, the N-type work function material includes titanium aluminum, and the P-type work function material includes titanium nitride or tantalum nitride.

[0061] The material of the second insulating layer 205 includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride, and silicon carbon nitride oxynitride. In this embodiment, the material of the second insulating layer 205 includes silicon oxide.

[0062] The first ions in the source / drain doping region 203 are of N-type or P-type. The N-type ions include phosphorus ions, arsenic ions, or antimony ions. The P-type ions include boron ions, boron fluoride ions, or indium ions.

[0063] Please refer to Figure 7 and Figure 8 , Figure 8 for Figure 7 The top view of the second insulating layer 205 is omitted. Figure 7 for Figure 8 Schematic diagram of the cross-sectional structure along the section line BB1, an initial metal layer 206 is formed in the second insulating layer 205, the extension direction of the initial metal layer 206 is the same as the arrangement direction of the fin structure 201, and the initial metal layer 206 is located on the source and drain doping region 203 and is electrically connected to the source and drain doping region 203.

[0064] The method for forming the initial metal layer 206 includes: forming a patterned layer (not shown) on the second insulating layer 205, wherein the patterned layer exposes a portion of the surface of the second insulating layer 205 on the source-drain doped region 203; etching the second insulating layer 205 using the patterned layer as a mask until the surface of the source-drain doped region 203 is exposed, thereby forming a plurality of conductive openings (not shown) in the second insulating layer 205; forming a metal material layer (not shown) in the conductive openings and on the second insulating layer 205; and planarizing the metal material layer until the surface of the second insulating layer 205 is exposed, thereby forming the initial metal layer 206 in the second insulating layer 205.

[0065] The material of the initial metal layer 206 includes metal or metal nitride; the metal includes one or more combinations of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes one or more combinations of tantalum nitride and titanium nitride.

[0066] Please refer to Figure 9 、 Figure 10 and Figure 11 , Figure 11 for Figure 9 and Figure 10 A top view of Figure 9 for Figure 11 Schematic diagram of the cross-section structure along the section line CC1, Figure 10 for Figure 11 A schematic diagram of the cross-sectional structure along the section line DD1 shows that a mask structure 207 is formed on the substrate 200, and the mask structure 207 has a plurality of first openings 208. The extension direction of the first openings 208 is the same as the arrangement direction of the fin structure 201, and the first openings 208 expose part of the surface of the initial metal layer 206.

[0067] In this embodiment, the mask structure 207 further has a plurality of second openings 209 , the extension direction of the second openings 209 being the same as the extension direction of the fin structure 201 , and the second openings 209 exposing portions of the second insulating layer 205 surface and the initial metal layer 206 surface between adjacent fin structures 201 .

[0068] The first opening 208 is an opening for subsequently forming a first isolation structure, and the second opening 209 is an opening for cutting the initial metal layer 206. Integrating the openings for cutting the initial metal layer 206 and forming the first isolation structure into one mask can save costs and simplify the process.

[0069] The mask structure 207 includes a liner layer (not shown), an anti-reflection layer (not shown) on the liner layer, and a photoresist layer (not shown) on the anti-reflection layer.

[0070] The material of the liner layer includes an amorphous material, and the amorphous material includes amorphous silicon or amorphous carbon; the anti-reflection layer includes a thin silicon anti-reflection layer (Si-ARC), an organic bottom anti-reflection layer (organic BARC), a dielectric anti-reflection layer (DARC) or a combination of an organic bottom anti-reflection layer and a dielectric anti-reflection layer.

[0071] Please refer to Figure 12 、 Figure 13 and Figure 14 , Figure 14 for Figure 12 and Figure 13 A top view of Figure 12 for Figure 14 Schematic diagram of the cross-section structure along the section line EE1, Figure 13 for Figure 14 The schematic cross-sectional structure diagram along the section line FF1 shows that the mask structure 207 is used as a mask to remove the initial metal layer 206 exposed by the first opening 208 and form a first groove 210 in the second insulating layer 205. The first groove 210 exposes the surface of the source and drain doped region 203.

[0072] The process of removing the initial metal layer 206 exposed by the first opening 208 includes a wet etching process or a dry etching process; the gas of the dry etching process includes carbon fluorine gas, and one or more of oxygen and hydrogen; the etching solution of the wet etching process includes an acidic solution, and the acidic solution includes sulfuric acid, hydrochloric acid or hydrofluoric acid.

[0073] In this embodiment, using the mask structure 207 as a mask to remove the initial metal layer 206 exposed by the first opening 208 , the process also includes removing the initial metal layer 206 exposed by the second opening 209 to form a third groove 212 in the second insulating layer 205 .

[0074] Please refer to Figure 15 , Figure 15 For Figure 12 Based on the structural diagram, the source and drain doped regions 203 exposed by the first groove 210 are removed until the surface of the fin structure 201 is exposed, and a second groove 213 is formed in the fin structure 201.

[0075] In this embodiment, the process for removing the source / drain doped region 203 exposed by the first groove 210 includes a pulsed plasma etching process. The parameter range of the pulsed plasma etching process is as follows: power of 400W to 1400W; bias voltage of 100V to 1000V; duty cycle of 5% to 60%; gas of halogen-containing gas, C x H y O zand one or more of hydrogen, and one or more of helium or argon, the halogen-containing gas includes chlorine-containing gas or bromine-containing gas, the x is a natural number greater than or equal to 1, the value of the y is a natural number greater than or equal to 1, and the z is a natural number greater than or equal to 0.

[0076] The pulsed plasma etching process can form a second groove 213 with a large depth-to-width ratio and good dimensional accuracy under the adjustment of bias voltage and duty cycle parameters.

[0077] Please refer to Figure 16 , Figure 16 For Figure 15 Based on the structural diagram, the fin structure 201 exposed by the second groove 213 is removed until the surface of the substrate 200 is exposed, and a fourth groove 214 is formed in the fin structure 201.

[0078] The process of removing the fin structure 201 exposed by the second groove 213 includes a pulse plasma etching process, wherein the parameter range of the pulse plasma etching process is: power of 400W to 1400W; bias voltage of 100V to 1000V; duty cycle of 5% to 60%; gas containing halogen gas, C x H y O z and one or more of hydrogen, and one or more of helium or argon, the halogen-containing gas includes chlorine-containing gas or bromine-containing gas, the x is a natural number greater than or equal to 1, the value of the y is a natural number greater than or equal to 1, and the z is a natural number greater than or equal to 0.

[0079] The pulsed plasma etching process can form the fourth groove 214 with a large depth-to-width ratio and good dimensional accuracy under the adjustment of bias voltage and duty cycle parameters.

[0080] Please refer to Figure 17 and Figure 18 , Figure 17 For Figure 16 The structural diagram of the foundation, Figure 18 For Figure 13 As shown in the structural diagram based on FIG, a first isolation structure 215 is formed in the first groove 210 and the second groove 213.

[0081] The first isolation structure 215 is used to isolate the fin structure 201 to prevent ions in the fin structure 201 from diffusing and affecting the performance of the semiconductor structure.

[0082] In this embodiment, a first isolation structure 215 is further formed in the fourth groove 214. The first isolation structure 215 is also located in the fourth groove 214, that is, the first isolation structure 215 completely cuts off and isolates the fin structure 201, so that the first isolation structure 215 has a better isolation capability for the fin structure 201.

[0083] In this embodiment, while forming the first isolation structure 215 in the first groove 210 and the second groove 213, a blocking structure 216 is also formed in the third groove 212. The blocking structure 216 and the first isolation structure 215 are formed simultaneously, thereby saving process steps.

[0084] The blocking structure 216 is used to cut off and isolate the initial metal layer 206 to meet design requirements.

[0085] The material of the blocking structure 216 includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbide, silicon carbide nitride, and silicon oxycarbide nitride.

[0086] The material of the first isolation structure 215 includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbide, silicon carbide nitride, and silicon oxycarbide nitride.

[0087] The method for forming the isolation structure 216 and the first isolation structure 215 includes: forming an isolation material layer (not shown) in the first groove 210, the second groove 213, the third groove 212, the fourth groove 214 and on the second insulating layer 205; flattening the isolation material layer until the surface of the second insulating layer 205 is exposed to form the isolation structure 216 and the first isolation structure 215.

[0088] The formation method first forms an initial metal layer 206 on the source and drain doped regions 203, then forms a mask structure 207 having a plurality of first openings 208 therein. The first openings 208 extend in the same direction as the arrangement of the fin structures 201. A portion of the initial metal layer 206 is removed to form a first groove 210. The source and drain doped regions 103 are then removed to form a second groove 213. A first isolation structure 215 is then formed within the first groove 210 and the second groove 213. By first forming the initial metal layer 206 and then removing a portion of the initial metal layer 206 to form the first isolation structure 215, the process of forming the first isolation structure 215 does not damage the gate structure 204, thereby improving the performance of the semiconductor structure.

[0089] Accordingly, the embodiment of the present invention further provides a semiconductor structure, please continue to refer to Figure 18and Figure 19 ,include:

[0090] A substrate 200 having a plurality of parallel fin structures 201 and a first insulating layer thereon, wherein the first insulating layer is located on the sidewalls of the fin structures 201 and a top plane of the first insulating layer is lower than the top surface of the fin structures 201;

[0091] A gate structure 204 located on a substrate 200, source / drain doped regions 203 located within the fin structure 201 on both sides of the gate structure 204, and a second insulating layer 205, wherein the source / drain doped regions 203 have first ions, the gate structure 204 spans the fin structure 201, and the gate structure 204 is located within the second insulating layer 205, wherein a top plane of the second insulating layer 205 is higher than a top plane of the gate structure 204;

[0092] A metal layer located within the second insulating layer 205 , wherein the extension direction of the metal layer is the same as the arrangement direction of the fin structure 201 , and the metal layer is located on the source / drain doped region 203 and electrically connected to the source / drain doped region 203 ;

[0093] The first isolation structure 215 is located in the second insulating layer 205 and the fin structure 201 . The extension direction of the first isolation structure 215 is the same as the arrangement direction of the fin structure 201 . The first isolation structure 215 is located between adjacent metal layers.

[0094] In this embodiment, the first isolation structure 215 is located on the substrate 200 and isolates the fin structure 201 .

[0095] In this embodiment, the first ions include N-type ions or P-type ions.

[0096] In this embodiment, the present invention further includes a blocking structure 216 located in the second insulating layer 205 . The extending direction of the blocking structure 216 is the same as the extending direction of the fin structure 201 . The blocking structure 216 is located between adjacent metal layers.

[0097] In this embodiment, the material of the blocking structure 216 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbide nitride.

[0098] In this embodiment, the material of the first isolation structure 215 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0099] Figures 19 to 20It is a schematic cross-sectional structural diagram of a semiconductor structure forming process in another embodiment of the present invention.

[0100] Please refer to Figure 19 , Figure 19 For Figure 15 Based on the structural schematic diagram, after the second groove 213 is formed in the fin structure 201, the fin structure 201 exposed by the second groove 213 is ion-implanted with a second ion, and the conductivity type of the second ion is opposite to the conductivity type of the first ion in the source-drain doping area 203, thereby forming a second isolation structure 301 in the fin structure 201.

[0101] The second ions include N-type ions or P-type ions.

[0102] The second isolation structure 301 is formed by ion implantation of second ions into the fin structure 201. The conductivity type of the second ions is opposite to that of the first ions in the source / drain doped regions 203. During operation, the second ions have an opposite conductivity type to that of the ions in the fin structure 201, thereby acting as an inversion barrier. This allows the first isolation structure 302 and the second isolation structure 301 to provide improved isolation for the fin structure 201. Furthermore, the implantation of the second ions can repair lattice defects in the fin structure 201 caused by the removal of the source / drain doped regions 203, thereby improving the performance of the fin structure 201.

[0103] Please refer to Figure 20 , Figure 20 For Figure 19 Schematic diagram of the structure based on the present invention, a first isolation structure 302 is formed in the first groove 210 and the second groove 213.

[0104] The formation process of the first isolation structure 302 can be referred to Figure 17 and Figure 18 , I will not go into details here.

[0105] Accordingly, the embodiment of the present invention further provides a semiconductor structure, please continue to refer to Figure 20 ,include:

[0106] A substrate 200 having a plurality of parallel fin structures 201 and a first insulating layer thereon, wherein the first insulating layer is located on the sidewalls of the fin structures 201 and a top plane of the first insulating layer is lower than the top surface of the fin structures 201;

[0107] A gate structure 204 located on a substrate 200, source / drain doped regions 203 located within the fin structure 201 on both sides of the gate structure 204, and a second insulating layer 205, wherein the source / drain doped regions 203 have first ions, the gate structure 204 spans the fin structure 201, and the gate structure 204 is located within the second insulating layer 205, wherein a top plane of the second insulating layer 205 is higher than a top plane of the gate structure 204;

[0108] A metal layer located within the second insulating layer 205 , wherein the extension direction of the metal layer is the same as the arrangement direction of the fin structure 201 , and the metal layer is located on the source / drain doped region 203 and electrically connected to the source / drain doped region 203 ;

[0109] The first isolation structure 302 is located in the second insulating layer 205 and the fin structure 201 . The extension direction of the first isolation structure 302 is the same as the arrangement direction of the fin structure 201 . The first isolation structure 302 is located between adjacent metal layers.

[0110] In this embodiment, it also includes: a second isolation structure 301 located in the fin structure 201, the first isolation structure 302 is located on the second isolation structure 301, and the second isolation structure 301 has second ions, and the conductivity type of the second ions is opposite to the conductivity type of the first ions.

[0111] The material of the second isolation structure 301 is the material of the fin structure 201 doped with the second ions. In this embodiment, the material of the second isolation structure 301 is silicon doped with the second ions.

[0112] In this embodiment, the first ions include N-type ions or P-type ions; the second ions include N-type ions or P-type ions.

[0113] In this embodiment, the present invention further includes: a blocking structure located in the second insulating layer 205 , wherein the extending direction of the blocking structure is the same as the extending direction of the fin structure 201 , and the blocking structure is located between adjacent metal layers.

[0114] In this embodiment, the material of the blocking structure includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbide nitride.

[0115] In this embodiment, the material of the first isolation structure 302 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0116] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: a substrate having a plurality of fin structures arranged in parallel and a first insulating layer, wherein the first insulating layer is located on sidewalls of the fin structures and a top plane of the first insulating layer is lower than a top surface of the fin structures; A gate structure located on the substrate and source / drain doped regions in the fin structures on both sides of the gate structure, wherein the source / drain doped regions have first ions, and the gate structure spans the fin structures; a second insulating layer located on the substrate, wherein the gate structure is located in the second insulating layer, and a top plane of the second insulating layer is higher than a top plane of the gate structure; a metal layer located within the second insulating layer, wherein the extension direction of the metal layer is the same as the arrangement direction of the fin structure, and the metal layer is located on the source-drain doped region and electrically connected to the source-drain doped region; a first isolation structure located within the second insulating layer and the fin structure, wherein an extension direction of the first isolation structure is the same as an arrangement direction of the fin structure, and the first isolation structure is located between adjacent metal layers; A second isolation structure is located in the substrate, wherein the second isolation structure has second ions, the conductivity type of the second ions is opposite to the conductivity type of the first ions, the extension direction of the second isolation structure is the same as the arrangement direction of the fin structure, the first isolation structure is located on the second isolation structure, and the first isolation structure and the second isolation structure are located between adjacent metal layers.

2. The semiconductor structure according to claim 1, wherein The material of the second isolation structure is a fin structure material having second ions.

3. The semiconductor structure according to claim 1, wherein: The first ions include N-type ions or P-type ions; the second ions include N-type ions or P-type ions.

4. The semiconductor structure according to claim 1, wherein: Also includes: A barrier structure is located in the second insulating layer, wherein an extending direction of the barrier structure is the same as an extending direction of the fin structure, and the barrier structure is located between adjacent metal layers.

5. The semiconductor structure according to claim 4, wherein: The material of the blocking structure includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

6. The semiconductor structure according to claim 1, wherein The material of the first isolation structure includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

7. The semiconductor structure according to claim 1, wherein: Also includes: An etch stop layer is located within the second insulating layer, wherein a bottom surface of the etch stop layer is coplanar with a top surface of the gate structure.

8. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate having a plurality of fin structures arranged in parallel and a first insulating layer, wherein the first insulating layer is located on the sidewalls of the fin structures and a top plane of the first insulating layer is lower than a top surface of the fin structures; A gate structure, source / drain doped regions within the fin structures on both sides of the gate structure, and a second insulating layer are formed on the substrate, wherein the source / drain doped regions have first ions, the gate structure spans the fin structure, the gate structure is located within the second insulating layer, and a top plane of the second insulating layer is higher than a top plane of the gate structure; forming an initial metal layer in the second insulating layer, wherein the extension direction of the initial metal layer is the same as the arrangement direction of the fin structure, and the initial metal layer is located on the source and drain doped regions and is electrically connected to the source and drain doped regions; forming a mask structure on a substrate, wherein the mask structure has a plurality of first openings, wherein the first openings extend in the same direction as the arrangement direction of the fin structures, and the first openings expose a portion of the surface of the initial metal layer; Using the mask structure as a mask, removing the initial metal layer exposed by the first opening, forming a first groove in the second insulating layer, wherein the first groove exposes the surface of the source and drain doped regions; removing the source and drain doped regions exposed by the first groove until the surface of the fin structure is exposed, and forming a second groove in the fin structure; A first isolation structure is formed in the first groove and the second groove.

9. The method for forming a semiconductor structure according to claim 8, wherein: The mask structure further has a plurality of second openings therein. The extension direction of the second openings is the same as the extension direction of the fin structures. The second openings expose portions of the second insulating layer surface and the initial metal layer surface between adjacent fin structures.

10. The method for forming a semiconductor structure according to claim 9, wherein: Using the mask structure as a mask, while removing the initial metal layer exposed by the first opening, the method also includes: removing the initial metal layer exposed by the second opening, and forming a third groove in the second insulating layer.

11. The method for forming a semiconductor structure according to claim 10, wherein: While forming the first isolation structure in the first groove and the second groove, the method further includes: forming a blocking structure in the third groove.

12. The method for forming a semiconductor structure according to claim 11, wherein: The material of the blocking structure includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

13. The method for forming a semiconductor structure according to claim 8, wherein: After forming the second groove in the fin structure and before forming the first isolation structure in the first groove and the second groove, it also includes: removing the fin structure exposed by the second groove until the substrate surface is exposed, and forming a fourth groove in the fin structure; the first isolation structure is also located in the fourth groove.

14. The method for forming a semiconductor structure according to claim 13, wherein: The material of the first isolation structure includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

15. The method for forming a semiconductor structure according to claim 13, wherein: The process of removing the fin structure exposed by the second groove includes a pulse plasma etching process, wherein the parameter range of the pulse plasma etching process is: power of 400W~1400W; bias voltage of 100V~1000V; duty cycle of 5%~60%; gas containing halogen gas, C x H y O z and one or more of hydrogen, and one or more of helium or argon, the halogen-containing gas includes chlorine-containing gas or bromine-containing gas, the x is a natural number greater than or equal to 1, the value of the y is a natural number greater than or equal to 1, and the z is a natural number greater than or equal to 0.

16. The method for forming a semiconductor structure according to claim 8, wherein: After forming the second groove in the fin structure and before forming the first isolation structure in the first groove and the second groove, it also includes: ion implantation of second ions into the fin structure exposed by the second groove, where the conductivity type of the second ions is opposite to the conductivity type of the first ions in the source and drain doping regions, to form a second isolation structure in the fin structure.

17. The method for forming a semiconductor structure according to claim 16, wherein: The first ions include N-type ions or P-type ions; the second ions include N-type ions or P-type ions.

18. The method for forming a semiconductor structure according to claim 8, wherein: The process of removing the source and drain doped regions exposed by the first groove includes a pulsed plasma etching process, wherein the parameter range of the pulsed plasma etching process is: power of 400W to 1400W; bias voltage of 100V to 1000V; duty cycle of 5% to 60%; gas of halogen-containing gas, C x H y O z and one or more of hydrogen, and one or more of helium or argon, the halogen-containing gas includes chlorine-containing gas or bromine-containing gas, the x is a natural number greater than or equal to 1, the value of the y is a natural number greater than or equal to 1, and the z is a natural number greater than or equal to 0.

19. The method for forming a semiconductor structure according to claim 8, wherein: The process of removing the initial metal layer exposed by the first opening includes a wet etching process or a dry etching process; the gas of the dry etching process includes carbon fluorine gas, and one or more of oxygen and hydrogen; the etching solution of the wet etching process includes an acidic solution, and the acidic solution includes sulfuric acid, hydrochloric acid or hydrofluoric acid.

20. The method for forming a semiconductor structure according to claim 8, wherein: The mask structure includes a liner layer, an anti-reflection layer on the liner layer, and a photoresist layer on the anti-reflection layer.

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