Vertical cavity surface emitting laser and method of forming the same

Abstract

A vertical cavity surface emitting laser and a method of forming the same, the laser comprising: an active region, an inner trench, an outer trench, a first injection region. The active region comprises a first mirror, an active region, a second mirror, an etch stop layer. The first mirror is formed on a substrate. The active region is formed on the first mirror. The second mirror is formed on the active region. The etch stop layer with an aperture is formed between the active region and the second mirror. The inner trench surrounds the active region in a top view. The outer trench is formed beside the inner trench, and the first injection region is formed under the inner trench. The present application can improve the uniformity of the inner trench depth by forming an additional inner trench on the etch stop layer.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a semiconductor structure, and particularly relate to a vertical-cavity surface-emitting laser (VCSEL) and a method of forming a vertical-cavity surface-emitting laser. BACKGROUND

[0002] A vertical-cavity surface-emitting laser is a semiconductor laser diode that emits a laser beam in a direction perpendicular to its surface. The vertical-cavity surface-emitting laser can be tested in a production process. The vertical-cavity surface-emitting laser is widely used in various fields, such as fiber-optic communications and biometric identification.

[0003] A mesa of an active region of a vertical-cavity surface-emitting laser can be isolated by a trench. The power performance of the vertical-cavity surface-emitting laser can be affected by the trench depth. However, the trench depth varies in a 6-inch or larger wafer. In addition, an implant region can be formed to isolate an emitter region of the vertical-cavity surface-emitting laser. However, if the implant region is too deep, a higher photoresist and a wider photoresist pitch are required. Therefore, the chip design can be limited.

[0004] Although the existing vertical-cavity surface-emitting laser is sufficient for the original purpose, it is not satisfactory in all aspects and needs to be improved. In particular, uniformity and chip design margin need to be improved. SUMMARY

[0005] Embodiments of the present disclosure provide a vertical-cavity surface-emitting laser, comprising: an active region, an inner trench, an outer trench, and a first implant region. The active region comprises a first mirror, an active region, a second mirror, and an etch stop layer. The first mirror is formed on a substrate. The active region is formed on the first mirror. The second mirror is formed on the active region. The etch stop layer with an aperture is formed between the active region and the second mirror. The inner trench surrounds the active region in a top view. The outer trench is formed beside the inner trench. The first implant region is formed under the inner trench.

[0006] Embodiments of the present disclosure also provide a vertical-cavity surface-emitting laser, comprising: an active region sandwiched between a first mirror and a second mirror. An etch stop layer is formed between the active region and the second mirror. An outer trench is formed through the second mirror, the etch stop layer, the active region, and the first mirror. An inner trench is formed through the second mirror. A first implant region is formed under the inner trench. A second implant region is formed under the outer trench. A bottom surface of the inner trench is flush with the etch stop layer.

[0007] Embodiments of the present application also provide a method of forming a vertical cavity surface emitting laser. The method includes forming a first mirror over a substrate. The method also includes forming an active region over the first mirror. The method also includes forming a second mirror over the active region. The method also includes forming an outer trench in the first mirror, the active region, and the second mirror. The method also includes oxidizing a spacer layer between the active region and the second mirror to form an etch stop layer. The method also includes forming an inner trench stopping over the etch stop layer. The method also includes forming a first injection region under the inner trench. BRIEF DESCRIPTION OF DRAWINGS

[0008] Embodiments of the present application will be described below with reference to the accompanying drawings. It should be noted that various features are not drawn to scale and are only intended to illustrate the example. In fact, the size of the elements can be enlarged or reduced to clearly show the technical features of the embodiments of the present application.

[0009] Figure 1 A top view of a vertical cavity surface emitting laser is shown according to some embodiments.

[0010] Figures 2A-2E Cross-sectional views of stages of forming a vertical cavity surface emitting laser are shown according to some embodiments.

[0011] Figures 3A-3B Cross-sectional views of stages of forming a vertical cavity surface emitting laser are shown according to some embodiments.

[0012] Figure 4 A top view of a vertical cavity surface emitting laser is shown according to some embodiments.

[0013] Figure 5 A cross-sectional view of a vertical cavity surface emitting laser is shown according to some embodiments.

[0014] LIST OF ABBREVIATIONS

[0015] 10a, 10b, 10c, 10d: vertical cavity surface emitting laser

[0016] 102: substrate

[0017] 104a: first mirror

[0018] 104b: second mirror

[0019] 106a: first semiconductor layer

[0020] 106b: third semiconductor layer

[0021] 108a: second semiconductor layer

[0022] 108b: fourth semiconductor layer

[0023] 110a: first spacer

[0024] 110b: Second spacer

[0025] 110b-1, 110b-2, 110b-3: Second spacer layer

[0026] 112: Active Area

[0027] 114: Quantum Well

[0028] 116: Quantum Well Barrier

[0029] 118: Cap layer

[0030] 120: Contact electrode

[0031] 122: First dielectric layer

[0032] 124: External groove

[0033] 126: Etching Stop Layer

[0034] 126-1, 126-2, 126-3: Oxide layer

[0035] 127: Central Current Hole

[0036] 128: Inner groove

[0037] 129: Active Zone

[0038] 130: Second dielectric layer

[0039] 132: Injection Area

[0040] 132a: First injection region

[0041] 132b: Second injection region

[0042] 132c: Third injection region

[0043] 134: Third dielectric layer

[0044] 136: Metal layer

[0045] 138: Opening

[0046] 140: Back electrode

[0047] D1, D2: Depth

[0048] 2-2: Line Detailed Implementation

[0049] The following detailed description is presented to provide a thorough understanding of the application. Numbered names are used for components and arrangements thereof as a convenience in order to provide a clear and concise description of embodiments of the present application. However, the application can be practiced without these specific detailed numbers. In some instances, components or arrangements can be shown in diagram form in order to more particularly illustrate and describe an implementation of the present application. These are exemplary methods of the application. Unless otherwise specified, "a" or "an" shall mean "one or more", "at least one", "one or more than one" or "one or more but not all" for any term so used, not only "one" or "an". The use of the terms first, second, etc. does not imply any particular ordering, but these terms are used to distinguish one from another. Furthermore, the use of the terms top, bottom, over, under and the like are used for clarity in only a planar direction of the figures, not necessarily in a specific orientation in use or operation, and are understood to be relative terms and not absolute terms.

[0050] Also, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", and the like, can be used herein for ease of describing one element or feature to

[0051] As used herein, the terms "about", "approximately", "substantially" and the like are understood not to be absolute terms, but are understood to allow a reasonable amount of variation based on experimental error, measurement techniques, variability in the manufacture of reagents and raw materials, interpretation of results by those skilled in the art, and the like. As used herein, the terms "about", "approximately", "substantially" and the like generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or 3%, or 2%, or 1%, or 0.5%. It should be noted that quantities provided in the specification are approximate, and that the meaning of "about", "approximately", "substantially" and the like is implied where not specifically stated.

[0052] Although the steps in some embodiments are presented in a particular order, the steps can be performed in other logical orders. Some of the steps described can be replaced or omitted, and other steps can be performed before, during, and / or after the steps described in the embodiments. The semiconductor structures in the embodiments can include additional features. Some of the features can be replaced or omitted in different embodiments.

[0053] Embodiments of the present application provide a vertical cavity surface emitting laser. An oxidation layer can be used as an etch stop layer to form an additional trench around an active region of the vertical cavity surface emitting laser with well-controlled depth. Thus, depth uniformity of the additional trench can be improved. Furthermore, an implant region is formed under the additional trench to vertically isolate the device. Since lower implant energy is needed, the thickness and pitch of photoresist used to form the implant region can be reduced. Thus, design margin can be improved.

[0054] Figure 1 A top view of a vertical cavity surface emitting laser 10a is illustrated in accordance with some embodiments. Figures 2A-2E Cross-sectional views of stages of forming a vertical cavity surface emitting laser 10a are illustrated in accordance with some embodiments. Figures 2A-2E A cross-sectional view along line 2-2 is illustrated. Figure 1

[0055] In accordance with some embodiments, as illustrated in Figure 2A A substrate 102 is provided, as illustrated inThe substrate 102 can include a semiconductor substrate. The substrate 102 can include a III-V semiconductor, such as GaAs, GaN, AlGaN, AlN, AlGaAs, InP, InAlAs, InGaAs, or a combination thereof. In some embodiments, the substrate 102 includes GaAs.

[0056] Next, in accordance with some embodiments, as illustrated in Figure 2AAs shown in FIG. 1, a first mirror 104a is formed over a substrate 102. The first mirror 104a includes first semiconductor layers 106a and second semiconductor layers 108a. In some embodiments, the first mirror 104a is an alternating stack of first semiconductor layers 106a and second semiconductor layers 108a over the substrate 102. The first semiconductor layers 106a and the second semiconductor layers 108a can be used in pairs. The first semiconductor layers 106a and the second semiconductor layers 108a can include a III-V semiconductor, such as GaAs, AlGaAs, AlAs, GaN, AlGaN, A1N, InP, InAlAs, InGaAs, or a combination thereof. The first semiconductor layers 106a and the second semiconductor layers 108a can be made of different materials with different indices of refraction. In some embodiments, the first semiconductor layers 106a and the second semiconductor layers 108a have a first conductivity type. In some embodiments, the first conductivity type is N-type. The first mirror 104a can be referred to as a distributed Bragg reflector (DBR) of the first conductivity type. The thickness of each layer of the first semiconductor layers 106a and the second semiconductor layers 108a depends on the center wavelength of the laser light generated in the vertical cavity surface emitting laser. The first semiconductor layers 106a and the second semiconductor layers 108a can be formed by a low pressure chemical vapor deposition (LPCVD) process, an epitaxial growth process, other available processes, or a combination thereof. The epitaxial growth process can include molecular-beam epitaxy (MBE), metalorganic chemical vapor deposition (MOCVD), or vapor phase epitaxy (VPE).

[0057] It should be noted that although Figure 2A Although only two pairs of the first semiconductor layers 106a and the second semiconductor layers 108a are shown in FIG. 1, the total number of pairs of the first semiconductor layers 106a and the second semiconductor layers 108a is not limited thereto and depends on the design requirements.

[0058] Next, according to some embodiments, as shown in FIG. 2, a second mirror 104b is formed over the first mirror 104a. The second mirror 104b includes first semiconductor layers 106b and second semiconductor layers 108b. In some embodiments, the second mirror 104b is an alternating stack of first semiconductor layers 106b and second semiconductor layers 108b over the first mirror 104a. The first semiconductor layers 106b and the second semiconductor layers 108b can be used in pairs. The first semiconductor layers 106b and the second semiconductor layers 108b can include a III-V semiconductor, such as GaAs, AlGaAs, AlAs, GaN, AlGaN, A1N, InP, InAlAs, InGaAs, or a combination thereof. The first semiconductor layers 106b and the second semiconductor layers 108b can be made of different materials with different indices of refraction. In some embodiments, the first semiconductor layers 106b and the second semiconductor layers 108b have a second conductivity type. In some embodiments, the second conductivity type is P-type. The second mirror 104b can be referred to as a distributed Bragg reflector (DBR) of the second conductivity type. The thickness of each layer of the first semiconductor layers 106b and the second semiconductor layers 108b depends on the center wavelength of the laser light generated in the vertical cavity surface emitting laser. The first semiconductor layers 106b and the second semiconductor layers 108b can be formed by a low pressure chemical vapor deposition (LPCVD) process, an epitaxial growth process, other available processes, or a combination thereof. The epitaxial growth process can include molecular-beam epitaxy (MBE), metalorganic chemical vapor deposition (MOCVD), or vapor phase epitaxy (VPE). Figure 2AAs shown in FIG. 1, a first spacer 110a is formed over the first mirror 104a. The first spacer 110a can include a III-V semiconductor with a graded refractive index. The first spacer 110a can include a III-V semiconductor such as GaAs, AlGaAs, AlAs, GaN, AlGaN, AlN, InP, InAlAs, InGaAs, or a combination thereof. In some embodiments, the first spacer 110a has a first conductivity type. In some embodiments, the first conductivity type is N-type. The first spacer 110a can have a lower doping concentration than the first semiconductor layer 106a and the second semiconductor layer 108a. The first spacer 110a can be a multi-layer III-V semiconductor with different dopants and doping concentrations. The first spacer 110a can be formed by a low pressure chemical vapor deposition process, an epitaxial growth process, other available processes, or a combination thereof. The epitaxial growth process can include molecular beam epitaxy, metal organic chemical vapor deposition, or vapor phase epitaxy.

[0059] Thereafter, according to some embodiments, as shown in FIG. 1, a first spacer 110a is formed over the first mirror 104a. The first spacer 110a can include a III-V semiconductor with a graded refractive index. The first spacer 110a can include a III-V semiconductor such as GaAs, AlGaAs, AlAs, GaN, AlGaN, AlN, InP, InAlAs, InGaAs, or a combination thereof. In some embodiments, the first spacer 110a has a first conductivity type. In some embodiments, the first conductivity type is N-type. The first spacer 110a can have a lower doping concentration than the first semiconductor layer 106a and the second semiconductor layer 108a. The first spacer 110a can be a multi-layer III-V semiconductor with different dopants and doping concentrations. The first spacer 110a can be formed by a low pressure chemical vapor deposition process, an epitaxial growth process, other available processes, or a combination thereof. The epitaxial growth process can include molecular beam epitaxy, metal organic chemical vapor deposition, or vapor phase epitaxy. Figure 2A Thereafter, according to some embodiments, as shown in FIG. 1, a first spacer 110a is formed over the first mirror 104a. The first spacer 110a can include a III-V semiconductor with a graded refractive index. The first spacer 110a can include a III-V semiconductor such as GaAs, AlGaAs, AlAs, GaN, AlGaN, AlN, InP, InAlAs, InGaAs, or a combination thereof. In some embodiments, the first spacer 110a has a first conductivity type. In some embodiments, the first conductivity type is N-type. The first spacer 110a can have a lower doping concentration than the first semiconductor layer 106a and the second semiconductor layer 108a. The first spacer 110a can be a multi-layer III-V semiconductor with different dopants and doping concentrations. The first spacer 110a can be formed by a low pressure chemical vapor deposition process, an epitaxial growth process, other available processes, or a combination thereof. The epitaxial growth process can include molecular beam epitaxy, metal organic chemical vapor deposition, or vapor phase epitaxy.

[0060] Figure 2A ​As illustrated, a second spacer 110b is formed over the active region 112. The second spacer 110b may comprise a III-V semiconductor with a gradient refractive index. The second spacer 110b may comprise a III-V semiconductor, such as GaAs, AlGaAs, AlAs, GaN, AlGaN, AlN, InP, InAlAs, InGaAs, or a combination thereof. In some embodiments, the second spacer 110b comprises AlGaAs. In some embodiments, the second spacer 110b has a second conductivity type. The second conductivity type may be the opposite of the first conductivity type. In some embodiments, the second conductivity type is P-type. The doping concentration of the second spacer 110b may be less than the doping concentration of the film layer in the subsequently formed second mirror. The process for forming the second spacer 110b may be similar to or the same as the process for forming the first spacer 110a described above, and will not be repeated here for the sake of brevity.

[0061] Next, according to some embodiments, such as Figure 2A As illustrated, a second mirror 104b is formed on the second spacer 110b. The second mirror 104b may include a third semiconductor layer 106b and a fourth semiconductor layer 108b, alternately stacked on the second spacer 110b. The third semiconductor layer 106b and the fourth semiconductor layer 108b may include III-V group semiconductors, such as GaAs, AlGaAs, AlAs, GaN, AlGaN, AlN, InP, InAlAs, InGaAs, or combinations thereof. The third semiconductor layer 106b and the fourth semiconductor layer 108b may be made of different materials with different refractive indices. In some embodiments, the third semiconductor layer 106b and the fourth semiconductor layer 108b have a second conductivity type. In some embodiments, the second conductivity type is P-type. The second mirror 104b may be referred to as a distributed Bragg reflector of the second conductivity type. Light generated by the active region 112 can be reflected by the first mirror 104a and the second mirror 104b. Light can resonate between the first mirror 104a and the second mirror 104b. The process used to form the second mirror 104b may be similar to or the same as the process used to form the first mirror 104a, and will not be repeated here for the sake of brevity.

[0062] It should be noted that, although Figure 2A The diagram shows two third semiconductor layers 106b and three fourth semiconductor layers 108b. The number of third semiconductor layers 106b and fourth semiconductor layers 108b is not limited to this and depends on the design requirements.

[0063] Next, according to some embodiments, such as Figure 2AAs shown in the middle, a cap layer 118 is formed over the second mirror 104b. The cap layer 118 can include a III-V semiconductor, such as GaAs, AlGaAs, AlAs, GaN, AlGaN, AlN, InP, InAlAs, InGaAs, or a combination thereof. In some embodiments, the cap layer 118 has a second conductivity type. In some embodiments, the second conductivity type is P-type. In some embodiments, the cap layer 118 is highly doped, which facilitates the formation of an ohmic contact between the cap layer 118 and a subsequently formed contact electrode. The cap layer 118 can be formed by a low pressure chemical vapor deposition process, an epitaxial growth process, other available processes, or a combination thereof. The epitaxial growth process can include molecular beam epitaxy, metal organic chemical vapor deposition, or vapor phase epitaxy.

[0064] Next, according to some embodiments, as shown in the middle, Figure 2A As shown in the middle, a contact electrode 120 is formed over the cap layer 118. The contact electrode 120 can include Au, Ti, Al, Pd, Pt, Cu, W, other suitable metals, alloys thereof, or a combination thereof. The contact electrode material can first be formed over the cap layer 118 by physical vapor deposition (PVD) (e.g., e-beam evaporation, resistive heating evaporation, electroplating, sputtering), chemical vapor deposition (CVD), atomic layer deposition (ALD), other suitable methods, or a combination thereof. In some embodiments, the contact electrode material is formed by e-beam evaporation. The electrode material is then patterned by a photolithography and etching process, forming the contact electrode 120.

[0065] Next, according to some embodiments, as shown in the middle, Figure 2A As shown in the middle, a first dielectric layer 122 is conformally formed over the cap layer 118 and the contact electrode 120. As shown in the middle, Figure 2A As shown in the middle, the first dielectric layer 122 is over the second mirror 104b. The first dielectric layer 122 can be made of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride (SiCN), silicon oxide carbonitride (SiOCN), or a combination thereof. In some embodiments, the first dielectric layer 122 includes silicon nitride. The first dielectric layer 122 can be formed by a deposition process. The deposition process can include a chemical vapor deposition process (e.g., low pressure chemical vapor deposition, plasma- enhanced chemical vapor deposition, sub-atmospheric chemical vapor deposition, or flowable chemical vapor deposition), an atomic layer deposition process, other available methods, or a combination thereof. In some embodiments, the first dielectric layer 122 is deposited by a plasma-enhanced chemical vapor deposition process.

[0066] Next, according to some embodiments, as shown in Figure 2A The outer trench 124 is formed through the first dielectric layer 122, the cap layer 118, the second mirror 104b, the second spacer 110b, the active region 112, the first spacer 110a, and stops in the first mirror 104a. The patterning and etching processes can be performed to form the outer trench 124. The patterning processes can include photoresist coating, soft bake, mask alignment, exposure, post-exposure bake, photoresist development, cleaning, and drying. The etching process can be a dry etching process or a wet etching process. In some embodiments, the etching process is a reactive ion etching (RIE) using inductively coupled plasma (ICP) as the etchant. In some embodiments, as shown in Figure 1 The first mirror 104a is exposed from the outer trench 124. A portion of the first mirror 104a can be consumed by the etching process when forming the outer trench 124. In some embodiments, the bottom surface of the outer trench 124 is below the bottom surface of the active region 112. In some embodiments, the bottom surface of the outer trench 124 is in the first mirror 104a.

[0067] As shown in Figure 2A and Figure 1 The outer trench 124 includes trench segments separated from each other in the top view. It should be noted that although Figure 2B six trench segments of the outer trench 124 are shown, the number of trench segments of the outer trench 124 is not limited thereto and depends on the design requirements.

[0068] Next, as shown in Figure 2B the top portion of the second spacer 110b is oxidized to form an oxide layer 126 on the top surface of the second spacer layer 110b. The oxide layer 126 can be an etch stop layer 126 for a subsequent etching process. The top portion of the second spacer 110b can be an Al-doped layer with a high Al composition. In some embodiments, the top portion of the second spacer 110b has an Al composition of about 97% to about 100%. The Al composition can affect the oxidation rate. It is desirable to keep the oxidation rate stable. If the Al composition is too high, the Al can diffuse too fast and it can be difficult to control the position of the oxide layer 126. If the Al composition is too low, the oxidation time can be too long. In some embodiments, the top portion of the second spacer 110b is made of AlGaAs. The high Al composition portion of the second spacer 110b can be oxidized to form the oxide layer 126. In some embodiments, the oxide layer 126 includes an oxide. In some embodiments, the oxide layer 126 includes Al2O3. In some embodiments, the oxide layer 126 is formed by a tube furnace oxidation process.

[0069] like Figure 2C As illustrated, only a portion of the upper surface of the second spacer 110b is oxidized. In some embodiments, a central current aperture 127 is formed to separate the etch stop layer 126. The central current aperture 127 may restrict the current from the contact electrode 120 through the underlying active region 112 and the first mirror 104a.

[0070] Next, according to some embodiments, such as Figure 2C As illustrated, the inner trench 128 is formed through the first dielectric layer 122, the capping layer 118, and the second mirror 104b. Patterning and etching processes can be performed to form the inner trench 128. The process for forming the inner trench 128 can be similar to or the same as the process for forming the outer trench 124 described above, and will not be repeated here for the sake of brevity. In some embodiments, the inner trench 128 is formed by reactive ion etching using inductively coupled plasma as the etchant. In some embodiments, such as Figure 2C As illustrated, an inner trench 128 is formed using an etching process, stopping above an etch stop layer 126. Therefore, the etch stop layer 126 is exposed from the inner trench 128. In some embodiments, the bottom surface of the inner trench 128 is substantially flush with the top surface of the etch stop layer 126. Therefore, by forming the etch stop layer 126, the depth of the inner trench 128 can be well controlled. Figure 2C As shown in the illustration, the depth of the inner groove 128 is less than the depth of the outer groove 124. Furthermore, as... Figure 1 As shown in the illustration, the inner groove 128 and the outer groove 124 are separated from each other.

[0071] like Figure 2C and Figure 2D As illustrated in the top view, a platform 129, including a capping layer 118, a contact electrode 120, and a second mirror 104b, is surrounded by an inner trench 128 above the central current aperture 127. The platform 129 can be surrounded by the inner trench 128. The first mirror 104a, the active region 112, the central current aperture 127, and the second mirror 104b surrounded by the inner trench 128 can be referred to as the active region 129 or emitter region 129 of a vertical-cavity surface-emitting laser. The inner trench 128 provides lateral isolation for the active region 129.

[0072] Subsequently, according to some embodiments, such as Figure 2D As illustrated, a second dielectric layer 130 is compliantly formed on the capping layer 118, the contact electrode 120, the first dielectric layer 122, and the sidewalls and bottom surfaces of the inner trench 128 and the outer trench 124. Figure 2DAs illustrated, a second dielectric layer 130 is formed within the inner trench 128 and the outer trench 124. The processes and materials used to form the second dielectric layer 130 may be similar to or the same as those used to form the first dielectric layer 122, and will not be repeated here for the sake of brevity. In some embodiments, the second dielectric layer 130 and the first dielectric layer 122 are made of the same materials. In some embodiments, the second dielectric layer 130 comprises silicon nitride.

[0073] Next, according to some embodiments, such as Figure 2D As shown in the diagram, injection region 132 is formed using an injection process. (See diagram for reference.) Figure 2D As illustrated, the implantation region 132 includes a first implantation region 132a below the inner trench 128, a second implantation region 132b below the outer trench 124, and a third implantation region 132c between the inner trench 128 and the outer trench 124. In some embodiments, the first implantation region 132a, the second implantation region 132b, and the third implantation region 132c are formed using the same implantation process. In some embodiments, the implantation region 132 is doped with helium or boron, which will determine the implantation depth.

[0074] like Figure 2D As illustrated, the bottom surface of the first injection region 132a is below the bottom surface of the first spacer 110a. Furthermore, the bottom surface of the first injection region 132a is below the top surface of the first mirror 104a. The bottom surface of the second injection region 132b is also below the top surface of the first mirror 104a. For chip isolation, the first injection region 132a may penetrate the active region 112. In some embodiments, the bottom surface of the first injection region 132a is below the bottom surface of the active region 112.

[0075] When the inner trench 128 is formed through the active region 112, a non-radiative recombination center can be generated near the inner trench 128. The first injection region 132a can vertically isolate the active region 129 to reduce the influence of the non-radiative recombination center. Since the inner trench 128 is annular in the top view, the injection energy required to form the first injection region 132a under the inner trench 128 can be reduced. With lower injection energy, high-resistivity materials can be obtained, and leakage current can be reduced. The injection process can also be more easily controlled. Figure 2DAs illustrated, the first injection region 132a has a depth of approximately 0.60 μm to approximately 0.70 μm. In some embodiments, the first injection region 132a has a depth of approximately 0.65 μm. In some embodiments, the first injection region 132a has a depth of approximately half the wavelength of the laser generated in a vertical-cavity surface-emitting laser. If the first injection region 132a is too deep, the thickness and spacing of the photoresist may be too large, potentially limiting chip design. If the first injection region 132a is too shallow, the isolation to avoid the influence of non-radiative coincidence centers may be insufficient.

[0076] In some embodiments, such as Figure 2D As illustrated, since the first injection region 132a and the second injection region 132b are formed using the same mask, the depth D1 of the first injection region 132a and the depth D2 of the second injection region 132b are substantially the same. Furthermore, since the injection is performed at an angle, the sidewalls of the inner trench 128 and the outer trench 124 are also injected. Therefore, a third injection region 132c is formed between the inner trench 128 and the outer trench 124. In some embodiments, the injection has an angle of inclination ranging from about 6° to about 8°. In some embodiments, the angle of inclination is about 7°. The injection energy or power source can be increased to achieve the desired injection depth. Figure 2E As illustrated, an injection region 132 may also be formed in the capping layer 118 outside the outer trench 124 and in a portion of the second mirror 104b.

[0077] Subsequently, according to some embodiments, such as Figure 2E As illustrated, a third dielectric layer 134 is compliantly formed on the capping layer 118, the contact electrode 120, and the sidewalls and bottom surface of the inner trench 128 and the outer trench 124. Figure 2E As illustrated, a third dielectric layer 134 is formed within the inner trench 128 and the outer trench 124. The processes and materials used to form the third dielectric layer 134 may be similar to or the same as those used to form the first dielectric layer 122 and the second dielectric layer 130, and will not be repeated here for the sake of brevity. In some embodiments, the third dielectric layer 134, the second dielectric layer 130, and the first dielectric layer 122 are made of the same materials. In some embodiments, the third dielectric layer 134 comprises silicon nitride.

[0078] Next, an opening (not individually shown) is formed over the contact electrode 120 through the third dielectric layer 134, the second dielectric layer 130, and the first dielectric layer 122. The opening exposes the contact electrode 120. The opening can be formed in the third dielectric layer 134, the second dielectric layer 130, and the first dielectric layer 122 by photolithography (e.g., photoresist coating, soft baking, exposure, post-exposure baking, development, other available processes, or combinations thereof), etching (e.g., wet etching, dry etching, other available processes, or combinations thereof), other available processes, or combinations thereof.

[0079] Next, as Figure 2E As illustrated, a metal layer 136 is compliantly formed on the sidewalls and bottom surface of the capping layer 118, the opening, the inner trench 128, and the outer trench 124. In some embodiments, the metal layer 136 directly contacts the contact electrode 120. The metal layer 136 may comprise a conductive material such as Au, Ti, Al, Pd, Pt, Cu, W, other suitable metals, alloys thereof, or combinations thereof. The metal layer material may be formed by physical vapor deposition (e.g., electroplating, electron beam evaporation, resistance heating evaporation, sputtering), chemical vapor deposition, atomic layer deposition, other suitable methods, or combinations thereof. In some embodiments, the metal layer 136 is formed by electroplating. Subsequently, the metal layer material is patterned by photolithography and etching processes to form an opening 138 on the central current aperture 127 in the etch stop layer 126. The opening 138 in the metal layer 136 may be directly above the central current aperture 127 in the etch stop layer 126.

[0080] In some embodiments, such as Figure 2E As illustrated, the inner trench 128 is filled with a metal layer 136. In some embodiments, the metal layer 136 substantially fills the inner trench 128. Filling the inner trench 128 with the metal layer 136 can improve heat dissipation of the vertical cavity surface-emitting laser.

[0081] Next, the substrate 102 is thinned to a target thickness (not shown). In some embodiments, the substrate 102 is thinned using a grinding and polishing process. A thinner substrate 102 reduces thermal resistance. A thinner wafer improves thermal conductivity and heat dissipation.

[0082] Next, according to some embodiments, such as Figures 3A-3BAs illustrated, a back electrode 140 is formed on the back side of the substrate 102. The back electrode 140 may be a metal layer. The back electrode 140 may include Au, Ti, Al, Pd, Pt, Cu, W, other suitable metals, alloys thereof, or combinations thereof. The back electrode 140 on the back side of the substrate 102 may be formed by physical vapor deposition (e.g., electron beam evaporation, resistance heating evaporation, electroplating, sputtering), chemical vapor deposition, atomic layer deposition, other suitable methods, or combinations thereof. In some embodiments, the back electrode 140 is formed by electron beam evaporation.

[0083] Many changes and / or modifications can be made to the embodiments of the present invention. Figure 3A Cross-sectional views of the various stages of forming a vertical-cavity surface-emitting laser 10b are illustrated according to some other embodiments. Some processes or components are the same as or similar to those in the above embodiments, and therefore these processes and components are not repeated here. Unlike the above embodiments, according to some other embodiments, such as... Figure 3A The illustration shows the use of the same mask for the injection process and etching of the inner trench 128.

[0084] like Figure 3B As illustrated, after the inner trench 128 is formed, an injection process is performed using the same mask. Therefore, the injection region 132 includes only a first injection region 132a formed under the inner trench 128 and a third injection region 132c on the sidewall of the inner trench 128. In some embodiments, the third injection region 132c is formed in a portion of the second mirror 104b between the inner trench 128 and the outer trench 124. Because the bottom surface of the first injection region 132a is lower than the active region 112, the active region 129 is isolated from the external region by the inner trench 128 and the first injection region 132a. Therefore, one photomask can be saved, and the manufacturing cost and time required can be reduced.

[0085] As described above, the inner trench 128 stops above the oxide etch stop layer 126. This allows for good control of the depth of the inner trench 128 and improves uniformity within the wafer. Figure 4 As illustrated, the inner trench 128 can be filled with a metal layer 136, which improves heat dissipation. Through the inner trench 128, the implantation region 132 can be formed with lower implantation energy, improving chip design margin and reducing manufacturing costs and time. The same mask can be used for the implantation process and to form the inner trench, further reducing manufacturing costs and time.

[0086] Many changes and / or modifications can be made to the embodiments of the present invention. Figure 4A top view illustrating the formation of a vertical-cavity surface-emitting laser 10c is shown according to some other embodiments. Some processes or elements are the same as or similar to those in the above embodiments, and therefore these processes and elements are not repeated here. Unlike the above embodiments, according to some other embodiments, such as... Figure 5 As shown in the drawing, the outer groove 124 is annular in the top view.

[0087] The shape of the outer trench 124 in the top view is not limited as long as the inner trench 128 and the first injection region 132a provide isolation between the active region 129 and the outer region. The outer trench 124 can be annular or any other shape that can separate the active region 129 from the outer region, provided that sufficient oxidation is available to form the etch stop layer of the inner trench 128.

[0088] As described above, the inner trench 128 stops above the oxide etch stop layer 126. This allows for good control of the depth of the inner trench 128 and improves uniformity within the wafer. The inner trench 128 can be filled with a metal layer 136, which improves heat dissipation. Through the inner trench 128, the implantation region 132 can be formed with lower implantation energy, improving chip design margin and reducing manufacturing costs and time. The shape of the outer trench 124 in the top view is not limited, depending on the chip design requirements.

[0089] Many changes and / or modifications can be made to the embodiments of the present invention. Figure 5 A cross-sectional view of forming a vertical-cavity surface-emitting laser 10d is illustrated according to some other embodiments. Some processes or components are the same as or similar to those in the above embodiments, and therefore these processes and components are not repeated here. Unlike the above embodiments, according to some other embodiments, such as... Figure 5 As illustrated, the second spacer 110b may be a multilayer III-V semiconductor layer with different elemental compositions.

[0090] In some embodiments, the second spacer 110b may be a multilayer III-V semiconductor layer with different Al compositions. For example... Figure 5 As illustrated, the second spacer 110b comprises multiple spacer layers 110b-1, 110b-2, and 110b-3, each with different Al compositions. The oxidation rate of subsequent oxidation processes can depend on the Al composition of the second spacer layers. A higher Al composition in the second spacer layers may result in a higher oxidation rate. Figure 5 As illustrated, after the oxidation process, oxide layers 126-1, 126-2, and 126-3 are formed in the second spacer layers 110b-1, 110b-2, and 110b-3, respectively. Figure 5As illustrated, the central current pores formed in the second spacer layers 110b-1, 110b-2, and 110b-3 have different widths. The second spacer layers 110b-1, 110b-2, and 110b-3, which have a higher Al content, may have narrower central current pores.

[0091] It should be noted that, although Figure 5 The diagram illustrates three oxide layers: 126-1, 126-2, and 126-3. The number of oxide layers is not limited by this and depends on the process requirements. Furthermore, although... Figure 5 As illustrated, the uppermost oxide layer 126-3 has the narrowest central current pore, but the width of the central current pores in oxide layers 126-1, 126-2, and 126-3 is not limited to this. Each oxide layer 126-1, 126-2, and 126-3 may have the narrowest central current pore.

[0092] Next, according to some embodiments, such as ​ As illustrated, an inner trench 128 is formed using an etching process, and the etching process stops at one of the oxide layers 126-1, 126-2, and 126-3. Oxide layers 126-1, 126-2, and 126-3 can also be referred to as etching stop layers 126-1, 126-2, and 126-3.

[0093] It should be noted that although the etching process used to form the inner trench 128 stops at the uppermost oxide layer 126-3, the oxide layer to which the etching process stops is not limited to this. Furthermore, although the etching process used to form the inner trench 128 stops at the oxide layer 126-3 with the narrowest central current aperture, the oxide layer to which the etching process stops is not limited to this. The etching process used to form the inner trench 128 may stop at any of the oxide layers 126-1, 126-2, and 126-3 formed in the second spacer layer 110b.

[0094] As described above, the inner trench 128 stops above the oxide etch stop layer 126. This allows for good control of the depth of the inner trench 128 and improves uniformity within the wafer. The inner trench 128 can be filled with a metal layer 136, which improves heat dissipation. Through the inner trench 128, the implantation region 132 can be formed with lower implantation energy, improving chip design margin and reducing manufacturing costs and time. The second spacer 110b can be a multilayer with different Al compositions, resulting in oxide layers with different central current aperture widths. The etching process used to form the inner trench 128 can stop at any oxide layer.

[0095] As described above, embodiments of the present invention provide a vertical-cavity surface-emitting laser (VCSEL) and a method for forming a VCSEL. By forming additional inner trenches above the etch stop layer, the uniformity of the inner trench depth can be improved. Furthermore, the injection depth in the injection region below the inner trenches can be reduced, resulting in improved design margins due to lower photoresistivity. Filling the inner trenches with a metal layer also improves heat dissipation. The same mask can be used to form both the inner trenches and the injection region, reducing manufacturing costs and time.

[0096] Multiple vertical-cavity surface-emitting lasers as described in the embodiments of the present invention can be integrated into a vertical-cavity surface-emitting laser array. In some embodiments, the array may be an addressable array. In some embodiments, the vertical-cavity surface-emitting laser array described in the embodiments of the present invention may be used as a light source in a light-emitting system (e.g., automotive light-emitting system).

[0097] It should be noted that while some benefits and effects are described in the above embodiments, not all embodiments are required to achieve all benefits and effects.

[0098] The foregoing description outlines the feature components of numerous embodiments, enabling those skilled in the art to better understand the embodiments of the present invention from various aspects. Those skilled in the art will understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art will also understand that these equivalent structures do not depart from the inventive spirit and scope of the embodiments of the present invention. Various changes, substitutions, or modifications can be made to the embodiments of the present invention without departing from the inventive spirit and scope of the embodiments; therefore, the scope of protection of the present invention shall be determined by the scope of the appended claims. Furthermore, although the present invention has been disclosed above with reference to several preferred embodiments, it is not intended to limit the invention, and not all advantages have been described in detail herein.

Claims

1. A vertical-cavity surface-emitting laser, characterized in that, include: One active area, including: The first mirror is formed on a substrate; An active region is formed on the first mirror; A second mirror is formed on the active region; and An etch stop layer having a pore is formed between the active region and the second mirror; An inner groove surrounds the active region and extends through the second mirror; An outer trench is formed next to the inner trench, passing through the second mirror, the etch stop layer, the active region, and the first mirror; and A first injection region is formed beneath the inner trench.

2. The vertical-cavity surface-emitting laser according to claim 1, characterized in that, One bottom surface of the inner trench is flush with one top surface of the etching stop layer.

3. The vertical-cavity surface-emitting laser according to claim 1, characterized in that, The etching stop layer comprises oxides.

4. The vertical-cavity surface-emitting laser according to claim 1, characterized in that, The bottom surface of the injection area, located directly below the inner groove, is located below the top surface of the first mirror.

5. The vertical-cavity surface-emitting laser according to claim 1, characterized in that, One bottom surface of the outer groove is located below one bottom surface of the active region.

6. The vertical-cavity surface-emitting laser according to claim 1, characterized in that, Also includes: A second injection region is formed beneath the outer trench.

7. The vertical-cavity surface-emitting laser according to claim 1, characterized in that, Also includes: A third injection region is formed in the second mirror between the inner groove and the outer groove.

8. A vertical-cavity surface-emitting laser, characterized in that, include: An active area, sandwiched between a first mirror and a second mirror; An etch stop layer having a pore is formed between the active region and the second mirror; An outer trench extends through the second mirror, the etching stop layer, the active region, and the first mirror; An inner groove passes through the second mirror; A first injection region is formed beneath the inner trench; and A second injection region is formed beneath the outer trench; The bottom surface of the inner trench is located above the etching stop layer.

9. The vertical-cavity surface-emitting laser according to claim 8, characterized in that, The depth of the inner groove is less than the depth of the outer groove.

10. The vertical-cavity surface-emitting laser according to claim 8, characterized in that, The depth of the first injection region is the same as the depth of the second injection region.

11. The vertical-cavity surface-emitting laser according to claim 8, characterized in that, The inner groove and the outer groove are separated from each other.

12. The vertical-cavity surface-emitting laser according to claim 8, characterized in that, The outer trench comprises trench sections that are separated from each other.

13. The vertical-cavity surface-emitting laser according to claim 8, characterized in that, The outer groove is annular.

14. A method for forming a vertical-cavity surface-emitting laser, characterized in that, include: A first mirror is formed on a substrate; An active region is formed on the first mirror; A second mirror is formed over the active region; An outer groove is formed in the first mirror, the active region, and the second mirror; Oxidize a spacer layer between the active region and the second mirror to form an etch stop layer with a pore; An inner trench is formed and stops above the etching stop layer; as well as A first injection region is formed below the inner trench.

15. The method for forming a vertical-cavity surface-emitting laser according to claim 14, characterized in that, One bottom surface of the outer groove is located within the first mirror.

16. The method for forming a vertical-cavity surface-emitting laser according to claim 14, characterized in that, Also includes: A second injection region is formed below the outer trench; The depth of the first injection region is different from the depth of the second injection region.

17. The method for forming a vertical-cavity surface-emitting laser according to claim 14, characterized in that, Also includes: A metal layer is formed in the inner trench and the outer trench; The inner trench is filled with the metal layer.

18. The method for forming a vertical-cavity surface-emitting laser according to claim 14, characterized in that, Also includes: Before forming the outer trench, a first dielectric layer is deposited on the second mirror; After the inner trench is formed, a second dielectric layer is compliantly deposited in the outer trench and the inner trench; as well as After the first injection region is formed, a third dielectric layer is compliantly deposited in the outer trench and the inner trench.

19. The method for forming a vertical-cavity surface-emitting laser according to claim 18, characterized in that, The first dielectric layer, the second dielectric layer, and the third dielectric layer are made of the same material.

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