Segmented linear function generator, corresponding generator, amplifier, method and computer program product

Abstract

The present disclosure relates to a segmented linear function generation electronic circuit, a corresponding generator, an amplifier, a method and a computer program product. The cell comprises a first MOS transistor pair and a second MOS transistor pair. Each MOS transistor of the first MOS transistor pair and the second MOS transistor pair has a drain coupled to a respective common input node. Each MOS transistor of the first MOS transistor pair and the second MOS transistor pair comprises a diode-connected MOS transistor and a latching MOS transistor. The latching MOS transistors of the first MOS transistor pair and the second MOS transistor pair have cross-coupled gates and drains. The sources of the diode-connected MOS transistors from the first MOS transistor pair and the second MOS transistor pair are coupled to a first current output common node to output current to a first current sink circuit. The sources of the latching MOS transistors of the first MOS transistor pair and the second MOS transistor pair are coupled to a second current output common node to output current to a second current sink circuit.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to Italian Patent Application No. 102021000007340 filed on March 25, 2021, the contents of which are incorporated herein in its entirety to the maximum extent permitted by law. TECHNICAL FIELD

[0003] Embodiments of the present disclosure relate to a solution for the generation of a piecewise linear current transfer function.

[0004] Embodiments of the present disclosure specifically relate to a module performing a current limiter function and / or a current maximization function. BACKGROUND

[0005] Some applications require a current piecewise linear (PWL) transfer function. One possible case is a current limiter.

[0006] Figure 1 An example of a known current limiter 10 is shown, comprising a NMOS transistor M l1 having a respective threshold voltage VTH1, the NMOS transistor M 11 receives an input voltage on its gate through a series resistor R1, and the drain of the NMOS transistor M 11 is coupled to a voltage source VDD, the source of the NMOS transistor M 11 is coupled to ground through a sense resistor R2. The gate of a second NMOS transistor M 11 having a respective threshold voltage VTH2 is coupled to the source of the NMOS transistor M 12 , the drain of the second NMOS transistor M 11 is coupled to the gate of M 12 , and the emitter of the second NMOS transistor M 11 is coupled to ground GND. A current I 12 flows through the NMOS transistor M L . As long as the voltage across the sense resistor R2 is less than V 11 (gate-source voltage of the transistor M GS2 ), only the NMOS transistor M 12 is on. In this case, the output current is fixed by the resistor R2. Whenever the load current I 11 reaches a value such that the voltage across the sense resistor R2 exceeds the threshold voltage VTH2 of the transistor M L , the second NMOS transistor M 12 is also turned on, and the current I 12 flows through the second NMOS transistor M D .Start conducting. In this case, the output current is fixed by VGS2 / R2.

[0007] In such a circuit, the precision of the current limiting function depends on several uncertain variables VTH1, VTH2, R1, R2 (with a precision of ±20%), which is not sufficient for many applications.

[0008] Therefore, there is a need in the art for a solution that overcomes one or more of the aforementioned drawbacks. SUMMARY

[0009] According to one or more embodiments, an electronic circuit for generating a piecewise linear current transfer function is proposed. Embodiments also relate to a corresponding method of correlation and to a corresponding computer program product of correlation, which is loadable in the memory of at least one computer and comprises software code portions for performing the steps of the method when the product is run on the computer.

[0010] As used herein, reference to such a computer program product is intended to be equivalent to a reference to a computer-readable medium containing instructions for controlling a computer system to coordinate the performance of the method. The reference to "at least one computer" is obviously intended to highlight the possibility of implementing the present disclosure in a distributed / modular way.

[0011] In one embodiment, an electronic circuit for generating a piecewise linear current transfer function comprises at least one latch circuit module or unit comprising a first pair of MOS transistors and a second pair of MOS transistors, the drains of each of the first and second pairs of MOS transistors being coupled to a respective common input node; each of the first and second pairs of MOS transistors comprising a diode-connected MOS transistor and a latching MOS transistor, the respective gates of the latching MOS transistors of the two pairs of transistors being coupled to the drain of the other latching MOS transistor; the sources of the diode-connected MOS transistors of the first and second pairs of MOS transistors being coupled to a respective first output common node, and the sources of the latching MOS transistors of the first and second pairs of MOS transistors being coupled to a respective second output common node.

[0012] In variant embodiments, the latch unit is coupled to a first collection circuit coupled to collect the current at the first output common node, in particular implementing an input current maximization function between the currents applied at the input nodes of said latch unit, and / or to a second collection circuit coupled to collect the current at the second output node, in particular implementing a current minimization function between the currents applied at the input nodes of said latch unit.

[0013] In variant embodiments, the latching unit is coupled to one or more current supply circuits configured to supply a first current to the common input node of one of the pairs of transistors and / or to supply a second current to the common input node of the other pair of transistors.

[0014] In variant embodiments, the first input current in the electronic circuit is variable, in particular a current ramp, and the second current is a constant reference current.

[0015] In variant embodiments, the MOS transistors are NMOS.

[0016] In variant embodiments, the MOS transistors are PMOS.

[0017] In variant embodiments, the latching unit is configured to make the input current and the output current flow in opposite directions with respect to its input node and output node.

[0018] In variant embodiments, the latching unit is configured to make the input current and the output current enter or exit its input node and output node.

[0019] In variant embodiments, the MOS transistors are of the same size.

[0020] In variant embodiments, the unit receives as input a current ramp and a constant value current corresponding to a negative offset value, and comprises a first collection circuit coupled to collect the current at a first output common node to implement an input current maximization function between the currents applied at the input nodes of the latching unit; a subtraction block in which the current constant value is subtracted from the output of the latching unit, the latching unit being configured to perform the maximization function, the circuit further comprising a multiplier block configured to multiply the output of the multiplier by an integer in order to implement the current ramp with a negative offset generator.

[0021] The solution described herein also relates to a segmented linear generator comprising one or more of the circuits according to the above.

[0022] The solution described herein also relates to a class AB amplifier having a differential structure, comprising respective positive and negative input stages coupled to a level shifter, wherein the positive and negative input stages are coupled to respective circuits.

[0023] The solution described herein also relates to a method for generating a segmented linear transfer function, comprising using one or more of the circuits for generating a segmented linear current transfer function of any of the preceding embodiments.

[0024] In a variant embodiment, a method comprises defining a piecewise linear current characteristic as a sequence of functions nested one into another; configuring a first circuit for generating a piecewise linear current transfer function implementing the innermost nested function; and configuring subsequent circuits of the cascade for generating piecewise linear current transfer functions to perform the subsequent nested functions.

[0025] The solution described herein also relates to a computer program product, which can be loaded into the memory of at least one processor and comprises software code portions for implementing the method according to the aforementioned method. BRIEF DESCRIPTION OF DRAWINGS

[0026] Embodiments of the present disclosure will now be described with reference to the accompanying drawings, which are provided by way of non-limiting example only, in which:

[0027] Figure 1 has been described above;

[0028] Figures 2A-2B An embodiment of the circuit described herein is shown;

[0029] Figures 3A-3C A characteristic diagram of the current of the circuit of Figure 2A , Figure 2B is shown;

[0030] Figure 4 An embodiment of the circuit described herein is shown;

[0031] Figures 5A-5C A characteristic diagram of the current of the circuit of the aforementioned embodiment is shown;

[0032] Figures 6A-6B An embodiment of the circuit described herein is shown;

[0033] Figures 7A-7B An embodiment of the circuit described herein is shown;

[0034] Figures 8A-8B An embodiment of the circuit described herein is shown;

[0035] Figures 9A-9B An embodiment of the circuit described herein is shown;

[0036] Figures 10A-10C A characteristic diagram of the current of the circuit of Figure 9A , Figure 9B is shown;

[0037] Figures 11A-11B An embodiment of the circuit described herein is shown;

[0038] Figures 12A-12C An embodiment of the circuit described herein is shown;Figure 11A ,a plot of current of the circuit of Figure 11B

[0039] Figures 13A-13B An embodiment of the circuit described herein is shown;

[0040] Figures 14A-14C A plot of current of the circuit of Figure 13A ,a plot of current of the circuit of Figure 13B

[0041] Figures 15A-15B An embodiment of the circuit described herein is shown;

[0042] Figures 16A-16B A plot of current of the circuit of Figure 15A ,a plot of current of the circuit of Figure 15B

[0043] Figure 17 A schematic circuit of a class AB amplifier is shown;

[0044] Figure 18 A schematic circuit of a class AB amplifier implemented by the circuit described herein is shown;

[0045] Figures 19A-19B A schematic plot of a piecewise linear function implemented by the circuit described herein is shown;

[0046] Figure 20A and Figure 20B A plot showing details of a piecewise linear function representing Figures 19A-19B DETAILED DESCRIPTION

[0047] In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments. One or more embodiments can be practiced without one or more of the specific details or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail in order to avoid obscuring aspects of the embodiments.

[0048] Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0049] The headings provided herein are merely for convenience and do not interpret the scope or meaning of the embodiments.

[0050] Reference has been made to Figures 1-4 ​The described figures parts, elements or components are denoted by the same reference signs as previously used in these figures; the description of these previously described elements will not be repeated below in order not to burden the detailed description of the invention with too much.

[0051] Figure 2A A circuit schematic of an embodiment of the electronic circuit 20 for generating a piecewise linear current transfer function is shown, which comprises a latch unit 21. Such a latch unit 21 comprises a first pair of NMOS transistors M1, M2, the drain electrodes of which are coupled together at a respective input common node, denoted by VI, which reference sign also denotes the voltage formed at this node for simplicity of representation. Figure 2A An embodiment of the circuit 20 without the current collection circuit coupled to its output is denoted by the dashed line. Then, the latch unit 21 comprises a second pair of NMOS transistors M3, M4, which are similarly coupled, the drain electrodes being coupled together in a second input common node, denoted by V2. The NMOS transistors M1 and M4 are diode-connected (i.e. their drain is coupled to their gate). The respective gates of the NMOS transistors M2 and M3 are coupled to the drain of the other NMOS, and are also the input nodes VI and V2. Figure 2A The source electrodes of the transistors M1, M2, M3, M4 are coupled together, and then to ground GND. However, this is merely because for simplicity of representation in Figure 2A The unit 21 is not shown coupled to the current collection circuit in Figure 2B The actual configuration of the source nodes is shown, in which the collection circuit 50 is coupled to the outputs of the latch unit 21.

[0052] Two respective current generators 221 and 222 are coupled between the voltage source VDD and the input common nodes VI and V2 for injecting respective first and second input currents II and I2 into the drain electrodes of the two pairs of transistors M1, M2 and M3, M4, respectively. The current generators 221 and 222 represent a current supply circuit, which can supply for example a constant current or a current ramp. Such a current supply circuit can also be implemented by other electronic circuits for generating a piecewise linear current transfer function at its output, the output of which is coupled to Figure 2A The circuit 20 of

[0053] Thus, the NMOS transistors M1 and M4 can be defined as the diode-connected transistors of this pair of transistors, while the NMOS M2 and M3 are denoted as the latch transistors of the two pairs of transistors.

[0054] It is thus considered thatFigure 2A In the electronic circuit 20, when the current I1 = I2, if the NMOS transistors M1, M2, M3, and M4 are of the same size (i.e., these NMOS transistors are identical, for example, having matched MOS parameters), then the first input current I1 is evenly divided between the NMOS transistors M1 and M2 of the first transistor pair, and is used for the drain current I. D I D1 =I D2 =I1 / 2 and I D3 =I D4 =I2 / 2.

[0055] As described above, V1 (the voltage on the drain electrode of the first transistor pair, i.e., the voltage on the input node of the transistor pair) and V2 (the voltage on the drain electrode of the second transistor pair, i.e., the voltage on the input node of the second transistor pair) are at the equilibrium point, i.e., when the current I1 = I2 and V1 = V2, the NMOS transistors M1, M2, M3 and M4 are each in the saturation region.

[0056] It is emphasized that Figure 2A The circuit shown is a schematic representation of the circuit described herein to aid in understanding its working principle, while embodiments of the circuit are described in... Figure 2B As shown in the image. Figure 2A The circuit operates as a current comparator that compares the first input current I1 and the second input current I2; however, in order to read the comparison result, the output current I... D1 I D2 I D3 I D4 It is necessary to avoid merging them in the grounding node, such as Figure 2A As shown. (Described below) Figure 2B In some embodiments, these currents are grouped accordingly (i.e., I0). D6 =I D1 +I D4 and I D5 =I D2 +I D3 ).

[0057] Therefore, in Figure 2B The text shows the relationship with... Figure 2A An equivalent circuit, wherein circuit 50 is coupled to electronic circuit 20, circuit 50 is merely an example of a current harvesting circuit or a current collection circuit, collecting currents from the first transistor pair and the second transistor pair (i.e., from the sources of NMOS M1 and M2 of the first transistor pair and from the sources of NMOS M3 and M4), respectively, the sources of NMOS M1 and M2 and the sources of NMOS M3 and M4 of the first transistor pair are in... Figure 2AThe NMOS transistor M5 is simply collected by a first diode connection of its drain to the sources of the NMOS transistors M2, M3 from which a first current I5 flows to ground, the first diode connection of the source of the NMOS transistor M5 being coupled to ground. A second diode connection of the collector NMOS transistor M6 is similarly coupled to the sources of the NMOS transistors Ml, M4. The voltages on the drains of the transistors M5 and M6 are denoted V3 and V4, respectively, as described above, Figure 2B The circuit of Figure 2A is equivalent at equilibrium because V3 = V4 and the transistors M5 and M6 are collecting the currents from M 1-4 and M 2-3 .

[0058] Although Figure 2B the circuit shows the circuit 20 comprising the latch unit 21 in use, and in particular shows the outputs of the latch unit 21, i.e. the sources of the diode-connected MOS transistors Ml, M4 of the first and second transistor pairs are coupled to respective current maximization output common nodes V4, and the sources of the latching MOS transistors M2, M3 of the first and second transistor pairs are coupled to respective current minimization output common nodes V3, for simplicity the equivalence of the circuit of Figure 2A is assumed to be considered.

[0059] Thus, considering small signal currents applied on the input nodes Vl and V2 and the input impedance Z IN of the circuit 20 (i.e. the cross-coupled latch) is:

[0060] Z IN →∞

[0061] Thus, applying a small signal current the circuit reacts with an ideal output :

[0062]

[0063] This means that if a small current difference is applied between the latch input nodes Vl and V2, the latch saturates the output carrying only the first current II on the NMOS Ml or M2 of the first transistor pair, and similarly for the second current I2.

[0064] Thus, the equilibrium point discussed previously is an unstable equilibrium point.

[0065] It can be summarized that if II > I2, then:

[0066] I1→ M1 and I2→ M3

[0067] If, on the other hand, I1→ I2, then:

[0068] I1→ M2 and I2→ M4

[0069] In other words, the larger current will always flow through the diode- connected devices M1, M4.

[0070] Thus, if the current flowing through the diode-connected devices M1, M4 and the current flowing in the latch stage M2, M3 are collected, this corresponds to performing the mathematical operation

[0071] I6 = max(I1, I2)

[0072] I5 = min(I1, I2)

[0073] where I5 and I6 are a first output current and a second output current from the output nodes V3 and V4, which can for example flow through the circuit 50 of Figure 2B Thus, the node V4, through which the current I6 flows, is the current maximization output common node, while the node V3, through which the current I5 flows, is the current minimization output common node V3, which also serves as a current limiter.

[0074] In this view, the collection circuit 50 comprises a first collection circuit, transistor M6, coupled to collect the current I6 at the first output common node V4, in particular to implement an input current maximization function between the currents applied at the input nodes; and / or a second collection circuit, transistor M5, coupled to collect the current I5 as a second output node V3, in particular to implement a current minimization function between the currents applied at the input nodes. The current collection circuit 50 comprises both the first and the second collection circuits, however, it is clear that if the circuit 20 is configured to implement only a current maximization function or a current minimization function, i.e.

[0075] I6 = max(I1, I2)

[0076] I5 = min(I1, I2)

[0077] then there can be only the first collection circuit (transistor M6) or the second collection circuit (transistor M5).

[0078] Moreover, such first and second collection circuits can correspond to the inputs of other circuits of the electronic circuit 20, which are used to generate a piecewise linear current transfer function.

[0079] In the same way, the electronic circuit 20 for generating a piecewise linear current transfer function can be coupled to one or more current supply circuits configured to provide a first current II to the common input node of one transistor pair between the first transistor pair Ml, M2 and the second transistor pair M3, M4 and / or a second current I2 to the common input node of the other transistor pair. Such current supply circuits as mentioned can be implemented by current generators or other circuits similar to the electronic circuit for generating a piecewise linear current transfer function 20.

[0080] As shown in the diagram in Figures 3A-3C , the input currents II, I2 are shown as a function of the first input current II. Here and in the following figures, all diagrams showing currents are plotted with the first input current on the abscissa. The first input current II is a current ramp, the second current I2 is constant Figure 3A ).

[0081] Figures 3A-3C Concerning the static condition. Here, the slope of the first input current II is one, because the first input current II Figure 3A ) is a quantity on the x- and y-axis.

[0082] On the contrary, in Figures 10A-10C and Figures 12A-12C , the slope can be different from the value one, because they contain inputs different from the first input current II, for example I4. In an embodiment, the circuit 20 can use a variable first input current II, for example a current ramp, while the second input current I2 can be a constant reference current. The first output current I5 Figure 3B ) is limited to the minimum of the input currents II and I2, i.e. it follows the first input current II and then remains at the constant reference value of I2 when II exceeds I2. Thus, on the first output current I5, the circuit 20 operates as a current limiter, i.e. it performs the function of min(II, I2). Of course, the latching unit 21 can receive at its inputs any type of current, i.e. with any type of temporal variation, performing its current maximization or minimization operation according to the selected output.

[0083] On the other hand, the second output current I6 Figure 3C ) follows the maximum of the input currents II and I2, i.e. it follows I2 and then the increase of the first current II when II exceeds I2. Thus, on the second output current I6, the circuit 20 operates as a current maximizer, i.e. it performs the function of max(II, I2).

[0084] In Figure 4 , the latching unit 21 uses here denoted as I IN1 , IIN2 the first and second input currents and the output currents I O1 , I O2 corresponding to the currents I5, I6 output from the two NMOS transistor pairs of the latch 21 IN1 , I IN2 corresponding to I1 and I2 applied by the current generator in Figure 2A , 2B . The currents I IN1 , I IN2 , I O1 , I O2 behave as in Figures 5A-5C and correspond to the behavior of Figures 3A-3C .

[0085] The latch unit 21 described previously can be seen as a basic logic block having as input currents the first input current I IN1 and the second input current I IN2 and as output currents I O1 , I O2 , the output currents I O1 , I O2 provide the minimum or maximum of the input currents. If one of the input currents is a constant current, for example I IN2 , then the output current I O1 obtained on the source of the latching transistor implements a current limiter.

[0086] In the variant embodiment 31 shown in Figure 6A , the latch unit or basic logic block can have outputs on the same side as the inputs, i.e. a basic logic block in which the input currents and the output currents both enter (or double exit) their respective input or output nodes (i.e. they have the same direction with respect to their respective input or output nodes), contrary to the latch unit 21 in which the input currents and the output currents have opposite directions, i.e. the input currents enter the block and the output currents exit the block.

[0087] This facilitates cascading a series of basic units.

[0088] As shown in detail in the corresponding circuit in Figure 6B , the sources of the diode-connected NMOS M1, M4 are coupled in the same node coupled to M6, while the sources of the latching NMOS M1, M4 are coupled in the same node coupled to M5, on which nodes the output currents I O1 and I O2 are respectively collected. In the case of Figure 6B , M5 is coupled to the NMOS M8 to form the output first output current I O1of a current mirror, while M5 is coupled to a corresponding NMOS M7 to form an output second output current I O2 of a current mirror. Figures 6A-6B The cell 31 still behaves as described in Figures 3A-3C the figures.

[0089] Figures 7A-7B and Figures 8A-8B The same blocks 21 and 31 are shown implemented with PMOS transistors instead of NMOS transistors. The structure of the latch is the same, i.e. the latch PMOS couples one drain to the other gate, and the input current I IN1 , I IN2 leaves its drain to ground or to a current generator coupled to ground, while at the source of this transistor pair is the output current I O1 , I O2 , the output current I O1 , I O2 flows from a PMOS digital voltage source VSS.

[0090] Figure 9A An embodiment is shown in which two latch cells or basic blocks 21a, 21b are cascaded to implement a nested function.

[0091] In this case, the output of the first latch 21a with NMOS transistors receives the input current I IN1 , I IN2 . The first output current I O1 is provided as the first input current I IN3 of the second latch 21b, while the second input current of the second latch 21b is the current I IN4 , the output current I O4 is collected, which results in:

[0092] I O4 = max(I IN3 , I IN4 ) = max(min(I IN1 , I IN2 ), I IN4 )

[0093] The behavior of the corresponding currents is shown in Figures 10A-10C , Figures 10A-10C also shows the current as a function of the first current I IN1 . In particular, Figure 10A shows the behavior of the input currents I IN1 and I IN2 corresponding to the input currents I IN1 and I IN2 of Figure 5A , while the output current IIN4 It also increases with a slope, similar to I. IN1 . Figure 10C The result shown is the current I O4 Follow current I O1 until I O4 Exceeding the reference input current I IN2 A constant value, then follow I IN4 The value of , as indicated by the equation above, results in Figure 10C The piecewise linearity of .

[0094] Figure 11A An embodiment using two switching units (i.e., NMOS latch 31 and PMOS latch 31p) is shown. This limits the use of large rails (V). dd -V ss V dd and V ss Indicates the positive and negative power supply voltage.

[0095] The output current I of the PMOS latch 31p O1 Input I is coupled to NMOS latch 31 IN3 Another input I IN4 The corresponding current is fed to the NMOS latch 31.

[0096] Output I O4 yes:

[0097] I O4 =max(I IN3 I IN4 ) = max(min(I IM1 I IN2 ), I IN4 )

[0098] This is Figure 9A The circuits are the same, in Figures 10A-10C As shown in the diagram.

[0099] Output current I O4 It can be a function f(I) IN1 ) and current reference slope (CRR)I IN4 =m·I IN1 -I Q The comparison results between them, where m is the slope and I... Q It is the value of the y-intercept, that is, for I. IN1 =0. In this case, I O1 =I IN3 =f(I IN1 ).

[0100] These currents are Figures 12A-12C As shown in the diagram.Figure 12B It shows that it is limited to a constant value I. IN3 Current ramp (I) IN1 The function f(I) IN1 ).

[0101] To generate a current reference ramp (CRR) with a negative offset, i.e., when I IN =0I O A value less than 0 may indicate difficulty, as the current flow in the latch is unidirectional.

[0102] Since this ramp must be used only for positive current comparisons, it can be generated as follows:

[0103] For I IN >I q =I Q / m, I O =m·I IN -I Q

[0104] Figure 13A The circuit 71, i.e., I, which generates a ramp with a negative offset is schematically shown. Q >0. Circuit 71 includes a latch unit 21 that performs the maximum function, i.e., the output is collected on the maximizing node, which is provided as input I. I1 Similar to Figure 5A The slope current of the slope current, and I IN2 =I Q A constant current corresponding to a negative offset value is then used to maximize the output (e.g., I). O2 The value is acquired. In subtraction block 41, the current constant value I is then subtracted from the output of latch 21. Q The result, multiplied by an integer m, is fed into block 42 to generate the final output current I. O =m·I IN -mI q =m·I IN -I Q That is, a slope with negative offset.

[0105] Figure 13B The corresponding circuit implementation is shown, where latch 31 is coupled to circuit 60. Subtraction block 41 generates a constant current I. Q This is achieved using a current generator, which is coupled between the output of latch 31 and ground, drawing current from the output node of latch 31. Current I O2 (i.e., the maximum output of latch 31) is obtained from the second mirror, which has a 1:m mirror ratio, thus forming multiplier 42.

[0106] Figure 14AThe input current I, executed by block 21, is shown. I1 I I2 Slope I IN and constant value I and max(I) IN I Q (The image is shown.) Figure 14B The input current max(I) of the subtraction module 41 is shown. IN I Q ) and I Q and the maximum output current (I) IN ,I Q )-I Q The image, in Figure 14C In this case, the maximum current (I) IN ,I Q )-I Q As input to multiplier 42, and after being multiplied by m in multiplier 42, the final output is I. O =m·I IN -I Q .

[0107] If you need to generate a positive offset I O =m·I IN +I Q If the current reference ramp is obtained, it can be obtained as a circuit 81 consisting of a chain of multipliers 82 including multiplier m, the output of which is summed in summing block 83 to a constant offset current I. Q ,like Figure 15A As illustrated in the diagram. Figure 15B The circuit implementation is shown, where multiplier 82 is obtained from a 1:m proportional mirror circuit, and current generator 83 applies the output to a constant offset current I. Q .

[0108] Figures 16A-16B It shows Figure 15A , Figure 15B The current characteristic diagram of the circuit, that is, Figure 16A The input current and ramp I are shown. IN and constant value I Q The image, and Figure 14B The final output I is shown. O =m·I IN +I Q The image.

[0109] Hence, as shown above, the solution first targets an electronic circuit for generating a piecewise linear current transfer function, the electronic circuit comprising at least a circuit module, e.g. a latch unit 21 (or 31, 21P, 31P), the latch unit comprising a first pair of MOS transistors M1, M2 (e.g. NMOS or PMOS) and a second pair of MOS transistors M3, M4, the drains of each of the pairs of MOS transistors M1, M2 and M3, M4 being coupled to a respective common input node (e.g. V1, V2).

[0110] Each of the pairs of MOS transistors M1, M2 and M3, M4 comprises a diode-connected MOS transistor (e.g. M1, M4) and a latching MOS transistor M2, M3, the respective gate electrodes of the latching MOS transistors M2 and M3 of the two pairs of transistors being coupled to the drain of the other latching MOS transistor M3 and M2, respectively.

[0111] The sources of the diode-connected MOS transistors M1, M4 of the first and second pairs of transistors are coupled to a respective first output common node I O2 , and the sources of the latching MOS transistors M2, M3 of the first and second pairs of transistors are coupled to a respective second output common node I O1 .

[0112] The electronic circuit can be coupled to or comprise a first collection circuit, such as a transistor M6, coupled to collect a current (e.g. I6) at the first output common node (e.g. V4), in particular for implementing an input current maximization function between the currents applied at the input nodes, and / or a second collection circuit, e.g. a transistor M6, coupled to collect a current (e.g. I6) at the second output node (e.g. V3), in particular for implementing a current minimization function between the currents applied at the input nodes.

[0113] The electronic circuit can be coupled to or comprise one or more current supply circuits, e.g. a generator 22, configured to supply a first current (e.g. I IN1 ) to the common input node of one of the pairs of transistors M1, M2 and M3, M4, and / or a second current I IN2 .

[0114] Generally, two input currents are provided, but as shown above, only one input current can also be provided. Then, the electronic circuit 20 can have a first input current I IN1 being a variable current, in particular a ramp, and a second current I IN2 being a constant reference current I IN1 .

[0115] Moreover, by combining two or more such cells with outputs max(I IN1 , I IN2 ) and / or min(I IN1 , I IN2 ), possibly not using some inputs or some outputs (in this case preferably coupled to ground), it is possible to combine the outputs of each piecewise linear generating circuit or cell to obtain other PWL functions, for example as shown in Figure 9A , Figure 9B , Figure 11A , Figure 11B .

[0116] To this end, as an example, it is possible to obtain a "triangle to quadratic" PWL generator by nesting the functions (max() and min()) previously discussed, with parameters being a set of current reference ramps, encoded as two vectors containing the angular coefficient "m" and the offset coefficient "I q ", by cascading the corresponding latching cells, by using the described latch blocks 21, 31, 21p, 31p.

[0117] As shown in Figures 19A-19B , it is possible to implement a piecewise linear transfer function f(I IN ) between an input current I O and an output current I IN determining a quadratic output. By applying as input to the circuit a triangular waveform current I IN obtained by cascading latching cells selected from the latching cells 21, 31, 21p, 31p and selecting the desired maximization or minimization output to be coupled with the next cascaded cell, it is possible to implement a symmetric transfer function f(I 2 ) comprising -x 2 and +x IN parabolic branches.

[0118] As shown in Figure 20A and Figure 20B , due to the different concavity of the two branches of the transfer function f(I IN ), the implementation of the PWL generator is divided into two portions I IN = [0-0.5] and I IN = [0.5-1.0], [0-1] being the amplitude of the triangular input current I I . In Figure 20A the values of the angular coefficient m and the offset coefficient I IN of the eight ramps forming the piecewise linear transfer function f(I IQ ) are shown, four ramps for one portion.

[0119] As shown in the figure, a sequence of four linear segments S1, S2, S3, and S4 is used. These four linear segments S1, S2, S3, and S4 are determined by the coefficient m and the offset current I. q The values ​​are defined as (0.25, -0.01562), (0.5, -0.06250), (0.75, -0.14062), and (1, -0.25) respectively in the examples shown. The coefficient m and the offset current I... q The value can be easily calculated using approximations of the curve, generated, for example, using programs like Matlab or Octave, over a given number of linear segments.

[0120] Then, each segment S1…S4 can utilize the set offset current I q The required value of the angle coefficient m is similar to Figure 13A The corresponding circuit in the middle (because the offset current is negative) is used to generate it. Then the first two segments S1 and S2 can be sent as input to the first maximization block to obtain max(S1,S2). Then max(S1,S2) and segment S3 are sent as input to the second maximization block to obtain max(max(S1,S2),S3). Then max(max(S1,S2),S3) and segment S4 are sent to the third maximization block to obtain max(max(max(S1,S2),S3),S4).

[0121] for Figure 20B In the curved portion, four linear segments S5, S6, S7, and S8 are used, with paired coefficients m and offset current I of (1, -0.252), (0.75, -0.109375), (0.5, -0.00625), and (0.25, -0.2625), respectively. q .

[0122] The current ramps corresponding to segments S5, S6, S7, and S8 can be... Figure 13A (when offset I) q (for positive time) or Figure 15A (when offset I) q When negative, for example for circuits S7 and S8, based on their respective m and I... q The coefficients are obtained. Then, in the same manner as for segments S1, S2, S3, and S4, starting from the first two segments in the sequence, segments S5, S6, S7, and S8 are fed as input to the cascade of three maximizing blocks.

[0123] Thus, in general, the method for generating a piecewise linear characteristic can comprise performing a concatenation (i.e. coupling at least one output of a latch cell to an input of a concatenated latch cell), the latch cells selected among cells 21, 31, 21P, 31P being configured to select among configurations at least between a current maximizer configuration (i.e. the output of a latch cell is obtained on a current maximizer node), a current minimizer configuration (i.e. the output of a latch cell is obtained on a current minimizer node) and a current reference ramp generator configuration with a negative offset 71 or a positive offset 81 to obtain a given determined piecewise linear characteristic. Of course, other types of circuits than latch cells can be inserted in the concatenation.

[0124] Thus, the method of generating a piecewise linear characteristic can comprise defining a piecewise linear current characteristic to be obtained as a sequence of functions nested one in the other. For example, referring to figure 20, the sequence of reproducing segments S1, S2, S3, S4 of a quadratic function is defined as a sequence of nested max functions, with the innermost function between the first two adjacent segments S1, S2, and the result of the nested function and the next segment as parameters, i.e. max(max(max(S1, S2), S3), S4).

[0125] The method then comprises configuring a first circuit for generating a piecewise linear current transfer function implementing the innermost nested function, in this example cell 21, with for example segments S1, S2 as inputs, the maximized output being obtained. Of course, segments S1 and S2 can be current ramps generated by circuits 71 or 81.

[0126] The method then comprises configuring and concatenating subsequent circuits for generating a piecewise linear current transfer function to perform the subsequent nested function, i.e. coupling another cell 21 at each maximized output of cell 21, the other cell 21 having the next segment in the sequence as another input, and obtaining the maximized output of the other cell 21.

[0127] For a nested function, it is meant here a function that is closed in another function, called the enclosing function. In a sequence of nested functions, only the innermost function is the nested function, while the other functions are also enclosing functions, while the outermost function is only an enclosing function.

[0128] Further applications of circuits 20 and latch cells 21, 31 can be in the field of class AB amplifiers.

[0129] Amplifiers represent the most important module in many electronic applications.

[0130] Under this view, parameters related to the power consumption of an amplifier are of great relevance.

[0131] Due to the increasing popularity of today's battery-powered devices, it is important that power must be delivered to the load with negligible losses (i.e. efficiently).

[0132] Therefore, it is important to select an amplifier stage capable of delivering large currents to the load with negligible DC bias power consumption. These are the most important characteristics of AB class amplifiers, where the maximum deliverable current is much higher than the DC bias current.

[0133] On the other hand, even more applications require the delivery of large currents to low resistance / high capacitance loads at high frequencies. One example (but not limited to) can be the TV / display driver stage. Large currents and high frequency operation can cause electromagnetic interference to the adjacent environment.

[0134] For this reason, it is even more important to design very efficient architectures capable of increasing the lifetime of battery-powered devices without neglecting the magnitude of these currents (i.e. current steps).

[0135] The most important key factors that a device should meet can be emphasized. One possible definition of power efficiency is that it is directly proportional to the ratio of the current delivered to the load and the bias current consumption. On the other hand, the noise proportional to the high frequency current di should be minimized.

[0136] In class A stage, the efficiency is very low because the maximum delivered current is a fraction of the bias available current. This amplifier stage is very common when linearity is a priority.

[0137] The natural solution to maximize power efficiency is the class AB amplifier stage, which is capable of delivering currents to the load that are independent of and greater than the bias current.

[0138] The main drawback of the class AB amplifier stage is that, although it can deliver currents to the load that are independent of the DC bias current, the maximum magnitude of this current cannot be well controlled when an input voltage step is applied.

[0139] A class AB single stage operational transconductance amplifier is schematically represented to describe this drawback.

[0140] Figure 17 The shown class AB amplifier circuit has an input stage II, an input stage I2, and an input stage I3, the input stage II comprising an NMOS transistor M2 used as input terminal for the positive differential signal Vin(+) and a PMOS cascode diode load M4, the input stage I2 comprising an NMOS transistor Ml used as input terminal for the negative differential signal Vin(-) and a PMOS cascode diode load M4, the input stage I3 (with a shifted level, also known as "level shifted stage input") comprising an NMOS transistor M9 and M 10And PMOS transistors M7 and M8, wherein the source of M9 is connected to the source of M8, M 10 The source of M1 is connected to the source of M7. M7 and M8 have gates connected to their drains, which are coupled to ground via corresponding bias current generators Ib. M1 is coupled to VDD via its drain, while M2 is coupled to a first current mirror formed by PMOS M6A (diode connection, mirrored input) and PMOS M6B, where their sources are coupled to VDD. The drains of M3 and M6B are coupled to the drains of NMOS M5A (diode connection) and NMOS M5B, respectively, forming a second mirror coupled to ground. The common node defined by the coupled drains of M6B and M5B defines the output capacitance C. out The coupled output node. Under the condition of applying a large voltage step, the current IUP flowing in the first current mirror is injected into the drain of M2 and the output node, as described below.

[0141] from Figure 17 It can be seen that, under the bias condition, even for the bias applied to V IN+ and V IN- Small signals between, MOS device M 7，10 and M 8，9 This also forms a level shifter. In fact, due to these MOS devices, if a small signal input V is applied at node a... IN- Then it will be directly visible on node b. Because of this V IN- It is applied to the gate of the NMOSM4 and V IN+ When applied to the gate of M2, this pair of M2-M4 forms an equivalent transconductance:

[0142] g m_EQ =g m2 / / g m4

[0143] Where g m2 and g m4 These are the transconductances of M2 and M4, respectively.

[0144] Under DC bias conditions, if Vin - =Vin + Therefore, devices M7-M3 form a current mirror, so the bias current I B It appears on the drains of M3 and M1.

[0145] Now consider what is applied to V IN+ and V IN- Large voltage steps between, and under these conditions, according to the previously discussed g of M2-M4 m-EQ Generated current i UPat the same time, the MOS devices M1 and M3 are instantaneously turned off. For simplicity, consider the first mirror PMOS M 6A-6 of the same size, the current i UP is directly applied to the load C OUT .

[0146] Under these assumptions, when a large voltage step is applied at the input of the amplifier 20, then a large current i UP is applied to the load and this current is not related to the bias current I B .

[0147] Therefore, using an AB class amplifier is an effective way to deliver a large current to the load C OUT , but doing so would lose the possibility to control and / or limit the maximum current to the load, regardless of the amplitude of the input, i.e. to control the input slew rate.

[0148] The solution described here involves an AB class amplifier with controlled output slew rate.

[0149] The output current i OUT is:

[0150] i OUT = g m_EQ · v IN (1)

[0151] According to equation (1), the maximum deliverable current is proportional to the equivalent transconductance g m_EQ and to the differential input voltage v IN .

[0152] If the goal is to limit the power line drop to limit the noise injected to other devices, the current limit must be independent of the input voltage, as happens in class A in the transition condition.

[0153] Moreover, if the precision of the current limit must be high, this architecture is not very suitable, since it depends on the absolute precision of the equivalent transconductance g m-EQ and on the absolute value of the maximum input voltage v IN_MAX . Since they depend on many factors (process, temperature and voltage), neither quantity can be well controlled.

[0154] The solution described here introduces the slew rate limit to an architecture in which the deliverable current is intrinsically not limited (AB class).

[0155] Figure 18 A schematic circuit of the proposed AB class amplifier is shown, which includes the insertion of a current limiter on the current supplied to the load.

[0156] This current limiter is for example implemented by a latch 31. As shown, the current input I Figure 18 of a first latch unit 31p of PMOS type receives the current flowing in the second current mirror M IN1 , M 5A , in particular through the NMOS M 5B coupled in parallel with respect to the PMOS M 5B on the second mirror. The gate of the NMOS M XA , i.e. M XA , is coupled to the gates of M 5A and M 5B . The drain of the NMOS M XA is coupled to the current input I IN1 . The second input current I IN2 of the limiter 31 is coupled to the current generator from which the maximum current I MAX is drawn. The output of the latch 31p representing the limiter operated by I O2 is coupled to the NMOS transistor M1 which acts as input terminal for the negative differential signal Vin(-).

[0157] Symmetrically, the current input I IN1 of a second latch unit 31 of NMOS type receives the current flowing in the first current mirror M 6A , M 6B , in particular through the PMOS M XB coupled in parallel with respect to the NMOS M XB on the second mirror. The gate of the PMOS M 6A , i.e. M 6B , is coupled to the gates of M XB and M IN1 . The drain of the PMOS M IN2 is coupled to the current input I MAX . The second input current I B of the limiter 31 is coupled to the current generator in which the maximum current I MAX is injected.

[0158] With reference to the first latch 31p, it is assumed that I IN1 <I B , during DC operation, because I IN2 = I MAX and I O2 = I B .

[0159] If a voltage drop Δv is applied on the negative input Vin - , for example a voltage drop of short length of time, and the relative current generated on the drain of the NMOS is less than the maximum current IMAX then the current limiter (i.e. latch 31) is transparent and I O2 = I IN1 However, if the voltage drop Δv has an amplitude sufficient to generate a current at the drain of NMOS M3 such that I D3 >I MAX then the current limiter will limit the current such that:

[0160] I O2 = I MAX (2)

[0161] Since the need for a symmetric output current limitation, there are two different current limiters.

[0162] The solution just described with respect to the AB class amplifier overcomes the problems discussed. In particular:

[0163] the current level delivered to the load is greater than the bias current;

[0164] the current limitation (slew rate) is implemented in the AB class architecture; and

[0165] a high precision of the limited / controlled maximum output current is obtained.

[0166] The claims are an integral part of the technical teaching provided in the disclosure herein.

[0167] Of course, the details of construction and embodiments can vary widely with respect to what is described and illustrated herein only by way of example, without thereby departing from the scope of the invention as defined by the appended claims, without thereby departing from the principles of the invention.

Claims

1. A circuit for generating a piecewise linear current transfer function, comprising: a latch circuit module unit comprising a first pair of transistors and a second pair of transistors, each pair of transistors in the first pair of transistors and the second pair of transistors having a drain coupled to a respective common input node; a first current supply circuit configured to supply a first current to the common input node of the first pair of transistors, wherein the first current is a variable current comprising a current ramp; a second current supply circuit configured to supply a second current to the common input node of the second pair of transistors, wherein the second current is a constant reference current; wherein each pair of transistors in the first pair of transistors and the second pair of transistors comprises a diode-connected transistor and a latch transistor, wherein the latch transistors of the first pair of transistors and the second pair of transistors have cross-coupled gates and drains; wherein a source of the diode-connected transistor is coupled to a first current output common node, and wherein a source of the latch transistor is coupled to a second current output common node.

2. The circuit of claim 1, wherein the latch circuit module unit is coupled to a first current collection circuit coupled to collect current at the first current output common node in order to implement an input current maximization function between currents applied at the common input nodes of the latch circuit module unit.

3. The circuit of claim 1, wherein the latch circuit module unit is coupled to a second collection circuit coupled to collect current at the second current output node in order to implement a current minimization function between currents applied at the common input nodes of the latch circuit module unit.

4. The circuit of claim 1, wherein transistors in the first pair of transistors and the second pair of transistors are NMOS transistors.

5. The circuit of claim 1, wherein transistors in the first pair of transistors and the second pair of transistors are PMOS transistors.

6. The circuit of claim 1, wherein the latch circuit module unit is configured to have input and output currents flowing in opposite directions with respect to input and output nodes.

7. The circuit of claim 1, wherein the latch circuit module unit is configured to have input and output currents entering or exiting input and output nodes.

8. The circuit of claim 1, wherein transistors in the first pair of transistors and the second pair of transistors are the same size.

9. A circuit for generating a piecewise linear current transfer function, comprising: a latch circuit module unit comprising a first pair of transistors and a second pair of transistors, each pair of transistors in the first pair of transistors and the second pair of transistors having a drain coupled to a respective common input node; Each of the first transistor pair and the second transistor pair includes a diode-connected transistor and a latching transistor, wherein the latching transistor of the first transistor pair and the second transistor pair has a cross-coupled gate and a drain; The source of the diode-connected transistor is coupled to a first current output common node, and the source of the latching transistor is coupled to a second current output common node. as well as The latch circuit module unit receives an input current ramp and an input constant current corresponding to a negative offset value, and the circuit further includes: A first current harvesting circuit is coupled to harvest current at the first current output common node to achieve the function of maximizing the input current between the currents applied at the input node; The subtraction circuit is configured to subtract the current constant value from the first current output; and The multiplier circuit is configured to multiply by an integer in order to implement a current ramp using a negative offset generator.

10. The circuit of claim 9, wherein the transistors in the first transistor pair and the second transistor pair are NMOS transistors.

11. The circuit of claim 9, wherein the transistors in the first transistor pair and the second transistor pair are PMOS transistors.

12. The circuit of claim 9, wherein the latching circuit module unit is configured to have input current and output current flowing in opposite directions relative to the input node and the output node.

13. The circuit of claim 9, wherein the latching circuit module unit is configured to have input current and output current for entering or exiting the input node and output node.

14. The circuit of claim 9, wherein the transistors in the first transistor pair and the second transistor pair are of the same size.

15. A piecewise linear generator, comprising the circuitry of claim 9.

16. A piecewise linear generator, comprising the circuit according to claim 1.

17. A Class AB amplifier with a differential architecture, comprising: The corresponding positive and negative input stages are coupled to the level shifter; The positive input stage and the negative input stage are coupled to a circuit for generating a piecewise linear current transfer function, comprising: The latching circuit module unit includes a first transistor pair and a second transistor pair, each of the first transistor pair and the second transistor pair having a drain coupled to a corresponding common input node; Each of the first transistor pair and the second transistor pair includes a diode-connected transistor and a latching transistor, wherein the latching transistor of the first transistor pair and the second transistor pair has a cross-coupled gate and a drain; The source of the diode-connected transistor is coupled to a first current output common node, and the source of the latching transistor is coupled to a second current output common node.

18. A method for generating a piecewise linear current transfer function, comprising: Multiple circuits are used to generate piecewise linear currents for the transfer function, where each circuit includes: a latch circuit module unit including a first transistor pair and a second transistor pair, each of the first transistor pair and the second transistor pair having a drain coupled to a respective common input node; wherein each of the first transistor pair and the second transistor pair includes a diode-connected transistor and a latch transistor, wherein the latch transistors of the first transistor pair and the second transistor pair have cross-coupled gates and drains; and wherein a source of the diode-connected transistor is coupled to a first current output common node, and wherein a source of the latch transistor is coupled to a second current output common node; defining a piecewise linear current characteristic as a sequence of functions nested one into another; configuring one of the circuits to generate the piecewise linear current transfer function implementing the innermost nested function of the sequence of functions; and configuring a subsequent one of the circuits in cascade to generate a piecewise linear current transfer function to perform a subsequent nested function of the sequence of functions.

19. A computer program product loadable into the memory of at least one processor and comprising portions of software code for implementing the method according to claim 18.

20. A circuit comprising: a latch circuit module unit including a first transistor pair and a second transistor pair, the first transistor pair having a drain coupled to receive a first input current and the second transistor pair having a drain coupled to receive a second input current; wherein each of the first transistor pair and the second transistor pair includes a diode-connected transistor and a latch transistor, wherein the latch transistors of the first transistor pair and the second transistor pair have cross-coupled gates and drains; wherein a source of the diode-connected transistor is coupled to a first current output common node; and wherein a source of the latch transistor is coupled to a second current output common node; a first current collection circuit including a first diode-connected transistor coupled to collect a first current at the first current output common node, the first current being a maximum of the first input current and the second input current; and a second current collection circuit including a second diode-connected transistor coupled to collect a second current at the second current output common node, the second current being a minimum of the first input current and the second input current.

21. The circuit of claim 20: wherein the first input current is a variable current including a current ramp; and wherein the second input current is a constant reference current.

22. The circuit of claim 20: wherein the first input current is a first variable current including a first current ramp; and wherein the second input current is a second variable current including a second current ramp.

23. The circuit of claim 20, further comprising a current multiplier circuit configured to multiply one of the first current and the second current by an integer value.

24. The circuit of claim 20, further comprising a current subtraction circuit configured to subtract a fixed current from one of the first current and the second current.

25. A piecewise-linear generator comprising the circuit of claim 20.

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