A Fast Calibration Method and Circuit for Voltage-Controlled Oscillator

Abstract

The present invention discloses a method and a circuit for quickly calibrating a voltage-controlled oscillator. The circuit of the present invention includes a reference clock counter (11) for counting the reference clock and sending the calculation result to a control state machine (13); a feedback clock counter (12) for counting the feedback clock and sending the calculation result to the control state machine (13); a control state machine (13) for controlling the reference clock counter (11) and the feedback clock counter (12) to count simultaneously, controlling the reset timing of a frequency divider (15), and controlling the capacitance of a capacitance array in the voltage-controlled oscillator (14) to reach an optimal value according to the counting results; a frequency divider (15) for dividing the output frequency of the voltage-controlled oscillator (14); and a mapping or calculation module (16) for completing the mapping from the division ratio N to the count value cnt and sending the count value cnt to the reference clock counter (11).

Description

Technical Field

[0001] The present invention belongs to the field of electronic technology, and is specifically applicable but not limited to voltage-controlled oscillator and phase-locked loop technologies, and relates to a method and circuit for fast VCO calibration. Background Art

[0002] To improve bandwidth utilization and transmission convenience, signals need to be mixed to a high frequency before transmission. To reduce the deterioration of the signal-to-noise ratio of the signal, a high-quality local oscillator signal is required to complete the mixing. Transceivers commonly use a capacitor-inductor voltage-controlled oscillator (LCVCO) to generate a high-quality oscillation signal. The active device noise of the LC VCO circuit is injected into the resonator when the amplitude is maximum, which has little impact on the signal quality and excellent performance. However, the frequency adjustment generally uses a varactor diode, and the frequency adjustment range is relatively small.

[0003] Modern communication technologies often have higher requirements for signal bandwidth. When products need to be compatible with multiple communication standards, the requirements for bandwidth are also significantly increased.

[0004] To increase the frequency change range of the LCVCO, a capacitor array is generally used. By jointly providing capacitance changes through the capacitor array and the varactor diode, the frequency of the VCO (voltage-controlled oscillator) is changed. The capacitor array significantly expands the frequency change range of the LCVCO. However, the capacitor array needs to be calibrated before the VCO is used. Only at an appropriate capacitor array value can the VCO oscillate to the required frequency, otherwise the phase-locked loop cannot be locked.

[0005] When the VCO range is very wide, the required number of bits of the capacitor array is also very large, and the calibration time is also extended accordingly. The present invention aims to propose an adaptive count value method to reduce the calibration time. Summary of the Invention

[0006] In order to overcome the deficiencies of the prior art, the purpose of the present invention is to provide a method and circuit for fast calibration of a voltage-controlled oscillator, which reduces the calibration time of the voltage-controlled oscillator VCO.

[0007] The technical solution of the present invention is as follows:

[0008] A fast calibration circuit for a voltage-controlled oscillator, characterized by comprising a reference clock counter 11, a feedback clock counter 12, a control state machine 13, a frequency divider 15, and a mapping or calculation module 16; wherein

[0009] The reference clock counter 11 is used to count the reference clock and send the calculation result to the control state machine 13;

[0010] The feedback clock counter 12 is used to count the feedback clock and send the calculation result to the control state machine 13;

[0011] The control state machine 13 is respectively connected to the reference clock counter 11, the feedback clock counter 12, the voltage-controlled oscillator 14, and the frequency divider 15, and is used to control the reference clock counter 11 and the feedback clock counter 12 to count simultaneously, control the reset timing of the frequency divider 15, and control the capacitance of the capacitor array in the voltage-controlled oscillator 14 to reach the optimal value according to the calculation results of the reference clock counter 11 and the feedback clock counter 12;

[0012] The frequency divider 15 is connected to the voltage-controlled oscillator 14 and is used to divide the output frequency of the voltage-controlled oscillator 14;

[0013] The mapping or calculation module 16 is respectively connected to the reference clock counter 11 and the frequency divider 15, and is used to complete the mapping from the frequency division ratio N to the count value cnt according to the formula and send the count value cnt to the reference clock counter 11; where n is the ratio of the frequency difference f between adjacent frequency band lines in the voltage-controlled oscillator 14 d and the frequency detection accuracy f res The ratio of L is the inductance value in the voltage-controlled oscillator 14, and C u Is the unit capacitance of the capacitor array in the voltage-controlled oscillator 14, and f ref Is the set reference clock frequency.

[0014] Furthermore, the control state machine 13 controls the capacitance of the capacitor array in the voltage-controlled oscillator 14 to reach the optimal array value by using the successive approximation method.

[0015] Furthermore, the control mode of the capacitor array in the voltage-controlled oscillator 14 is binary control, and the number of control bits is b.

[0016] A method for quickly calibrating a voltage-controlled oscillator based on the above voltage-controlled oscillator quick calibration circuit, the steps of which include:

[0017] 1) The baseband processor determines the frequency point and configures the frequency division ratio register;

[0018] 2) The frequency division ratio register controls the frequency division ratio N of the feedback frequency divider, and at the same time inputs the frequency division ratio N into the mapping or calculation module 16 to obtain the count value cnt corresponding to the frequency division ratio N;

[0019] 3) Use the successive approximation method to find the optimal array value: When the count of the reference clock counter 11 reaches the adaptive count value cnt calculated by the mapping or calculation module 16, compare the count values output by the reference clock counter 11 and the feedback clock counter 12. If the count value output by the feedback clock counter 12 is less than the value of the reference clock counter 11, the control state machine 13 correspondingly adjusts the capacitor array to increase the frequency of the voltage-controlled oscillator 14; conversely, if the count value output by the feedback clock counter 12 is greater than the value output by the reference clock counter 11, the control state machine 13 correspondingly adjusts the capacitor array to decrease the output frequency of the voltage-controlled oscillator 14; through the successive approximation process, the capacitor array that makes the feedback clock and the reference clock closest is finally found.

[0020] Compared with the prior art, the positive effects of the present invention are as follows:

[0021] The system usually requires the broadband VCO to cover an octave, that is, the highest frequency is twice the lowest frequency. In this way, through a series of frequency divisions by two, continuous frequencies below the highest frequency can be obtained.

[0022] The traditional method uses a fixed count value and can only be set according to the maximum count value. In this way, when using high frequencies, more calibration time will be wasted. Using the adaptive count value method proposed by the present invention, the calibration time can be saved by up to 75%. Especially in broadband VCOs, the effect is significant.

[0023] Figure 4 It shows the calibration time that can be saved for different frequency division ratios. It can be seen that when the frequency division ratio is 1.2 times the minimum frequency division ratio, 30% of the calibration time can already be saved. Brief Description of the Drawings

[0024] Figure 1 is the adjacent frequency band line;

[0025] Figure 2 is an example of the relationship between the number of counting cycles and the frequency division ratio;

[0026] Figure 3 is a schematic diagram of the calibration circuit structure;

[0027] Figure 4 is a graph of the calibration time that can be saved for different frequency division ratios.

[0028] Among them, 11 - reference clock counter, 12 - feedback clock counter, 13 - control state machine, 14 - voltage-controlled oscillator, 15 - frequency divider, 16 - mapping or calculation module. Detailed Embodiment

[0029] The present invention will be further described in detail below with reference to the drawings.

[0030] As Figure 1As shown, the horizontal axis is the VCO control voltage, and the vertical axis is the VCO oscillation frequency. The two oblique lines represent the oscillation frequencies of two adjacent capacitor array values at different control voltages. The part between the two horizontal dotted lines is the overlapping part of the two frequency band line frequencies.

[0031] Assume that the inductance value in the VCO is L, and the fixed capacitance is C fix , the unit capacitance of the capacitor array is C u , the varactor capacitance is C v0 , and the number of unit capacitances turned on in the capacitor array is m. Then the VCO frequency f vco is:

[0032]

[0033] Taking the derivative of the VCO frequency with respect to m gives the frequency difference between the frequency band lines

[0034]

[0035] Transform formula (1) into the following formula

[0036] 2πf vco =[L(C fix +mC u +C v0 )] -1 / 2 (3)

[0037] Substitute formula (3) into formula (2) to obtain the relationship between the frequency band line spacing and the frequency

[0038]

[0039] So the frequency band line spacing

[0040]

[0041] Assume that the frequency detection accuracy is one nth of the adjacent frequency band frequency difference (i.e., the frequency band line spacing) f d ,

[0042] f res =f d / n (6)

[0043] If a frequency calibration method with reset (refer to the Chinese patent application document with patent application number CN201711387872.8) is used, then the frequency detection accuracy f res requires that the minimum count value is

[0044]

[0045] f vco =N*f ref , substitute into f resand f d

[0046]

[0047] In the above formula, the reference clock frequency f ref is a fixed value, the inductance value L and the unit capacitance C of the capacitor array u are circuit design parameters. n is the ratio of the frequency difference between adjacent frequency band lines to the frequency detection accuracy. The larger n is, the smaller the detectable frequency difference is, and the lower the requirement for frequency band overlap is. For a fixed circuit design, the count value cnt is only related to the division ratio N, and other variables can be regarded as constants.

[0048] A numerical example of the relationship between the counting period number and the division ratio is as Figure 2 shown. It can be seen from the above formula that the minimum count value is inversely proportional to the square of the division ratio. If the highest frequency of the wideband VCO is twice the lowest frequency, then the high-frequency count value is 1 / 4 of the low-frequency count value. The traditional calibration circuits are all implemented with fixed count values. To ensure locking, the counting period must be calculated according to the lowest frequency, but this wastes calibration time for most frequency points.

[0049] Assume that the control mode of the VCO capacitor array is binary control, and the number of control bits is b. Then the total capacitance of the array is 2^b - 1; generally, the successive approximation method is used to find the final array value after b counts. Then the total calibration time is approximately b * cnt * T ref , T ref is the reference clock period. Therefore, by reducing the minimum count value cnt, the total calibration time also decreases proportionally.

[0050] The schematic diagram of the principle of the present invention is as Figure 3 , the mapping or calculation module 16 completes the mapping from the division ratio to the count value according to formula (8) to achieve count value self-adaptation. Performing mapping or calculation for each division ratio N respectively, or performing mapping or calculation on segmented division ratios all fall within the scope of the present invention; the reference clock counter 11 and the feedback clock counter 12 are two counters that count the reference clock and the feedback clock respectively; the frequency divider 15 divides the output frequency of the voltage-controlled oscillator 14; the control state machine 13 controls the reference clock counter 11 and the feedback clock counter 12 to count simultaneously, controls the reset timing of the frequency divider 15, and controls the capacitance of the VCO capacitor array to reach the optimal value according to the calculation results of the reference clock counter 11 and the feedback clock counter 12; the voltage-controlled oscillator 14 has a control voltage input, which is connected to the reference voltage Vref during calibration; when the calibration is completed, it is connected to the control voltage Vtune output by the loop filter in the phase-locked loop.

[0051] The calibration process is as follows:

[0052] 1. The baseband processor determines the frequency point and configures the division ratio register.

[0053] 2. The division ratio register controls the division ratio N of the feedback divider, and at the same time inputs the division ratio N into the mapping or calculation module 16. According to the above formula 8, the count value cnt corresponding to the division ratio N is obtained and sent to the reference clock counter 11.

[0054] 3. Use the successive approximation method to find the optimal array value. When the count of the reference clock counter 11 reaches the adaptive count value cnt calculated by the mapping or calculation module 16, the state control machine 13 compares the count value outputs of the reference clock counter 11 and the feedback clock counter 12. If the count value output by the feedback clock counter 12 is less than the value of the reference clock counter 11, it means that the feedback clock frequency is low, then the state control machine 13 correspondingly adjusts the VCO capacitor array to increase the VCO frequency; on the contrary, if the count value output by the feedback clock counter 12 is greater than the output value of the reference clock counter 11, it means that the feedback clock frequency is high, and the state control machine 13 correspondingly adjusts the VCO capacitor array to reduce the VCO output frequency. Through the successive approximation process, the VCO capacitor array that makes the feedback clock and the reference clock closest is finally found.

[0055] Let the minimum supported division ratio be N_min, and the current division ratio be N. Then, using the adaptive count value method, the calibration time can become (N_min / N)^2 of the original. When N = 2*N_min, the calibration time becomes 1 / 4 of the original. Considerable calibration time can be saved in a wideband VCO.

[0056] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present invention shall be included in the protection scope of the present invention.

Claims

1. A voltage-controlled oscillator fast calibration circuit, characterized in that It includes a reference clock counter (11), a feedback clock counter (12), a control state machine (13), a frequency divider (15), and a mapping or calculation module (16); Wherein The reference clock counter (11) is used to count the reference clock and send the calculation result to the control state machine (13); The feedback clock counter (12) is used to count the feedback clock and send the calculation result to the control state machine (13); The control state machine (13) is connected to the reference clock counter (11), the feedback clock counter (12), the voltage-controlled oscillator (14), and the frequency divider (15) respectively. It is used to control the reference clock counter (11) and the feedback clock counter (12) to count simultaneously, control the reset timing of the frequency divider (15), and control the capacitance of the capacitor array in the voltage-controlled oscillator (14) to reach the optimal value according to the calculation results of the reference clock counter (11) and the feedback clock counter (12); The frequency divider (15) is connected to the voltage-controlled oscillator (14) and is used to divide the output frequency of the voltage-controlled oscillator (14); The mapping or calculation module (16) is respectively connected to the reference clock counter (11) and the frequency divider (15), and is used to complete the mapping from the frequency division ratio N to the count value cnt according to the formula and send the count value cnt to the reference clock counter (11); where n is the ratio of the adjacent frequency band line frequency difference f d and the frequency detection accuracy f res in the voltage-controlled oscillator (14), L is the inductance value in the voltage-controlled oscillator (14), C u is the unit capacitance of the capacitor array in the voltage-controlled oscillator (14), and f ref is the set reference clock frequency.

2. The fast calibration circuit of the controlled oscillator according to claim 1, wherein, The control state machine (13) controls the capacitance of the capacitor array in the voltage-controlled oscillator (14) to reach the optimal array value by using the successive approximation method.

3. The fast calibration circuit for a voltage-controlled oscillator according to claim 1, wherein The control mode of the capacitor array in the voltage-controlled oscillator (14) is binary control, and the number of control bits is b.

4. A method for quickly calibrating a voltage-controlled oscillator based on the voltage-controlled oscillator quick calibration circuit according to claim 1, the steps of which include: 1) The baseband processor determines the frequency point and configures the frequency division ratio register; 2) The frequency division ratio register controls the frequency division ratio N of the frequency divider (15), and at the same time inputs the frequency division ratio N into the mapping or calculation module (16) to obtain the count value cnt corresponding to the frequency division ratio N; 3) Use the successive approximation method to find the optimal array value: When the reference clock counter (11) counts up to the adaptive count value cnt calculated by the mapping or calculation module (16), compare the count values output by the reference clock counter (11) and the feedback clock counter (12). If the count value output by the feedback clock counter (12) is less than the value of the reference clock counter (11), the control state machine (13) correspondingly adjusts the capacitor array to increase the frequency of the voltage-controlled oscillator (14); otherwise, if the count value output by the feedback clock counter (12) is greater than the value output by the reference clock counter (11), the control state machine (13) correspondingly adjusts the capacitor array to reduce the output frequency of the voltage-controlled oscillator (14); After the successive approximation process, finally find the capacitor array that makes the feedback clock and the reference clock closest.

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