Double-edge counting circuit, readout circuit, and image sensor

Abstract

The application provides a double-edge counting circuit, which comprises a logic circuit, a latch and a counter, the logic circuit is used for receiving a clock signal and a counting control signal, and then performing logical operation on the clock signal and the counting control signal to obtain a first reset signal and a first set signal, the latch is connected with the logic circuit, a reset end of the latch receives the first reset signal, a set end of the latch receives the first set signal, and an inverting output end of the latch outputs the least significant bit of the double-edge counting circuit, and the counter is connected with a non-inverting output end of the latch and is used for outputting other bits of the double-edge counting circuit, so that double-edge counting is realized, and power consumption and area are reduced. The application further provides a readout circuit and an image sensor.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a dual-edge counting circuit, a readout circuit, and an image sensor. Background Technology

[0002] In CMOS image sensors, the light signal is typically converted into an analog voltage signal by the photosensitive unit, and then converted into a digital signal by an analog-to-digital converter (ADC) circuit. The resulting digital signal is then transmitted off-chip. Since the photosensitive units are usually in array form, to improve the frame rate, each column of photosensitive units is typically connected to a separate ADC circuit. All columns of ADCs perform analog-to-digital conversion simultaneously, significantly increasing the overall chip conversion speed. The digital code obtained from the ADC conversion is then read out through a storage unit and a column select circuit.

[0003] Analog-to-digital converters (ADCs) currently typically employ an SS (Signal Slope ADC) structure, which mainly consists of modules such as coupling capacitors, reset switches, comparator circuits, and counter circuits. This is because SS ADCs have a simple circuit structure, low noise, and are easily integrated into column-level ADCs, resulting in a significant increase in conversion speed. However, with the continuous increase in pixel array size and frame rate requirements of CIS chips, there is still an urgent need to significantly improve the conversion speed of current SS ADCs.

[0004] The SS ADC conversion time is limited by (1 / F)*2N (where N is the number of ADC bits and F is the counting clock frequency). It can be observed that as the number of ADC bits N increases, the conversion time increases exponentially, and the conversion speed decreases significantly. The most direct way to improve the SS ADC sampling rate is to increase the clock frequency F. However, directly increasing the clock frequency F requires system support, placing higher demands on the system, which is often difficult for the system to provide at very high frequencies. A dual-edge sampling counter, on the other hand, can achieve the effect of doubling the counting frequency F without increasing it, significantly improving the sampling rate without increasing system complexity.

[0005] However, traditional dual-edge counting circuit devices are widely used, occupy a large area, and high-frequency circuit nodes flip at a high frequency, resulting in high power consumption.

[0006] Therefore, it is necessary to provide a novel dual-edge counting circuit, readout circuit, and image sensor to solve the aforementioned problems existing in the prior art. Summary of the Invention

[0007] The purpose of this invention is to provide a dual-edge counting circuit, a readout circuit, and an image sensor that achieve dual-edge counting while reducing area and power consumption.

[0008] To achieve the above objectives, the dual-edge counting circuit of the present invention includes:

[0009] A logic circuit is used to receive a clock signal and a counting control signal, and then perform logical operations on the clock signal and the counting control signal to obtain a first reset signal and a first set signal;

[0010] A latch, connected to the logic circuit, wherein the latch's reset terminal receives the first reset signal, the latch's set terminal receives the first set signal, and the latch's inverting output terminal outputs the least significant bit of the dual-edge counting circuit; and

[0011] The counter is connected to the positive output terminal of the latch and is used to output the other bits of the dual-edge counting circuit.

[0012] The beneficial effects of the dual-edge counting circuit are as follows: the logic circuit receives a clock signal and a counting control signal, and then performs logical operations on the clock signal and the counting control signal to obtain a first reset signal and a first set signal. The latch is connected to the logic circuit. The reset terminal of the latch receives the first reset signal, the set terminal of the latch receives the first set signal, and the inverting output terminal of the latch outputs the least significant bit of the dual-edge counting circuit. The counter is connected to the non-inverting output terminal of the latch and is used to output the other bits of the dual-edge counting circuit, thus realizing dual-edge counting and reducing power consumption and area.

[0013] Optionally, the logic circuit includes a first inverter, a second inverter, a first NAND gate, and a second NAND gate. The input terminal of the first inverter and the first input terminal of the second NAND gate receive the clock signal. The second input terminal of the first NAND gate and the second input terminal of the second NAND gate receive the counting control signal. The output terminal of the first inverter is connected to the first input terminal of the first NAND gate. The output terminal of the first NAND gate is connected to the input terminal of the second inverter. The output terminal of the second inverter outputs the first reset signal, and the output terminal of the second NAND gate outputs the first set signal.

[0014] Optionally, the logic circuit includes a first inverter, a first NAND gate, a second NAND gate, a third NAND gate, and an AND gate. The input terminal of the first inverter and the first input terminal of the second NAND gate receive the clock signal. The second input terminals of the first NAND gate and the second NAND gate are connected to the counting control signal. The output terminal of the first inverter is connected to the first input terminal of the first NAND gate. The output terminal of the first NAND gate is connected to the first input terminal of the third NAND gate. The second input terminal of the third NAND gate is connected to a second reset signal. The output terminal of the third NAND gate outputs the first reset signal. The output terminal of the second NAND gate is connected to the first input terminal of the AND gate. The second input terminal of the AND gate is connected to a second set signal. The output terminal of the AND gate outputs the first set signal.

[0015] Optionally, the latch includes a third inverter, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor. The sources of the first PMOS transistor and the second PMOS transistor are connected to the power supply voltage. The gates of the first PMOS transistor and the third NMOS transistor are connected to the first set signal. The gates of the second PMOS transistor and the first NMOS transistor are connected to the first reset signal. The drain of the first PMOS transistor is connected to the drains of the third PMOS transistor, the first NMOS transistor, the second NMOS transistor, and the input terminal of the third inverter, serving as the non-inverting output terminal of the latch. The drain of the second PMOS transistor is connected to the source of the third PMOS transistor. The gate of the third PMOS transistor is connected to the gate of the second NMOS transistor and the output terminal of the third inverter, serving as the inverting output terminal of the latch. The source of the first NMOS transistor is connected to the source of the second NMOS transistor and the drain of the third NMOS transistor. The source of the third NMOS transistor is grounded.

[0016] Optionally, the third inverter includes a fourth PMOS transistor and a fourth NMOS transistor. The source of the fourth PMOS transistor is connected to the power supply voltage, the source of the fourth NMOS transistor is grounded, the gate of the fourth PMOS transistor is connected to the gate of the fourth NMOS transistor, serving as the input terminal of the third inverter, and the drain of the fourth PMOS transistor is connected to the drain of the fourth NMOS transistor, serving as the output terminal of the third inverter.

[0017] Optionally, the counter includes at least one D flip-flop, which are connected in stages. The clock terminal of the first-stage D flip-flop is connected to the non-inverting output terminal of the latch, the clock terminal of the next-stage D flip-flop is connected to the non-inverting output terminal of the previous-stage D flip-flop, the inverting output terminal of each stage D flip-flop is connected to its own data input terminal for outputting other bits of the dual-edge counting circuit, and the reset terminal of each stage D flip-flop is connected to a second reset signal.

[0018] Optionally, the counter includes at least one D flip-flop, which are connected in stages. The clock input of the first-stage D flip-flop is connected to the non-inverting output of the latch, the clock input of the next-stage D flip-flop is connected to the non-inverting output of the previous-stage D flip-flop, the inverting output of each stage D flip-flop is connected to its own data input, and is used to output other bits of the dual-edge counting circuit. The reset input of each stage D flip-flop is connected to a second reset signal, and the set input of each stage D flip-flop is connected to a second set signal.

[0019] The present invention also provides a readout circuit, comprising:

[0020] Comparator, and

[0021] The dual-edge counting circuit is connected to the output terminal of the comparator.

[0022] The beneficial effect of the readout circuit is that it achieves dual-edge counting by using the dual-edge counting circuit, and reduces power consumption and area.

[0023] The present invention also provides an image sensor, comprising:

[0024] A pixel unit array, used for light sensing to generate voltage signals;

[0025] A ramp signal generation unit is used to generate a ramp signal; and

[0026] At least one of the readout circuits is connected to the pixel unit array and the ramp signal generating unit.

[0027] The advantages of the image sensor are that it achieves dual-edge counting by using the readout circuit, and reduces power consumption and area. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of a conventional two-edge counting circuit implemented using dual D flip-flops in the prior art;

[0029] Figure 2 The timing diagram shows the implementation of a traditional two-edge counting circuit using dual D flip-flops in the prior art.

[0030] Figure 3 This is a circuit diagram of a dual-edge counting circuit in some embodiments of the present invention;

[0031] Figure 4 This is a circuit diagram of a dual-edge counting circuit in some embodiments of the present invention;

[0032] Figure 5 This is a circuit diagram of a latch in some embodiments of the present invention;

[0033] Figure 6 This is a circuit diagram of the first-stage D flip-flop in some embodiments of the present invention;

[0034] Figure 7 This is a timing diagram of a dual-edge counting circuit in some embodiments of the present invention;

[0035] Figure 8 This is a circuit diagram of an image sensor in some embodiments of the present invention;

[0036] Figure 9 This is a circuit diagram of the readout circuit in some embodiments of the present invention. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without inventive effort are within the scope of protection of this invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art. The terms "comprising" and similar expressions used herein mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, but do not exclude other elements or objects.

[0038] Figure 1 This is a schematic diagram of a conventional two-edge counting circuit implemented using dual D flip-flops in the prior art. (Refer to...) Figure 1 The conventional dual-edge counter 100 includes a first inverter 101, a first NAND gate 102, a second NAND gate 103, a first D flip-flop 104, a second D flip-flop 105, an XOR gate 106, and a counter 107.

[0039] Reference Figure 1The input terminals of the first inverter 101 and the first input terminal of the second NAND gate 103 are connected to a clock signal. The second input terminals of the first NAND gate 102 and the second input terminals of the second NAND gate 103 are connected to a counting control signal. The output terminal of the first inverter 101 is connected to the input terminal of the first NAND gate 102. The output terminal of the first NAND gate 102 is connected to the clock terminal of the first D flip-flop 104. The data input terminal of the first D flip-flop 104 is connected to the inverted output terminal of the first D flip-flop 104. The non-inverted output terminal of the first D flip-flop 104 is connected to the first input terminal of the XOR gate 106. The output terminal of the second NAND gate 106 is connected to the clock terminal of the second D flip-flop 105. The data input terminal of the second D flip-flop 105 is connected to the inverted output terminal of the second D flip-flop 105. The non-inverted output terminal of the second D flip-flop 105 is connected to the second input terminal of the XOR gate 106. The output terminal of the XOR gate 106 is used to output the least significant bit counted by the conventional dual-edge counting circuit 100.

[0040] Reference Figure 1 The counter 107 is a three-bit binary asynchronous counter, comprising a third D flip-flop 1071, a fourth D flip-flop 1072, and a fifth D flip-flop 1073. The output of the XOR gate 106 is connected to the clock input of the third D flip-flop 1071. The data input of the third D flip-flop 1071 is connected to its inverted output. The non-inverted output of the third D flip-flop 1071 is connected to the clock input of the fourth D flip-flop 1072. The data input of the fourth D flip-flop 1072 is connected to its inverted output. The non-inverted output of the fourth D flip-flop 1072 is connected to the clock input of the fifth D flip-flop 1073. The data input of the fifth D flip-flop 1073 is connected to its inverted output.

[0041] Figure 2 This is a timing diagram for a conventional two-edge counting circuit implemented using dual D flip-flops in existing technology. (Refer to...) Figure 1 and Figure 2CLK is the clock signal, CTR_EN is the counting control signal, CLK_ACT_B is the output signal of the first NAND gate 102, CLK_ACT is the output signal of the second NAND gate 103, CNT1 is the output signal of the non-inverting output of the first D flip-flop 104, CNT2 is the output signal of the non-inverting output of the second D flip-flop 105, and D... <0> The output signal of the XOR gate 106 is the least significant bit counted by the conventional dual-edge counting circuit 100, D. <1> The inverting output of the third D flip-flop 1071 outputs a signal, which is the second bit counted by the conventional dual-edge counting circuit 100. <2> The output signal is the inverted output of the fourth D flip-flop 1072, which is the third bit counted by the conventional dual-edge counting circuit 100. <3> The signal is output to the inverted output terminal of the fifth D flip-flop 1073, which is the fourth bit counted by the conventional dual-edge counting circuit 100.

[0042] To address the problems existing in the prior art, embodiments of the present invention provide a dual-edge counting circuit, referring to... Figure 3 and Figure 4 The dual-edge counting circuit 200 includes a logic circuit 201, a latch 202, and a counter 203.

[0043] Reference Figure 3 and Figure 4 The logic circuit 201 receives a clock signal and a counting control signal, and then performs logical operations on the clock signal and the counting control signal to obtain a first reset signal and a first set signal. The latch 202 is connected to the logic circuit 201. The reset terminal of the latch 202 receives the first reset signal, the set terminal of the latch 202 receives the first set signal, and the inverting output terminal of the latch 202 outputs the least significant bit of the dual-edge counting circuit 200. The counter 203 is connected to the non-inverting output terminal of the latch 202 and is used to output the other bits of the dual-edge counting circuit 200.

[0044] Reference Figure 3The logic circuit 201 includes a first inverter 2011, a second inverter 2012, a first NAND gate 2013, and a second NAND gate 2014. The input terminal of the first inverter 2011 and the first input terminal of the second NAND gate 2013 receive the clock signal. The second input terminal of the first NAND gate 2013 and the second input terminal of the second NAND gate 2014 receive the counting control signal. The output terminal of the first inverter 2011 is connected to the first input terminal of the first NAND gate 2013. The output terminal of the first NAND gate 2013 is connected to the input terminal of the second inverter 2012. The output terminal of the second inverter 2012 outputs the first reset signal, and the output terminal of the second NAND gate 2014 outputs the first set signal.

[0045] Reference Figure 4 The logic circuit 201 includes a first inverter 2011, a first NAND gate 2013, a second NAND gate 2014, a third NAND gate 2015, and an AND gate 2016. The input terminal of the first inverter 2011 and the first input terminal of the second NAND gate 2014 receive the clock signal. The second input terminals of the first NAND gate 2013 and the second NAND gate 2014 are connected to the counting control signal. The output terminal of the first inverter 2011 is connected to the first input terminal of the first NAND gate 2013. The output terminal of the first NAND gate 2013 is connected to the first input terminal of the third NAND gate 2015. The second input terminal of the third NAND gate 2015 is connected to a second reset signal. The output terminal of the third NAND gate 2015 outputs the first reset signal. The output terminal of the second NAND gate 2014 is connected to the first input terminal of the AND gate 2016. The second input terminal of the AND gate 2016 is connected to a second set signal. The output terminal of the AND gate 2016 outputs the first set signal.

[0046] Figure 5This is a circuit diagram of a latch in some embodiments of the present invention. Referring to 5, the latch 202 includes a third inverter 2021, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first NMOS transistor MN1, a second NMOS transistor MN2, and a third NMOS transistor MN3. The source of the first PMOS transistor MP1 and the source of the second PMOS transistor MP2 are connected to the power supply voltage. The gate of the first PMOS transistor MP1 and the gate of the third NMOS transistor MN3 are connected to the first set signal. The gate of the second PMOS transistor MP1 and the gate of the first NMOS transistor MN1 are connected to the first reset signal. The drain of the first PMOS transistor MP1 and the drain of the third PMOS transistor MP3 are connected to the first set signal. The drain of the first NMOS transistor MN1, the drain of the second NMOS transistor MN2, and the input terminal of the third inverter 2021 are connected to form the non-inverting output terminal Q of the latch 202. The drain of the second PMOS transistor MP2 is connected to the source of the third PMOS transistor MP3. The gate of the third PMOS transistor MP3 is connected to the gate of the second NMOS transistor MN2 and the output terminal of the third inverter 2021 to form the inverting output terminal QN of the latch 202. The source of the first NMOS transistor MN1 is connected to the source of the second NMOS transistor MN2 and the drain of the third NMOS transistor MN3. The source of the third NMOS transistor MN3 is grounded.

[0047] Reference Figure 5 The third inverter 2021 includes a fourth PMOS transistor MP4 and a fourth NMOS transistor MN4. The source of the fourth PMOS transistor MN4 is connected to the power supply voltage, and the source of the fourth NMOS transistor MN4 is grounded. The gate of the fourth PMOS transistor MP4 is connected to the gate of the fourth NMOS transistor MN4, serving as the input terminal of the third inverter 2021. The drain of the fourth PMOS transistor MP4 is connected to the drain of the fourth NMOS transistor MN4, serving as the output terminal of the third inverter 2021.

[0048] In some embodiments, the counter includes at least one D flip-flop connected in stages. The clock input of the first-stage D flip-flop is connected to the non-inverting output of the latch, the clock input of the next-stage D flip-flop is connected to the non-inverting output of the previous-stage D flip-flop, and the inverting output of each stage D flip-flop is connected to its own data input for outputting other bits of the dual-edge counting circuit.

[0049] Reference Figure 3 and Figure 4The counter 203 includes N-1 D flip-flops, where N is greater than or equal to 2. Taking the first three stages of the counter 203 as an example, the first three stages of the counter 203 include a first-stage D flip-flop 2031, a second-stage D flip-flop 2032, and a third-stage D flip-flop 2033. The clock terminal of the first-stage D flip-flop 2031 is connected to the non-inverting output terminal of the latch 202. The clock terminal of the second-stage D flip-flop 2032 is connected to the non-inverting output terminal of the first-stage D flip-flop 2031. The clock terminal of the third-stage D flip-flop 2033 is connected to the non-inverting output terminal of the second-stage D flip-flop. The data input terminal of the first-stage D flip-flop 2031 is connected to the inverting output terminal of the first-stage D flip-flop 2031. The data input terminal of the second-stage D flip-flop 2032 is connected to the inverting output terminal of the second-stage D flip-flop 2032. The data input terminal of the third-stage D flip-flop 2033 is connected to the inverting output terminal of the third-stage D flip-flop 2033.

[0050] Reference Figure 1 and Figure 3 The first-stage D flip-flop 2031, the second-stage D flip-flop 2032, the third-stage D flip-flop 2033, the first D flip-flop 104, the second D flip-flop 105, the third D flip-flop 1071, the fourth D flip-flop 1072, and the fifth D flip-flop 73 have the same structure.

[0051] Figure 6 This is a circuit diagram of the first-stage D flip-flop in some embodiments of the present invention. (Refer to...) Figure 6 The first-stage D flip-flop includes the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, the seventh PMOS transistor MP7, the eighth PMOS transistor MP8, the ninth PMOS transistor MP9, the tenth PMOS transistor MP10, the eleventh PMOS transistor MP11, the twelfth PMOS transistor MP12, the thirteenth PMOS transistor MP13, the fourteenth PMOS transistor MP14, the fifteenth PMOS transistor MP15, the sixteenth PMOS transistor MP16, the fifth NMOS transistor MN5, the sixth NMOS transistor MN6, the seventh NMOS transistor MN7, the eighth NMOS transistor MN8, the ninth NMOS transistor MN9, the tenth NMOS transistor MN10, the eleventh NMOS transistor MN11, the twelfth NMOS transistor MN12, the thirteenth NMOS transistor MN13, the fourteenth NMOS transistor MN14, the fifteenth NMOS transistor MN15, the sixteenth NMOS transistor MN16, and the seventeenth NMOS transistor MN17.

[0052] Reference Figure 6The drain of the fifth PMOS transistor MP5 is connected to the drain of the fifth NMOS transistor MN5, the drain of the seventh PMOS transistor MP7, the drain of the ninth PMOS transistor MP9, the drain of the eighth NMOS transistor MN8, the gate of the tenth PMOS transistor MP10, and the gate of the eleventh NMOS transistor MN11. The source of the fifth NMOS transistor MN5 is connected to the drain of the sixth NMOS transistor MN6. The source of the sixth NMOS transistor MN6 is connected to the drain of the seventh NMOS transistor MN7. The drain of the sixth PMOS transistor MP6 is connected to the source of the seventh PMOS transistor MP7. The drain of the eighth PMOS transistor MP8 is connected to the source of the ninth PMOS transistor MP9. The gate of the eighth PMOS transistor MP8 is connected to... The gate of the ninth NMOS transistor MN9, the drain of the tenth PMOS transistor MP10, the drain of the eleventh NMOS transistor MN11, the drain of the eleventh PMOS transistor MP11, and the drain of the twelfth NMOS transistor MN12 are connected. The source of the eighth NMOS transistor MN8 is connected to the drain of the ninth NMOS transistor MN9. The source of the ninth NMOS transistor MN9 is connected to the drain of the tenth NMOS transistor MN10. The drain of the twelfth PMOS transistor MP12 is connected to the source of the thirteenth PMOS transistor MP13. The source of the thirteenth NMOS transistor MN13 is connected to the drain of the fourteenth NMOS transistor MN14. The source of the fifteenth NMOS transistor MN15 is connected to the drain of the sixteenth NMOS transistor MN16.

[0053] Reference Figure 6 The source of the fifth PMOS transistor MP5, the source of the sixth PMOS transistor MP6, the source of the eighth PMOS transistor MP8, the source of the tenth PMOS transistor MP10, the source of the twelfth PMOS transistor MP12, the source of the fourteenth PMOS transistor MP14, the source of the fifteenth PMOS transistor MP15, and the source of the sixteenth PMOS transistor MP16 are all powered by the power supply voltage.

[0054] Reference Figure 6 The sources of the seventh NMOS transistor MN7, the tenth NMOS transistor MN10, the eleventh NMOS transistor MN11, the fourteenth NMOS transistor MN14, the sixteenth NMOS transistor MN16, and the seventeenth NMOS transistor MN17 are all grounded.

[0055] Reference Figure 6The gates of the seventh PMOS transistor MP7, the eighth NMOS transistor MN8, the thirteenth PMOS transistor MP13, the twelfth NMOS transistor MN12, the sixteenth PMOS transistor MP16, and the seventeenth NMOS transistor MN17 are interconnected and serve as the clock input of the first-stage D flip-flop to receive the clock signal CLK.

[0056] Reference Figure 6 The gates of the fifth NMOS transistor MN5, the ninth PMOS transistor MP9, the eleventh PMOS transistor MP11, and the thirteenth PMOS transistor MP13 are all connected to the drains of the sixteenth PMOS transistor MP16 and the seventeenth NMOS transistor MN17, and are used to receive the inverted clock signal CLK_N.

[0057] Reference Figure 6 The source of the eleventh PMOS transistor MP11 is connected to the source of the twelfth NMOS transistor MN12, the drain of the thirteenth PMOS transistor MP13, the gate of the fourteenth PMOS transistor MP14, and the gate of the sixteenth NMOS transistor MN16, serving as the positive output terminal Q of the first-stage D flip-flop.

[0058] Reference Figure 6 The gate of the twelfth PMOS transistor MP12 is connected to the gate of the fourteenth NMOS transistor MN14, the drain of the fifteenth PMOS transistor MP15, the drain of the fourteenth PMOS transistor MP14, and the drain of the fifteenth NMOS transistor MN15, serving as the inverting output terminal QN of the first-stage D flip-flop.

[0059] Reference Figure 6 The gates of the fifth PMOS transistor MP5, the seventh NMOS transistor MN7, the tenth NMOS transistor MN10, the fifteenth PMOS transistor MP15, and the fifteenth NMOS transistor MN15 are interconnected and serve as the reset terminal of the first-stage D flip-flop to receive the second reset signal RDN.

[0060] Reference Figure 6 The gates of the sixth PMOS transistor MP6 and the sixth NMOS transistor MN6 serve as the data input terminal D of the first-stage D flip-flop.

[0061] Figure 7 This is a timing diagram of a dual-edge counting circuit in some embodiments of the present invention. (Refer to...) Figure 3 and Figure 7Taking the timing of the counter 203 including three D flip-flops as an example, CLK is the clock signal, CTR_EN is the counting control signal, CLK_ACT_B is the output signal of the first NAND gate, CLK_ACT is the output signal of the second NAND gate, and D... <0> The output signal of the XOR NOT gate, i.e., the least significant bit counted by the conventional dual-edge counting circuit, is D. <1> The output signal is the inverted output of the third D flip-flop, which is the second bit counted by the conventional dual-edge counting circuit, D. <2> The output signal is the inverted output of the fourth D flip-flop, which is the third bit counted by the conventional dual-edge counting circuit. <3> The output signal is the inverted output terminal of the fifth D flip-flop, which is the fourth bit counted by the conventional dual-edge counting circuit.

[0062] Reference Figure 3 and Figure 7 When CTR_EN is high, the dual-edge counting circuit increments by 1. CLK_ACT_B is positively correlated with CLK, and CLK_ACT is negatively correlated with CLK. When CLK_ACT is low, CLK_ACT_B is high, the latch 202 is set (its positive output is high, and its negative output is low), and the latch 202 is reset (its positive output is low, and its negative output is high). When CLK_ACT is high, CLK_ACT_B is low, the latch 202 is reset (its positive output is low, and its negative output is high). This achieves the counting of the least significant bit D of the dual-edge counting circuit. <0> By toggling the CLK on both the rising and falling edges, dual-edge counting is achieved.

[0063] Reference Figure 3 and Figure 7 When CTR_EN is low and both CLK_ACT_B and CLK_ACT are high, the latch 202 maintains the current value, thus realizing the latching function. There are no additional unwanted counting actions due to CTR_EN changing from high to low. It can correctly stop counting under the control of CTR_EN while realizing dual-edge counting, and can save the value at the time of counting stop.

[0064] In some embodiments, the reset terminal of each stage of the D flip-flop is connected to a second reset signal, and the set terminal of each stage of the D flip-flop is connected to a second set signal.

[0065] Reference Figure 3 Each stage of the D flip-flop has a reset terminal but no set terminal. (Refer to...) Figure 4 Each stage of the D flip-flop has a reset terminal and a set terminal.

[0066] Reference Figure 3 and Figure 4The second input terminal of the third NAND gate 2015 is connected to the second reset signal RDN. <0> The reset terminal of the first-stage D flip-flop 2031 is connected to the second reset signal RDN. <1> The reset terminal of the second-stage D flip-flop 2032 is connected to the second reset signal RDN. <2> The reset terminal of the third-stage D flip-flop 2033 is connected to RDN. <3> Similarly, the reset terminal of the (N-1)th stage D flip-flop is connected to RDN. <n-1>.

[0067] Reference Figure 4 The second input terminal of the AND gate 2016 is connected to the second set signal SDN. <0> The set terminal of the first-stage D flip-flop 2031 is connected to the second set signal SDN. <1> The set terminal of the second-stage D flip-flop 2032 is connected to the second set signal SDN. <2> The set terminal of the third-stage D flip-flop 2033 is connected to the second set signal SDN. <3> Similarly, the set input of the (N-1)th stage D flip-flop is connected to the second set signal SDN. <n-1>.

[0068] Reference Figure 1 , Figure 3 and Figure 4 The present application replaces the first D flip-flop 104 and the second D flip-flop 105 in the traditional dual-edge counting circuit with a latch 202. The latch 202 has fewer components and fewer high-frequency nodes compared to the first D flip-flop 104 and the second D flip-flop 105, which greatly reduces the occupied area and power consumption.

[0069] Figure 8 This is a circuit diagram of an image sensor in some embodiments of the present invention. (Refer to...) Figure 8 The image sensor 300 includes a pixel unit array 301, a ramp signal generation unit 302, and at least one readout circuit 303. The pixel unit array 301 is used to sense light to generate a voltage signal VIN, the ramp signal generation unit 302 is used to generate a ramp signal VRAMP, and the readout circuit 303 is connected to the pixel unit array 301 and the ramp signal generation unit 302.

[0070] Reference Figure 8 The image sensor 300 also includes a storage and readout unit 304, along with all the readout circuits 303, for storing and reading out digital signals.

[0071] Figure 9 This is a circuit diagram of the readout circuit in some embodiments of the present invention. (Refer to...) Figure 9 The readout circuit 303 includes a comparator 3031 and a dual-edge counting circuit 200. The dual-edge counting circuit 200 is connected to the output of the comparator 3031, and the output of the comparator 3031 controls the counting of the dual-edge counting circuit.

[0072] Reference Figure 9 The readout circuit 303 further includes a first capacitor 3032 and a second capacitor 3033. One end of the first capacitor 3032 is connected to the pixel unit array for receiving the voltage signal VIN, and the other end of the first capacitor 3032 is connected to the non-inverting input of the comparator 3031. One end of the second capacitor 3033 is connected to the ramp signal generating unit for receiving the ramp signal VRAMP, and the other end of the second capacitor 3033 is connected to the inverting input of the comparator 3031.

[0073] While embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations fall within the scope and spirit of the invention as set forth in the claims. Furthermore, the invention described herein may have other embodiments and can be implemented or carried out in various ways.

Claims

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The double-edge counting circuit of claim 1, wherein, The latch comprises a third inverter, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor and a third NMOS transistor, the source of the first PMOS transistor and the source of the second PMOS transistor are connected to a power voltage, the gate of the first PMOS transistor and the gate of the third NMOS transistor are connected to the first set signal, the gate of the second PMOS transistor and the gate of the first NMOS transistor are connected to the first reset signal, the drain of the first PMOS transistor is connected to the drain of the third PMOS transistor, the drain of the first NMOS transistor, the drain of the second NMOS transistor and the input of the third inverter, serving as a non-inverted output of the latch, the drain of the second PMOS transistor is connected to the source of the third PMOS transistor, the gate of the third PMOS transistor is connected to the gate of the second NMOS transistor and the output of the third inverter, serving as an inverted output of the latch, the source of the first NMOS transistor is connected to the source of the second NMOS transistor and the drain of the third NMOS transistor, and the source of the third NMOS transistor is connected to ground.

3. The double-edge counting circuit of claim 2, wherein, The third inverter comprises a fourth PMOS transistor and a fourth NMOS transistor, the source of the fourth PMOS transistor is connected to a power voltage, the source of the fourth NMOS transistor is connected to ground, the gate of the fourth PMOS transistor is connected to the gate of the fourth NMOS transistor, serving as an input of the third inverter, and the drain of the fourth PMOS transistor is connected to the drain of the fourth NMOS transistor, serving as an output of the third inverter.

4. The double-edge counting circuit of claim 1, wherein, The counter comprises at least one D flip-flop, the D flip-flops are connected in sequence, the clock terminal of the D flip-flop of the first stage is connected to the non-inverted output of the latch, the clock terminal of the D flip-flop of the next stage is connected to the non-inverted output of the D flip-flop of the previous stage, the inverted output of the D flip-flop of each stage is connected to the data input terminal of itself, for outputting other bits of the double-edge counting circuit, and the reset terminal of the D flip-flop of each stage is connected to a second reset signal.

5. The double-edge counting circuit of claim 4, wherein, The set terminal of the D flip-flop of each stage in the counter is connected to a second set signal.

6. A sense circuit, comprising: It comprises: a comparator, and the double-edge counting circuit according to any one of claims 1-5, connected to the output of the comparator.

7. An image sensor, characterized by It comprises: a pixel unit array, for light sensing to generate a voltage signal; a slope signal generating unit, for generating a slope signal; and at least one readout circuit according to claim 6, connected to the pixel unit array and the slope signal generating unit. ​

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