A voltage regulation system, system on chip, and voltage regulation method

Abstract

The embodiment of the application discloses a voltage regulating system, a system on chip and a voltage regulating method, which are used for providing adjustable working voltage for the system on chip, and taking into account the initialization requirement and high-performance scene requirement of the system on chip. The voltage regulating system comprises the system on chip and a power supply chip. The system on chip is used for outputting a first PWM digital signal and a second PWM digital signal. The power supply chip is coupled with the system on chip, and is used for obtaining an output voltage signal according to a first duty cycle of the first PWM digital signal, a second duty cycle of the second PWM digital signal and a reference voltage of the power supply chip. The output voltage signal is used for providing an input voltage for the system on chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip technical field, and particularly to a voltage regulation system, a system on chip and a voltage regulation method. BACKGROUND

[0002] A system on chip (SoC) is an integrated circuit for implementing a specific function, which contains complete system hardware and embedded software. In order to comprehensively consider performance and power consumption, different working voltages need to be provided for the processor inside the SoC in different working scenarios.

[0003] The existing SoC voltage regulation scheme can be as shown in Figure 1 In this scheme, the SoC outputs a pulse width modulation (PWM) digital signal with adjustable duty cycle, and different duty cycles correspond to different analog voltage values. The SoC adjusts the power chip through the output PWM digital signal, so that the output voltage signal of the power chip is output after the peripheral circuit, and the working voltage required by the processor inside the SoC is output.

[0004] In actual application, the Vout input into the SoC needs to meet the working requirements of different application scenarios of the SoC: 1, the minimum value of the Vout cannot be lower than the minimum voltage V1 required by the processor; 2, in order to meet the high performance scenario requirement of the processor, the maximum value of the Vout cannot be lower than the working voltage V2 required by the processor in the high performance scenario; 3, in the initialization process of the SoC, an intermediate voltage value V3 between V1 and V2 needs to be provided for the processor to meet the initialization requirement of the SoC.

[0005] Therefore, the Figure 1The scheme shown has the following problems: during the initialization process of the SoC, the duty cycle of the PWM digital signal cannot be set, and the PWM pin can only output a high level (equivalent to a duty cycle of 1) or a low level (equivalent to a duty cycle of 0). When the PWM pin outputs a high level, the value of Vout is minimum. In actual application, the value of Vout when the PWM pin outputs a high level needs to be greater than V1 to meet the minimum voltage requirement of the SoC, but since the value of Vout when the PWM pin outputs a high level is much smaller than V3, the value of Vout cannot be used as the working voltage during the initialization of the SoC. When the PWM pin outputs a low level, the value of Vout is maximum. If the value of Vout when the PWM pin outputs a low level is set to V3, the initialization requirement of the SoC can be met, but since the value of Vout when the PWM pin outputs a low level is the maximum voltage that the SoC can provide, the SoC cannot provide the working voltage V2 (V2 is greater than V3) required in a high-performance scenario, and therefore, the processor cannot support the work in a high-performance scenario. If the value of Vout when the PWM pin outputs a low level is set to V2, then during the initialization process, the value of Vout is not equal to V3 (V3 is less than V2), which makes it difficult to meet the initialization requirement of the SoC, and the SoC initialization fails.

[0006] Therefore, the SoC voltage regulation scheme provided by the prior art has the problem that the initialization requirement and the high-performance scenario requirement are difficult to be met. SUMMARY

[0007] Embodiments of the present application provide a voltage regulation system, a system on chip, and a voltage regulation method, which are used to provide a tunable working voltage for a system on chip, and meet the initialization requirement and the high-performance scenario requirement of the system on chip.

[0008] In a first aspect, embodiments of the present application provide a voltage regulation system, which includes: a system on chip and a power supply chip. The system on chip is configured to output a first PWM digital signal and a second PWM digital signal. The power supply chip is coupled to the system on chip and configured to obtain an output voltage signal according to a first duty cycle of the first PWM digital signal, a second duty cycle of the second PWM digital signal, and a reference voltage of the power supply chip. The output voltage signal is used to provide an input voltage for the system on chip.

[0009] The system provided in the first aspect can output two PWM digital signals, i.e., the first PWM digital signal and the second PWM digital signal. When the system on chip is initialized, the first PWM digital signal can be configured to be at a high level (equivalent to a duty cycle of 1) or at a low level (equivalent to a duty cycle of 0), and the second PWM digital signal can also be configured to be at a high level or at a low level. Therefore, the output of the system on chip can be configured in four combinations, and the input voltage provided by the power chip for the system on chip can also have four combinations. Then, the maximum value of the input voltage of the system on chip is set as the working voltage V2 required in the high-performance scenario, the minimum value of the input voltage of the system on chip is set as a value greater than the minimum voltage V1 required by the processor, and the intermediate value of the input voltage of the system on chip is set as the working voltage V3 required when the system on chip is initialized, so that the initialization requirement and the high-performance scenario requirement of the system on chip can be met. After the system on chip is initialized, the system on chip can output the first PWM digital signal with an adjustable duty cycle and the second PWM digital signal with an adjustable duty cycle to instruct the power chip to adjust the output voltage signal, so that the system on chip obtains the desired working voltage. Therefore, the voltage regulating system provided in the embodiments of the present application can provide an adjustable working voltage for the system on chip when the system on chip is normally working, and can also meet the initialization requirement and the high-performance scenario requirement of the system on chip.

[0010] Specifically, when the first PWM digital signal is at a low level and the second PWM digital signal is at a high level, the input voltage provided by the output voltage signal for the system on chip is the working voltage of the system on chip in the initialization scenario; or when the first PWM digital signal is at a high level and the second PWM digital signal is at a low level, the input voltage provided by the output voltage signal for the system on chip is the working voltage of the system on chip in the initialization scenario.

[0011] Generally, the smaller the first duty cycle of the first PWM digital signal output by the system on chip, the greater the input voltage provided by the power chip for the system on chip; similarly, the smaller the second duty cycle of the second PWM digital signal output by the system on chip, the greater the input voltage provided by the power chip for the system on chip. Therefore, in the initialization scenario, one of the first PWM digital signal and the second PWM digital signal is configured to be at a high level and the other is configured to be at a low level.

[0012] Specifically, when the first PWM digital signal and the second PWM digital signal are both at a low level, the input voltage provided by the output voltage signal for the system on chip is the working voltage of the system on chip in the high-performance scenario; or when the first duty cycle is less than the first preset value and the second duty cycle is less than the second preset value, the input voltage provided by the output voltage signal for the system on chip is the working voltage of the system on chip in the high-performance scenario.

[0013] The first preset value and the second preset value can be configured according to requirements, and the values of the first preset value and the second preset value can be the same or different. As described above, the smaller the first duty cycle and the second duty cycle, the greater the input voltage provided by the power chip for the system on chip. In a high-performance scenario, the operating voltage required by the system on chip is relatively high. At this time, the first duty cycle can be less than the first preset value, the second duty cycle can be less than the second preset value, or the first duty cycle and the second duty cycle can be zero (i.e., the first PWM digital signal and the second PWM digital signal are both low), so that the system on chip obtains a relatively high input voltage as the operating voltage in the high-performance scenario.

[0014] In a possible design, the voltage regulation system provided by the first aspect further includes a peripheral circuit. The peripheral circuit is configured to convert the first PWM digital signal into a first feedback signal, and convert the second PWM digital signal into a second feedback signal. The peripheral circuit is further configured to obtain a third feedback signal by dividing the input voltage of the system on chip, and feed back the first feedback signal, the second feedback signal, and the third feedback signal to the power chip. Then, the power chip is specifically configured to obtain an output voltage signal according to the first feedback signal, the second feedback signal, the third feedback signal, and a reference voltage of the power chip.

[0015] By using the above scheme, the peripheral circuit can provide feedback signals for the power chip, so that the power chip adjusts the reference voltage according to the feedback signals to obtain the output voltage signal.

[0016] Specifically, the peripheral circuit can include: a first filter circuit configured to convert the first PWM digital signal into the first feedback signal, and feed back the first feedback signal to a feedback voltage input end of the power chip; a second filter circuit configured to convert the second PWM digital signal into the second feedback signal, and feed back the second feedback signal to the feedback voltage input end; and a voltage dividing circuit configured to obtain the third feedback signal by dividing the input voltage, and feed back the third feedback signal to the feedback voltage input end.

[0017] By using the above scheme, the first filter circuit, the second filter circuit, and the voltage dividing circuit provide the first feedback signal, the second feedback signal, and the third feedback signal for the power chip, respectively.

[0018] In a possible design, the voltage dividing circuit includes a first resistor and a second resistor, a first end of the first resistor is coupled with a port of the system-on-chip for receiving an input voltage, a second end of the first resistor is coupled with the feedback voltage input end and a first end of the second resistor, and a second end of the second resistor is coupled with a ground end; the first filter circuit includes a third resistor, a fourth resistor and a first capacitor, a first end of the third resistor is coupled with a port of the system-on-chip for outputting a first PWM digital signal, a second end of the third resistor is coupled with a first end of the first capacitor and a first end of the fourth resistor, a second end of the fourth resistor is coupled with the feedback voltage input end, and a second end of the first capacitor is coupled with the ground end; the second filter circuit includes a fifth resistor, a sixth resistor and a second capacitor, a first end of the fifth resistor is coupled with a port of the system-on-chip for outputting a second PWM digital signal, a second end of the fifth resistor is coupled with a first end of the second capacitor and a first end of the sixth resistor, a second end of the sixth resistor is coupled with the feedback voltage input end, and a second end of the second capacitor is coupled with the ground end.

[0019] With the above scheme, a specific structure of the peripheral circuit is provided.

[0020] In addition, the peripheral circuit can further include an output filter circuit, coupled with the voltage output end of the power supply chip, configured to perform filtering processing on the output voltage signal to obtain the input voltage of the system-on-chip.

[0021] With the above scheme, the output filter circuit can perform filtering processing on the output voltage signal to provide a stable input voltage for the system-on-chip.

[0022] In a second aspect, the embodiments of the present application further provide a system-on-chip, configured to: output a first PWM digital signal and a second PWM digital signal; receive an input voltage of the system-on-chip provided by a power supply chip, and work under the driving of the input voltage of the system-on-chip, wherein the input voltage is obtained by the power supply chip according to a first duty cycle of the first PWM digital signal, a second duty cycle of the second PWM digital signal and a reference voltage of the power supply chip.

[0023] In a possible design, when the first PWM digital signal is at a low level and the second PWM digital signal is at a high level, or the first PWM digital signal is at a high level and the second PWM digital signal is at a low level, the input voltage is a working voltage of the system-on-chip in an initialization scenario.

[0024] In a possible design, when the first PWM digital signal and the second PWM digital signal are both at a low level, or the first duty cycle is less than a first preset value and the second duty cycle is less than a second preset value, the input voltage is a working voltage of the system-on-chip in a high-performance scenario.

[0025] It should be noted that the system on chip provided in the second aspect can be regarded as the system on chip in the voltage regulation system provided in the first aspect, and the specific structure, functions and technical effects thereof can be referred to the related description in the first aspect, which will not be described here.

[0026] In a third aspect, the embodiments of the present application further provide a voltage regulation method, which comprises: a voltage regulation system obtaining a first PWM digital signal and a second PWM digital signal; the voltage regulation system obtaining an output voltage signal according to a first duty cycle of the first PWM digital signal, a second duty cycle of the second PWM digital signal and a reference voltage of a power supply chip, the output voltage signal being used to provide an input voltage for a system on chip.

[0027] In a possible design, when the first PWM digital signal is at a low level and the second PWM digital signal is at a high level, the input voltage provided by the output voltage signal for the system on chip is a working voltage of the system on chip in an initialization scenario; or, when the first PWM digital signal is at a high level and the second PWM digital signal is at a low level, the input voltage provided by the output voltage signal for the system on chip is the working voltage of the system on chip in the initialization scenario.

[0028] In a possible design, when the first PWM digital signal and the second PWM digital signal are both at a low level, the input voltage provided by the output voltage signal for the system on chip is a working voltage of the system on chip in a high-performance scenario; or, when the first duty cycle is less than a first preset value and the second duty cycle is less than a second preset value, the input voltage provided by the output voltage signal for the system on chip is the working voltage of the system on chip in the high-performance scenario.

[0029] Specifically, the voltage regulation system obtains the output voltage signal according to the first duty cycle of the first PWM digital signal, the second duty cycle of the second PWM digital signal and the reference voltage of the power supply chip, which can be implemented in the following manner: converting the first PWM digital signal into a first feedback signal; converting the second PWM digital signal into a second feedback signal; obtaining a third feedback signal by dividing the input voltage of the system on chip; and obtaining the output voltage signal according to the first feedback signal, the second feedback signal, the third feedback signal and the reference voltage of the power supply chip.

[0030] In a possible design, the output voltage signal is used to provide the input voltage for the system on chip, specifically comprising: performing filtering processing on the output voltage signal to obtain the input voltage of the system on chip.

[0031] It should be noted that the voltage regulation method provided in the third aspect can be regarded as a method performed by the voltage regulation system provided in the first aspect, and the specific implementation manner and technical effects thereof can be referred to the related description in the first aspect, which will not be described here.

[0032] In a fourth aspect, an embodiment of the present application provides a system on chip, comprising: a direct current power supply, a first resistor, a first switch tube, a second switch tube, a second resistor, and a PWM controller; the direct current power supply is coupled with a first end of the first resistor; a second end of the first resistor is coupled with a first end of the first switch tube; a second end of the first switch tube is coupled with a first end of the second switch tube, the PWM controller, and a power supply chip outside the system on chip; a second end of the second switch tube is coupled with a first end of the second resistor; a second end of the second resistor is coupled with a ground terminal; the power supply chip is configured to adjust an output voltage signal according to an output signal of the system on chip; the output voltage signal is configured to provide a working voltage for the system on chip; and when the system on chip is initialized, the first switch tube and the second switch tube are turned on, and the PWM controller is in a high resistance state.

[0033] With the above scheme, when the system on chip is initialized, the output of the PWM controller is zero, the output of the PWM controller has no effect on the power supply chip, and the system on chip provides, to the power supply chip, a voltage obtained by dividing the output voltage of the direct current power supply by the first resistor and the second resistor. The voltage can be adjusted by the output voltage of the direct current power supply, the resistance value of the first resistor, and the resistance value of the second resistor, so that the output voltage signal obtained by the power supply chip adjusting the reference voltage according to the voltage can meet the initialization requirement of the system on chip.

[0034] In a possible design, when the system on chip is working normally, the first switch tube and the second switch tube are turned off, and the PWM controller outputs a PWM digital signal.

[0035] With the above scheme, when the system on chip is working normally, the first switch tube and the second switch tube are turned off, and the direct current power supply, the first resistor, and the second resistor no longer work. The system on chip provides, to the power supply chip, a PWM digital signal output by the PWM controller. The power supply chip can adjust the output voltage signal according to the duty cycle of the PWM digital signal, so that the output voltage signal can meet the working voltage requirement of the system on chip in the normal working state. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 A schematic diagram of a voltage regulation scheme of a system on chip provided by the prior art;

[0037] Figure 2 A structural schematic diagram of a voltage regulation system provided by the prior art;

[0038] Figure 3 A structural schematic diagram of a first voltage regulation system provided by an embodiment of the present application;

[0039] Figure 4 A structural schematic diagram of a second voltage regulation system provided by an embodiment of the present application;

[0040] Figure 5 This is a schematic diagram of the structure of the third voltage regulating system provided in the embodiments of this application;

[0041] Figure 6 This is a schematic diagram of the structure of the fourth voltage regulating system provided in the embodiments of this application;

[0042] Figure 7 This is a schematic diagram of the structure of the fifth voltage regulating system provided in the embodiments of this application;

[0043] Figure 8 A schematic flowchart illustrating a voltage regulation method provided in an embodiment of this application;

[0044] Figure 9 This is a schematic diagram of a system-on-a-chip provided in an embodiment of this application. Detailed Implementation

[0045] As described in the background section, in existing SoC voltage regulation schemes, the SoC outputs a PWM digital signal with an adjustable duty cycle. Different duty cycles correspond to different voltage values. The SoC uses the output PWM digital signal to regulate the power supply chip, so that the power supply chip's output voltage signal, after passing through external circuitry, outputs the operating voltage required by the SoC's internal processor. Specifically, the PWM digital signal is converted into a corresponding voltage value by the external circuitry and output to the power supply chip. The power supply chip adjusts the reference voltage according to this voltage value to obtain the output voltage. This output voltage is then filtered by the external circuitry to obtain the operating voltage Vout required by the SoC's internal processor.

[0046] Specifically, adopt Figure 1 The voltage regulation scheme shown can be illustrated by the following structural diagram of the voltage regulation system: Figure 2 As shown. In Figure 2 In the voltage regulation system shown, the power chip includes an error amplifier and a voltage output circuit, and the peripheral circuit consists of resistors R1, R2, R3, R4, inductor L, capacitor C1, and capacitor C2.

[0047] The PWM digital signal output by the SoC is filtered by R3, R4 and C2 to obtain a feedback signal Vpwm, which is input to the inverting input terminal of the error amplifier; the input voltage Vout of the SoC is divided by R1 and R2 to obtain a feedback signal, which is input to the inverting input terminal of the error amplifier; the non-inverting input terminal of the error amplifier is connected to a reference voltage source for inputting a reference voltage Vref, and the inverting input terminal is used as a feedback input terminal; the error amplifier is used to output the voltage difference between the input voltage of the feedback input terminal and the reference voltage of the reference voltage source; it should be understood that the error amplifier adjusts the reference voltage signal input to the non-inverting input terminal based on the feedback signal input to the inverting input terminal, and the voltage difference output by the error amplifier is the adjusted voltage signal; the input terminal of the voltage output circuit is connected to the output terminal of the error amplifier to obtain the voltage difference, and the voltage output circuit processes the voltage difference output by the error amplifier to obtain an output voltage signal, which is filtered by L and C1 to obtain Vout and provided to the SoC.

[0048] As can be seen, when the duty cycle of the PWM digital signal output by the SoC changes, the voltage value of the feedback signal Vpwm obtained by filtering the PWM digital signal by R3, R4 and C2 also changes, and since the feedback signal Vpwm is the feedback signal of the error amplifier, the change in Vpwm will also affect the output voltage signal of the power supply chip, ultimately leading to a change in Vout. Therefore, the SoC can indicate the operating voltage required by the processor inside it through the output PWM digital signal, and thus obtain the desired Vout.

[0049] The output voltage Vout is determined according to the following formula:

[0050] Vout = Vref·(1+R1 / R2) + (Vref-Vpwm)(R1 / (R3+R4))

[0051] As can be seen from the above formula, Vref, R1, R2, R3 and R4 are all constants, so Vout is controlled by Vpwm converted from the PWM digital signal, i.e. controlled by the duty cycle of the PWM digital signal.

[0052] In addition, as can be seen from the above formula, the greater the duty cycle of the PWM digital signal, the greater the value of Vpwm, and the smaller the value of Vout.

[0053] Therefore, the PWM digital signal output by the SoC is controlled by the duty cycle of the PWM digital signal, and the output voltage Vout of the power supply chip is controlled by the duty cycle of the PWM digital signal. Figure 2The voltage regulation system shown has the following problem: during the initialization process of the SoC, the duty cycle of the PWM digital signal cannot be set, and the PWM pin can only output a high level (equivalent to a duty cycle of 1) or a low level (equivalent to a duty cycle of 0). When the PWM pin outputs a low level, the value of Vout is maximum. If the value of Vout when the PWM pin outputs a low level is set as the initialization voltage of the SoC, although the initialization demand of the SoC can be met, since the value of Vout when the PWM pin outputs a low level is the maximum value of Vout that can be provided by the power supply chip, the power supply chip cannot provide a voltage higher than the initialization voltage during the normal working process of the SoC, and thus it is difficult to meet the voltage demand of the SoC in a high-performance scenario; if the value of Vout when the PWM pin outputs a low level is set as the working voltage of the SoC in a high-performance scenario, then during the initialization process, the working voltage in the high-performance scenario is high, so that the SoC cannot complete initialization.

[0054] Based on the above problem, the embodiment of the present application provides a voltage regulation system, a system on chip and a voltage regulation method, which are used to provide an adjustable working voltage for a system on chip, and take into account the initialization demand and high-performance scenario demand of the system on chip.

[0055] The embodiments of the present application will be described in detail below with reference to the drawings.

[0056] Referring to Figure 3 The voltage regulation system provided by the embodiment of the present application has a structure as shown in the figure. The voltage regulation system 300 includes a system on chip 301 and a power supply chip 302.

[0057] The system on chip 301 is configured to output a first PWM digital signal and a second PWM digital signal; the power supply chip 302 is coupled with the system on chip 301, and is configured to obtain an output voltage signal according to a first duty cycle of the first PWM digital signal, a second duty cycle of the second PWM digital signal and a power supply chip reference voltage, and the output voltage signal is used to provide an input voltage for the system on chip 301.

[0058] The output voltage signal of the power supply chip 302 can be directly used as the input voltage of the system on chip 301, or can be used as the input voltage of the system on chip 301 after processing (such as filtering processing), and the input voltage is the working voltage required by the system on chip 301 in the current scenario.

[0059] The first PWM digital signal and the second PWM digital signal are both PWM digital signals with adjustable duty cycles. The system on chip 301 indicates the power supply chip 302 to adjust the output voltage signal through the first duty cycle of the first PWM digital signal and the second duty cycle of the second PWM digital signal, and then obtains the desired working voltage.

[0060] Exemplarily, assuming that the voltage value of the high level corresponding to the first PWM digital signal is 3.3V and the voltage value of the low level corresponding to the first PWM digital signal is 0V, then the duration of the high level output by the first PWM digital signal in a clock cycle can reflect the size of the first duty cycle. For example, the duration of a clock cycle is 100ms, the first PWM digital signal outputs the high level in the first 50ms and outputs the low level in the last 50ms, then the first duty cycle of the first PWM digital signal in this clock cycle is 50 / 100=0.5; for another example, the duration of a clock cycle is 100ms, the first PWM digital signal outputs the high level in the first 20ms and outputs the low level in the last 80ms, then the first duty cycle of the first PWM digital signal in this clock cycle is 20 / 100=0.2. In an extreme case, the first PWM digital signal outputs 3.3V in a clock cycle, then the first duty cycle of the first PWM digital signal is 1; the first PWM digital signal outputs 0V in a clock cycle, then the first duty cycle of the first PWM digital signal is 0. Of course, the second duty cycle of the second PWM digital signal can also be understood in the same way, which will not be described here.

[0061] It should be noted that in the embodiments of the present application, the voltage value of the low level corresponding to the first PWM digital signal and the second PWM digital signal can both be 0V, and the voltage value of the high level corresponding to the first PWM digital signal and the second PWM digital signal can be the same or different. For example, in one possible case, the voltage value of the high level corresponding to the first PWM digital signal is 3.3V and the voltage value of the high level corresponding to the second PWM digital signal is also 3.3V; in another possible case, the voltage value of the high level corresponding to the first PWM digital signal is 3.3V and the voltage value of the high level corresponding to the second PWM digital signal is 1.8V.

[0062] In actual application, the system on chip 301 can detect its attribute parameters, and generate the first PWM digital signal and the second PWM digital signal based on the detected attribute parameters; wherein the detected attribute parameters are parameters that can reflect the core voltage demand of the system on chip 301, such as the process parameters of the processor, the scene in which the processor runs, etc. The working voltage required by the processor can be obtained according to the attribute parameters. The corresponding relationship between the attribute parameters and the working voltage required by the processor can be a set mapping relationship, and the working voltage corresponding to different attribute parameters is determined in advance through the experience and test of the designer, and then the determined voltage value is identified by the first PWM digital signal with the first duty cycle and the second PWM digital signal with the second duty cycle. The system on chip 301 indicates the working voltage required by the internal processor by outputting the first PWM digital signal and the second PWM digital signal. Specifically, the generation of the first PWM digital signal and the second PWM digital signal can be performed by a PWM controller in the system on chip 301, for example, one PWM controller can generate the first PWM digital signal and the second PWM digital signal, or two PWM controllers can generate the first PWM digital signal and the second PWM digital signal respectively.

[0063] By using the voltage regulating system 300 provided in the embodiments of the present application, since the system on chip 301 outputs two PWM digital signals, i.e. the first PWM digital signal and the second PWM digital signal, when the system on chip 301 is initialized, the first PWM digital signal can be configured to be at high level (equivalent to the duty cycle being 1) or low level (equivalent to the duty cycle being 0), and the second PWM digital signal can also be configured to be at high level or low level. Therefore, the output of the system on chip 301 can be configured in four combinations: 1, the first PWM digital signal is at high level and the second PWM digital signal is at high level; 2, the first PWM digital signal is at high level and the second PWM digital signal is at low level; 3, the first PWM digital signal is at low level and the second PWM digital signal is at high level; and 4, the first PWM digital signal is at low level and the second PWM digital signal is at low level. Correspondingly, the input voltage provided for the system on chip 301 can also have four combinations under the above four combinations. The maximum value of the input voltage of the system on chip 301 corresponding to the four combinations is set as the working voltage V2 required in the high-performance scene, the minimum value of the input voltage of the system on chip 301 corresponding to the four combinations is set as a value greater than V1, and the intermediate value of the input voltage of the system on chip 301 corresponding to the four combinations is set as the working voltage V3 required when the system on chip 301 is initialized, so that the initialization requirement and the high-performance scene requirement of the system on chip 301 can be considered.

[0064] In addition, after the initialization of the system on chip 301 is completed, the system on chip 301 can output the first PWM digital signal with adjustable duty cycle and the second PWM digital signal with adjustable duty cycle to indicate the working voltage required by the processor inside the system on chip 301, so as to obtain the desired working voltage and meet the different working voltage requirements of the processor.

[0065] In summary, by using the voltage regulating system 300 provided in the embodiments of the present application, the adjustable working voltage can be provided for the system on chip 301 when the system on chip 301 is working normally, and in addition, the initialization requirements and high-performance scene requirements of the system on chip 301 can also be taken into account.

[0066] Specifically, when the system on chip 301 is being initialized, the first PWM digital signal and the second PWM digital signal can be configured as follows: when the first PWM digital signal is at low level and the second PWM digital signal is at high level, the output voltage signal of the power supply chip 302 is the input voltage provided for the system on chip 301, which is the working voltage of the system on chip 301 in the initialization scene. Alternatively, when the first PWM digital signal is at high level and the second PWM digital signal is at low level, the output voltage signal of the power supply chip 302 is the input voltage provided for the system on chip 301, which is the working voltage of the system on chip 301 in the initialization scene.

[0067] That is to say, in the initialization scene, one of the first PWM digital signal and the second PWM digital signal is configured at high level and the other is configured at low level.

[0068] Specifically, in the high-performance scene, the first PWM digital signal and the second PWM digital signal can be configured as follows: when the first PWM digital signal and the second PWM digital signal are both at low level, the output voltage signal of the power supply chip 302 is the input voltage provided for the system on chip 301, which is the working voltage of the system on chip 301 in the high-performance scene. Alternatively, when the first duty cycle is less than the first preset value and the second duty cycle is less than the second preset value, the output voltage signal of the power supply chip 302 is the input voltage provided for the system on chip 301, which is the working voltage of the system on chip 301 in the high-performance scene.

[0069] The first preset value and the second preset value can be configured according to requirements, and the values of the first preset value and the second preset value can be the same or different. In one specific example, the first preset value and the second preset value can both be 0.1, or the first preset value is 0.1 and the second preset value is 0.2.

[0070] Generally, the smaller the first duty cycle of the first PWM digital signal output by the system on chip 301, the greater the input voltage provided by the power chip 302 for the system on chip 301; similarly, the smaller the second duty cycle of the second PWM digital signal output by the system on chip 301, the greater the input voltage provided by the power chip 302 for the system on chip 301. Then, in a high-performance scenario, the system on chip 301 requires a higher operating voltage, at which time the first duty cycle can be less than the first preset value, the second duty cycle can be less than the second preset value, or the first duty cycle and the second duty cycle can be zero (i.e., the first PWM digital signal and the second PWM digital signal are both low), so that the system on chip 301 obtains a higher input voltage as the operating voltage in the high-performance scenario.

[0071] In addition, the voltage regulation system 300 can also include a peripheral circuit, as shown in the figure. The peripheral circuit is configured to convert the first PWM digital signal into a first feedback signal, and convert the second PWM digital signal into a second feedback signal. Figure 4

[0072] In the case of different first duty cycles, the voltage value of the first feedback signal converted by the peripheral circuit is also different; similarly, in the case of different second duty cycles, the voltage value of the second feedback signal converted by the peripheral circuit is also different. That is, the first feedback signal is a feedback signal that can reflect the size of the first duty cycle, and the second feedback signal is a feedback signal that can reflect the size of the second duty cycle. Since the system on chip 301 can indicate the operating voltage required by the processor inside it through the first duty cycle and the second duty cycle, the peripheral circuit indicates the first duty cycle and the second duty cycle through the first feedback signal and the second feedback signal respectively, so that the power chip 302 adjusts the output voltage signal according to the first feedback signal and the second feedback signal, and then the input voltage of the system on chip 301 is the operating voltage required by the processor.

[0073] In addition, the peripheral circuit can also be configured to obtain a third feedback signal by dividing the input voltage of the system on chip 301, and feed the first feedback signal, the second feedback signal and the third feedback signal to the power chip 302. Then, the power chip 302 is specifically configured to obtain the output voltage signal according to the first feedback signal, the second feedback signal, the third feedback signal and the power chip reference voltage.

[0074] Specifically, the power chip 302 can adjust the power chip reference voltage according to the first feedback signal, the second feedback signal and the third feedback signal to obtain the output voltage signal.

[0075] ​Based on the functional division of the peripheral circuits described above, it is easy to understand that the peripheral circuits may include a first filter circuit, a second filter circuit, and a voltage divider circuit. Specifically, the first filter circuit converts the first PWM digital signal into a first feedback signal and feeds it back to the feedback voltage input terminal of the power supply chip 302; the second filter circuit converts the second PWM digital signal into a second feedback signal and feeds it back to the feedback voltage input terminal; and the voltage divider circuit divides the input voltage to obtain a third feedback signal and feeds it back to the feedback voltage input terminal.

[0076] In practical applications, filter circuits can be composed of resistors and capacitors, and voltage divider circuits can be implemented using voltage divider resistors.

[0077] In a specific example, the voltage divider circuit may include a first resistor and a second resistor. The first end of the first resistor is coupled to the port of the on-chip system 301 for receiving the input voltage. The second end of the first resistor is coupled to the feedback voltage input terminal and the first end of the second resistor. The second end of the second resistor is coupled to ground. The first filter circuit may include a third resistor, a fourth resistor, and a first capacitor. The first end of the third resistor is coupled to the port of the on-chip system 301 for outputting a first PWM digital signal. The second end of the third resistor is coupled to the first end of the first capacitor and the first end of the fourth resistor. The second end of the fourth resistor is coupled to the feedback voltage input terminal. The second end of the first capacitor is coupled to ground. The second filter circuit includes a fifth resistor, a sixth resistor, and a second capacitor. The first end of the fifth resistor is coupled to the port of the on-chip system 301 for outputting a second PWM digital signal. The second end of the fifth resistor is coupled to the first end of the second capacitor and the first end of the sixth resistor. The second end of the sixth resistor is coupled to the feedback voltage input terminal. The second end of the second capacitor is coupled to ground.

[0078] See Figure 5 ,for Figure 4 A specific example of the voltage regulating system 300 shown is in Figure 5 The example illustrates the specific components of the peripheral circuit. R1 and R2 form a voltage divider circuit, where R1 can be considered the first resistor and R2 the second resistor; R3, R4, and C2 form a first filter circuit, where R3 can be considered the third resistor, R4 the fourth resistor, and C2 the first capacitor; R5, R6, and C3 form a second filter circuit, where R5 can be considered the fifth resistor, R6 the sixth resistor, and C3 the second capacitor.

[0079] In addition, Figure 5In the voltage regulation system 300 shown, the peripheral circuitry may further include an output filter circuit. This output filter circuit is coupled to the voltage output terminal of the power supply chip 302 and is used to filter the output voltage signal of the power supply chip 302 to obtain the input voltage of the on-chip system 301. For example, this output filter circuit may consist of an inductor L and a capacitor C1, such as... Figure 5 As shown.

[0080] and Figure 2 The voltage regulating system shown is similar, in Figure 5 In the voltage regulation system shown, the power supply chip may include an error amplifier and a voltage output circuit, specifically as follows: Figure 6 As shown.

[0081] Among them, the first PWM digital signal output by the system-on-chip 301 ( Figure 6 (Illustrated by PWM0) After filtering by R3, R4 and C2, the first feedback signal Vpwm0 is obtained. Vpwm0 serves as the inverting input of the first feedback signal into the error amplifier; the second PWM digital signal output by the system-on-chip 301 (… Figure 6 (Illustrated using PWM1) After filtering by R5, R6, and C3, the second feedback signal Vpwm1 is obtained. Vpwm1 serves as the inverting input of the second feedback signal to the error amplifier. The input voltage Vout of the system-on-chip 301 is divided by R1 and R2 and serves as the inverting input of the third feedback signal to the error amplifier. The non-inverting input of the error amplifier is connected to a reference voltage source and is used to input the reference voltage Vref. The inverting input serves as the feedback input, and the error amplifier outputs the voltage difference between the input voltage at the feedback input and the reference voltage source. It should be understood that the error amplifier adjusts the reference voltage signal at the non-inverting input based on the feedback signal input at the inverting input. The voltage difference output by the error amplifier is the adjusted voltage signal. The input of the voltage output circuit is connected to the output of the error amplifier to obtain this voltage difference. The voltage output circuit processes the voltage difference output by the error amplifier to obtain the output voltage signal. This output voltage signal is filtered by L and C1 to obtain Vout, which is provided to the system-on-chip 301.

[0082] It is understandable that when the first duty cycle of PWM0 output by the system on chip 301 changes, the voltage value of the first feedback signal Vpwm0 obtained after PWM0 is filtered by R3, R4 and C2 also changes; when the second duty cycle of PWM1 output by the system on chip 301 changes, the voltage value of the second feedback signal Vpwm1 obtained after PWM1 is filtered by R5, R6 and C3 also changes. Since Vpwm0 and Vpwm1 are feedback signals of the error amplifier, the changes of Vpwm0 and Vpwm1 will affect the output voltage signal of the power supply chip 302, and ultimately cause Vout to change. Therefore, the system on chip 301 can indicate the operating voltage required by the processor inside it through the output PWM0 and PWM1, and then obtain the desired Vout.

[0083] Specifically, the output voltage Vout is determined as follows:

[0084] Vout = Vdc + AV0 + AV1

[0085] Wherein, Vdc = Vref * (1 + R1 / R2), the value of Vdc depends on the characteristics of the power supply chip 302 and is a fixed value.

[0086] AV0 = (Vref-Vpwm0) * R1 / (R3+R4), AV0 changes with the first duty cycle set by the system on chip 301.

[0087] AV1 = (Vref-Vpwm1) * R1 / (R5+R6), AV1 changes with the second duty cycle set by the system on chip 301.

[0088] It is not difficult to see that the smaller the value of Vpwm0 is, the larger the value of Vout is; and Vpwm0 is obtained after PWM0 is filtered by R3, R4 and C2, the smaller the first duty cycle of PWM0 is, the smaller the value of Vpwm0 is. Therefore, the smaller the first duty cycle is, the larger the value of Vout is. Similarly, the smaller the value of Vpwm1 is, the larger the value of Vout is; and Vpwm1 is obtained after PWM1 is filtered by R5, R6 and C3, the smaller the second duty cycle of PWM1 is, the smaller the value of Vpwm1 is. Therefore, the smaller the second duty cycle is, the larger the value of Vout is.

[0089] Based on the above analysis, the following conclusions can be obtained:

[0090] ① When PWM0 and PWM1 are both set to low (Low), Vout can obtain the maximum value Vout_max;

[0091] ② When PWM0 and PWM1 are both set to high (High), Vout can obtain the minimum value Vout_min;

[0092] ③ Set one of PWM0 and PWM1 to high (High) and the other to low (Low) to obtain the intermediate voltage value Vout mid.

[0093] Therefore, during the initialization process of the system on chip 301, the configuration of ③ can be performed to obtain Vout mid as the working voltage of the system on chip 301 in the initialization scenario; in the high-performance scenario, the processor in the system on chip 301 needs a higher working voltage, and the configuration of ① can be performed to obtain Vout max as the working voltage of the system on chip 301 in the high-performance scenario; when the system on chip 301 normally works in the non-high-performance scenario, PWM0 and PWM1 can be digital signals with dynamically changing duty cycles, thereby meeting the dynamic voltage regulation requirement of the system on chip 301.

[0094] In summary, by using the voltage regulation system 300 provided in the embodiments of the present application, the system on chip 301 outputs two PWM digital signals, namely, the first PWM digital signal and the second PWM digital signal. During the initialization of the system on chip 301, the first PWM digital signal can be configured to high (equivalent to a duty cycle of 1) or low (equivalent to a duty cycle of 0), and the second PWM digital signal can also be configured to high or low. Therefore, the output of the system on chip 301 can be configured in four combinations, and correspondingly, the input voltage provided by the power supply chip 302 for the system on chip 301 can also have four combinations. Then, the maximum value of the input voltage of the system on chip 301 is set as the working voltage V2 required in the high-performance scenario, the minimum value of the input voltage of the system on chip 301 is set as a value greater than the minimum voltage V1 required by the processor, and the intermediate value of the input voltage of the system on chip 301 is set as the working voltage V3 required during the initialization of the system on chip 301, so that the initialization requirement and the high-performance scenario requirement of the system on chip 301 can be met. After the initialization of the system on chip 301 is completed, the system on chip 301 can output the first PWM digital signal with an adjustable duty cycle and the second PWM digital signal with an adjustable duty cycle to instruct the power supply chip to adjust the output voltage signal, so that the system on chip 301 obtains the desired working voltage. Therefore, by using the voltage regulation system 300 provided in the embodiments of the present application, an adjustable working voltage can be provided for the system on chip 301 when the system on chip 301 normally works, and the initialization requirement and the high-performance scenario requirement of the system on chip 301 can also be met.

[0095] Based on the same inventive concept, the embodiments of the present application also provide a voltage regulation system, which can be regarded as a specific example of the voltage regulation system 300 described above. The structure of the voltage regulation system can be as shown in Figure 7 .

[0096] In Figure 7In the voltage regulation system shown, chip U1 can be regarded as a specific example of the aforementioned power supply chip 302, chip U2 can be regarded as a specific example of the aforementioned system on chip 301, and the parts other than chip U1 and chip U2 can be regarded as a specific example of the aforementioned peripheral circuit. PWM0 can be regarded as the first PWM digital signal, PWM1 can be regarded as the second PWM digital signal, and Vout can be regarded as the input voltage of the system on chip 301. In chip U1, the FB port can be regarded as the feedback voltage input terminal of U1, and the LX port can be regarded as the voltage output terminal of U1. Vin is the power supply of chip U1.

[0097] In this voltage regulation system, during the initialization process of the SoC, PWM0 and PWM1 can be set to high and low respectively, and Vout is the working voltage of the SoC in the initialization scenario; in the high-performance scenario, PWM0 and PWM1 can be set to high, and Vout is the working voltage of the SoC in the high-performance scenario; when the SoC works normally in the non-high-performance scenario, PWM0 and PWM1 can be digital signals with dynamic duty cycle, thereby meeting the dynamic voltage regulation requirements of the SoC.

[0098] Based on the same inventive concept, the embodiments of the present application also provide a system on chip, which can be regarded as a specific example of the aforementioned system on chip 301. Specifically, the system on chip is configured to output a first PWM digital signal and a second PWM digital signal; receive an input voltage of the system on chip provided by a power supply chip, and work under the driving of the input voltage of the system on chip, wherein the input voltage is obtained by the power supply chip according to a first duty cycle of the first PWM digital signal, a second duty cycle of the second PWM digital signal, and a reference voltage of the power supply chip.

[0099] In a possible example, when the first PWM digital signal is low and the second PWM digital signal is high, or the first PWM digital signal is high and the second PWM digital signal is low, the input voltage is the working voltage of the system on chip in the initialization scenario.

[0100] In a possible example, when the first PWM digital signal and the second PWM digital signal are both low, or the first duty cycle is less than a first preset value and the second duty cycle is less than a second preset value, the input voltage is the working voltage of the system on chip in the high-performance scenario.

[0101] It should be noted that the specific functions of the system on chip and the interaction between the system on chip 301 and the power supply chip can be referred to the related description of the aforementioned voltage regulation system 300, which will not be described here again.

[0102] Based on the same inventive concept, the application further provides a voltage regulation method, which can be regarded as a method performed by the voltage regulation system 300. Referring to Figure 8 The method comprises the following steps.

[0103] S801: The voltage regulation system acquires a first PWM digital signal and a second PWM digital signal.

[0104] S802: The voltage regulation system obtains an output voltage signal according to a first duty cycle of the first PWM digital signal, a second duty cycle of the second PWM digital signal, and a reference voltage of a power supply chip.

[0105] The output voltage signal is used to provide an input voltage for the system on chip.

[0106] Optionally, when the first PWM digital signal is at a low level and the second PWM digital signal is at a high level, the input voltage provided by the output voltage signal for the system on chip is a working voltage of the system on chip in an initialization scenario; or, when the first PWM digital signal is at a high level and the second PWM digital signal is at a low level, the input voltage provided by the output voltage signal for the system on chip is the working voltage of the system on chip in the initialization scenario.

[0107] Optionally, when the first PWM digital signal and the second PWM digital signal are both at a low level, the input voltage provided by the output voltage signal for the system on chip is a working voltage of the system on chip in a high-performance scenario; or, when the first duty cycle is less than a first preset value and the second duty cycle is less than a second preset value, the input voltage provided by the output voltage signal for the system on chip is the working voltage of the system on chip in the high-performance scenario.

[0108] Specifically, the voltage regulation system obtains the output voltage signal according to the first duty cycle of the first PWM digital signal, the second duty cycle of the second PWM digital signal, and the reference voltage of the power supply chip, which can be achieved by the following manner: converting the first PWM digital signal into a first feedback signal; converting the second PWM digital signal into a second feedback signal; obtaining a third feedback signal by dividing the input voltage of the system on chip; and obtaining the output voltage signal according to the first feedback signal, the second feedback signal, the third feedback signal, and the reference voltage of the power supply chip.

[0109] In addition, the output voltage signal is used to provide the input voltage for the system on chip, which can be specifically achieved by: filtering the output voltage signal to obtain the input voltage of the system on chip.

[0110] In addition, the application further provides a system on chip, referring to Figure 9The system on chip 900 comprises a direct current power supply 901, a first resistor 902, a first switch tube 903, a second switch tube 904, a second resistor 905, and a PWM controller 906. The direct current power supply 901 is coupled with a first end of the first resistor 902. A second end of the first resistor 902 is coupled with a first end of the first switch tube 903. A second end of the first switch tube 903 is coupled with a first end of the second switch tube 904, the PWM controller 906, and a power supply chip outside the system on chip 900. A second end of the second switch tube 904 is coupled with a first end of the second resistor 905. A second end of the second resistor 905 is coupled with a ground. The power supply chip is configured to adjust an output voltage signal according to an output signal of the system on chip 900. The output voltage signal is configured to provide a working voltage for the system on chip 900.

[0111] In the embodiments of the present application, the types of the first switch tube 903 and the second switch tube 904 are not limited, for example, the first switch tube 903 and the second switch tube 904 can be metal-oxide-semiconductor field-effect transistors (MOSFETs), or can be insulated gate bipolar transistors (IGBTs), Figure 9 In the embodiments of the present application, the first switch tube 903 and the second switch tube 904 are taken as MOSFETs for example. In addition, the first switch tube 903 and the second switch tube 904 can be controlled by a controller inside the system on chip 900.

[0112] In the embodiments of the present application, when the system on chip 900 is initialized, the first switch tube 903 and the second switch tube 904 are turned on, and the PWM controller 906 is in a high resistance state.

[0113] That is to say, when the system on chip 900 is initialized, the output of the PWM controller 906 is zero, the output of the PWM controller 906 has no effect on the power supply chip, and the system on chip 900 provides, to the power supply chip, a voltage obtained by dividing the output voltage of the direct current power supply 901 by the first resistor 902 and the second resistor 905. The voltage can be adjusted by the output voltage of the direct current power supply 901, the resistance of the first resistor 902, and the resistance of the second resistor 905, so that the output voltage signal obtained by adjusting the reference voltage by the power supply chip can meet the initialization requirements of the system on chip 900.

[0114] Specifically, Figure 9 The system on chip 900 shown in the embodiments of the present application can be applied to Figure 1 or Figure 2 In the voltage regulating system shown in the embodiments of the present application, the composition of the power supply chip and the peripheral circuit can refer to the related description in Figure 1 and Figure 2 , and details are not described herein again.

[0115] In addition, when the system-on-chip 900 is in normal operation, the first switch tube 903 and the second switch tube 904 are turned off, and the PWM controller 906 outputs a PWM digital signal.

[0116] That is, when the system-on-chip 900 is in normal operation, the first switch tube 903 and the second switch tube 904 are turned off, and the direct current power supply 901, the first resistor 902 and the second resistor 905 no longer function. The system-on-chip 900 provides the power supply chip with a PWM digital signal output by the PWM controller 906, and the power supply chip can adjust the output voltage signal according to the duty ratio of the PWM digital signal, so that the output voltage signal can meet the working voltage requirement of the system-on-chip 900 in the normal operation state.

[0117] It should be noted that, in the system-on-chip 900 shown in FIG. 8, the positions of the first resistor 902 and the first switch tube 903 can be exchanged, and the positions of the second switch tube 904 and the second resistor 905 can also be exchanged. The above two position exchanges will not affect the function of the system-on-chip 900. Figure 9

[0118] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can adopt a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer usable program code.

[0119] The present application is described with reference to flowcharts and / or block diagrams according to the methods, devices (systems), and computer program products of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combination of flows and / or blocks in the flowcharts and / or block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to produce a machine, so that the instructions executed by the computer or other programmable data processing devices produce a device that implements the functions specified in the flowcharts and / or block diagrams. Figure 1 The functions specified in one flow or multiple flows and / or blocks Figure 1 The functions specified in one flow or multiple flows and / or blocks

[0120] These computer program instructions can also be stored in a computer readable storage medium that can guide the computer or other programmable data processing devices to work in a specific manner, so that the instructions stored in the computer readable storage medium produce a manufactured product including instruction devices that implement the functions specified in the flowcharts and / or block diagrams.​Figure 1 one or more processes and / or functions described in one or more blocks. Figure 1 one or more blocks.

[0121] These computer program instructions can also be loaded into computer or other programmable data processing devices, so that a series of operation steps are performed on the computer or other programmable devices to generate computer-implemented processes, so that the instructions executed on the computer or other programmable devices provide steps for implementing the processes described in the flowcharts Figure 1 one or more processes and / or functions described in one or more blocks. Figure 1 one or more blocks.

[0122] Obviously, those skilled in the art can make various modifications and variations to the present application without departing from the scope of the present application. Thus, if these modifications and variations of the present application belong to the scope of the claims of the present application and their equivalent technologies, the present application also intends to include these modifications and variations.

Claims

1. A pressure regulating system, characterized by, The system comprises: a system on chip, configured to output a first PWM digital signal and a second PWM digital signal; a power supply chip, coupled to the system on chip, configured to obtain an output voltage signal according to a first duty cycle of the first PWM digital signal, a second duty cycle of the second PWM digital signal, and a reference voltage of the power supply chip, the output voltage signal being configured to provide an input voltage for the system on chip.

2. The pressure regulating system of claim 1, wherein, When the first PWM digital signal is at a low level and the second PWM digital signal is at a high level, the input voltage provided by the output voltage signal for the system on chip is a working voltage of the system on chip in an initialization scenario; or when the first PWM digital signal is at a high level and the second PWM digital signal is at a low level, the input voltage provided by the output voltage signal for the system on chip is the working voltage of the system on chip in the initialization scenario.

3. A pressure regulating system as claimed in claim 1 or 2, characterised in that, When the first PWM digital signal and the second PWM digital signal are both at a low level, the input voltage provided by the output voltage signal for the system on chip is a working voltage of the system on chip in a high-performance scenario; or when the first duty cycle is less than a first preset value and the second duty cycle is less than a second preset value, the input voltage provided by the output voltage signal for the system on chip is the working voltage of the system on chip in the high-performance scenario.

4. The pressure regulating system of claim 1 or 2, wherein, The voltage regulation system further comprises: a peripheral circuit, configured to convert the first PWM digital signal into a first feedback signal, and convert the second PWM digital signal into a second feedback signal; the peripheral circuit is further configured to obtain a third feedback signal by voltage dividing the input voltage of the system on chip, and feed back the first feedback signal, the second feedback signal, and the third feedback signal to the power supply chip; the power supply chip is specifically configured to: obtain the output voltage signal according to the first feedback signal, the second feedback signal, the third feedback signal, and the reference voltage of the power supply chip.

5. The pressure regulating system of claim 4, wherein, The peripheral circuit comprises: a first filter circuit, configured to convert the first PWM digital signal into the first feedback signal, and feed back the first feedback signal to a feedback voltage input end of the power supply chip; a second filter circuit, configured to convert the second PWM digital signal into the second feedback signal, and feed back the second feedback signal to the feedback voltage input end; a voltage dividing circuit, configured to obtain the third feedback signal by voltage dividing the input voltage, and feed back the third feedback signal to the feedback voltage input end.

6. The pressure regulating system of claim 5, wherein, The voltage dividing circuit comprises a first resistor and a second resistor, a first end of the first resistor is coupled to a port of the system on chip for receiving the input voltage, a second end of the first resistor is coupled to the feedback voltage input end and a first end of the second resistor, and a second end of the second resistor is coupled to a ground end. The first filter circuit comprises a third resistor, a fourth resistor and a first capacitor, a first end of the third resistor is coupled with a port of the system on chip for outputting the first PWM digital signal, a second end of the third resistor is coupled with a first end of the first capacitor and a first end of the fourth resistor, a second end of the fourth resistor is coupled with the feedback voltage input end, and a second end of the first capacitor is coupled with the ground end. The second filter circuit comprises a fifth resistor, a sixth resistor and a second capacitor, a first end of the fifth resistor is coupled with a port of the system on chip for outputting the second PWM digital signal, a second end of the fifth resistor is coupled with a first end of the second capacitor and a first end of the sixth resistor, a second end of the sixth resistor is coupled with the feedback voltage input end, and a second end of the second capacitor is coupled with the ground end.

7. A pressure regulating system as claimed in claim 5 or 6, characterised in that, The peripheral circuit further comprises: An output filter circuit coupled with a voltage output end of the power supply chip, configured to filter the output voltage signal to obtain the input voltage of the system on chip.

8. A system on chip, characterized by The system on chip is configured to: output first and second PWM digital signals; receive an input voltage of the system on chip provided by the power supply chip, and work under the drive of the input voltage, wherein the input voltage is obtained by the power supply chip according to a first duty cycle of the first PWM digital signal, a second duty cycle of the second PWM digital signal and a power supply chip reference voltage.

9. The system on chip of claim 8, wherein, When the first PWM digital signal is at a low level and the second PWM digital signal is at a high level, or the first PWM digital signal is at a high level and the second PWM digital signal is at a low level, the input voltage is a working voltage of the system on chip in an initialization scenario.

10. The system on chip as claimed in claim 8 or 9, characterized in that, When the first and second PWM digital signals are both at a low level, or the first duty cycle is less than a first preset value and the second duty cycle is less than a second preset value, the input voltage is a working voltage of the system on chip in a high-performance scenario.

11. A method of regulating pressure, characterized by, The method comprises: a voltage regulation system obtaining first and second PWM digital signals output by a system on chip; the voltage regulation system obtaining an output voltage signal according to a first duty cycle of the first PWM digital signal, a second duty cycle of the second PWM digital signal and a power supply chip reference voltage, wherein the output voltage signal is used to provide an input voltage for the system on chip.

12. The method of claim 11, wherein, When the first PWM digital signal is at a low level and the second PWM digital signal is at a high level, or the first PWM digital signal is at a high level and the second PWM digital signal is at a low level, the output voltage signal is a working voltage of the system on chip in an initialization scenario.

13. The method of claim 11 or 12, wherein, When the first PWM digital signal and the second PWM digital signal are both low, the output voltage signal is an input voltage provided by the system on chip for an operating voltage of the system on chip in a high performance scenario; or when the first duty cycle is less than a first preset value and the second duty cycle is less than a second preset value, the output voltage signal is an input voltage provided by the system on chip for an operating voltage of the system on chip in a high performance scenario.

14. The method of claim 11 or 12, wherein, The voltage regulating system obtains an output voltage signal according to a first duty cycle of the first PWM digital signal, a second duty cycle of the second PWM digital signal, and a power chip reference voltage, and specifically includes: Converting the first PWM digital signal into a first feedback signal; Converting the second PWM digital signal into a second feedback signal; Obtaining a third feedback signal by dividing the input voltage of the system on chip; Obtaining the output voltage signal according to the first feedback signal, the second feedback signal, the third feedback signal, and the power chip reference voltage.

15. The method of claim 11 or 12, wherein, The output voltage signal is used to provide an input voltage for the system on chip, and specifically includes: Filtering the output voltage signal to obtain the input voltage of the system on chip.

16. A system on a chip, comprising: It includes: A direct current power supply, a first resistor, a first switch tube, a second switch tube, a second resistor, and a PWM controller, the direct current power supply is coupled with a first end of the first resistor, a second end of the first resistor is coupled with a first end of the first switch tube, a second end of the first switch tube is coupled with a first end of the second switch tube, the PWM controller, and a power chip outside the system on chip, a second end of the second switch tube is coupled with a first end of the second resistor, a second end of the second resistor is coupled with a ground terminal, the power chip is used to adjust an output voltage signal according to an output signal of the system on chip, and the output voltage signal is used to provide an operating voltage for the system on chip; When the system on chip is initialized, the first switch tube and the second switch tube are turned on, and the PWM controller is in a high resistance state.

17. The system on chip of claim 16, wherein, When the system on chip is normally working, the first switch tube and the second switch tube are turned off, and the PWM controller outputs a PWM digital signal.

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