Parallel NPC three-level inverter of the DC link without a midpoint connection

Abstract

Embodiments of the present disclosure relate to a parallel three-level inverter without a midpoint connection. The parallel three-level inverter includes a plurality of parallel converters coupled in parallel between a common DC bus and a common AC output, wherein each of the plurality of parallel converters includes a midpoint, and the midpoints of the plurality of parallel converters are disconnected from each other. The parallel three-level inverter includes one or more controllers configured to: determine a first average value of the upper half DC bus voltages of the plurality of parallel converters of the inverter and a second average value of the lower half DC bus voltages of the plurality of parallel converters; determine a modulation index for each of the plurality of parallel converters based on the first average value, the second average value, and an AC voltage reference for the converter such that the upper half DC bus voltages of the plurality of converters are equal to each other and the lower half DC bus voltages of the plurality of converters are equal to each other; perform zero-sequence control based on the modulation index to make the first average value equal to the second average value.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to the field of electric fields, and more particularly to a parallel three-level inverter without a midpoint connection. Background Art

[0002] AC three-phase converters increasingly employ three-level converter topologies because they offer overall increased density and reduced losses. However, the additional voltage levels of the DC bus do increase the additional complexity.

[0003] For typical DC-AC inverter applications, the power flow does not require an additional DC midpoint, and thus the midpoint is generally not drawn out from the inverter. The DC midpoint does require special consideration and may require control to maintain its voltage balance.

[0004] When converters are paralleled, since the converters may be in physically separated enclosures, it is desirable to only need to provide interconnection cables for the current-carrying points, and thus it is preferred that no DC midpoint interconnection is required because under normal operating conditions, this line does not carry any current.

[0005] For paralleled converter applications, the requirement to interconnect the DC midpoints is undesirable for several reasons. For example, the DC midpoint interconnection does not carry any current under normal conditions, however, any cable must be overcurrent protected and armored for fault conditions. Additionally, each paralleled converter can be in its own separate enclosure, so the interconnection of the DC midpoints requires additional connectors and cables between each converter, which is both inconvenient and incurs additional cost.

[0006] Currently, the management and balancing of the DC midpoint for a single three-level converter are well known. There are many control techniques available that allow for actively balancing the DC midpoint by using the common-mode (also known as zero-sequence) voltage between DC and AC, which is achieved at the fundamental frequency or harmonic frequencies, or by utilizing redundant PWM switching vectors.

[0007] Conventional techniques only apply to single or paralleled converters with a single common interconnected DC midpoint. The reason for this is that if the DC midpoint remains disconnected, the latest control methods that attempt to balance the local midpoint will in turn unbalance the adjacent midpoints.

[0008] Therefore, there is a need for a parallel three-level inverter without a DC midpoint interconnection. Summary of the Invention

[0009] Generally, example embodiments of the present disclosure provide a parallel three-level inverter without a midpoint connection.

[0010] In a first aspect, a parallel three-level inverter is provided, the parallel three-level inverter comprising: a plurality of parallel converters coupled in parallel between a common DC bus and a common AC output, wherein each converter of the plurality of parallel converters includes a midpoint, and the midpoints of the plurality of parallel converters are disconnected from each other.

[0011] In a second aspect, a method for use in a parallel three-level inverter without a DC midpoint connection is provided. The method includes: determining a first average value of the upper half DC bus voltages of the plurality of parallel converters of the inverter and a second average value of the lower half DC bus voltages of the plurality of parallel converters; determining a modulation index for each converter of the plurality of parallel converters based on the first average value, the second average value, and an AC voltage reference for the converter such that the upper half DC bus voltages of the plurality of converters are equal to each other and the lower half DC bus voltages of the plurality of converters are equal to each other; and performing zero-sequence control based on the modulation index to make the first average value of the upper half DC bus voltage equal to the second average value of the lower half DC bus voltage.

[0012] It should be understood that the summary section is not intended to identify key or essential features of embodiments of the present disclosure, nor is it intended to be used to limit the scope of the present disclosure. Other features of the present disclosure will become readily apparent through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other objects, features, and advantages of the present disclosure will become more apparent from a more detailed description of some embodiments of the present disclosure in the accompanying drawings, in which:

[0014] Figure 1 A circuit diagram showing a parallel three-level inverter without a midpoint interconnection according to an embodiment of the present disclosure is shown;

[0015] Figure 2 A flowchart showing a method for use in a parallel three-level inverter according to an embodiment of the present disclosure is shown;

[0016] Figure 3 A DC bus decoupling block according to one embodiment of the present disclosure is shown; and

[0017] Figure 4 A DC bus decoupling block according to another embodiment of the present disclosure is shown.

[0018] Throughout the drawings, the same or similar reference numerals denote the same or similar elements. DETAILED DESCRIPTION

[0019] The principles of the present disclosure will now be described with reference to some example embodiments. It should be understood that the description of these embodiments is only for illustration and to assist those skilled in the art in understanding and implementing the present disclosure, and does not represent any limitation on the scope of the present disclosure. The disclosure described herein can be implemented in a variety of other ways than those described below.

[0020] As used herein, the term "comprising" and its variants should be understood as open terms meaning "including but not limited to". The term "based on" should be understood as "at least partially based on". The terms "one embodiment" and "embodiment" should be understood as "at least one embodiment". The term "another embodiment" should be understood as "at least one other embodiment". Other definitions (explicit and implicit) may be included below.

[0021] Figure 1 A circuit diagram showing a parallel three-level inverter 100 without a midpoint interconnection according to some embodiments of the present disclosure is shown. The parallel three-level inverter 100 is coupled to a DC bus, including a positive power rail DC+ and a negative power rail DC-. The parallel three-level inverter 100 converts the DC voltage on the DC bus into an AC output voltage, including three phases U, V, and W. The parallel three-level inverter 100 includes a first three-level converter 120 and a second three-level converter 140. It should be understood that the parallel three-level inverter 100 may include more than two three-level converters.

[0022] As Figure 1 shown, an upper DC bus capacitor 101 and a lower DC bus capacitor 102 are coupled across the DC bus, and a first DC midpoint (the common node of the upper DC bus capacitor 101 and the lower DC bus capacitor 102) is coupled to the first three-level converter 120. Additionally, an upper DC bus capacitor 103 and a lower DC bus capacitor 104 are coupled across the DC bus, and a second DC midpoint (the common node of the upper DC bus capacitor 103 and the lower DC bus capacitor 104) is coupled to the second three-level converter 140. The first DC midpoint is not coupled to the second DC midpoint, as Figure 1 shown by the dashed line in

[0023] The output of the first three-level converter 120 is coupled to a filter 105, and the filter 105 is coupled to the AC output. The output of the second three-level converter 140 is coupled to a filter 106, and the filter 106 is also coupled to the AC output.

[0024] Ideally, it is desirable to perform both active balancing (i.e., local balancing) and global active balancing relative to each other in the inverter 100. However, in practice, this cannot be achieved. The only "lever" for active balancing is the voltage offset on the modulation index (commonly referred to as the common-mode or zero-sequence voltage). This can be used to achieve global active balancing, but typically not active balancing relative to each other. The main reason it cannot be used relative to each other is that since the converters are connected in parallel (input and output tied together), the converters should not have different common-mode voltages.

[0025] Conversely, embodiments of the present disclosure advantageously achieve natural balancing relative to each other as well as global active balancing. This approach is ideal in any sense. For example, global active balancing can be used, which allows the use of parallel converters in many applications, and then simple (non-additional control) natural balancing can be used between the converters (relative to each other).

[0026] Figure 2 A flowchart illustrating a method 200 for use in a parallel three-level inverter 100 is shown. The method 200 can be implemented at a single common controller or at each converter of the parallel three-level inverter 100. Now referring to a single common controller, it should be understood that the method 200 can also be applied to other controller arrangements.

[0027] At block 202, the common controller determines a first average value of the upper half DC bus voltage of the parallel converters of the inverter 100 and a second average value of the lower half DC bus voltage of the parallel converters of the inverter 100. For example, each converter 120, 140 can measure its upper half DC bus and lower half DC bus with a voltage sensor. The common controller can be communicatively coupled to each converter and obtain the voltage measurements from the converters to calculate the average values. Each converter can receive the first average value and the second average value calculated at the common controller. Alternatively, each converter can receive the half DC bus voltages of each other converter and perform the averaging locally.

[0028] In the case of the inverter 100, the first average value of the upper half DC bus voltage of the parallel converters of the inverter 100 is the average of the upper half DC bus voltage of the first converter 120 and the upper half DC bus voltage of the second converter 140. In the case of the inverter 100, the second average value of the lower half DC bus voltage of the parallel converters of the inverter 100 is the average of the lower half DC bus voltage of the first converter 120 and the lower half DC bus voltage of the second converter 140.

[0029] At block 204, each converter of the inverter 100 determines a modulation index based on a first average value, a second average value, and the AC voltage reference of the converter, such that the upper half DC bus voltages of the plurality of converters are equal to each other and the lower half DC bus voltages of the plurality of converters are equal to each other. In this way, each converter decouples its PWM output voltage using the average half DC bus voltage, and a "natural" DC midpoint balance is achieved. By using the average half DC bus for decoupling, if a converter has a local DC midpoint imbalance different from the global average imbalance, it will experience a local "natural" DC midpoint balance, but only relative to other paralleled converters.

[0030] The key point of decoupling is that the PWM reference (modulation index) is simply the ratio of the AC output voltage to the DC bus voltage. If a specific AC voltage is desired to be generated, the DC bus voltage must be decoupled. For example, for a simple two-level converter, if the DC bus voltage is 100 V, and if the output AC voltage is a sine wave with a peak-to-peak voltage of 100 V, the modulation index is equal to 1.0. If the DC bus voltage increases to 125 V, but the same output voltage is required, the modulation index should be recalculated as 100 V / 125 V = 0.8.

[0031] V upper and V lower are the measured upper half bus voltage and lower half bus voltage respectively. The sum of the upper half bus voltage and the lower half bus voltage is the total or sum bus voltage. The midpoint imbalance is introduced with respect to what the balanced voltage would be. When the upper half bus and the lower half bus are equal, it is a balanced midpoint voltage. The average value of the bus half voltages can be called V upper_avg and V lower_avg .

[0032] "Local midpoint imbalance" refers to the deviation of the actual midpoint voltage of the converter from half of the total bus voltage. Mathematically, V busTotal = V lower + V upper and V unbalance = V lower - (V busTotal / 2)

[0033] For example, if V lower = 2V and V upper = 1V, then V busTotal = 3V. The midpoint is unbalanced because V lower is greater than V upper . V unbalance = 2 - (3 / 2) = 0.5V.

[0034] In one example, two converters are unbalanced relative to each other, but globally balanced: Vupper_1 = 1V, V lower_1 = 2V, V upper_2 = 2V, V lower_2 = 1V. Here, V total = 3V. "Average upper bus voltage" is 1.5V = V upper_avg = (V upper_1 + V upper_2 ) / 2. "Average lower bus voltage" is also 1.5V = V lower_avg = (Vlower_1 + V lower_2 ) / 2. The average bus halves are equal, and thus the converter is globally balanced. The individual converter halves are unbalanced relative to each other because their individual (upper and lower) half voltages differ from the average value.

[0035] In another example, two converters are balanced relative to each other but globally unbalanced: V upper_1 = 1V, V lower_1 = 2V, V upper_2 = 1V, V lower_2 = 2V. Similarly, V total = 3V. V upper_avg = 1V, V lower_avg = 2V. The average bus halves are different, and thus the converter is globally unbalanced. The individual upper half converters are the same as the average value: V upper_1 = V upper_2 = V_upper_avg, and V lower_1 = V lower_2 = V lower_avg . Therefore, the converter is locally balanced.

[0036] The term "naturally DC midpoint balanced, but only relative to other paralleled converters" means using natural balance relative to each other rather than globally. Thus natural balance will result in V lower_1 = V lower_2 = V lower_avg and V upper_1 = V upper_1 = V upper_avg . But natural balance is not used for global balance.

[0037] Figure 3A block diagram of a DC bus decoupling 10 according to an embodiment of the present disclosure is shown. An AC voltage reference 11 is provided to two limiters 12 and 13. The lower limit of limiter 12 is zero, and the upper limit of limiter 13 is zero. Voltage 17 is the first average value of the upper half DC bus voltage of the converter, and voltage 18 is the second average value of the lower half DC bus voltage of the converter. If the AC voltage reference 11 is greater than zero, the AC voltage reference 11 will be provided to a divider 14 via limiter 12, and the divider 14 divides the positive AC voltage reference by voltage 18. If the AC voltage reference 11 is less than zero, the AC voltage reference 11 will be provided to a divider 15 via limiter 13, and the divider 15 divides the negative AC voltage reference by voltage 17. The outputs of dividers 14 and 15 are added at an adder 16 to obtain a modulation index for use in controlling the converter.

[0038] Figure 4 A block diagram of a DC bus decoupling 20 according to an embodiment of the present disclosure is shown. Voltage 24 is the first average value of the upper half DC bus voltage of the converter, and voltage 25 is the second average value of the lower half DC bus voltage of the converter. Voltages 24 and 25 are added at an adder 23 to become a total voltage. The AC voltage reference 21 and the total voltage are provided to a divider 22, and the divider 22 divides the AC voltage reference 21 by the total voltage to obtain a modulation index for use in controlling the converter.

[0039] Although there is a natural balance of the midpoint of each converter relative to the average midpoint balance, the average decoupling still results in no overall average midpoint balance, and thus a global midpoint balance control mechanism is needed. For this purpose, at block 206, zero-sequence control can be performed based on the modulation index to make the first average value of the upper half DC bus voltage equal to the second average value of the lower half DC bus voltage. For example, the overall midpoint controller is implemented based on the average DC bus midpoint imbalance, and the reference from the balance controller is evenly distributed to all converters. The global active balance controller can only change the common-mode voltage. The common-mode voltage is the sum of all 3 three-phase voltage references. Usually, this voltage is zero. In a 3-wire AC system, power is transmitted between 3 phases, and the common-mode voltage does not affect the operation because there is no common-mode current path.

[0040] The balance controller can be implemented in a single controller, and then its reference is distributed to each converter. Traditional midpoint balance control algorithms can be used for global DC midpoint balance. Parallel converters can be used in high-reliability applications where the loss of one converter in a parallel group of converters is tolerable. Redundancy is only effective when the loss of one part of the system (e.g., one converter) does not stop the rest. In this case, a single-point failure is not tolerable, and the controller can be replicated in each converter.

[0041] According to an embodiment of the present disclosure, a way that allows natural balance relative to each other (natural balance without individual decoupling) but is then used for global active balance (which does require individual decoupling) is to make each converter decouple its voltage reference not locally from its measured DC bus half, but from the average DC bus half. For example, if the upper half of the DC bus of a converter is lower than the average upper half of the DC bus, when the converter decouples through the average upper half of the DC bus, it will actually decouple through the wrong voltage (because its upper half of the DC bus is lower than the average), and thus natural balance will be achieved. However, because all converters decouple through the average value, any active balance (i.e., global balance) operating on the average value will be able to balance globally. In this way, method 200 achieves midpoint balance between converters (using natural balance) and allows global active balance and does not have to connect the midpoints of parallel converters.

[0042] In some embodiments, each converter may measure the zero-sequence current of each of the plurality of parallel converters and control the zero-sequence current to zero. In other words, each converter locally attempts to eliminate any zero-sequence current using a local feedback controller. The zero-sequence current causes imbalance, so eliminating any spurious zero-sequence current removes the source of midpoint imbalance.

[0043] According to an embodiment of the present disclosure, each converter decouples the DC bus voltage through the average value of the DC bus half to allow the use of active global balance and relies on natural balance to achieve balance between converters. The benefits are clear because no cable connection is required between the DC midpoints of each converter, thus reducing the system wiring cost and complexity. This method has been shown to be insensitive to the practical realities of component variations and sensing errors of parallel converters. In addition, the embodiments of the present disclosure are capable of achieving four-quadrant operation of parallel three-level converters without connecting the DC midpoints.

[0044] Although the present disclosure has been described in language specific to structural features and / or method acts, it is to be understood that the disclosure defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the above specific features and acts are disclosed as example forms of implementing the claims.

Claims

1. A parallel three-level inverter, comprising: a plurality of parallel converters, coupled in parallel between a common DC bus and a common AC output, wherein each converter of the plurality of parallel converters includes a midpoint, and the midpoints of the plurality of parallel converters are disconnected from each other; and one or more controllers configured to: determine a first average value of the upper half DC bus voltage of the plurality of parallel converters of the inverter and a second average value of the lower half DC bus voltage of the plurality of parallel converters; determine a modulation index for each converter of the plurality of parallel converters based on the first average value, the second average value, and an AC voltage reference for the converter, such that the upper half DC bus voltages of the plurality of converters are equal to each other and the lower half DC bus voltages of the plurality of converters are equal to each other; and perform zero-sequence control based on the modulation index to make the first average value of the upper half DC bus voltage equal to the second average value of the lower half DC bus voltage.

2. The parallel three-level inverter according to claim 1, wherein: the common DC bus includes a positive power rail and a negative power rail, each converter of the plurality of parallel converters includes a first input electrically coupled to the positive power rail and a second input electrically coupled to the negative power rail, and the midpoint capacitor of each converter of the plurality of parallel converters is capacitively coupled to each of the positive power rail and the negative power rail.

3. The parallel three-level inverter according to claim 1, wherein the one or more controllers are configured to: measure the zero-sequence current for each converter of the plurality of parallel converters; and control the zero-sequence current to zero.

4. The parallel three-level inverter according to claim 1 or 3, wherein the one or more controllers are configured to: divide the AC voltage reference by the sum of the first average value of the upper half DC bus voltage and the second average value of the lower half DC bus voltage to determine the modulation index.

5. The parallel three-level inverter according to any one of claims 1 and 3, wherein the one or more controllers are configured to: a) if the AC voltage reference is less than zero, divide the AC voltage reference by the first average value of the upper half DC bus voltage; b) if the AC voltage reference is greater than zero, divide the AC voltage reference by the second average value of the lower half DC bus voltage; and c) add the quotient values obtained in steps a) and b) to determine the modulation index.

6. A method for use in a parallel three-level inverter without a DC midpoint connection, the method comprising: determine a first average value of the upper half DC bus voltage of the plurality of parallel converters of the inverter and a second average value of the lower half DC bus voltage of the plurality of parallel converters; Determine a modulation index for each of the plurality of parallel converters based on the first average value, the second average value, and an AC voltage reference for the converter, such that the upper half DC bus voltages of the plurality of converters are equal to each other and the lower half DC bus voltages of the plurality of converters are equal to each other; and Perform zero - sequence control based on the modulation index to make the first average value of the upper half DC bus voltage equal to the second average value of the lower half DC bus voltage.

7. The method according to claim 6, further comprising: Measure the zero - sequence current for each of the plurality of parallel converters; and Control the zero - sequence current to zero.

8. The method according to claim 6 or 7, wherein determining the modulation index comprises: Dividing the AC voltage reference by the sum of the first average value of the upper half DC bus voltage and the second average value of the lower half DC bus voltage.

9. The method according to any one of claims 6 to 7, wherein determining the modulation index comprises: a) If the AC voltage reference is less than zero, divide the AC voltage reference by the first average value of the upper half DC bus voltage; b) If the AC voltage reference is greater than zero, divide the AC voltage reference by the second average value of the lower half DC bus voltage; and c) Add the quotient values obtained in steps a) and b) to determine the modulation index.

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