Sensor device and related methods and systems

Abstract

Embodiments of the present disclosure relate to sensor devices and related methods and systems. The sensor is configured to provide a digital output signal and has a digital detector configured to detect a physical quantity and generate a conditioned digital signal indicative of the detected physical quantity; and a rate modification stage configured to receive the conditioned digital signal and a parameter set, the parameter set including an interpolation factor and a downsampling factor, and provide a digital output signal. The rate modification stage has an interpolator and a decimation element. The interpolator is configured to receive and upsample the conditioned digital signal based on the interpolation factor and provide an interpolated signal. The decimation element is configured to downsample the interpolated signal based on the downsampling factor to generate a digital output signal.

Description

Technical Field

[0001] The present disclosure relates to a sensor, for example, to a sensor manufactured using MEMS (“Micro Electro Mechanical Systems”) technology. Background Art

[0002] As is known, electronic devices are prevalent, for example in the consumer electronics field as well as in the industrial and automotive fields, comprising one or more sensors configured to each detect one or more physical quantities associated with use of the respective electronic device.

[0003] For example, the one or more sensors may be an accelerometer, a gyroscope, a temperature sensor, a pressure sensor, a resistance sensor, a mechanical stress sensor, a strain sensor.

[0004] It is also known to manufacture such sensors using MEMS technology, which allows obtaining sensors having small dimensions, low energy consumption and high detection accuracy.

[0005] The MEMS sensor is configured to convert a physical quantity into an analog type electrical signal, the trend of which over time is in accordance with the trend of the corresponding detected physical quantity over time.

[0006] It is known to design an electronic device incorporating a MEMS sensor so that the analog signal generated by the MEMS sensor is sequentially processed by an analog front end, such as amplified; using a sampling frequency f s converted into a digital signal; and filtered by a filtering stage, for example by a low-pass filter, thereby filtering the signal from a signal having a sampling frequency equal to f s The sampling frequency of the MEMS sensor is used to obtain the output signal.

[0007] Analog front end, sampling frequency f s The subsequent filtering allows the output signal to meet a set of technical requirements of the MEMS sensor and the electronic equipment containing the MEMS sensor. For example, the sampling frequency f s In accordance with the Nyquist sampling theorem related to the frequency band of the analog signal output by the MEMS sensor A mpling theorem), and filtering so that it suppresses noise and / or possible demodulated tones generated at the output by the analog-to-digital converter.

[0008] Furthermore, if the MEMS sensor includes a mechanical oscillator, the output data rate from the MEMS sensor is determined by the operating frequency at which the mechanical oscillator is actuated.

[0009] As a result, the output data rate from known MEMS sensors has a low level of individuality.

[0010] To increase the range of available output data rate values, it is known to incorporate a phase-locked loop (PLL) into electronic devices. However, the output data rate is only variable within the frequency range available in the oscillator used to create the PLL circuit. Furthermore, PLL circuits consume a large amount of die area and energy, and in certain applications, it is not always possible to meet the desired design requirements.

[0011] Alternatively, if the MEMS sensor includes an electronic oscillator, such as a clock, methods are known for trimming the oscillation frequency of the electronic oscillator, which also allow the output data rate from the MEMS sensor to be varied. However, such trimming methods are only able to vary the oscillation frequency within a limited range of values, for example, within ±20%.

[0012] It is also known to incorporate decimation circuitry in electronic devices that is capable of scaling the output signal from the MEMS sensor by an integer factor, in particular a power of 2. However, even this solution does not allow a high degree of personalization of the output data rate from the MEMS sensor. Summary of the Invention

[0013] In one embodiment, a sensor includes: a digital detector that detects a physical quantity and generates a conditioned digital signal indicative of the detected physical quantity; and signal processing circuitry coupled to the digital detector, wherein the signal processing circuitry generates a digital output signal of the sensor based on the conditioned digital signal and a parameter set including an interpolation factor and a downsampling factor. Generating the digital output signal includes upsampling the conditioned digital signal based on the interpolation factor to generate an interpolated signal; and downsampling the interpolated signal based on the downsampling factor to generate the digital output signal.

[0014] In one embodiment, a system includes: a sensor, which, in operation: detects a physical quantity and generates a conditioned digital signal indicative of the detected physical quantity, and generates a digital output signal of the sensor based on the conditioned digital signal and a parameter set including an interpolation factor and a downsampling factor, generating the digital output signal including: upsampling the conditioned digital signal based on the interpolation factor to generate an interpolated signal, and downsampling the interpolated signal based on the downsampling factor to generate the digital output signal; and an interface coupled to the sensor, wherein the sensor receives the parameter set via the interface in operation.

[0015] In one embodiment, a method includes: detecting a physical quantity by a detection circuit device of a sensor; generating an adjusted digital signal indicating the detected physical quantity by the detection circuit device of the sensor; and generating a digital output signal of the sensor based on the adjusted digital signal and a parameter set including an interpolation factor and a downsampling factor by a signal processing circuit device of the sensor, wherein generating the digital output signal includes: upsampling the adjusted digital signal based on the interpolation factor to generate an interpolated signal; and downsampling the interpolated signal based on the downsampling factor to generate the digital output signal.

[0016] In one embodiment, the content of a non-transitory computer-readable medium configures a sensor to perform a method comprising: detecting a physical quantity through a detection circuit device of the sensor; generating an adjusted digital signal indicating the detected physical quantity through the detection circuit device of the sensor; and generating a digital output signal of the sensor based on the adjusted digital signal and a parameter set including an interpolation factor and a downsampling factor by a signal processing circuit device of the sensor, wherein generating the digital output signal comprises: upsampling the adjusted digital signal based on the interpolation factor to generate an interpolated signal; and downsampling the interpolated signal based on the downsampling factor to generate the digital output signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] For a better understanding of the present disclosure, embodiments thereof will now be described, by way of non-limiting examples only, with reference to the accompanying drawings, in which:

[0018] Figure 1 A block diagram of an electronic device including an embodiment of the present sensor is shown;

[0019] Figure 2 Shown Figure 1 A block diagram of an embodiment of an output data rate modification block of an electronic device;

[0020] Figure 3 Shown Figure 2 a block diagram of an embodiment of a first decimator of an output data rate modification block;

[0021] Figure 4 A flow chart illustrating a method for personalizing output data rate according to an embodiment; and

[0022] Figure 5 The embodiment according to the embodiment is shown in detail Figure 4 Steps of flow chart.

[0023] In the following, unless stated otherwise, reference will be made to the frequency of a discretized (digital) signal to indicate its sampling frequency, and the data rate at which the respective block generating the discretized signal provides samples of the discretized signal at the output. DETAILED DESCRIPTION

[0024] Figure 1 There is schematically shown an electronic device 1 comprising a sensor 5 , a memory 6 and a processing unit or circuit 7 operatively coupled to one another.

[0025] The sensor 5 comprises a detection unit or circuit 9 , a signal conditioning stage or circuitry 10 and an output data rate (ODR) modification block or circuit 15 , hereinafter also referred to as ODR modification block 15 .

[0026] The sensor 5, in particular the detection unit 9, is configured to detect one or more physical quantities associated with the operation of the electronic device 1 and to generate one or more electrical signals, here analog signals S, according to such physical quantities. A .

[0027] The sensor 5 may be, for example, an acceleration sensor, a temperature sensor, a pressure sensor, a mechanical stress sensor, a resistance sensor, a gyroscope, etc.

[0028] In this embodiment, the sensor 5 is of the MEMS type, ie the detection unit 9 is obtained using MEMS technology and is formed in a die of semiconductor material, in particular silicon.

[0029] In particular, in this embodiment, the detection unit 9 comprises a sensing element 18 and a mechanical oscillator 20 .

[0030] The mechanical oscillator 20 comprises a movable and / or deformable structure, for example elastically deformable, such as a cantilever, a diaphragm or a structure having any other shape, which has a resonance frequency f r .

[0031] In use, the mechanical oscillator 20 is actuated, for example, according to electrostatic, piezoelectric or electromagnetic actuation principles, so that the corresponding movable and / or deformable structure oscillates at an operating frequency f0. Typically, the operating frequency f0 is determined according to the resonant frequency f r , for example it is equal to the resonant frequency f r .

[0032] The mechanical oscillator 20 is configured such that the physical quantity to be detected modifies the movement of a movable and / or deformable structure of the mechanical oscillator 20 , for example modifies its phase, amplitude and / or frequency.

[0033] The sensing element 18 is configured to detect the movement of the movable and / or deformable structure of the mechanical oscillator 20, for example according to electrostatic, piezoresistive, piezoelectric or electromagnetic detection principles, and convert it into an analog signal S A . Analog signal S A The trend over time is therefore indicative of the change in movement of the movable and / or deformable structure of the mechanical oscillator 20 caused by the physical quantity to be detected.

[0034] The signal conditioning stage 10 is configured to receive an analog signal S at an input A , and provides at the output the analog signal S A The corresponding digital signal S D .

[0035] In detail, the signal conditioning stage 10 includes an analog front end (AFE) 23 , an analog-to-digital converter 26 , and a filter 28 .

[0036] The analog front end 23 includes, for example, one or more operational amplifiers, and is configured to, for example, process the analog signal S A Filter, amplify or demodulate to provide a conditioned analog signal S' at the output A .

[0037] The analog-to-digital converter 26 is configured to receive the conditioned analog signal S' at an input. A and provides a sampled signal S at the output S By sampling at a frequency f s Discretize the conditioned analog signal S' A To obtain the sampled signal S S .

[0038] The sampling frequency f is selected during the design step based on the requirements of the specific application s For example, the sampling frequency f s It can be made to comply with the Nyquist sampling theorem and be greater than twice the operating frequency f0 of the mechanical oscillator 20 of the detection unit 9 .

[0039] Therefore, the sampling signal S output by the analog-to-digital converter 26 is S With a sampling frequency equal to f s The sampling frequency of .

[0040] The filter 28 comprises one or more low-pass or band-pass type filters, having one or more corresponding cut-off frequencies, and is configured to receive the sampled signal S at an input. S and provides a digital signal S at the output D Therefore, by sampling the signal S S Filter to obtain the digital signal S D, for example to remove its unwanted spectral components introduced by the analog-to-digital converter 26 , the analog front end 23 and / or the detection unit 9 .

[0041] According to specific application and design requirements, for example, to meet die area requirements, the filter 28 can also be configured to convert the sampled signal S S The frequency is reduced by, for example, an integer reduction factor, for example comprised between 1 and 1024.

[0042] Therefore, the digital signal S D With an adjusted sampling frequency f′ s , which is lower than the sampling frequency f s In other applications, the adjusted sampling frequency f′ s Equal to the sampling frequency f s .

[0043] The ODR modification block 15 is configured to receive at input the digital signal S D and provides an output signal S at the output O , the output signal has the same D The adjusted sampling frequency f′ s Different output frequencies f oU .

[0044] From the digital signal S D Get the output signal S O , modifying its sampling frequency based on the parameter set K, as described in detail below.

[0045] Output signal S O An output signal from the sensor 5 is formed.

[0046] The electronic device 1 further comprises an interface 30 and a configuration register 33. The interface 30 is configured to receive an output signal S from the sensor 5 from a user of the electronic device 1 or from an application executed on the processor 7. O The expected output frequency f oU The user signal S U .

[0047] The interface 30 is configured to convert the user signal S U The parameter set K is converted into a parameter set K, and the parameter set K is stored in the configuration register 33 .

[0048] According to another embodiment, the user signal S U The parameter set K is converted by the processing unit 7 , and the interface 30 serves as a signal transmission bus between the processing unit 7 and the configuration register 33 .

[0049] The parameter set K is formed by the interpolation factor I1 and the first decimation factor D1.

[0050] In addition, in this embodiment, the parameter set K also includes a second decimation factor M.

[0051] like Figure 2 As shown, the ODR modification block or circuit 15 includes an interpolation device (or interpolator) 36 and a first decimator 40 .

[0052] The interpolator 36 comprises an interpolation filter 38 configured to receive at input the interpolation factor I1 and the digital signal S D (At the adjusted sampling frequency f′ s and is configured to provide an interpolated digital signal S at an output D,int . Interpolated digital signal S D,int With a sampling frequency greater than the adjusted f′ s The interpolation frequency f int In particular, here, by adjusting the sampling frequency f′ s Add the interpolation factor I1 to obtain the interpolation frequency f int .

[0053] The interpolator 36, and in particular the corresponding interpolation filter 38, can be obtained in a known manner, for example using linear or nonlinear phase interpolation circuits, in particular of the CIC (“Cascaded Integrator Comb”, spline, Lagrangian, Hermitian type.

[0054] The first decimator 40 is configured to receive at input the interpolated digital signal S D,int and the first decimation factor D1.

[0055] In detail, such as Figure 3 As shown, the first decimator 40 includes a filtering stage or filter 43 , a downsampler 46 coupled to a counter 49 , and a gain block or circuit 52 .

[0056] The filter stage 43 may be a low-pass filter, for example an infinite impulse response (IIR) or finite impulse response (FIR) filter, such as a CIC circuit, and is configured to receive at input the first decimation factor D1 and the interpolated digital signal S D,int And a filtered signal F is provided at the output.

[0057] The filter stage 43 has a corresponding transfer function H(f, D1) with a corresponding cutoff frequency f c , can be based on the output frequency f oU , in particular, the cutoff frequency f is selected based on the first decimation factor D1 c .

[0058] For example, the cutoff frequency f can be selected c , so that the extracted digital signal S D,decThe frequency and cut-off frequency f c The ratio between them complies with the Nyquist sampling theorem. In addition, the cutoff frequency f c To suppress the high frequency spectral image introduced by the interpolator 36.

[0059] The transfer function H(f, D1) of the filter stage 43, in particular the corresponding cut-off frequency f c , can be modified in a known manner during use. For example, in the case where the filter stage 43 is formed by a CIC filter of order N, the relative coefficients determining its transfer function H(f, D1) can be obtained in a known manner from the extracted digital signal S D,dec The frequency of the interpolated digital signal S D,int In the case where the filter stage 43 is formed by an IIR filter, the relative coefficients determining its transfer function H(f, D1) can be selected from a specific look-up table stored in the memory 6, for example.

[0060] The counter 49 is configured to receive the first decimation factor D1 at an input and to provide a counter command signal SC representing the first decimation factor D1 at an output.

[0061] According to an embodiment, the sensor 5 comprises a clock configured to generate a clock signal having a corresponding frequency, for example in the order of megahertz, and the counter 49 is further configured to receive the clock signal at an input. Furthermore, the counter 49 is configured to store a count and to increase the count by one unit at each cycle of the clock signal.

[0062] In this embodiment, the first decimation factor D1 indicates the number of clock cycles.

[0063] Furthermore, the counter 49 is configured to compare the count with the first decimation factor D1 at each clock cycle.If the count is equal to the first decimation factor D1, the counter 49 generates a counter command signal SC.

[0064] The downsampler 46 is configured to receive the filtered signal F and the counter command signal SC at its input and to provide a downsampled signal DS at its output. The downsampled signal DS is obtained from the filtered signal F. Specifically, the counter command signal SC causes the downsampler 46 to provide every D1th sample of the filtered signal F at its output. In other words, the downsampled signal DS has a lower sampling frequency than the filtered signal F, as described in detail below.

[0065] The gain block 52 is configured to receive the downsampled signal DS and the first decimation factor D1 at an input and to provide a decimated digital signal S at an output. D,dec .

[0066] In detail, the gain block 52 is configured to amplify or attenuate the sampled values ​​of the downsampled signal DS corresponding to the DC component (at zero frequency) of the downsampled signal DS by a gain factor G. For example, the zero-frequency component of the downsampled signal DS is identified by performing a Fourier transform on the downsampled signal DS. The gain factor G may be selected based on the first decimation factor D1 and the filter type used in the filter stage 43.

[0067] In particular, if the filtering stage 43 is obtained using an IIR filter, the gain factor G may be selected from a specific lookup table stored in the memory 6. If the filtering stage 43 is obtained using a CIC filter, the gain factor G may be calculated as 1 / D1 N , where N is the order of the CIC filter of the filter stage 43 .

[0068] Reference again Figure 2 , the ODR modification block 15 further comprises a second decimator 60 comprising a decimation filter 65. The decimation filter 65 is configured in a known manner to perform power-of-two decimation on the discrete signal received at the input. In detail, the second decimator 60 is configured to receive the decimated digital signal S at the input D,dec and a second decimation factor M, and the second decimator 60 is configured to provide an output signal S at the output O .

[0069] In fact, in order to generate the output signal S O The second extractor 60 extracts the digital signal S D,dec Downsampling is performed to reduce the sampling frequency by 2 M times. In other words, by extracting the digital signal S D,dec Every 2nd M The output of the sample S Oi To obtain the output signal S O According to an embodiment, the second extractor 60 is further configured to extract the digital signal S D,dec Filtering is performed, for example, so that the output signal S O Complies with the Nyquist sampling theorem.

[0070] In use, the sensor 5 performs personalization of its output data rate, for example using the following reference Figure 4 A personalization method 100 is described.

[0071] When the user of the electronic device 1 or the application executed by the electronic device passes the user signal S U Send to interface 30 ( Figure 1 ) to indicate the expected output data rate ODR from the sensor 5 E , that is, the output signal S O The expected output frequency f oUWhen , method 100 begins.

[0072] For example, the user signal S U The user may be instructed to select a desired output data rate ODR from a list of defined values ​​stored in the memory 6. E The defined list may be predefined. The parameter set K also stored in the memory 6 corresponds to the desired output data rate ODR E Each defined value of .

[0073] Alternatively, the user can use the user signal S U Directly indicate one or more parameters forming parameter set K.

[0074] When the interface 30 receives the user signal S U , that is, here, the interpolation factor I1, the first decimation factor D1 and the second decimation factor M are determined and written into the configuration register 33.

[0075] Purely by way of example, in this embodiment, the interpolation factor I1 may be equal to 64, while the first decimation factor D1 and the second decimation factor M may be equal to the desired output data rate ODR selected by the user. E However, the interpolation factor I1 may have different values, in particular be equal to a power of 2.

[0076] In particular, here, the first decimation factor D1 may be comprised between 48 and 95, and the second decimation factor M may be comprised between 0 and 10.

[0077] Subsequently, in step 105 , the sensor 5 , in particular the ODR modification block 15 , receives the parameter set K and configures the corresponding interpolator 36 , the corresponding first decimator 40 and the corresponding second decimator 60 .

[0078] In detail, interpolator 36 receives interpolation factor I1, and interpolator 36 sets the coefficients of corresponding interpolation filter 38 from interpolation factor I1 so that interpolation filter 38 performs an interpolation equal to interpolation factor I1. First decimator 40 receives first decimation factor D1 and configures corresponding filter stage 43, counter 49 and gain block 52 accordingly.

[0079] Furthermore, here, the second decimator 60 receives a second decimation factor M, which sets the coefficients of the corresponding decimation filter 65 so that the decimation filter 65 performs a value of 2. M , where M is the second decimation factor.

[0080] In use, the ODR modification block 15 uses the adjusted sampling frequency f′ s Receives the digital signal S from the signal conditioning stage 10 DAs an example, consider the adjusted sampling frequency f′ s It is 6.25kHz.

[0081] When the modification block receives the digital signal S D When the interpolator 36 ( Figure 2 ) for the digital signal S D The interpolator 36 generates an interpolated signal S D,int , its sampling frequency is relative to the digital signal S D The sampling frequency is increased by the interpolation factor I1. The interpolated digital signal S D,int The sampling frequency of f′ is thus given by the formula s I1 is given by , and is therefore equal to 400 kHz in the example considered.

[0082] The first decimator 40 receives at input the interpolated digital signal S D,int , and interpolate the digital signal S D,int The digital signal S is downsampled (first decimation 115) by an amount indicated by the first decimation factor D1. D,dec With f′ s The sampling frequency is given by I1 / D1. For example, consider a case where the first decimation factor D1 is included in the range of 48-95 and where the interpolated digital signal S D,int The frequency is 400kHz, and the extracted digital signal S D,dec The sampling frequency included in this example is within the range of 4.21kHz-8.33kHz.

[0083] In detail, Figure 5 As shown, Figure 4 The first decimation 115 of the method 100 includes sequential filtering 115A, downsampling 115B, and amplification 115C.

[0084] During filtering 115A, the filtering stage 43 of the first decimator 40 receives the interpolated digital signal S D,int , and the interpolated digital signal S D,int Thus, the filtering stage 43 allows the removal of the interpolated digital signal S introduced by the interpolator 36 in the upsampling 110. D,int high-frequency components.

[0085] Subsequently, during downsampling 115B, the downsampler 46 receives at input the filtered signal F and the counter command signal SC and provides at output a downsampled signal DS formed by every D1 -th sample of the filtered signal F.

[0086] The gain block 52 receives the downsampled signal DS at input and amplifies (amplifies 115C) its DC component (at zero frequency) to compensate for the attenuation caused by the filtering stage 43, as described above.

[0087] According to different embodiments, the gain block 52 may be configured to amplify or attenuate the DC component of the downsampled signal DS, depending on whether the filtering stage 43 introduces attenuation or amplification in the filtered signal F, respectively.

[0088] Reference again Figure 4 , the decimated digital signal SD,dec output by the gain block 52 (and therefore by the first decimator 40) undergoes a second decimation 120. In detail, the second decimator 60 receives at input the decimated digital signal S D,dec , and reduce its sampling frequency by 2 M , where M is the second decimation factor. In other words, the output signal S O By extracting the digital signal S D,dec Every 2nd M A sample is formed.

[0089] The output signal S from the ODR modification block 15 O and the output signal S from the sensor 5 obtained thereby O Further equipment (not shown here) may be provided inside or outside the electronic device 1 for subsequent processing.

[0090] Therefore, the desired output sampling rate ODR E , that is, the output signal S O The sampling output frequency f oU , in general, through the formula ODR E =f′ s I1 / D1 / 2 M With the digital signal S D The adjusted sampling frequency f′ s Related.

[0091] As a result, using the method 100, the electronic device 1 allows the personalized sensor 5 to provide at an output a physical quantity corresponding to the physical quantity detected by the detection unit 9 (and thus from the analog signal S A The frequency of data related to the sampling export).

[0092] In particular, as is apparent from the description above, the presence of the interpolator 36 and the first decimator 40 facilitates the output signal S O The output frequency f oU and the adjusted sampling frequency f′ to be obtained s Any ratio between , whether integers or rational numbers.

[0093] By properly selecting the value of the parameter set K, the output signal S O The output frequency f oU Greater than the adjusted sampling frequency f′ s .

[0094] As a result, the ODR modification block 15, and in particular the interpolator 36 and the first decimator 40, endow the electronic device 1 with a high degree of versatility, while allowing it to meet the frequency band and sampling requirements of a particular application. In practice, the ODR modification block 15 is arranged in cascade with the signal conditioning stage 10, which is designed to condition the digital signal S D For example, the sampling frequency f of the analog-to-digital converter 26 is s The cutoff frequency of the filter 28 is determined according to the analog signal S A The frequency band and / or the operating frequency f of the mechanical oscillator 20 o is selected.

[0095] In addition, the second decimator 60 modifies the output frequency f ou Further freedom is given in

[0096] The electronic device 1 can thus be used in a variety of applications requiring different output data rate values ​​from the sensor 5 , for example comprised between 1 Hz and 10 kHz.

[0097] Furthermore, the ODR modification block 15 also allows compensating for variations in the output data rate of the sensor 5 relative to the corresponding designed nominal value.

[0098] The change in the output data rate can actually be determined by the resonant frequency f of the mechanical oscillator 20. r caused by possible deviations from the corresponding design nominal values.

[0099] For example, the variation in the output data rate of the sensor 5 may be caused by variability in the manufacturing process of the detection unit 9 of the sensor 5. In this case, the resonant frequency f r Deviations from the corresponding design nominal values ​​will also result in the operating frequency f o As a result, according to the operating frequency f o The sampling frequency f is selected s will also be affected by the variation, which in turn will cause the output data rate of the sensor to deviate from the corresponding design nominal value in the absence of the ODR modification block 15 .

[0100] Variations in the output data rate may also be caused by possible deviations of the oscillation frequency of the electronic oscillator (eg clock) of the sensor 5 from a designed nominal value.

[0101] Thus, the present sensor allows correction of deviations of the output data rate from the sensor itself relative to a desired nominal value.

[0102] Furthermore, the gain block 52 is arranged in cascade with the downsampler 46 and thus Figure 5 The first decimator 40 is then executed after the corresponding downsampling 115B Figure 5 The fact that the amplification 115C is performed before the downsampling 115B allows the sensor 5, and therefore the electronic device 1, to have a low energy consumption. In fact, the gain block 52 is configured to operate at the sampling frequency of the downsampled signal DS, which is, for example, lower than the sampling frequency of the filtered signal F output by the filtering stage 43. Vice versa, for example, if the amplification 115C is performed before the downsampling 115B, the gain block 52 should be configured to operate at the frequency of the filtered signal F (which is higher than the frequency of the downsampled signal DS) and would therefore require a greater energy consumption of the sensor 5 and the electronic device 1.

[0103] Finally, it is clear that modifications and variations may be made to the sensor, the electronic device and the method for personalizing the output data rate described and illustrated herein without departing from the scope of protection of the present disclosure as defined in the accompanying claims.

[0104] For example, Figure 4 and 5 The steps of the method 100 can be obtained by using a hardware solution, by means of a dedicated circuit, as well as by using a software solution, by means of a dedicated computer program.

[0105] For example, the sensor 5 can be formed in a single die or multiple dies of semiconductor material. In particular, the detection unit 9 can be formed in a first die, and the signal conditioning stage 10 and the ODR modification block 15 can be formed in a second die. Alternatively, the analog circuit (here, the analog front end 23) and the digital circuit (here, the analog-to-digital converter 26, the filter 28 and the ODR modification block 15) can be formed on two different dies.

[0106] However, in general, in the sensor 5, the detection unit 9, the analog front end 23 and the analog-to-digital converter 26 may be considered functionally to form a digital detector 13, which is Figure 1 In some applications, the filter 28 may also be considered as belonging to the digital detector 13.

[0107] A sensor (5) is configured to provide a digital output signal (S O ), the sensor can be summarized as comprising: a digital detector (13) configured to detect a physical quantity and generate a conditioned digital signal (S) indicative of the detected physical quantity D); and a rate modification stage (15) configured to receive the conditioned digital signal and a parameter set (K), the parameter set comprising an interpolation factor (I1) and a downsampling factor (D1, M), and the rate modification stage being configured to provide a digital output signal, wherein the rate modification stage comprises an interpolator (36) and a decimation element (40, 60), the interpolator being configured to receive and upsample the conditioned digital signal based on the interpolation factor and provide an interpolated signal (S D,int ), the decimation element is configured to downsample the interpolated signal based on a downsampling factor to generate a digital output signal.

[0108] The sensor may be a MEMS sensor.

[0109] The digital detector (13) may comprise a detection unit (9) and a conditioning stage (10), the detection unit (9) being configured to detect a physical quantity and to generate an analog signal (S) indicative of the detected physical quantity. A ), the regulating stage (10) is configured to receive an analog signal (S A ) and discretize it to generate the adjustment digital signal (S D ).

[0110] The detection unit (9) may include a mechanical oscillator (20) configured to be actuated at an operating frequency (f0) and to oscillate at an oscillation frequency that depends on the operating frequency and the physical quantity to be detected, and a sensing element (18) configured to convert the oscillation of the mechanical oscillator into an analog signal (S A ).

[0111] The decimation element may include: a first decimator (40) including a filter stage (43), a downsampling stage (46, 49) and a gain stage (52); the filter stage (43) including a low-pass filter having a corresponding cut-off frequency (f c ) and is configured to receive the interpolation signal (S D,int ) and generates a filtered signal (F); a downsampling stage (46, 49) configured to downsample the filtered signal using a first decimation factor (D1) and generate a downsampled signal (DS) having a DC component; and the gain stage (52) configured to amplify or attenuate the DC component of the downsampled signal by a gain value (G).

[0112] The cutoff frequency of the filter stage (43) and the gain value of the gain stage (52) may be based on the first decimation factor (D1).

[0113] The decimation unit may include a first decimator (40) configured to receive the interpolated signal (S D,int ) and downsamples the interpolated signal using a first decimation factor (D1) to generate a decimated signal (SD,dec ); The extraction unit may include a second extractor (60), which is configured to receive the extraction signal (S D,dec ) and perform 2 on the extracted signal M The values ​​are downsampled by powers of 2, where M is the second decimation factor.

[0114] The regulation stage (10) may include an analog front end (23) configured to receive an analog signal (S A ) and having an output; an analog-to-digital converter (26) coupled to the output of the analog front end and configured to provide a sampled signal (S S ); and a filter (28) configured to receive the sampled signal and filter it to generate an adjusted digital signal (S D ).

[0115] An electronic apparatus may be summarized as comprising: a sensor, and may further comprise an interface device (7, 30, 33) configured to send the set of parameters (K) to a rate modification block (15) of the sensor.

[0116] A method for personalizing a digital output signal (S) from a sensor (5) O ) of the sampling rate, the sensor comprises: a rate modification stage (15) which receives a conditioned digital signal (S) associated with the detected physical quantity D ), the rate modification stage comprising an interpolator (36) and a decimation element (40, 60), the method can be summarized as comprising: receiving, by the rate modification stage (15), a parameter set (K) comprising an interpolation factor (I1) and a downsampling factor (D1, M); upsampling the conditioned digital signal using the interpolation factor to obtain an interpolated signal (S D,int ); and interpolating the signal using the downsampling factor (S D,int ) is down-sampled to obtain a digital output signal (S O ).

[0117] The sensor may be a MEMS sensor comprising a detection unit (9), the detection unit (9) comprising a mechanical oscillator (20), the mechanical oscillator being configured to be actuated at an operating frequency (f0), the conditioned digital signal having a conditioned sampling rate (f′) according to the operating frequency of the mechanical oscillator s ).

[0118] Use the downsampling factor to interpolate the signal (S D,int ) can be down-sampled by having a cut-off frequency (f c) filters (115A) an interpolated signal provided by the interpolator (36) by a low-pass filter (43) to obtain a filtered signal (F); downsamples (115B) the filtered signal using a first decimation factor (D1) to obtain a downsampled signal (DS) having a DC component; and modifies (115C) the DC component of the downsampled signal by amplifying or attenuating the DC component using a gain value.

[0119] The cutoff frequency and gain value may be based on the first decimation factor (D1).

[0120] The decimation element may include a first decimator (40) and a second decimator (60), and wherein downsampling the interpolated signal may include downsampling the interpolated signal by the first decimator (40) using a first decimation factor to obtain a decimated signal (S D,dec ); and performing 2 on the extracted signal by the second extractor (60); M The digital output signal (S O ), where M is the second decimation factor.

[0121] In one embodiment, a sensor includes: a digital detector that, in operation, detects a physical quantity and generates a conditioned digital signal indicative of the detected physical quantity; and signal processing circuitry coupled to the digital detector, wherein the signal processing circuitry, in operation, generates a digital output signal for the sensor based on the conditioned digital signal and a parameter set including an interpolation factor and a downsampling factor. Generating the digital output signal includes: upsampling the conditioned digital signal based on the interpolation factor to generate an interpolated signal; and downsampling the interpolated signal based on the downsampling factor to generate the digital output signal. In one embodiment, the signal processing circuitry includes: an interpolator coupled to the digital detector, wherein the interpolator, in operation, upsamples the conditioned digital signal based on the interpolation factor to generate the interpolated signal; and decimation circuitry coupled to the interpolator, wherein the decimation circuitry, in operation, downsamples the interpolated signal based on the downsampling factor. In one embodiment, the sensor is a MEMS sensor. In one embodiment, the digital detector includes: a detection circuit device that detects the physical quantity and generates an analog signal indicative of the detected physical quantity; and a conditioning circuit coupled to the detection circuit device, wherein the conditioning circuit digitizes the analog signal to generate the conditioned digital signal. In one embodiment, the detection circuit device includes a mechanical oscillator and a sensing element coupled to the mechanical oscillator, wherein the mechanical oscillator is configured to be actuated at an operating frequency and oscillate at an oscillation frequency based on the operating frequency and the physical quantity to be detected, and the sensing element is configured to convert the oscillation of the mechanical oscillator into an analog signal. In one embodiment, the decimation circuit device includes a first decimator, the first decimator including: a low-pass filter having a cutoff frequency, wherein the low-pass filter generates a filtered signal based on the interpolated signal; a downsampler coupled to the low-pass filter, wherein the downsampler downsamples the filtered signal using a first decimation factor to generate a downsampled signal having a DC component; and a gain circuit coupled to the downsampler, wherein the gain circuit applies gain to amplify or attenuate the DC component of the downsampled signal. In one embodiment, the cutoff frequency of the filter and the gain of the gain circuit are based on a first decimation factor. In one embodiment, the decimation circuit device includes a first decimator configured to receive the interpolated signal and downsample the interpolated signal using the first decimation factor to generate a decimated signal; the decimation circuit device includes a second decimator configured to receive the decimated signal and apply 2 decimation to the decimated signal. MThe scalar value is downsampled to a power of two, where M is a second decimation factor. In one embodiment, the conditioning circuit includes: an analog front end configured to receive an analog signal and having an output; an analog-to-digital converter coupled to the output of the analog front end and configured to provide a sampled signal; and a filter configured to filter the sampled signal to generate a conditioned digital signal. In one embodiment, the sensor includes an input that receives the parameter set in operation.

[0122] In one embodiment, a system includes: a sensor that, in operation, detects a physical quantity and generates a conditioned digital signal indicative of the detected physical quantity; and generates a digital output signal of the sensor based on the conditioned digital signal and a parameter set including an interpolation factor and a downsampling factor, wherein generating the digital output signal includes: upsampling the conditioned digital signal based on the interpolation factor to generate an interpolated signal; and downsampling the interpolated signal based on the downsampling factor to generate the digital output signal; and an interface coupled to the sensor, wherein the sensor receives the parameter set via the interface in operation. In one embodiment, the system includes a configuration register, wherein the interface stores the parameter set in the configuration interface. In one embodiment, the system includes an application processor coupled to the interface, wherein the application processor, in operation, executes an application that generates the parameter set.

[0123] In one embodiment, a method includes: detecting a physical quantity via detection circuitry of a sensor; generating, via the detection circuitry of the sensor, a conditioned digital signal indicative of the detected physical quantity; and generating, by signal processing circuitry of the sensor, a digital output signal of the sensor based on the conditioned digital signal and a parameter set including an interpolation factor and a downsampling factor, wherein generating the digital output signal includes: upsampling the conditioned digital signal based on the interpolation factor to generate an interpolated signal; and downsampling the interpolated signal based on the downsampling factor to generate the digital output signal. In one embodiment, the method includes: receiving the parameter set by the signal processing circuitry of the sensor. In one embodiment, the sensor is a MEMS sensor including a detector, the detector including a mechanical oscillator configured to be actuated at an operating frequency, and the conditioned digital signal has a sampling rate conditioned according to the operating frequency of the mechanical oscillator. In an embodiment, downsampling the interpolated signal based on the downsampling factor includes: filtering the interpolated signal using a low-pass filter having a cutoff frequency to obtain a filtered signal; downsampling the filtered signal using a first decimation factor to obtain a downsampled signal having a DC component; and amplifying or attenuating the DC component using a gain value. In one embodiment, the cutoff frequency and the gain value are based on the first decimation factor. In one embodiment, downsampling the interpolated signal includes: downsampling the interpolated signal using the first decimation factor using a first decimator to obtain a decimated signal; and decimating the decimated signal using a second decimator. M The digital output signal is obtained by downsampling the signal to the power of , where M is the second decimation factor.

[0124] In one embodiment, the contents of a non-transitory computer-readable medium configure a sensor to perform a method comprising: detecting a physical quantity by a detection circuit device of the sensor; generating a conditioned digital signal indicative of the detected physical quantity by the detection circuit device of the sensor; and generating a digital output signal of the sensor by a signal processing circuit device of the sensor based on the conditioned digital signal and a parameter set including an interpolation factor and a downsampling factor, wherein generating the digital output signal comprises: upsampling the conditioned digital signal based on the interpolation factor to generate an interpolated signal; and downsampling the interpolated signal based on the downsampling factor to generate the digital output signal. In one embodiment, the contents comprise instructions executed by the signal processing circuit device of the sensor. In one embodiment, the method comprises receiving the parameter set via an interface coupled to the signal processing circuit device.

[0125] Some embodiments may take the form of or include a computer program product. For example, according to one embodiment, a computer readable medium is provided that includes a computer program suitable for performing one or more of the above methods or functions. The medium may be a physical storage medium, such as a read-only memory (ROM) chip, or a disk, such as a digital versatile disk (DVD-ROM), a compact disk (CD-ROM), a hard disk, a memory, a network, or a portable medium article to be read by an appropriate drive or via an appropriate connection, including one or more bar codes or other related codes encoded on one or more such computer readable media and readable by an appropriate reader device.

[0126] In addition, in some embodiments, some or all of these methods and / or functions may be implemented or provided in other manners, such as at least partially implemented or provided in firmware and / or hardware, which firmware and / or hardware include but are not limited to one or more application-specific integrated circuits (ASICs), digital signal processors, discrete circuits, logic gates, standard integrated circuits, controllers (e.g., by executing appropriate instructions, and including microcontrollers and / or embedded controllers), field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), etc., as well as devices using RFID technology and various combinations thereof.

[0127] The various embodiments described above can be combined to provide further embodiments. If necessary, aspects of the embodiments can be modified to employ concepts of the various patents, applications, and publications to provide further embodiments.

[0128] These and other changes can be made to the embodiments in light of the above detailed description. Generally, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and claims, but should be construed to include all possible embodiments and the full scope of equivalents to which such claims are entitled. Therefore, the claims are not limited by this disclosure.

Claims

1. A sensor comprising: a digital detector that, in operation, detects a physical quantity and generates a conditioned digital signal indicative of the detected physical quantity; as well as signal processing circuitry coupled to the digital detector, wherein the signal processing circuitry is operable to generate a digital output signal of the sensor based on the conditioned digital signal and a set of parameters, the set of parameters including an interpolation factor and a downsampling factor, generating the digital output signal comprising: upsampling the conditioned digital signal based on the interpolation factor to generate an interpolated signal; and downsampling the interpolated signal based on the downsampling factor to generate the digital output signal; The signal processing circuit device comprises: an interpolator coupled to the digital detector, wherein the interpolator is operative to upsample the conditioned digital signal based on the interpolation factor to generate the interpolated signal; and decimation circuitry coupled to the interpolator, wherein the decimation circuitry is operative to downsample the interpolated signal based on the downsampling factor; The extraction circuit device includes a first extractor, and the first extractor includes: a low-pass filter having a cutoff frequency, wherein the low-pass filter is operable to generate a filtered signal based on the interpolated signal; a downsampler coupled to the low pass filter, wherein the downsampler is operative to downsample the filtered signal using a first decimation factor to generate a downsampled signal having a DC component; and a gain circuit device coupled to the downsampler, wherein the gain circuit device is operative to apply a gain to amplify or attenuate the DC component of the downsampled signal; The cutoff frequency of the filter and the gain of the gain circuit device depend on the first decimation factor. The sensor according to claim 1 , wherein the sensor is a MEMS sensor.

3. The sensor of claim 1 , wherein the digital detector comprises: detection circuitry operable to detect the physical quantity and generate an analog signal indicative of the detected physical quantity; as well as Conditioning circuitry is coupled to the detection circuitry, wherein the conditioning circuitry is operative to digitize the analog signal to generate the conditioned digital signal.

4. The sensor according to claim 3, wherein the detection circuit device comprises: a mechanical oscillator and a sensing element coupled to the mechanical oscillator, the mechanical oscillator being configured to be actuated at an operating frequency and configured to oscillate at an oscillation frequency according to the operating frequency and the physical quantity to be detected, and the sensing element being configured to convert the oscillation of the mechanical oscillator into the analog signal.

5. The sensor according to claim 1, wherein: The decimation circuitry includes a first decimator configured to receive the interpolated signal and downsample the interpolated signal using a first decimation factor to generate a decimated signal; as well as The decimation circuit arrangement includes a second decimator configured to receive the decimated signal and apply 2 M The values ​​are downsampled by powers of 2, where M is the second decimation factor.

6. The sensor of claim 3, wherein the conditioning circuitry comprises: an analog front end configured to receive the analog signal and having an output; an analog-to-digital converter coupled to the output of the analog front end and configured to provide a sampled signal; and a filter configured to filter the sampled signal to generate the conditioned digital signal.

7. The sensor of claim 1, comprising an input operable to receive the set of parameters.

8. A system comprising: A sensor, the sensor in operation: detecting a physical quantity and generating a conditioned digital signal indicative of the detected physical quantity; as well as Generating a digital output signal of the sensor based on the conditioned digital signal and a set of parameters, the set of parameters including an interpolation factor and a downsampling factor, the generating the digital output signal comprising: upsampling the conditioned digital signal based on the interpolation factor to generate an interpolated signal; and downsampling the interpolated signal based on the downsampling factor to generate the digital output signal; and an interface coupled to the sensor, wherein the sensor is operable to receive the set of parameters via the interface; Wherein downsampling the interpolation signal based on the downsampling factor comprises: filtering the interpolated signal using a low-pass filter having a cutoff frequency to obtain a filtered signal; downsampling the filtered signal using a first decimation factor to obtain a downsampled signal having a DC component; and amplifying or attenuating the DC component using a gain value; The cutoff frequency and the gain value depend on the first decimation factor.

9. The system of claim 8, comprising a configuration register, wherein the interface stores the set of parameters in the configuration interface.

10. The system of claim 9, comprising an application processor coupled to the interface, wherein the application processor is operable to execute an application that generates the set of parameters.

11. A method comprising: The physical quantity is detected by the detection circuit device of the sensor; generating, by the detection circuitry of the sensor, a conditioned digital signal indicative of the detected physical quantity; as well as Generating, by signal processing circuitry of the sensor, a digital output signal of the sensor based on the conditioned digital signal and a parameter set, the parameter set including an interpolation factor and a downsampling factor, wherein generating the digital output signal comprises: upsampling the conditioned digital signal based on the interpolation factor to generate an interpolated signal; and downsampling the interpolated signal based on the downsampling factor to generate the digital output signal; Wherein downsampling the interpolation signal based on the downsampling factor comprises: filtering the interpolated signal using a low-pass filter having a cutoff frequency to obtain a filtered signal; downsampling the filtered signal using a first decimation factor to obtain a downsampled signal having a DC component; and amplifying or attenuating the DC component using a gain value; The cutoff frequency and the gain value depend on the first decimation factor.

12. The method according to claim 11, comprising: The parameter set is received by the signal processing circuitry of the sensor.

13. The method of claim 11 , wherein the sensor is a MEMS sensor comprising a detector comprising a mechanical oscillator configured to be actuated at an operating frequency, the conditioned digital signal having a conditioned sampling rate dependent on the operating frequency of the mechanical oscillator.

14. The method of claim 11 , wherein downsampling the interpolated signal comprises: downsampling the interpolated signal using a first decimator using a first decimation factor to obtain a decimated signal; as well as The decimated signal is 2 M The digital output signal is obtained by downsampling the value by a power of 2, where M is a second decimation factor.

15. A non-transitory computer-readable medium having content for configuring a sensor to perform a method comprising: detecting a physical quantity by a detection circuit device of the sensor; generating, by the detection circuitry of the sensor, a conditioned digital signal indicative of the detected physical quantity; as well as Generating, by signal processing circuitry of the sensor, a digital output signal of the sensor based on the conditioned digital signal and a parameter set, the parameter set including an interpolation factor and a downsampling factor, wherein generating the digital output signal comprises: upsampling the conditioned digital signal based on the interpolation factor to generate an interpolated signal; and downsampling the interpolated signal based on the downsampling factor to generate the digital output signal; Wherein downsampling the interpolation signal based on the downsampling factor comprises: filtering the interpolated signal using a low-pass filter having a cutoff frequency to obtain a filtered signal; downsampling the filtered signal using a first decimation factor to obtain a downsampled signal having a DC component; and amplifying or attenuating the DC component using a gain value; The cutoff frequency and the gain value depend on the first decimation factor.

16. The non-transitory computer-readable medium of claim 15, wherein the content comprises instructions executed by the signal processing circuitry of the sensor. 17 . The non-transitory computer-readable medium of claim 15 , wherein the method comprises receiving the set of parameters via an interface coupled to the signal processing circuitry.

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