A power line rejection filter suitable for a sigma-delta ADC

Abstract

The application discloses a power frequency suppression filter suitable for a Sigma-delta ADC, comprising SINC1 filters SINC1_1-SINC1_6, FIR filters F1 and F2, decimation modules M1-M6, data selectors MUX1 and MUX2, mean filters MF1 and MF2; the power frequency suppression filter circuit suitable for the Sigma-delta ADC can simultaneously suppress 50Hz and 60Hz power frequency interference; the application adopts a multistage SINC1 filter and a FIR cascade structure, and can complete power frequency suppression under a set output sampling frequency; the application adopts a SINC1 filter multiplexing structure, reduces circuit area and power consumption; the application adopts a FIR filter multiplexing structure, maximally reduces multiplier use resources, and optimizes circuit area and power consumption.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of filter, in particular to a power frequency rejection filter suitable for Sigma-delta ADC. BACKGROUND

[0002] Power frequency interference is a kind of interference caused by power system, the power frequency in mainland China is composed of 50Hz and its harmonics, the amplitude is about 50% of ECG signal, and there is also 60Hz power frequency in some other countries. When the circuit is used for high-precision sensitive signal measurement, the power frequency interference will make the measurement signal submerged in the power frequency waveform, which seriously affects the measurement stability. Sigma-delta ADC is often used for high-precision signal measurement, and its internal usually integrates digital filter circuit, so it is necessary to design corresponding digital notch filter according to its output frequency through hardware to filter out 50Hz or 60Hz power frequency and suppress power frequency interference.

[0003] The simplest notch filter structure realized by using second-order single-pole IIR filter has the following transfer function:

[0004]

[0005] In the formula, ω0=2πf0 / f s , represents the notch digital frequency (rad); f0 is the notch frequency (Hz), f s is the sampling frequency (Hz), and r represents the notch depth, the larger the number, the deeper the notch depth. The transfer function can be calculated by software to obtain specific coefficients, which is convenient for circuit implementation. The transfer function of the generated parameters is as follows:

[0006]

[0007] The implementation structure is shown in Figure 1 . As can be seen from formula (2), the system structure of IIR digital filter IIR is zero and pole structure, that is, there is a feedback loop in the system structure, and the positions of zero and pole are determined by the coefficients, so the stability of IIR filter system needs to be considered in the design, and it is more susceptible to the problem of finite length algorithm; at the same time, for multi-rate signal processing applications such as Sigma-delta ADC, IIR filter has no advantage in calculation.

[0008] Other commonly used notch filters also include adaptive notch filter based on LMS algorithm, and its main principle is as follows: Figure 2The input signal x(t) is superimposed by two frequency interference signals, and the adaptive filter needs to filter out the two interference signals ω1 and ω2, and s(t) is the useful signal that needs to be reserved. The adaptive filter needs to use two mutually orthogonal single-frequency signals, such as cos(ω1t) and sin(ω1t), to adjust the weights w1 and w2 through the LMS algorithm, so as to synthesize the same signal as the interference signal, and then realize the limited filtering of the interference signal through subtraction operation. The core of the LMS algorithm notch filter is the FIR filter, which will use a large number of multiplier resources, and two reference signals need to be input for filtering out one frequency of interference signal, and the operation is relatively complex. SUMMARY

[0009] The purpose of the present application is to provide a power frequency suppression filter suitable for Sigma-delta ADC, which adopts a multi-stage SINC1 filter and a FIR cascade structure to complete power frequency suppression at a set output sampling frequency.

[0010] The technical scheme of the present application is:

[0011] A power frequency suppression filter suitable for Sigma-delta ADC, comprising SINC1 filters SINC1_1-SINC1_6, FIR filters F1 and F2, decimation modules M1-M6, data selectors MUX1 and MUX2, and mean filters MF1 and MF2.

[0012] The input end of the SINC1 filter SINC1_1 is the input end of the power frequency suppression filter, the output ends of SINC1_1 are connected to the input ends of SINC1_2 and SINC1_5 respectively, the output end of SINC1_2 is connected to the input ends of SINC1_3 and SINC1_4 respectively, the output end of SINC1_3 is connected to the input ends of the FIR filter F1 and the decimation module M3 respectively, the output ends of SINC1_4 and SINC1_5 are connected to the input end of the decimation module M1 respectively, the output end of the FIR filter F1 is connected to the input end of the decimation module M4, the output end of the decimation module M1 is connected to the input ends of the FIR filter F2 and the data selector MUX1 respectively, the output end of the FIR filter F2 is connected to the other input end of the data selector MUX1, the output end of the data selector MUX1 is connected to the decimation module M2, the SINC1_6, the mean filters MF1 and MF2 in turn, the output ends of the mean filters MF1 and MF2 are connected to the input ends of the decimation modules M5 and M6 respectively, the output ends of the decimation modules M3-M6 are connected to the input ends of the data selector MUX2 respectively, and the output end of the data selector MUX2 is the output end of the power frequency suppression filter.

[0013] Preferably, SINC1_1 is composed of a 1st order integrator and a 1st order 24 differential delay comb filter, which completes low-pass filtering of the output signal of the previous stage and provides a notch point at 50Hz and its multiple frequencies;

[0014] SINC1_2 and SINC1_4 have the same structure, both of which are composed of a 1st order integrator and a 1st order 2 differential delay comb filter, which further filters and provides a notch point at 600Hz and its multiple frequencies;

[0015] SINC1_3 is composed of a 1st order integrator and a 1st order 20 differential delay comb filter, which further filters and provides a notch point at 60Hz and its multiple frequencies;

[0016] SINC1_5 is composed of a 1st order integrator and a 1st order 11 differential delay comb filter, which further filters and provides a notch point at 110Hz and its multiple frequencies;

[0017] SINC1_6 is composed of a 1st order integrator and a 1st order 6 differential delay comb filter, which filters after down-sampling by the previous stage filter and provides a notch point at 50Hz and its multiple frequencies.

[0018] Preferably, the SINC1 filters SINC1_3, SINC1_4 and SINC1_5 adopt a multiplexing mode.

[0019] Preferably, the FIR filters F1 and F2 each include a multiply-accumulator and a plurality of storage units for storing filter coefficients, the coefficients of each storage unit are multiplied by the data output by the corresponding SINC1 filter, and finally all the products are added.

[0020] Preferably, the FIR filters F1 and F2 have the same order, and the two FIR filters adopt a multiplexing mode.

[0021] Preferably, the decimation modules M1 to M6 respectively reduce the frequency of the output data to the actual required frequency, and a counter is used to achieve this in the circuit, and the counter value is adjusted according to the different decimation numbers.

[0022] Preferably, the decimation modules M3 to M6 adopt a multiplexing mode.

[0023] The advantages of the present application are:

[0024] 1. The power frequency suppression filter circuit suitable for Sigma-delta ADC provided by the present application can simultaneously suppress 50Hz and 60Hz power frequency interference;

[0025] 2. The present application adopts a multi-stage SINC1 filter and FIR cascade structure, which can complete power frequency suppression at a set output sampling frequency;

[0026] 3. This invention adopts a SINC1 filter multiplexing structure to reduce circuit area and power consumption;

[0027] 4. This invention adopts an FIR filter multiplexing structure to minimize the resources used by the multiplier and optimize circuit area and power consumption. Attached Figure Description

[0028] The present invention will be further described below with reference to the accompanying drawings and embodiments:

[0029] Figure 1 This is a typical IIR notch filter direct type II implementation architecture diagram;

[0030] Figure 2 The schematic diagram shows the implementation principle of an adaptive notch filter based on the LMS algorithm.

[0031] Figure 3 This is a block diagram of the power frequency suppression filter circuit described in this invention;

[0032] Figure 4 This is the SINC1 filter implementation architecture described in this invention;

[0033] Figure 5 This is the FIR filter implementation architecture described in this invention;

[0034] Figure 6 This is the implementation architecture of the mean filter described in this invention;

[0035] Figure 7 The above are the simulation results of the amplitude-frequency response at an output rate of 27.27Hz in the example.

[0036] Figure 8 The above are the simulation results of the amplitude-frequency response at an output rate of 25Hz in the example.

[0037] Figure 9 The above are the simulation results of the amplitude-frequency response at an output rate of 20Hz in the example.

[0038] Figure 10 The above are the simulation results of the amplitude-frequency response at an output rate of 16.67Hz in the example. Detailed Implementation

[0039] like Figure 1 The diagram shown is a block diagram of the power frequency suppression filter circuit for Sigma-delta ADCs described in this invention. The filter circuit mainly consists of sub-circuit modules such as SINC1 filters SINC1_1 to SINC1_6, FIR filters F1 and F2, decimation modules M1 to M6, data selectors MUX1 and MUX2, and mean filters MF1 and MF2.

[0040] The input end of the SINC1 filter SINC1_1 is the input end of the power frequency suppression filter, the output ends of SINC1_1 are respectively connected with the input ends of SINC1_2 and SINC1_5, the output end of SINC1_2 is respectively connected with the input ends of SINC1_3 and SINC1_4, the output ends of SINC1_3 are respectively connected with the input ends of the FIR filter F1 and the decimation module M3, the output ends of SINC1_4 and SINC1_5 are respectively connected with the input ends of the decimation module M1, the output end of the FIR filter F1 is connected with the input end of the decimation module M4, the output end of the decimation module M1 is respectively connected with the input ends of the FIR filter F2 and the data selector MUX1, the output end of the FIR filter F2 is connected with another input end of the data selector MUX1, the output end of the data selector MUX1 is connected with the decimation module M2, SINC1_6, the mean filter MF1 and MF2 in turn, the output ends of the mean filters MF1 and MF2 are respectively connected with the input ends of the decimation modules M5 and M6, the output ends of the decimation modules M3 to M6 are respectively connected with the input ends of the data selector MUX2, and the output end of the data selector MUX2 is the output end of the power frequency suppression filter.

[0041] Taking a 1.2 kHz frequency signal as an example.

[0042] The main structure of the SINC1 filter is shown in Figure 4 The N represents the number of differential delay units, wherein:

[0043] SINC1_1 is composed of a first integrator and a first 24 differential delay comb filter, which completes the low-pass filtering of the output signal of the previous stage and provides the notch point at 50 Hz and its multiple frequencies;

[0044] SINC1_2 and SINC1_4 have the same structure, which are composed of a first integrator and a first 2 differential delay comb filter, which further filter and provide the notch point at 600 Hz and its multiple frequencies;

[0045] SINC1_3 is composed of a first integrator and a first 20 differential delay comb filter, which further filters and provides the notch point at 60 Hz and its multiple frequencies;

[0046] SINC1_5 is composed of a first integrator and a first 11 differential delay comb filter, which further filters and provides the notch point at 110 Hz and its multiple frequencies;

[0047] SINC1_6 is composed of a first integrator and a first 6 differential delay comb filter, which completes the filtering after the decimation of the previous stage filter and provides the notch point at 50 Hz and its multiple frequencies. Here, since the structure of the SINC1 filter is similar, the detailed description is omitted here. Figure 3The SINC1 filters SINC1_3, SINC1_4 and SINC1_5 at the middle dotted line box adopt a multiplexing mode, thereby saving area.

[0048] The FIR filter is essentially obtained by multiplying each coefficient with the data output by the SINC1 filter, and finally adding all the products, as shown in the specific architecture. Figure 5 As shown, the entire filter design only needs one multiply-accumulator and a storage unit for storing filter coefficients, which is equivalent to adding a pipeline design, thereby greatly saving circuit area. Since the two FIR filters have the same order, as shown in the specific architecture, Figure 3 the two FIR filters MF1 and MF2 also adopt a multiplexing mode, thereby further reducing circuit hardware consumption.

[0049] Figure 3 As shown, M1 to M6 are decimation modules commonly used in multi-rate signal processing applications, which can reduce the output data frequency to the actual required frequency. In the circuit, a counter is usually used to achieve this, and only the count value needs to be adjusted according to the decimation number, so in the specific architecture, Figure 3 the decimation modules M3 to M6 in the last output stage also adopt a multiplexing mode.

[0050] Figure 6 As shown, the mean filter is cascaded after the SINC1, which can further improve the 50Hz or 60Hz interference suppression capability.

[0051] Figures 7 to 10 As shown, the amplitude-frequency response simulation results of the power frequency suppression filter according to the present application under several output rates are obtained by Figure 10 When the data output rate is the lowest at 16.67Hz, the 50Hz±1Hz and 60Hz±1Hz power frequency interference can be simultaneously suppressed, and the suppression capability is above 90dB. The filter according to the present application is particularly suitable for multi-rate signal processing systems such as Sigma-delta ADC, and can complete the down-sampling filter output while realizing 50Hz and 60Hz power frequency interference suppression.

[0052] The above embodiments are only for illustrating the technical concept and characteristics of the present application, and the purpose is to enable those skilled in the art to understand the content of the present application and implement it, and cannot limit the protection scope of the present application. Any modification made according to the spirit and essence of the main technical solution of the present application should be covered within the protection scope of the present application.

Claims

1. A power frequency suppression filter suitable for Sigma-delta ADCs, characterized in that, Includes SINC1 filters SINC1_1 to SINC1_6, FIR filters F1 and F2, decimation modules M1 to M6, data selectors MUX1 and MUX2, and mean filters MF1 and MF2. The input of SINC1_1 filter is the input of the power frequency suppression filter. The output of SINC1_1 is connected to the inputs of SINC1_2 and SINC1_5 respectively. The output of SINC1_2 is connected to the inputs of SINC1_3 and SINC1_4 respectively. The output of SINC1_3 is connected to the inputs of FIR filter F1 and decimation module M3 respectively. The outputs of SINC1_4 and SINC1_5 are connected to the inputs of decimation module M1 respectively. The output of FIR filter F1 is connected to the input of decimation module M4. Decimation module M1... The output terminals are connected to the input terminals of FIR filter F2 and data selector MUX1, respectively. The output terminal of FIR filter F2 is connected to the other input terminal of data selector MUX1. The output terminals of data selector MUX1 are cascaded with decimation module M2, SINC1_6, mean filter MF1, and MF2 in sequence. The output terminals of mean filter MF1 and MF2 are connected to the input terminals of decimation module M5 and M6, respectively. The output terminals of decimation modules M3 to M6 are connected to the input terminals of data selector MUX2, and the output terminal of data selector MUX2 is the output terminal of power frequency suppression filter. SINC1_1 consists of a single-stage integrator and a single-stage comb with 24 differential delays, which performs low-pass filtering of the output signal of the pre-stage while providing notch points at 50Hz and its harmonics. SINC1_2 and SINC1_4 have the same structure, both consisting of a single-stage integrator and a single-stage comb with two differential delays, which further filters the signal while providing notch points at 600Hz and its harmonics. SINC1_3 consists of a single-stage integrator and a single-stage comb with 20 differential delays, which further filters the signal while providing notch points at 60Hz and its harmonics. SINC1_5 consists of a single-stage integrator and a single-stage comb with 11 differential delays, which further filters the signal while providing notch points at 110Hz and its harmonics. SINC1_6 consists of a single-stage integrator and a single-stage comb with six differential delays. It is filtered by downsampling from the pre-stage filter and provides notch points at 50Hz and its harmonics.

2. The power frequency suppression filter suitable for Sigma-delta ADC according to claim 1, characterized in that, The SINC1 filters SINC1_3, SINC1_4, and SINC1_5 are multiplexed.

3. The power frequency suppression filter suitable for Sigma-delta ADC according to claim 1, characterized in that, The FIR filters F1 and F2 each include a multiply-accumulate unit and several storage units for storing filter coefficients. The coefficients of each storage unit are multiplied by the data output of the corresponding SINC1 filter, and finally all the products are added together.

4. The power frequency suppression filter suitable for Sigma-delta ADC according to claim 3, characterized in that, The FIR filters F1 and F2 have the same order, and the two FIR filters are multiplexed.

5. The power frequency suppression filter suitable for Sigma-delta ADC according to claim 3, characterized in that, The extraction modules M1 to M6 reduce the output data frequency to the actual required frequency, which is achieved by using a counter in the circuit, and adjusting the count value according to the different extraction numbers.

6. The power frequency suppression filter suitable for Sigma-delta ADC according to claim 5, characterized in that, The extraction modules M3 to M6 are reused.

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