Memory management method, memory controller and memory storage device

Abstract

The present invention belongs to the field of storage technology, and provides a memory management method, a memory controller, and a memory storage device, which obtains the number of reads of multiple physical units, and records the physical units whose number of reads exceeds a first threshold as risk physical units; obtains the first read time value of the risk physical unit, and records the risk physical unit whose first read time value is not greater than a second threshold as a target physical unit; and copies the data in the target physical unit to the first physical unit, which is the physical unit with the smallest operation value in the memory module. In this way, on the one hand, the number of times the data read at a high frequency is re-executed with the data moving operation is reduced; on the other hand, it is prevented that some physical units in the memory storage device quickly reach the maximum value of their erasure times, thereby affecting the life of the memory storage device.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a memory management method, a memory controller and a memory storage device. Background Art

[0002] Rewritable non-volatile memory has the characteristics of data non-volatility, power saving, small size and no mechanical structure, so it is widely used in various electronic devices. Rewritable non-volatile memory has multiple physical units (physical blocks), each of which includes multiple physical programming units (physical pages). Among them, the physical unit is the smallest unit for erasing data, and the physical programming unit page is the smallest unit for writing data.

[0003] When the host system wants to read the stored data from the memory storage device, the memory storage device reads the data from the physical unit according to the read instruction. Generally, when performing data operations on the physical programming unit multiple times, the data operations of other physical programming units in the same physical unit may be interfered, resulting in read data errors.

[0004] How to deal with the read disturbance problem is one of the topics that technicians in the field of the present invention have devoted themselves to studying. Summary of the invention

[0005] The present invention provides a memory management method, a memory controller and a memory storage device, which can solve the technical problem of read disturbance of a physical unit in the memory storage device.

[0006] An embodiment of the present invention provides a memory management method, which is applied to a memory storage device, wherein the memory storage device includes a memory module, the memory module includes multiple entity units, and the entity units include multiple entity programming units. The method includes: obtaining the number of reads of the multiple entity units, and recording the entity units whose reads exceed a first threshold as risk entity units; obtaining the first read time value of the risk entity unit, and recording the risk entity units whose first read time value is not greater than a second threshold as target entity units; copying the data in the target entity unit to the first entity unit, the first entity unit being the entity unit with the smallest operation value in the memory module; and updating the logical-to-physical mapping relationship of the data according to the physical address of the first entity unit.

[0007] Further, in one embodiment, the step of obtaining the reading times of the plurality of entity units and obtaining the first reading time value of the risk entity unit includes: establishing a first reading times table and a second reading times table;

[0008] The first reading number table is used to record the reading times of the multiple entity units, and the entity units in the first reading number table are sorted according to the reading times, wherein the larger the reading times, the higher the ranking of the entity unit; the second reading number table is used to record the first reading time value of the risk entity unit, and the first reading time value is the time interval from the last time the risk entity unit was read to the present, and the risk entity units are sorted according to the first reading time value, wherein the smaller the first reading time value, the higher the ranking of the risk entity unit; the risk entity unit whose first reading time value is not greater than the second threshold is selected from the second reading number table, and the risk entity unit whose first reading time value is not greater than the second threshold is recorded as the second entity unit; the target entity unit is selected from the second entity unit.

[0009] Further, in one embodiment, the step of selecting the target entity unit from the second entity unit includes: obtaining a second read time value of the first entity programming unit of the second entity unit, recording the second entity unit whose second read time value is greater than a third threshold as the target entity unit, the second read time value being the time for successfully reading the data stored in the first entity programming unit in response to a data read instruction.

[0010] Further, in one embodiment, the step of obtaining the second read time value of the first physical programming unit of the second physical unit and recording the second physical unit whose second read time value is greater than a third threshold as the target physical unit includes: obtaining the third read time value of the second physical programming unit of the second physical unit and recording the second physical unit whose third read time value is greater than a third threshold as the target physical unit, the third read time value being the time for successfully reading the data stored in the second physical programming unit in response to a data read instruction, and the first physical programming unit and the second physical programming unit belong to the same physical unit.

[0011] Further, in one embodiment, the step of copying the data in the target physical unit to the first physical unit includes: dividing the multiple physical units in the memory module into a data area and an idle area; grouping the multiple physical units in the idle area according to the number of erase times of the physical units to obtain multiple groups, each group corresponding to a different erase time value range; according to the amount of data in the target physical unit, selecting a suitable number of physical units from the group with the smallest erase time value range as the first physical unit, performing an erase operation on the first physical unit, and writing the data in the target physical unit into the first physical unit; marking the data in the target physical unit as invalid data or dividing the target physical unit into the idle area; dividing the first physical unit into the data area.

[0012] The present invention further provides a memory controller in one embodiment for controlling a memory module, wherein the memory module includes multiple physical units, and the physical units include multiple physical programmed units; the memory controller includes: a host interface for connecting to a host system; a memory interface for connecting to the memory module; and a memory control circuit connected to the host interface and the memory interface; the memory control circuit obtains the number of reads of the multiple physical units, and records the physical units whose read times exceed a first threshold as risky physical units; the memory control circuit obtains a first read time value of the risky physical unit, and records the risky physical unit whose first read time value is not greater than a second threshold as a target physical unit; the memory control circuit copies the data in the target physical unit to the first physical unit, and the first physical unit is the physical unit with the smallest operation value in the memory module; the memory control circuit updates the logical to physical mapping relationship of the data according to the physical address of the first physical unit.

[0013] Further, in one embodiment, the operation of the memory control circuit obtaining the number of reads of the multiple entity units and obtaining the first read time value of the risk entity unit includes: establishing a first read number table and a second read number table; the first read number table is used to record the number of reads of the multiple entity units, and the memory control circuit sorts the entity units in the first read number table according to the number of reads, wherein the greater the number of reads, the higher the ranking of the entity unit; the second read number table is used to record the first read time value of the risk entity unit, and the first read time value is the time interval from the last time the risk entity unit was read to the present, and the memory control circuit sorts the risk entity unit according to the first read time value, wherein the smaller the first read time value, the higher the ranking of the risk entity unit; the memory control circuit selects the risk entity unit whose first read time value is not greater than a second threshold from the second read number table, and records the risk entity unit whose first read time value is not greater than the second threshold as the second entity unit; the memory control circuit selects the target entity unit from the second entity unit.

[0014] Further, in one embodiment, the operation of the memory control circuit selecting the target physical unit from the second physical unit includes: the memory control circuit obtaining a second read time value of the first physical programming unit of the second physical unit, and the memory control circuit recording the second physical unit whose second read time value is greater than a third threshold as the target physical unit, wherein the second read time value is the time for successfully reading the data stored in the first physical programming unit in response to a data read instruction.

[0015] Further, in one embodiment, the memory control circuit obtains the second read time value of the first physical programming unit of the second physical unit, and the operation of recording the second physical unit whose second read time value is greater than a third threshold as the target physical unit includes: the memory control circuit obtains the third read time value of the second physical programming unit of the second physical unit, and the memory control circuit records the second physical unit whose third read time value is greater than a third threshold as the target physical unit, the third read time value is the time for successfully reading the data stored in the second physical programming unit in response to a data read instruction, and the first physical programming unit and the second physical programming unit belong to the same physical unit.

[0016] Further, in one embodiment, the operation of the memory control circuit copying the data in the target physical unit to the first physical unit includes: the memory control circuit divides the multiple physical units in the memory module into a data area and an idle area; and the memory control circuit divides the multiple physical units in the idle area into groups according to the number of erase times of the physical units to obtain multiple groups, each group corresponding to a different erase number value interval; the memory control circuit selects a suitable number of physical units from the group with the smallest erase number value interval as the first physical unit according to the amount of data in the target physical unit, and the memory control circuit performs an erase operation on the first physical unit to write the data in the target physical unit into the first physical unit; the memory control circuit marks the data in the target physical unit as invalid data or divides the target physical unit into the idle area; the memory control circuit divides the first physical unit into the data area.

[0017] The present invention further provides a memory storage device, which includes a connection interface, a memory module and a memory controller; the connection interface is used to connect the memory storage device to a host system; the memory module includes multiple physical units, and the physical units include multiple physical programming units; the memory controller is connected to the connection interface and the memory module; the memory controller obtains the number of reads of the multiple physical units, and records the physical units whose read times exceed a first threshold as risky physical units; and the memory controller obtains the first read time value of the risky physical unit, and records the risky physical unit whose first read time value is not greater than a second threshold as a target physical unit; the memory controller copies the data in the target physical unit to the first physical unit, and the first physical unit is the physical unit with the smallest operation value in the memory module; the memory controller updates the logical to physical mapping relationship of the data according to the physical address of the first physical unit.

[0018] Furthermore, the memory storage device includes a connection interface, a memory module and a memory controller; the connection interface is used to connect the memory storage device to a host system; the memory module includes a plurality of physical units, each of which includes a plurality of physical programming units; the memory controller is connected to the connection interface and the memory module; the memory controller is used to obtain the number of reads of the plurality of physical units, and record the physical units whose reads exceed a first threshold as risky physical units; the memory controller is used to obtain a first read time value of the risky physical unit, and record the risky physical unit whose first read time value is not greater than a second threshold as a target physical unit; the memory controller is used to copy the data in the target physical unit to the first physical unit, which is the physical unit with the smallest operation value in the memory module; the memory controller is used to update the logical-to-physical mapping relationship of the data according to the physical address of the first physical unit.

[0019] Further, in one embodiment, the operation of the memory controller obtaining the number of reads of the multiple entity units and obtaining the first read time value of the risk entity unit includes: establishing a first read number table and a second read number table; the first read number table is used to record the number of reads of the multiple entity units, and the memory controller sorts the entity units in the first read number table according to the number of reads, wherein the greater the number of reads, the higher the ranking of the entity unit; the second read number table is used to record the first read time value of the risk entity unit, and the first read time value is the time interval from the last time the risk entity unit was read to the present, and the memory controller sorts the risk entity unit according to the first read time value, wherein the smaller the first read time value, the higher the ranking of the risk entity unit; the memory controller selects the risk entity unit whose first read time value is not greater than a second threshold from the second read number table, and records the risk entity unit whose first read time value is not greater than the second threshold as the second entity unit; the memory controller selects the target entity unit from the second entity unit.

[0020] Further, in one embodiment, the operation of the memory controller selecting the target physical unit from the second physical unit includes: the memory controller obtaining a second read time value of the first physical programming unit of the second physical unit, and the memory controller recording the second physical unit whose second read time value is greater than a third threshold as the target physical unit, wherein the second read time value is the time for successfully reading the data stored in the first physical programming unit in response to a data read instruction.

[0021] Further, in one embodiment, the memory controller obtains the second read time value of the first physical programming unit of the second physical unit, and records the second physical unit whose second read time value is greater than a third threshold as the target physical unit. The operation includes: the memory controller obtains the third read time value of the second physical programming unit of the second physical unit, and the memory controller records the second physical unit whose third read time value is greater than a third threshold as the target physical unit, the third read time value is the time for successfully reading the data stored in the second physical programming unit in response to a data read instruction, and the first physical programming unit and the second physical programming unit belong to the same physical unit.

[0022] Further, in one embodiment, the operation of the memory controller copying the data in the target physical unit to the first physical unit includes: the memory controller divides the multiple physical units in the memory module into a data area and an idle area; and the memory controller divides the multiple physical units in the idle area into groups according to the number of erase times of the physical units to obtain multiple groups, each group corresponding to a different erase time value interval; the memory controller selects a suitable number of physical units as the first physical unit from the group with the smallest erase time value interval according to the amount of data in the target physical unit, and the memory controller performs an erase operation on the first physical unit to write the data in the target physical unit into the first physical unit; the memory controller marks the data in the target physical unit as invalid data or divides the target physical unit into the idle area; the memory controller divides the first physical unit into the data area.

[0023] The present invention provides a memory management method, a memory controller and a memory storage device, which obtain the number of reads of multiple physical units, record the physical units whose number of reads exceeds a first threshold as risk physical units; obtain the first read time value of the risk physical unit, record the risk physical unit whose first read time value is not greater than a second threshold as a target physical unit; copy the data in the target physical unit to the first physical unit, which is the physical unit with the smallest operation value in the memory module. In this way, on the one hand, the number of times the data read at a high frequency is re-executed with the data moving operation is reduced; on the other hand, it is prevented that some physical units in the memory storage device quickly reach the maximum number of erase times, thereby affecting the life of the memory storage device.

[0024] In order to make the above technical features and beneficial effects of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic diagram of a memory storage device according to an embodiment of the present invention;

[0026] Figure 2 A structural block diagram of a memory controller according to an embodiment of the present invention;

[0027] Figure 3 A schematic diagram of a memory management module according to an embodiment of the present invention;

[0028] Figure 4 A schematic diagram of a memory management module according to an embodiment of the present invention;

[0029] Figure 5 A schematic diagram showing the first reading times of a physical unit according to an embodiment of the present invention;

[0030] Figure 6 A schematic diagram showing a second reading number of a physical unit according to an embodiment of the present invention;

[0031] Figure 7 A schematic diagram of a physical unit erasure times table according to an embodiment of the present invention;

[0032] Figure 8 A schematic diagram of a memory management module according to an embodiment of the present invention;

[0033] Fig. 9 A schematic diagram of a bad block table according to an embodiment of the present invention;

[0034] Fig.10 A schematic diagram of a memory management module according to an embodiment of the present invention;

[0035] Fig.11 A flowchart of a memory management method is shown in an embodiment of the present invention. DETAILED DESCRIPTION

[0036] The specific structure and implementation scheme of the storage system described in the embodiment of the present application are described in detail below with reference to the accompanying drawings and examples.

[0037] Figure 1 is a schematic diagram of a storage system according to an embodiment of the present invention. Figure 1, the storage system 10 includes a host system 11 and a memory storage device 12. The host system 11 can be any type of computer system. For example. The host system 11 can be a notebook computer, a desktop computer, a smart phone, a tablet computer, an industrial computer, a game console, a digital camera and other electronic systems. The memory storage device 12 is used to store data from the host system 11. For example, the memory storage device 12 may include a solid state drive, a USB flash drive, a memory card or other types of non-volatile storage devices. The host system 11 can be electrically connected to the memory storage device 12 via a Serial Advanced Technology Attachment (SATA) interface, a high-speed peripheral component connection interface (PCI Express), a Universal Serial Bus (USB) or other types of connection interfaces. Therefore, the host system 11 can store data to the memory storage device 12 and / or read data from the memory storage device 12.

[0038] The memory storage device 12 may include a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the memory storage device 12 to the host system 11. For example, the connection interface 121 may support connection interface standards such as SATA, PCI Express, or USB. The memory storage device 12 may communicate with the host system 11 via the connection interface 121.

[0039] The memory module 122 is used to store data. The memory module 122 may include a rewritable non-volatile memory module. The memory module 122 includes a memory cell array. The memory cells in the memory module 122 store data in the form of voltage. For example, the memory module 122 may include a single-level cell (SLC) NAND flash memory module, a multi-level cell (MLC) NAND flash memory module, a triple-level cell (TLC) NAND flash memory module, a quad-level cell (QLC) NAND flash memory module, or other memory modules with similar characteristics.

[0040] The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 can be used to control the memory storage device 12. For example, the memory controller 123 can control the connection interface 121 and the memory module 122 to perform data access and data management. For example, the memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (Digital Signal Processor, DSP), programmable controllers, application specific integrated circuits (Application Specific Integrated Circuits, ASIC), programmable logic devices (Programmable Logic Device, PLD) or other similar devices or combinations of these devices.

[0041] In one embodiment, the memory controller 123 is also called a flash memory controller. In one embodiment, the memory module 122 is also called a flash memory module. The memory module 122 can receive a command sequence from the memory controller 123 and access the storage unit according to the command sequence.

[0042] Figure 2 FIG. 1 is a block diagram of a memory controller according to an embodiment of the present invention. Figure 2 The memory controller 123 includes a memory control circuit 204 , a host interface 202 and a memory interface 206 .

[0043] The memory control circuit 204 is used to control the overall operation of the memory controller 123. Specifically, the memory control circuit 204 has a plurality of control instructions, and when the memory storage device 12 operates, these control instructions are executed to perform operations such as writing, reading and erasing data. The following description of the operation of the memory control circuit 204 is equivalent to the description of the operation of the memory controller 123.

[0044] In this embodiment, the control instructions of the memory control circuit 204 are operated in the form of firmware. For example, the memory control circuit 204 has a microprocessor unit ( Figure 2 ) and a read-only memory ( Figure 2 ), and the control instructions are burned into the read-only memory. When the memory storage device 12 is in operation, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading and erasing data.

[0045] In another embodiment, the control instructions of the memory control circuit 204 can also be stored in a specific area of ​​the memory module 122 (for example, a system area in the memory module dedicated to storing system data) in the form of program code. In addition, the memory control circuit 204 has a microprocessor unit (not shown), a read-only memory (not shown) and a random access memory (not shown). In particular, the read-only memory has a boot code, and when the memory controller 123 is enabled, the microprocessor unit will first execute the boot code to load the control instructions stored in the memory module 122 into the random access memory of the memory control circuit 204. Afterwards, the microprocessor unit will run these control instructions to perform operations such as writing, reading and erasing data.

[0046] The host interface 202 is electrically connected to the memory control circuit 204 and is used to receive and identify instructions and data transmitted by the host system 11. In other words, the instructions and data transmitted by the host system 11 are transmitted to the memory control circuit 204 through the host interface 202. In the present embodiment, the host interface 202 is compatible with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 202 may also be compatible with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard or other suitable data transmission standards.

[0047] The memory interface 206 is electrically connected to the memory control circuit 204 and is used to access the memory module 122. That is, the data to be written to the memory module 122 will be converted into a format acceptable to the memory module 122 via the memory interface 206. Specifically, if the memory control circuit 204 wants to access the memory module 122, the memory interface 206 will transmit the corresponding instruction sequence. For example, these instruction sequences may include a write instruction sequence indicating writing data, a read instruction sequence indicating reading data, an erase instruction sequence indicating erasing data, and corresponding instruction sequences for indicating various memory operations (for example, changing the read voltage level or performing garbage collection operations, etc.). These instruction sequences are, for example, generated by the memory control circuit 204 and transmitted to the memory module 122 through the memory interface 206. These instruction sequences may include one or more signals, or data on the bus. These signals or data may include instruction codes or program codes. For example, in the read instruction sequence, information such as the read identification code and memory address will be included.

[0048] In this embodiment, the memory controller 123 can perform single-frame encoding for data stored in the same physical programming unit, or can perform multi-frame encoding for data stored in multiple physical programming units. According to the encoding algorithm adopted, the memory controller 123 can encode the data to be protected to generate corresponding error correction codes and / or error checking codes.

[0049] In one embodiment, the memory controller 123 further includes a buffer memory 210, an error checking and correction circuit 212, and a power management circuit 208. The buffer memory 210 is electrically connected to the memory control circuit 204 and is used to temporarily store data and instructions from the host system 11 or data from the memory module 122. The power management circuit 208 is electrically connected to the memory control circuit 204 and is used to control the power of the memory storage device 12. The error checking and correction circuit 212 is electrically connected to the memory control circuit 204 and is used to perform error checking and correction operations to ensure the correctness of the data.

[0050] Specifically, when the memory control circuit 204 receives a write instruction from the host system 11, the error checking and correction circuit 212 generates a corresponding error correction code (ECC) and / or an error detecting code (EDC) for the data corresponding to the write instruction, and the memory control circuit 204 writes the data corresponding to the write instruction and the corresponding error correction code and / or error checking code into the memory module 122. Afterwards, when the memory control circuit 204 reads data from the memory module 122, it simultaneously reads the error correction code and / or error checking code corresponding to the data, and the error checking and correction circuit 212 performs error checking and correction operations on the read data according to the error correction code and / or error checking code.

[0051] Figure 3 FIG. 1 is a schematic diagram of a management memory module according to an embodiment of the present invention. Figure 3 , the memory module 122 includes a plurality of physical units 301(0)--301(A). Each physical unit includes a plurality of storage cells and is used to store data in a non-volatile manner. For example, a physical unit may include one or more physical blocks. Each physical block may include a plurality of physical programming units. A physical programming unit may include one or more storage cells. Multiple storage cells in a physical programming unit may be programmed simultaneously to store data. In addition, all physical programming units in a physical unit may be erased simultaneously.

[0052] Further, if Figure 3 As shown, the memory control circuit 204 can configure multiple logical units 302 (0)--302 (B) to map physical units 301 (1)--301 (A). For example, a logical unit can be composed of one or more logical addresses. The mapping relationship between the logical unit and the physical unit can be recorded in a logical-to-physical mapping table (L2P). Exemplarily, the mapping of the logical physical unit to the physical physical unit is called block (block) mapping; the mapping of the logical physical programming unit to the physical physical programming unit is called physical programming unit (page) mapping. In the following, the logical-to-physical mapping table can be understood as a logical-to-physical mapping table. When receiving an access instruction from the host system 11, the memory control circuit 204 can access data to the physical unit according to the corresponding logical-to-physical mapping table.

[0053] Figure 4 is a schematic diagram of a management memory module according to an embodiment of the present invention. Figure 4 As shown, in one embodiment, the memory control circuit 204 logically groups the physical units 301 ( 0 )- 301 (A) into a data area 506 , a spare area 504 , a system area 502 , and a replacement area 508 .

[0054] It should be understood that in this embodiment, when describing the operation of the physical units of the memory module 122, the words "extract", "group", "partition", "associate", etc. to operate the physical units are logical concepts. In other words, the actual position of the physical units of the memory module 122 is not changed, but the physical units of the memory module 122 are operated logically.

[0055] The physical units logically belonging to the data area 506 and the idle area 504 are used to store data from the host system 11. Specifically, the physical units of the data area 506 are regarded as physical units that have stored data, and the physical units of the idle area 504 are used to replace the physical units of the data area 506. That is, when receiving a write instruction and data to be written from the host system 11, the memory control circuit 204 extracts physical units from the idle area 504 to write data, and the physical units written with data are then divided from the idle area 504 into the data area 506 and are no longer divided into the idle area 504. When receiving a read instruction and data to be read from the host system 11, the memory control circuit 204 reads data from the physical units in the data area 506 according to the corresponding logic-to-physical mapping table.

[0056] Specifically, the data area 506, the idle area 504, the system area 502 and the replacement area 508 include one or more physical units respectively. The physical units in the data area 506 are regarded as physical units that have stored valid data, and the physical units in the idle area 504 also store data, but these data are invalid data. The physical units have data stored (even if they are invalid data) to avoid leakage of the physical units, and effectively improve the life of the physical units or the memory module 122. When the physical units in the idle area 504 need to be used later, the data (invalid data) in them are erased first, and then new data is written into these physical units.

[0057] The physical units logically belonging to the system area 502 are used to record system data. For example, the system data includes the manufacturer and model of the memory module 122, the number of physical units of the memory module 122, the number of physical programmed units of each physical unit, etc. Specifically, the system area 502 is used to store a logical to physical mapping table, a read count table, an erase count table of a physical unit, and a bad block table of a physical unit.

[0058] The physical cells logically belonging to the replacement area 508 are used for the bad physical cell replacement procedure to replace the damaged physical cells. Specifically, if there are still normal physical cells in the replacement area 508 and the physical cells in the data area 506, the idle area 504, and the system area 502 are damaged, the memory control circuit 204 will extract normal physical cells from the replacement area 508 to replace the damaged physical cells in the data area 506, the idle area 504, and the system area 502.

[0059] Furthermore, the number of physical units in the data area 506, the idle area 504, the system area 502, and the replacement area 508 may vary according to different memory specifications. In addition, it should be understood that during the operation of the memory storage device 12, the grouping relationship of the physical units associated with the data area 506, the idle area 504, the system area 502, and the replacement area 508 may change dynamically. For example, when the physical unit in the idle area 504 is damaged and replaced by the physical unit in the replacement area 508, the physical unit originally in the replacement area 508 will be associated with the idle area 504.

[0060] Further, the physical units in the data area 506 are regarded as physical units that have stored data, while the physical units in the idle area 504 are physical units for storing new data. When the physical units to which the new data is written are divided into the data area 506, they become physical units in the data area 506. That is, when a write instruction and data to be written are received from the host system 11, the memory control circuit 204 extracts physical units from the idle area 504 to write data according to the corresponding logic-to-physical mapping table, and updates the region relationship of the physical units, that is, the physical units that originally belong to the idle area 504 and store the new data become physical units in the data area 506. When a read instruction and data to be read are received from the host system 11, the memory control circuit 204 reads data from the physical units in the data area 506 according to the corresponding logic-to-physical mapping table.

[0061] The physical unit has a threshold limit for the number of reads. As the memory storage device 10 is used, the number of reads of some physical units may reach the limit of the read disturbance threshold, and the data in these physical units needs to be moved to new physical units to ensure the stability of the data stored in the memory module 122.

[0062] Based on this, in one embodiment, the memory control circuit 204 obtains the number of reads of the multiple physical units in the memory module 122, and the memory control circuit 204 determines whether the number of reads of the multiple physical units in the memory module 122 is greater than a first threshold, and the memory control circuit 204 records or marks the physical units whose number of reads exceeds the first threshold as risky physical units;

[0063] In detail, the memory control circuit 204 establishes and maintains a physical unit read count table (also referred to as a first read count table, Table 1), such as Figure 5 shown. Figure 5 FIG. 1 is a schematic diagram showing the number of physical unit reads according to an embodiment of the present invention. Figure 5 In FIG. 2 , H is used to represent the read count of entity units 301(C) to 301(D), 301(C) represents the entity unit with serial number C. Hc represents the read count of the entity unit with serial number c. After the memory control circuit 204 executes the read instruction for a certain entity unit, Figure 5 The number of reads of the entity unit with the same serial number in the sequence is increased by 1 to achieve Figure 5 maintenance.

[0064] Further, the entity units in the first reading number table are sorted according to the number of readings, wherein the entity units with a greater number of readings have a higher ranking. Preferably, the entity units with a higher ranking are arranged in Figure 5This facilitates the management of entity units. Figure 5 It is used to record the number of times all entity units are read. However, when the number of times a entity unit is read reaches K times (the first threshold), these entity units are removed from Figure 5 Put it into Table 2 (also called the second reading count table) and use Table 2 to manage it. Figure 5 Table 1 in no longer manages these entity units. In other words, Table 2 is used to maintain and manage entity units that have been read more than K times.

[0065] In one embodiment, the entity units that have been read more than K times are marked as risky entity units and Figure 5 Eliminate and use Figure 6 Further, Table 2 is used to record the entity units whose reading times exceed the first threshold value. In addition to recording the reading times of the risk entity units, Table 2 also records the first reading time value T of the risk entity units, where the T value is the time interval from the last time the risk entity unit was read to now; the risk entity units are sorted according to the T value, wherein the smaller the T value, the higher the ranking of the risk entity unit.

[0066] Compared with using one reading count table to record and maintain the reading counts of all entity units, this embodiment uses two reading count tables to record and maintain the reading counts of entity units, especially the entity units in Table 2 are all read more than K times (the first threshold), so that when subsequently screening the target entity units, the entity units can be selected in Table 2 according to the second threshold, which makes the operation speed of selecting the target entity units faster.

[0067] In detail, the memory control circuit 204 forms a queue with all the physical units in Table 2. If a physical unit is read, the memory control circuit 204 not only adds 1 to the number of reads of the physical unit, but also arranges the physical unit at the front of the queue. Similarly, the physical unit at the front of the queue is the most recently read physical unit. This can increase the speed of selecting the target physical unit.

[0068] Further, in one embodiment, a second threshold is introduced to select the target entity unit from Table 2. Specifically, the memory control circuit 204 records the risk entity unit in Table 2 whose T value is less than or equal to the second threshold as the second entity unit. The second entity unit includes one or more risk entity units. The memory control circuit 204 selects the target entity unit from the second entity unit or records the second entity unit as the target entity unit according to the second threshold. For example, if there are 10 entity units with T1=5S recorded in Table 2, 12 entity units with T2=10S, 15 entity units with T3=15S, and 25 entity units with T4=20S. If the second threshold is 18S, then the number of entity units that meet the requirements of being recorded as the second entity unit is 37, that is, the target entity unit is selected from these 37 entity units. If the second threshold is 10S, then the number of entity units that meet the requirements of being recorded as the second entity unit is 22, and similarly, the target entity unit is selected from these 22 entity units.

[0069] Furthermore, if the second physical unit includes a plurality of risk physical units, in one embodiment, a method is also provided in which the memory control circuit 204 selects a target physical unit from the second physical unit and records the selected risk physical unit as the target physical unit.

[0070] Specifically, the step of the memory control circuit 204 selecting a physical unit from the second physical unit and recording the selected physical unit as a target physical unit includes: the memory control circuit 204 obtains the second read time value of the first physical programming unit of the second physical unit, and the memory control circuit 204 records the second physical unit whose second read time value is greater than a third threshold as the target physical unit, and the above-mentioned second read time value is the time for successfully reading the data stored in the first physical programming unit in response to the data read instruction.

[0071] Furthermore, in another embodiment, the memory control circuit 204 also obtains a third read time value of the second physical programming unit of the second physical unit, and the memory control circuit 204 records the second physical unit whose third read time value is greater than a third threshold as a target physical unit, the third read time value being the time for successfully reading the data stored in the second physical programming unit in response to a data read instruction, and the first physical programming unit and the second physical programming unit belong to the same risk physical unit.

[0072] In another embodiment, the first physical programming unit and the second physical programming unit belong to different word lines.

[0073] Exemplarily, if the number of the second entity units is 100 entity units, 20 entity units need to be selected from these 100 entity units as target entity units. The read time (referred to as the second read time value) of some entity programming units (referred to as the first entity programming unit) in these 100 entity units is determined. If the read time of some entity programming units (the first entity programming unit) is greater than the third threshold value, then based on the principle of Nand Flash storing data, it can be known that the process of reading the data in these entity programming units has undergone a reread operation or due to a long ECC decoding operation; thus, the time spent reading the data in these entity programming units is longer than that of reading the data in other entity programming units. It can be determined that the entity units to which these entity programming units belong can be identified as target entity units. It is necessary to perform a data migration operation on the data stored thereon, so as to improve the data reading speed of the memory storage device 12 on the one hand, and to ensure the security and stability of the data stored in the memory module 122 on the other hand.

[0074] In another embodiment, the first physical programming unit and / or the second physical programming unit is any one of the second physical units storing valid data.

[0075] Furthermore, if the number of entity units whose second reading time value of the first entity programming unit is greater than the third threshold is 50, then it is necessary to further select 20 target entity units that meet the needs from these 50 entity units. Determine the third reading time value of the second entity programming unit among the 50 entity units, and record the second entity unit whose third reading time value is greater than the third threshold as the target entity unit. The third reading time value is the time when the data stored in the second entity programming unit is successfully read in response to the data read instruction. The first entity programming unit and the second entity programming unit belong to the same risk entity unit. Exemplarily, a physical unit includes 200 physical programmings, the first physical programming unit is P0, and the second physical programming unit is P199. By detecting the reading time of two physical programming units in the same risk entity unit, the detection or screening of target entity units is more accurate.

[0076] Furthermore, on this basis, the number of entity programming units in the same risk entity unit can be increased, such as the third entity programming unit or more entity programming units.

[0077] In one embodiment, even-numbered or odd-numbered physical programming units in the same risk physical unit are detected.

[0078] In another embodiment, the physical programming unit with serial number "0" in the same risk physical unit is detected, such as P0, P10, P20, and so on.

[0079] The above-mentioned limitation on the first entity programming unit and the second entity programming unit is intended to make the target entity unit selected from the second entity unit more representative, that is, to select the target entity unit on which the data migration operation is most likely to be performed.

[0080] In one embodiment, a physical unit erase count table (P / E table) [stored in the system area] is also established to record the usage status of the physical units in the memory module 122. The P / E table records the erase counts of all physical units in the memory module 122, such as Figure 7 shown. Figure 7 In the figure, M in 301(M) represents the serial number of the physical unit 301, and N represents the number of times the serial number physical unit 301(M) is erased.

[0081] Preferably, in one embodiment, the memory control circuit 204 sorts the multiple physical units according to the number of erasures of the physical units, and the memory control circuit 204 arranges the sorted multiple physical units at the head of the erasure number table according to the physical unit number with the smallest erasure number, so as to facilitate subsequent Figure 7 In the selection of physical units, the physical units are selected according to the number of erasures. This can increase the speed of selecting physical units.

[0082] Further, after the memory control circuit 204 completes recording or selecting the target physical unit, it is necessary to perform a data moving operation on the target physical unit. In one embodiment, the data moving operation is to copy the valid data (first data) in the target physical unit to the first physical unit, while the invalid data (second data) in the physical unit does not perform the data moving operation. After the data moving operation is performed on the first data, the physical unit (i.e., the target physical unit) that originally stores the first data is marked to indicate that the data stored in one (some) of the physical programming units in these (these) physical units is invalid data. If the data stored in all the physical programming units in these (these) physical units is invalid data, then the physical unit (these) is reclassified from the data area 506 to the idle area 504.

[0083] In one embodiment, the first physical unit is a physical unit with the smallest operation value in the memory module 122. With respect to the first physical unit being a physical unit with the smallest operation value in the memory module 122, in one embodiment, the operation value can be considered as the number of erasures. That is, the physical unit with the smallest operation value can be considered as the physical unit with the smallest number of erasures.

[0084] Preferably, in one embodiment, the target physical unit is a physical unit in the data area 506 , and the physical unit with the smallest erase times is selected from the idle area 504 .

[0085] Furthermore, in another embodiment, a method for managing physical units in the idle area 504 is provided to provide first physical units that meet the needs.

[0086] Specifically, the memory control circuit 204 divides the multiple physical units in the idle area 504 into groups according to the number of erase times of the physical units, and obtains multiple groups 41(0)--41(G) [G+1 represents the number of groups], each group corresponds to a different erase times value interval; wherein each group may include one or more physical units and each physical unit can only belong to a certain group in a certain time period due to the number of erase times; the erase times value interval of each group is different. The memory control circuit 204 selects a suitable number of physical units from the group with the smallest erase times value interval to store the first data according to the amount of data of the first data stored in the target physical unit. Preferably, a suitable number of physical units with the smallest erase times value interval are selected from the group with the smallest erase times value interval to store the first data. Managing the physical units in the memory module 122 in a group manner can increase the speed of selecting the first physical unit that meets the needs, thereby increasing the speed of data transfer.

[0087] For example, the idle area 504 includes 200 physical units, assuming that the 200 physical units are Block 15 to Block 214. The 200 physical units are divided into groups according to the number of erase times of the physical units, and the following is obtained: Figure 8 The four groups shown are 41(0), 41(1), 41(2) and 41(3). Figure 8 It is a schematic diagram showing an embodiment of the present invention, in which a plurality of physical units are divided into groups according to the number of erasure times of the physical units to obtain a plurality of groups, each group corresponding to a different erasure number value range.

[0088] Specifically, Figure 8 As shown, the group number with the smallest erasure count value range is 41(0), and the erasure count value range of group 41(0) is 0-200, which includes 50 physical units, and the erasure count details of these 50 physical units are 30 physical units with an erasure count of 80 times, 10 physical units with an erasure count of 120 times, and 10 physical units with an erasure count of 180 times. If the number of first physical units is required to be 2, then 2 physical units are selected from the 30 physical units with an erasure count of 80 times as the first physical units.

[0089] Furthermore, in another embodiment, the selection operation of the first physical unit further includes: the memory control circuit 204 selects a physical unit with the smallest erase count and the smallest error bit value from a subgroup with the smallest erase count value interval and the smallest error bit value interval as the first physical unit.

[0090] Specifically, the memory control circuit 204 further divides the group with the smallest erase count value interval into groups according to the error bit value of the physical unit, and obtains multiple subgroups based on the same erase count value interval but different error bit value value intervals; wherein each subgroup may include one or more physical units and the error bit value of each physical unit in a certain time period can only belong to a certain subgroup; each subgroup may belong to the same erase count value interval but corresponds to different error bit value value intervals. The number of physical units contained in each subgroup may be the same or different. The memory control circuit 204 selects the physical unit with the smallest erase count value interval and the smallest error bit value from the subgroup with the smallest erase count value interval and the smallest error bit value interval as the first physical unit.

[0091] For example, the number of error bits of a physical unit can be obtained from a bad block table (stored in the system area), such as Fig. 9 shown. Fig. 9 In the figure, F in 301(F) represents the serial number of the entity unit 301, and S represents the number of error bits of the serial number entity unit 301(F).

[0092] Exemplarily, the memory control circuit 204 obtains the number of error bits of each physical unit in the group 41(0), and further divides the group 41(0) into groups according to the number of error bits of each physical unit, thereby obtaining a plurality of subgroups 51(0)--51(R) having the same erase count value interval but different error bit value value intervals, such as Fig.10 shown. Fig.10 This is a schematic diagram showing an embodiment of the present invention in which a group with a minimum erasure count value interval is further divided into groups according to error bit values ​​of physical units to obtain multiple subgroups with the same erasure count value interval but different error bit value value intervals.

[0093] Specifically, Fig.10 Among them, Block 15 and Block 17 have the smallest erasure times and the smallest error bit values. Therefore, Block 15 and Block 17 are selected as the first physical unit.

[0094] In summary, in another embodiment, according to the size of the first data, the memory control circuit 204 selects an appropriate number of physical units as the first physical unit. Specifically, according to the size of the first data, the memory control circuit 204 selects an appropriate number of physical units from the group with the smallest erase count value interval as the first physical unit. Furthermore, according to the size of the first data, the memory control circuit 204 selects a physical unit with the smallest erase count and the smallest error bit value from a subgroup with the smallest erase count value interval and the smallest error bit value interval as the first physical unit.

[0095] It should be understood that when describing the operation of the physical units of the memory module in the present embodiment, the use of the term "group division" to operate the physical units is a logical concept. In other words, the actual position of the physical units in the memory module 122 is not changed, but the physical units in the memory module 122 are operated logically.

[0096] In one embodiment, the sorting algorithm may be any one of insertion sort, shell sort, selection sort, bubble sort, quick sort, merge sort, counting sort and bucket sort.

[0097] In one embodiment, the logical-to-physical mapping relationship of the first data is updated according to the physical address of the first physical unit. Since the data move operation is performed on the target physical unit, the physical address of the first data is changed from the physical address to which the original target physical unit belongs to the physical address to which the first physical unit belongs. That is, the physical address storing the first data has changed. For example, the first logical address is mapped to the first physical address, and the first physical address is the physical address to which the first data was originally stored. Now the physical address to which the first data is stored is the second physical address, then the memory control circuit 204 will remove the mapping relationship between the first logical address and the first physical address, and the memory control circuit 204 will re-establish the mapping relationship between the first logical address and the second physical address. The second physical address is the new physical address of the first data. It is also the physical address of the first physical unit.

[0098] In one embodiment, the memory control circuit 204 selects the first physical unit, and the step of copying the first data in the target physical unit to the first physical unit further includes: the memory control circuit 204 first performs an erase operation on the first physical unit, erases the data (invalid data) in the first physical unit, and then writes the first data into the first physical unit. The data in the target physical unit is marked as invalid data or the target physical unit is divided into the idle area; the first physical unit is divided into the data area.

[0099] Fig.11is a flowchart of a memory management method according to an embodiment of the present invention.

[0100] Please refer to Fig.11 In step S100, the number of reads of the plurality of entity units is obtained, and the entity units whose number of reads exceeds a first threshold are recorded as risk entity units. In step S200, the first read time value of the risk entity unit is obtained, and the risk entity unit whose first read time value is not greater than a second threshold is recorded as a target entity unit. In step S300, the data in the target entity unit is copied to the first entity unit, and the first entity unit is the entity unit with the smallest operation value in the memory module. In step S400, the logical-to-physical mapping relationship of the data is updated according to the physical address of the first entity unit.

[0101] However, Fig.11 The steps in the above are described in detail, so I will not repeat them here. It is worth noting that Fig.11 Each step in the above process can be implemented as multiple codes or circuits, which is not limited by the present invention. Fig.11 The method can be used in conjunction with the above exemplary embodiments or can be used alone, and the present invention is not limited thereto.

[0102] In summary, when the host system 11 wants to read the stored data from the memory storage device 12, the memory storage device 12 will read the data from the physical unit according to the read instruction. Generally, when performing data operations on the physical programming unit multiple times, it may interfere with the data operations of other physical programming units in the same physical unit, causing errors in the read data. On the one hand, the present application proposes a method for selecting a physical unit (target physical unit) for storing such high-frequency read data. After the target physical unit is selected, a data migration operation is performed on the first data; on the other hand, a method for selecting a first physical unit from the idle area 504 in the memory module 122 to store the first data is also proposed. Specifically, the first physical unit is the physical unit with the smallest operation value in the memory module 122. Further, the physical unit with the smallest operation value can be understood as the physical unit with the smallest number of erases. Further, the physical unit with the smallest operation value can be understood as selecting the physical unit with the smallest number of erases and the smallest error bit value from the subgroup with the smallest erase number value interval and the smallest error bit value interval. The logical-to-physical mapping relationship of the first data is updated according to the physical address of the first physical unit. Moving (copying) the first data to a physical unit with a relatively small error bit value can also reduce the number of times the data will be moved (copied) to a new physical unit again, which can improve the life of the memory storage device. Even if the first data is still frequently read, the number of times the data will be moved (copied) to a new physical unit again can be reduced, which can also improve the life of the memory storage device. In addition, moving (copying) the first data to a physical unit with a relatively small error bit value can also increase the speed of subsequent first data reading and improve the security and stability of data stored in the memory storage device.

[0103] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method, applied to a memory storage device, characterized in that: The memory storage device comprises a memory module, the memory module comprises a plurality of entity units, the entity units comprise a plurality of entity programming units, and the method comprises: Acquire the number of times the plurality of entity units are read, and record the entity units whose number of times exceeds a first threshold as risky entity units; Acquire a first reading time value of the risk entity unit, wherein the first reading time value is a time interval from when the risk entity unit was last read to now, and record the risk entity unit whose first reading time value is not greater than a second threshold as a second entity unit; Selecting a target entity unit from the second entity unit, wherein the step of selecting the target entity unit from the second entity unit comprises: acquiring a second read time value of a first entity programming unit of the second entity unit, recording the second entity unit whose second read time value is greater than a third threshold as the target entity unit, wherein the second read time value is the time when the data stored in the first entity programming unit is successfully read in response to a data read instruction; Copying the data in the target physical unit to a first physical unit, where the first physical unit is a physical unit with a minimum operation value in the memory module; The logical-to-physical mapping relationship of the data is updated according to the physical address of the first physical unit.

2. The memory management method according to claim 1, characterized in that: The steps of obtaining the number of times the plurality of entity units are read and obtaining the first reading time value of the risk entity unit include: Establish a first reading number table and a second reading number table; The first reading number table is used to record the reading times of the plurality of entity units, and the entity units in the first reading number table are sorted according to the reading times, wherein the greater the reading times, the higher the ranking of the entity unit; The second reading frequency table is used to record the first reading time value, and to sort the risk entity units according to the first reading time value, wherein the smaller the first reading time value is, the higher the ranking of the risk entity unit is.

3. The memory management method according to claim 1, characterized in that: The step of obtaining the second read time value of the first physical programming unit of the second physical unit and recording the second physical unit whose second read time value is greater than a third threshold as the target physical unit comprises: A third read time value of the second physical programming unit of the second physical unit is obtained, and the second physical unit whose third read time value is greater than a third threshold is recorded as the target physical unit, wherein the third read time value is the time when the data stored in the second physical programming unit is successfully read in response to a data read instruction, and the first physical programming unit and the second physical programming unit belong to the same physical unit.

4. The memory management method according to any one of claims 1 to 3, characterized in that: The step of copying the data in the target entity unit to the first entity unit includes: Dividing a plurality of physical units in the memory module into a data area and an idle area; Dividing the plurality of physical units in the idle area into groups according to the number of erasure times of the physical units to obtain a plurality of groups, each group corresponding to a different erasure number value interval; According to the amount of data in the target physical unit, a suitable number of physical units are selected from the group with the smallest erase times interval as first physical units, and an erase operation is performed on the first physical units to write the data in the target physical unit into the first physical unit; Marking the data in the target entity unit as invalid data or dividing the target entity unit into the idle area; The first entity unit is divided into the data area.

5. A memory controller for controlling a memory module, wherein the memory module comprises a plurality of physical units, and the physical units comprise a plurality of physical programming units; the memory controller comprises: A host interface for connecting to a host system; a memory interface for connecting to the memory module; and a memory control circuit connected to the host interface and the memory interface; characterized in that: The memory control circuit acquires the number of times the plurality of entity units are read, and records the entity units whose number of times exceeds a first threshold as risky entity units; The memory control circuit acquires a first read time value of the risk entity unit, wherein the first read time value is a time interval from when the risk entity unit was last read to now, and records the risk entity unit whose first read time value is not greater than a second threshold as a second entity unit; The memory control circuit selects a target physical unit from the second physical unit, wherein the operation of selecting the target physical unit from the second physical unit includes: Acquire a second read time value of the first physical programming unit of the second physical unit, and record the second physical unit whose second read time value is greater than a third threshold as the target physical unit, wherein the second read time value is the time when the data stored in the first physical programming unit is successfully read in response to a data read instruction; The memory control circuit copies the data in the target physical unit to a first physical unit, where the first physical unit is a physical unit with a minimum operation value in the memory module; The memory control circuit updates the logical-to-physical mapping relationship of the data according to the physical address of the first physical unit.

6. The memory controller according to claim 5, characterized in that: The operation of the memory control circuit acquiring the number of read times of the plurality of entity units and acquiring the first read time value of the risk entity unit comprises: Establish a first reading number table and a second reading number table; The first reading number table is used to record the reading number of the plurality of physical units, and the memory control circuit sorts the physical units in the first reading number table according to the reading number, wherein the greater the reading number, the higher the physical unit is sorted; The second reading frequency table is used to record the first reading time value, and to sort the risk entity units according to the first reading time value, wherein the smaller the first reading time value is, the higher the ranking of the risk entity unit is.

7. The memory controller according to claim 5, characterized in that: The memory control circuit acquires the second read time value of the first physical programming unit of the second physical unit, and records the second physical unit whose second read time value is greater than a third threshold as the target physical unit, including: The memory control circuit obtains a third read time value of a second physical programming unit of the second physical unit, and the memory control circuit records the second physical unit whose third read time value is greater than a third threshold as the target physical unit, the third read time value being the time for successfully reading data stored in the second physical programming unit in response to a data read instruction, and the first physical programming unit and the second physical programming unit belong to the same physical unit.

8. The memory controller according to any one of claims 5 to 7, characterized in that: The operation of the memory control circuit copying the data in the target physical unit to the first physical unit includes: The memory control circuit divides the plurality of physical units in the memory module into a data area and an idle area; and The memory control circuit divides the multiple physical units in the idle area into groups according to the erasure times of the physical units to obtain multiple groups, each group corresponding to a different erasure times value interval; The memory control circuit selects a suitable number of physical units from the group with the smallest erase times interval as first physical units according to the amount of data in the target physical unit, and the memory control circuit performs an erase operation on the first physical unit to write the data in the target physical unit into the first physical unit; The memory control circuit marks the data in the target physical unit as invalid data or divides the target physical unit into the idle area; The memory control circuit divides the first physical unit into the data area.

9. A memory storage device, comprising a connection interface, a memory module and a memory controller; the connection interface is used to connect the memory storage device to a host system; the memory module comprises a plurality of physical units, and the physical units comprise a plurality of physical programming units; the memory controller is connected to the connection interface and the memory module; characterized in that The memory controller obtains the number of read times of the plurality of physical units, and records the physical units whose number of read times exceeds a first threshold as risky physical units; and The memory controller acquires a first read time value of the risk entity unit, wherein the first read time value is a time interval from when the risk entity unit was last read to now, and records the risk entity unit whose first read time value is not greater than a second threshold as a second entity unit; The memory controller selects a target physical unit from the second physical unit, wherein the operation of selecting the target physical unit from the second physical unit includes: Acquire a second read time value of the first physical programming unit of the second physical unit, and record the second physical unit whose second read time value is greater than a third threshold as the target physical unit, wherein the second read time value is the time when the data stored in the first physical programming unit is successfully read in response to a data read instruction; The memory controller copies the data in the target physical unit to a first physical unit, where the first physical unit is a physical unit with a minimum operation value in the memory module; The memory controller updates the logical-to-physical mapping relationship of the data according to the physical address of the first physical unit.

10. The memory storage device according to claim 9, characterized in that: The operation of the memory controller obtaining the number of read times of the plurality of entity units and obtaining the first read time value of the risk entity unit includes: Establish a first reading number table and a second reading number table; The first reading number table is used to record the reading times of the plurality of physical units, and the memory controller sorts the physical units in the first reading number table according to the reading times, wherein the greater the reading times, the higher the ranking of the physical unit; The second reading frequency table is used to record the first reading time value, and to sort the risk entity units according to the first reading time value, wherein the smaller the first reading time value is, the higher the ranking of the risk entity unit is.

11. The memory storage device according to claim 9, characterized in that: The memory controller acquires the second read time value of the first physical programming unit of the second physical unit, and records the second physical unit whose second read time value is greater than a third threshold as the target physical unit, including: The memory controller obtains a third read time value of a second physical programming unit of the second physical unit, and the memory controller records the second physical unit whose third read time value is greater than a third threshold as the target physical unit, the third read time value being the time for successfully reading data stored in the second physical programming unit in response to a data read instruction, and the first physical programming unit and the second physical programming unit belong to the same physical unit.

12. The memory storage device according to any one of claims 9 to 11, characterized in that: The operation of the memory controller copying the data in the target physical unit to the first physical unit includes: The memory controller divides a plurality of physical units in the memory module into a data area and an idle area; and The memory controller divides the multiple physical units in the idle area into groups according to the erasure times of the physical units to obtain multiple groups, each group corresponding to a different erasure times value interval; The memory controller selects a suitable number of physical units from the group with the smallest erase times interval as first physical units according to the amount of data in the target physical unit, and the memory controller performs an erase operation on the first physical unit to write the data in the target physical unit into the first physical unit; The memory controller marks the data in the target physical unit as invalid data or divides the target physical unit into the idle area; The memory controller divides the first physical unit into the data area.

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