A module verification method based on chip system design

Abstract

This invention discloses a module verification method based on chip system design, specifically relating to the field of chip design. The method includes: 1. Analyzing verification requirements and extracting functional test points. For the verification of a specific module, the design intent is first communicated with the designer to correctly understand the module's function and decompose the function. The proposed verification points need to be reviewed and confirmed. Finally, based on the reviewed and approved verification points, the verification environment is expanded and test cases are written. The stimulus states, boundary values, and corresponding correct results that the verification platform needs to provide are analyzed. 2. Building a verification environment. Multiple modules are run in parallel by connecting themselves to each other, without redesigning surrounding modules. 3. Completing module verification based on test cases. The module verification is completed based on the test cases written in step 1. The name of the test case is found from the command line using UVM_TEST_NAME, an instance of it is created, and it is run.

Description

Technical Field

[0001] This invention relates to the field of chip design technology, and more specifically, to a module verification method based on chip system design. Background Technology

[0002] System-on-a-chip (SoC) is characterized by its flexible configuration. It is formed by combining multiple integrated circuit modules (IP cores) with specific functions on a single chip. It is the "brain chip system" of smart devices. Unlike simply stacking the same type of chips, SoC has obvious advantages in performance and power consumption. It can meet the diverse computing needs of mobile processors. The combination of various chips can also greatly improve the response speed of various functions of mobile devices. Typically, an SoC chip contains one or more processors, memory, analog circuit modules, mixed-signal modules, and on-chip programmable logic, which requires high module-level verification.

[0003] Verification constitutes a significant portion of chip design. With the increasing variety and quantity of chips, and their growing complexity, the verification complexity of SoCs (System-on-a-Chip) is growing exponentially. Using UVM (Ultraviolet Modeling) to verify RTL (Real-Time Level) designs is becoming increasingly necessary. In the early stages of chip design, each designed module needs verification to determine if its functionality and performance meet design requirements. However, some modules require the assistance of other modules for verification. This means that verifying one module must wait until several other modules are completed, reducing efficiency and increasing manpower costs. Summary of the Invention

[0004] To overcome the aforementioned deficiencies of the prior art, embodiments of the present invention provide a module verification method based on chip system design. For modules that require the assistance of other modules to complete verification, multiple modules are verified in parallel by connecting themselves to each other, without redesigning the surrounding modules, thus solving the problems of low verification efficiency and high verification cost mentioned in the background art.

[0005] To achieve the above objectives, the present invention provides the following technical solution: a module verification method based on chip system design, comprising the following steps:

[0006] Step 1: Analyze and verify requirements, extract functional test points, and for the verification of a specific module, first communicate the design intent with the designers, correctly understand the module function and decompose the function. The proposed verification points need to be reviewed and confirmed. Finally, based on the verification points that have passed the review, complete the expansion of the verification environment and the writing of test cases. Analyze the stimulus states, boundary value conditions and corresponding correct results that the verification platform needs to provide.

[0007] Step 2: Set up the verification environment. By connecting itself to itself, multiple modules can be parallelized without redesigning the surrounding modules. First, the C program code of a specific module 1 in the SOC chip is stored in the test stimulus C code file. Then, the C program code in the test stimulus C code file is read and compiled by the program compiler to generate an assembly program, which improves the verification component and the communication task between components.

[0008] Step 3: Based on the test cases, complete the module verification work. Based on the test cases written in Step 1, complete the module verification work. Use UVM_TEST_NAME to find the name of the test case from the command line, create an instance of it and run it.

[0009] In a preferred embodiment, the specific module 1 is a module that requires the assistance of other modules to complete the verification.

[0010] In a preferred embodiment, the verification environment is implemented based on the UVW verification component tree structure from bottom to top, as shown in the UVW verification component tree structure diagram. Figure 2 As shown, based on the nodes in the UVM tree structure, the bus excitation, input and output monitoring and collection, scoreboard comparison, register model and converter components of the entire verification platform are completed, and communication between verification components is completed through UVMTLM1.0 communication.

[0011] In a preferred embodiment, the verification environment automatically collects the end-to-end latency of the ARM processor accessing memory via the switching bus. When performing performance verification, it is necessary to determine the type of ARM's AHB interface operation and typical applications.

[0012] In a preferred embodiment, the verification components include other components of the verification platform such as transaction, uvm_env container, monitor, reference model, and scoreboard, and the transfer of information between these components is based on transaction.

[0013] In a preferred embodiment, scripts are often used in the verification process. During the process, configuring the environment, configuring the test modules, and performing regression testing of test cases are all relatively tedious tasks. In order to simplify the verification process, reduce the difficulty of the work, and improve the verification efficiency, script files are generally used in the verification environment to replace manual modification of configuration files and complete tasks such as regression test cases. When the script runs successfully, an automated verification platform can be established, which greatly simplifies the verification work and reduces the subsequent input of verification manpower.

[0014] The technical effects and advantages of this invention are as follows:

[0015] 1. This module verification method based on chip system design verifies multiple modules in parallel by connecting them to each other, eliminating the need to redesign surrounding modules, thus improving verification efficiency and saving costs.

[0016] 2. This module verification method based on chip system design, using the UVM methodology verification strategy based on the System Verilog language, has good flexibility and can be applied to module verification scenarios of different chips. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the verification environment framework structure of the present invention.

[0018] Figure 2 This is a schematic diagram of the UVW verification component tree structure of the present invention.

[0019] Figure 3 This is a schematic diagram of the start-up and testing process of the test cases of the present invention. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] Example

[0022] Embodiments of this invention provide a module verification method based on chip system design. This method utilizes the UVM methodology verification strategy based on the SystemVerilog language. For modules that require other modules for verification, it verifies multiple modules in parallel by connecting them to themselves, eliminating the need to redesign surrounding modules. This invention provides such... Figure 1 The verification environment framework diagram shown includes the following steps:

[0023] Step 1: Analyze and verify requirements, extract functional test points, and for the verification of a specific module, first communicate the design intent with the designers, correctly understand the module function and decompose the function. The proposed verification points need to be reviewed and confirmed. Finally, based on the verification points that have passed the review, complete the expansion of the verification environment and the writing of test cases. Analyze the stimulus states, boundary value conditions and corresponding correct results that the verification platform needs to provide.

[0024] The specific module 1 is a module that requires the assistance of other modules to complete the verification.

[0025] Step 2: Set up the verification environment. By connecting itself to itself, multiple modules can be parallelized without redesigning the surrounding modules. First, the C program code of a specific module 1 in the SOC chip is stored in the test stimulus C code file. Then, the C program code in the test stimulus C code file is read and compiled by the program compiler to generate an assembly program, which improves the verification component and the communication task between components.

[0026] The verification environment is based on the UVW verification component tree structure from bottom to top, as shown in the UVW verification component tree structure diagram. Figure 2 As shown, based on the nodes in the UVM tree structure, the bus excitation, input and output monitoring and collection, scoreboard comparison, register model and converter components of the entire verification platform are completed, and communication between verification components is completed through UVMTLM1.0 communication.

[0027] The test environment automatically collects the end-to-end latency of the ARM processor accessing memory via the switching bus. When performing performance verification, it is necessary to determine the type of ARM's AHB interface operation and typical applications.

[0028] The verification components include other components of the verification platform such as transaction, uvm_env container, monitor, reference model, and scoreboard. Information transfer between these components is based on transaction.

[0029] Step 3: Based on the test cases, complete the module verification. Using the test cases written in Step 1, find the test case name from the command line using UVM_TEST_NAME, create an instance of it, and run it. The test case startup and testing flowchart is shown below. Figure 3 .

[0030] The verification process often utilizes scripts, and configuring the environment, test modules, and performing regression testing on test cases are all tedious tasks. To simplify the verification process, reduce workload, and improve efficiency, script files are typically used in the verification environment to replace manual modification of configuration files and complete tasks such as regression test cases. Once the script runs successfully, an automated verification platform can be established, greatly simplifying the verification work and reducing the subsequent manpower required for verification.

[0031] As can be seen from the above embodiments, this module verification method based on chip system design verifies multiple modules in parallel by connecting them to each other, eliminating the need to redesign surrounding modules, thus improving verification efficiency and saving costs. The UVM methodology verification strategy based on the System Verilog language has good flexibility and can be applied to module verification scenarios of different chips.

[0032] In conclusion, the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for module verification based on chip system design, characterized in that: Comprise the following steps: Step 1, analysis and verification requirements, extraction function test point, for the verification of specific module, first communicate with the design personnel design intention, correct understanding of module function and function decomposition, the proposed verification point needs to be reviewed and confirmed, finally based on the review passed verification point, complete the extension of the verification environment and test case writing, analysis and verification platform need to provide the excitation state, boundary value condition and corresponding correct result; Step 2, build verification environment, by using its own and its own way of connecting, for multiple modules in parallel, no longer to the surrounding module re-design, first, through the test excitation c code file to store the SOC chip in the specific module 1 c program code, then through the program compiler to read the test excitation c code file in the c program code and compile, produce assembly program, perfect verification component, and component communication task; Step 3, according to the test case, complete the module verification work, according to the test case written in step 1, complete the module verification work, use UVM_TEST_NAME to find the name of the test case from the command line, create its instance and run; The specific module 1 is a module that must be assisted by other modules to complete the verification; The verification environment is based on UVW verification component tree structure from bottom to top to complete, according to the node in the UVM tree structure, the bus excitation of the whole verification platform, input and output monitoring and collection, score board comparison, register model and converter component, and through UVMTLM1.0 communication to complete the communication between verification components.

2. The method of claim 1, wherein: The verification environment automatically collects the end-to-end delay of ARM processor accessing memory through the exchange bus, when doing performance verification, the type of ARM AHB interface operation and typical application need to be determined.

3. The method of claim 1, wherein: The verification component includes: transaction, uvm_env container, monitor, reference model, scoreboard verification platform other components, information transmission between these components is based on transaction.

4. The method of claim 1, wherein: The verification work uses script running, during the process, the configuration of the environment, the configuration of the test module and the regression test of the test case are relatively tedious work tasks, in order to simplify the verification program, reduce the work difficulty and improve the verification efficiency, the verification environment will use script file to replace manual modification of configuration file, complete the regression test case work, when the script runs successfully, an automatic verification platform is established, which greatly simplifies the verification work and reduces the subsequent verification manpower investment.

5. The method of claim 1, wherein: The module verification method based on chip system design is based on the UVM methodology verification strategy of SystemVerilog language, which has good flexibility and can be applied to different chip module verification scenarios. The module verification method based on chip system design is based on the UVM methodology verification strategy of SystemVerilog language, which has good flexibility and can be applied to different chip module verification scenarios.

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