Sense Amplifier and Semiconductor Memory

Abstract

The present disclosure provides a sense amplifier and a semiconductor memory, including a control module which is provided with an input end and a first output end, and is used for acquiring temperature data of a storage unit, delaying a first control signal received at its input end according to the temperature data of the storage unit to generate a second control signal, adjusting the time for an amplification module to connect to a first power supply end, adjusting the charge sharing time between a bit line or a complementary bit line and the storage unit, and an amplification module, whose first control end is connected to the first output end of the control module, and is used for connecting to the first power supply end under the control of the second control signal in a sense amplification stage, and amplifying a voltage difference between the bit line and the complementary bit line under the drive of the first power supply end. By such an arrangement, it is ensured that the charge sharing voltage on the bit line and the complementary bit line is the maximum value at the end moment of the charge sharing stage, and accurate amplification of the voltage on the bit line and the complementary bit line is achieved in the sense amplification stage.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, sense amplifiers and semiconductor memories. Background Art

[0002] With the popularization of electronic devices such as mobile phones, tablets, and personal computers, semiconductor memory technology has also developed rapidly.

[0003] A sense amplifier (abbreviated as SA) is an important component of a semiconductor memory. Its main function is to sense and amplify small signals on the bit line, and then perform read or write operations. The small signals on the bit line are generated by charge sharing between the storage unit and the bit line or complementary bit line. The magnitude of the small signals on the bit line is related to the accuracy of the sense amplification of the sense amplifier. Summary of the Invention

[0004] The present disclosure provides a sense amplifier, including:

[0005] A control module, which has an input terminal and a first output terminal, is used to obtain the temperature data of the storage unit, delay-process the first control signal received at its input terminal according to the temperature data of the storage unit to generate a second control signal, adjust the time for the amplification module to connect to the first power supply terminal, and adjust the charge sharing time between the bit line or complementary bit line and the storage unit;

[0006] An amplification module, whose first control terminal is connected to the first output terminal of the control module, is used to connect to the first power supply terminal under the control of the second control signal during the sense amplification stage, and amplify the voltage difference between the bit line and the complementary bit line under the drive of the first power supply terminal.

[0007] In some embodiments, the control module further has a second output terminal, and is further used to perform a NOT operation on the second control signal to generate a third control signal;

[0008] The amplification module further has a second control terminal; its second control terminal is connected to the second output terminal of the control module, and is used to connect to the second power supply terminal under the control of the third control signal;

[0009] Wherein, the voltage of the first power supply terminal is greater than the voltage of the second power supply terminal.

[0010] In some embodiments, the control module includes:

[0011] A control unit, which has an output terminal, is used to generate a delay adjustment signal according to the temperature data of the storage unit;

[0012] An adjustment unit is provided with an input end, an output end and a control end. Its control end is connected to the output end of the control unit. Its input end receives a first control signal and delays the first control signal according to a delay adjustment signal, and outputs a second control signal.

[0013] In some embodiments, the control module further includes:

[0014] A first inverter, whose input end is connected to the output end of the adjustment unit, is used to perform a NOT operation on the second control signal and output a third control signal.

[0015] In some embodiments, the control unit includes three output ends, the delay adjustment signal includes three gating signals, and the adjustment unit includes:

[0016] A first adjustment sub-unit, whose output end is connected to the first input end of the selection unit, is used to delay the first control signal and output a fourth control signal;

[0017] A second adjustment sub-unit, whose output end is connected to the second input end of the selection unit, is used to delay the first control signal and output a fifth control signal;

[0018] A third adjustment sub-unit, whose output end is connected to the third input end of the selection unit, is used to delay the first control signal and output a sixth control signal; wherein, the delay amounts of the fourth control signal, the fifth control signal and the sixth control signal are all different;

[0019] A selection unit is further provided with an output end and three control ends. Each control end is connected to the corresponding output end of the control unit and receives the corresponding gating signal; it is used to select one of the fourth control signal, the fifth control signal and the sixth control signal for output under the control of the three gating signals; the output signal of the selection unit is used to control the first control end of the amplification module.

[0020] In some embodiments, the adjustment unit further includes:

[0021] A second inverter, whose input end is connected to the output end of the selection unit, is used to perform a NOT operation on the output signal of the selection unit and then output; the output signal of the second inverter is used to control the first control end of the amplification module.

[0022] In some embodiments, the control unit is used for:

[0023] When the temperature data is within the first temperature range, the first gating signal output is valid, and the second gating signal and the third gating signal output are invalid; control the selection unit to select the fourth control signal for output;

[0024] When the temperature data is within the second temperature range, the output second strobe signal is valid, and the output first strobe signal and third strobe signal are invalid; the control selection unit selects and outputs the fifth control signal;

[0025] When the temperature data is within the third temperature range, the output third strobe signal is valid, and the output first strobe signal and second strobe signal are invalid; the control selection unit selects and outputs the sixth control signal;

[0026] Wherein, the upper limit value of the first temperature range is less than or equal to the lower limit value of the second temperature range, and the upper limit value of the second temperature range is less than or equal to the lower limit value of the third temperature range; the delay amount of the fourth control signal is less than the delay amount of the fifth control signal, and the delay amount of the fifth control signal is less than the delay amount of the sixth control signal.

[0027] In some embodiments, the first adjustment subunit includes:

[0028] A first pulse generator, whose input terminal receives the first control signal and is used to generate a first pulse signal according to the first control signal;

[0029] A first delay circuit, whose input terminal receives the first control signal, delays the first control signal and then outputs a first delay signal;

[0030] A second pulse generator, whose input terminal is connected to the output terminal of the first delay circuit and is used to generate a second pulse signal according to the first delay signal;

[0031] A first latch, whose first input terminal is connected to the first pulse generator, whose second input terminal is connected to the second pulse generator, and is used to generate a fourth control signal according to the first pulse signal and the second pulse signal.

[0032] In some embodiments, the second adjustment subunit includes:

[0033] A third pulse generator, whose input terminal receives the first control signal and is used to generate a third pulse signal according to the first control signal;

[0034] A second delay circuit, whose input terminal receives the first control signal, delays the first control signal and then outputs a second delay signal, and the delay amount of the second delay circuit is greater than that of the first delay circuit;

[0035] A fourth pulse generator, whose input terminal is connected to the output terminal of the second delay circuit and is used to generate a fourth pulse signal according to the second delay signal;

[0036] A second latch, whose first input terminal is connected to the third pulse generator, whose second input terminal is connected to the fourth pulse generator, and is used to generate a fifth control signal according to the third pulse signal and the fourth pulse signal.

[0037] In some embodiments, the third adjustment subunit includes:

[0038] A fifth pulse generator, whose input terminal receives a first control signal and is configured to generate a fifth pulse signal according to the first control signal;

[0039] A third delay circuit, whose input terminal receives the first control signal, delays the first control signal and then outputs a third delay signal, and the delay amount of the third delay circuit is greater than that of the second delay circuit;

[0040] A sixth pulse generator, whose input terminal is connected to the output terminal of the third delay circuit and is configured to generate a sixth pulse signal according to the third delay signal;

[0041] A third latch, whose first input terminal is connected to the fifth pulse generator, whose second input terminal is connected to the sixth pulse generator, and is configured to generate a sixth control signal according to the fifth pulse signal and the sixth pulse signal.

[0042] In some embodiments, the first pulse generator, the second pulse generator, the third pulse generator, the fourth pulse generator, the fifth pulse generator, and the sixth pulse generator have the same structure.

[0043] In some embodiments, the first pulse generator includes:

[0044] An odd number of third inverters, the output terminal of the upper-level third inverter is connected to the input terminal of the lower-level third inverter; the input terminal of the first-level third inverter receives the first control signal, and the output terminal of the last-level third inverter is connected to the second input terminal of the first NAND gate;

[0045] A first NAND gate, whose first input terminal receives the first control signal, and whose output terminal outputs the first pulse signal.

[0046] In some embodiments, the first latch, the second latch, and the third latch have the same structure. The first latch includes:

[0047] A second NAND gate; its first input terminal serves as the first input terminal of the first latch, its second input terminal is connected to the output terminal of the third NAND gate, and its output terminal is connected to the first input terminal of the third NAND gate;

[0048] A third NAND gate; the second input terminal serves as the second input terminal of the first latch, and its output terminal serves as the output terminal of the first latch.

[0049] In some embodiments, the first delay circuit includes:

[0050] A first buffer, whose input terminal receives the first control signal;

[0051] A second buffer, whose input end is connected to the output end of the first buffer, and whose output end outputs a first delay signal.

[0052] In some embodiments, the second delay circuit includes:

[0053] A third buffer, whose input end receives a first control signal;

[0054] A fourth buffer, whose input end is connected to the output end of the third buffer;

[0055] A fifth buffer, whose input end is connected to the output end of the fourth buffer;

[0056] A sixth buffer, whose input end is connected to the output end of the fifth buffer, and whose output end outputs a second delay signal.

[0057] In some embodiments, the third delay circuit includes:

[0058] A seventh buffer, whose input end receives a first control signal;

[0059] An eighth buffer, whose input end is connected to the output end of the seventh buffer;

[0060] A ninth buffer, whose input end is connected to the output end of the eighth buffer;

[0061] A tenth buffer, whose input end is connected to the output end of the ninth buffer;

[0062] An eleventh buffer, whose input end is connected to the output end of the tenth buffer;

[0063] A twelfth buffer, whose input end is connected to the output end of the eleventh buffer, and whose output end outputs a third delay signal.

[0064] In some embodiments, the control unit includes:

[0065] A temperature sensor, which is used to detect the temperature data of the storage unit and generate temperature encoded data according to the temperature data;

[0066] A temperature decoder, whose input end is connected to the output end of the temperature sensor, and which is used to generate a delay adjustment signal according to the temperature encoded data.

[0067] In some embodiments, the amplification module includes:

[0068] A third P-type transistor, whose source is connected to the first power supply terminal, and whose gate serves as the first control terminal of the amplification module;

[0069] A first P-type transistor, whose source is connected to the drain of the third P-type transistor, and whose gate is connected to the drain of the second P-type transistor;

[0070] A second P-type transistor, having a source connected to the source of the first P-type transistor and a gate connected to the drain of the first P-type transistor;

[0071] A first N-type transistor, having a drain connected to the drain of the first P-type transistor, a gate connected to the second N-type transistor, a gate connected to a complementary bit line, and a source indirectly coupled to a second power supply terminal;

[0072] A second N-type transistor, having a drain connected to the drain of the second P-type transistor, a gate connected to the first N-type transistor, a gate connected to a bit line, and a source connected to the source of the first N-type transistor.

[0073] In some embodiments, the amplification module includes:

[0074] A third N-type transistor, having a source connected to the second power supply terminal, a gate serving as a second control terminal of the amplification module, and a drain connected to the source of the first N-type transistor.

[0075] Another embodiment of the present disclosure provides a semiconductor memory, including the sense amplifier involved in the above embodiments.

[0076] The sense amplifier and the semiconductor memory provided by the present disclosure include a control module and an amplification module. The control module delays the first control signal according to the temperature data of the memory cell to adjust the level change moment of the first control signal, so as to adjust the end moment of the charge sharing stage according to the temperature data of the memory cell, compensate for the change in the voltage driving ability of the memory cell due to the change in temperature data, ensure that the charge sharing voltage formed on the bit line and the complementary bit line at the end moment of the charge sharing stage is the maximum value, and realize accurate amplification of the voltages on the bit line and the complementary bit line in the sense amplification stage. BRIEF DESCRIPTION OF THE DRAWINGS

[0077] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present disclosure and used together with the specification to explain the principles of the present disclosure.

[0078] Figure 1 It is a schematic circuit diagram of a sense amplifier;

[0079] Figure 2A It is a schematic diagram of a working principle of a sense amplifier in a charge sharing stage;

[0080] Figure 2B It is another schematic diagram of a working principle of a sense amplifier in a charge sharing stage;

[0081] Figure 2C It is yet another schematic diagram of a working principle of a sense amplifier in a charge sharing stage;

[0082] Figure 3 Schematic diagram of the circuit structure of the sense amplifier provided by an embodiment of the present application;

[0083] Figure 4 Schematic diagram of the circuit structure of the control module provided by an embodiment of the present application;

[0084] Figure 5A Schematic diagram of the circuit structure of the first adjustment circuit provided by an embodiment of the present application;

[0085] Figure 5B Schematic diagram of the working principle of the first adjustment circuit provided by an embodiment of the present application;

[0086] Figure 5C Another schematic diagram of the working principle of the first adjustment circuit provided by an embodiment of the present application;

[0087] Figure 6A Schematic diagram of the circuit structure of the second adjustment circuit provided by an embodiment of the present application;

[0088] Figure 6B Schematic diagram of the working principle of the second adjustment circuit provided by an embodiment of the present application;

[0089] Figure 7A Schematic diagram of the circuit structure of the third adjustment circuit provided by an embodiment of the present application;

[0090] Figure 7B Schematic diagram of the working principle of the third adjustment circuit provided by an embodiment of the present application;

[0091] Figure 8A Schematic diagram of the working principle of the sense amplifier provided by an embodiment of the present application;

[0092] Figure 8B Another schematic diagram of the working principle of the sense amplifier provided by an embodiment of the present application;

[0093] Figure 8C Another schematic diagram of the working principle of the sense amplifier provided by an embodiment of the present application.

[0094] Reference numerals:

[0095] 200, amplification module; 300, storage unit; 100, control module; 120, control unit; 110, adjustment unit; 111, first adjustment subunit; 112, second adjustment subunit; 113, third adjustment subunit; 121, temperature sensor; 122, temperature decoder; 130, first inverter; 140, second inverter;

[0096] 310, First pulse generator; 330, Second pulse generator; 320, First delay circuit; 340, First latch; 311, First NAND gate; 312, Third inverter; 331, Fourth NAND gate; 332, Fourth inverter; 341, Second NAND gate; 342, Third NAND gate; 321, First buffer; 322, Second buffer;

[0097] 410, Third pulse generator; 420, Second delay circuit; 430, Fourth pulse generator; 440, Second latch; 411, Fifth NAND gate; 412, Fifth inverter; 431, Sixth NAND gate; 432, Sixth inverter; 441, Seventh NAND gate; 442, Eighth NAND gate; 421, Third buffer; 422, Fourth buffer; 423, Fifth buffer; 424, Sixth buffer;

[0098] 510, Fifth pulse generator; 520, Third delay circuit; 530, Sixth pulse generator; 540, Third latch; 511, Ninth NAND gate; 512, Seventh inverter; 531, Tenth NAND gate; 532, Eighth inverter; 541, Eleventh NAND gate; 542, Twelfth NAND gate; 521, Seventh buffer; 522, Eighth buffer; 523, Ninth buffer; 524, Tenth buffer; 525, Eleventh buffer; 526, Twelfth buffer.

[0099] Through the above-mentioned drawings, specific embodiments of the present disclosure have been shown, and there will be more detailed descriptions hereinafter. These drawings and textual descriptions are not intended to limit the scope of the concept of the present disclosure in any way, but to illustrate the concept of the present disclosure to those skilled in the art by referring to specific embodiments. Detailed Embodiments

[0100] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0101] As Figure 1 shown, a sense amplifier includes an amplification module 200, and the amplification module 200 includes a first P-type transistor P1, a second P-type transistor P2, a third P-type transistor P3, a first N-type transistor N1, a second N-type transistor N2, and a third N-type transistor N3.

[0102] After the source of the first P-type transistor P1 is connected to the source of the second P-type transistor P2, it is connected to the drain of the third P-type transistor P3, and the source of the third P-type transistor P3 is connected to the first power supply terminal. After the source of the first N-type transistor N1 is connected to the source of the second N-type transistor N2, it is connected to the drain of the third N-type transistor N3, and the source of the third N-type transistor N3 is connected to the second power supply terminal.

[0103] The drain of the first N-type transistor N1 is connected to the drain of the first P-type transistor P1 and then connected to the bit line BL. The drain of the second N-type transistor N2 is connected to the drain of the second P-type transistor P2 and then connected to the complementary bit line BLB. The gate of the first N-type transistor N1 is connected to the drain of the second N-type transistor N2, the gate of the second N-type transistor N2 is connected to the drain of the first N-type transistor N1, the gate of the second P-type transistor P2 is connected to the drain of the first P-type transistor P1, and the gate of the first P-type transistor P1 is connected to the drain of the second P-type transistor P2.

[0104] The memory cell 300 includes a control transistor SN and a storage capacitor Cs. The gate of the control transistor SN is connected to the word line WL, the first end of the control transistor SN is connected to the bit line BL, the second end of the control transistor SN is connected to the first end of the storage capacitor Cs, and the second end of the storage capacitor Cs is connected to the ground terminal.

[0105] The following combines Figure 2A , the working timing of the sense amplifier when the memory cell 300 stores data as "1":

[0106] In the charge sharing stage T1, the gate of the third P-type transistor P3 receives the first power supply enable signal SAP as a high level, the gate of the third N-type transistor N3 receives the second power supply enable signal SAN as a low level, both the third N-type transistor N3 and the third P-type transistor P3 are turned off, and the amplification module 200 is disconnected from both the first power supply terminal and the second power supply terminal. The word line signal on the word line WL is at a high level, the control transistor SN in the memory cell 300 is turned on, the storage capacitor Cs in the memory cell 300 shares charge with the bit line BL, and the voltage of the bit line BL increases.

[0107] In the sense amplification stage T2, the gate of the third P-type transistor P3 receives the first power supply enable signal SAP as a low level, the gate of the third N-type transistor N3 receives the second power supply enable signal SAN as a high level, the amplification module 200 is connected to both the first power supply terminal and the second power supply terminal, the amplification module 200 further drives the voltages on the bit line BL and the complementary bit line BLB, and a larger voltage difference is formed on the bit line BL and the complementary bit line BLB.

[0108] In the charge sharing stage T1, the word line signal on the word line WL is at a high level, the control transistor SN is turned on, and the storage capacitor Cs of the memory cell 300 and the parasitic capacitance C of the bit line BLBL Charge sharing is performed. After the charge sharing ends, a charge sharing voltage VCS is formed on the bit line BL and the complementary bit line BLB. The charge sharing voltage VCS is relatively weak. In the sense amplification stage T2, the amplification module 200 connects the first power supply terminal and the second power supply terminal, and the amplification module 200 performs sense amplification, which can amplify the weak charge sharing voltage VCS into a full swing data voltage difference. That is, the voltage of the bit line BL is the voltage of the first power supply terminal, and the voltage of the complementary bit line BLB is the voltage of the second power supply terminal, or the voltage of the complementary bit line BLB is the voltage of the first power supply terminal, and the voltage of the bit line BL is the voltage of the second power supply terminal.

[0109] In the sense amplification stage T2, a certain sense voltage is required for the sense amplification operation. The sense margin is defined as the difference between the charge sharing voltage VCS and the sense voltage. The magnitude of the charge sharing voltage VCS is related to the charge sharing stage T1.

[0110] If the time of the charge sharing stage T1 is too short, the charge sharing between the memory cell 300 and the bit line BL or the complementary bit line BLB has not ended, the charge sharing voltage VCS has not reached the maximum value of the charge sharing, the charge sharing voltage VCS is relatively small, which will make the sense margin relatively small, and the sense margin will be lost. Further, if the charge sharing voltage VCS is too small, resulting in the sense margin being less than zero, the sense result will fail. If the time of the charge sharing stage T1 is too long, the leakage path on the bit line BL or the complementary bit line BLB will cause greater charge loss, and the charge sharing voltage VCS will become smaller, and the sense margin will also be relatively small or even less than zero.

[0111] At the beginning of the design of the sense amplifier, a reasonable time of the charge sharing stage T1 will be set so that the charge sharing voltage VCS on the bit line BL and the complementary bit line BLB is the maximum value at the end of the charge sharing stage. However, the voltage driving ability of the memory cell 300 will change with the change of the temperature data. As Figure 2B shown, when the temperature data is relatively low, the voltage driving ability of the memory cell 300 becomes stronger, and the charge sharing voltage VCS on the bit line BL and the complementary bit line BLB reaches the maximum value in advance. The charge is lost through the leakage path of the bit line BL, and the charge sharing voltage VCS is still relatively small at the end of the charge sharing stage T1, which will make the sense margin relatively small or even less than zero, resulting in incorrect data reading. For example, the voltage of the bit line BL is greater than the voltage of the complementary bit line BLB in the charge sharing stage T1. After the sense amplification stage T2, the voltage of the bit line BL is less than the voltage of the complementary bit line BLB, and the data "1" in the memory cell is read as data "0". As Figure 2CAs shown, when the temperature data is relatively high, the voltage driving ability of the storage unit 300 becomes weak. At the end of the charge sharing stage T1, the bit line BL or the complementary bit line BLB fails to complete charge sharing with the storage capacitor Cs, and the charge sharing voltage VCS on the bit line BL and the complementary bit line BLB is still relatively small, which will result in a relatively small sensing margin or even less than zero.

[0112] To solve the above problems, the present disclosure provides a sense amplifier and a semiconductor memory, including a control module 100 and an amplification module 200. The control module 100 delays the first control signal EN1 according to the temperature data of the storage unit 300 to adjust the time when the amplification module 200 is connected to the first power supply terminal, so as to adjust the time for the bit line BL or the complementary bit line BLB to perform charge sharing with the storage unit 300, ensuring that the charge sharing voltage VCS on the bit line BL and the complementary bit line BLB is the maximum value at the end of the charge sharing stage T1, and realizing accurate amplification of the voltage difference between the bit line BL and the complementary bit line BLB in the sense amplification stage T2.

[0113] As Figure 3 shown, an embodiment of the present disclosure provides a sense amplifier, including a control module 100 and an amplification module 200. The control module 100 is provided with an input terminal and a first output terminal, and the amplification module 200 is provided with a first control terminal. The first output terminal of the control module 100 is connected to the first control terminal of the amplification module 200.

[0114] The input terminal of the control module 100 receives the first control signal EN1. The control module 100 obtains the temperature data of the storage unit 300, and delays the first control signal EN1 according to the temperature data of the storage unit 300 to generate a second control signal EN2. The amplification module 200 connects to the first power supply terminal under the control of the second control signal EN2 in the sense amplification stage T2, and amplifies the voltage difference between the bit line BL and the complementary bit line BLB under the drive of the first power supply terminal.

[0115] Among them, the charge sharing stage T1 and the sense amplification stage T2 are two adjacent stages, and the end moment of the charge sharing stage T1 is the start moment of the sense amplification stage T2. The second control signal EN2 controls the amplification module 200 to connect to the first power supply terminal, enabling the sense amplifier to enter the sense amplification stage T2. Then, the level change moment of the second control signal EN2 determines the start moment of the sense amplification stage T2, and also determines the end moment of the charge sharing stage T1.

[0116] When the second control signal EN2 is valid for the rising edge, the level change moment of the second control signal EN2 is the rising edge moment. When the second control signal EN2 is valid for the falling edge, the level change moment of the second control signal EN2 is the falling edge moment.

[0117] When the temperature data of the storage unit 300 is relatively high, the delay amount for delaying the first control signal EN1 is relatively large, that is, the level change moment of the second control signal EN2 is relatively late, and the time for the sense amplifier to be in the charge sharing stage T1 is relatively long, so as to compensate for the weakening of the voltage driving ability of the storage unit 300 due to the increase in temperature data.

[0118] When the temperature data of the storage unit 300 is relatively low, the delay amount for delaying the first control signal EN1 is relatively small. That is, the level change moment of the second control signal EN2 is relatively early, and the time for the sense amplifier to be in the charge sharing stage T1 is relatively short, so as to compensate for the strengthening of the voltage driving ability of the storage unit 300 due to the decrease in temperature data.

[0119] In the above technical solution, the control module 100 delays the first control signal EN1 according to the temperature data of the storage unit 300 to adjust the level change moment of the first control signal EN1, so as to realize adjusting the end moment of the charge sharing stage T1 according to the temperature data of the storage unit 300, and compensate for the change in the voltage driving ability of the storage unit 300 due to the change in temperature data. Ensure that at the end moment of the charge sharing stage T1, the charge sharing voltage VCS on the bit line BL and the complementary bit line BLB is the maximum value, and realize accurately amplifying the voltages on the bit line BL and the complementary bit line BLB in the sense amplification stage T2.

[0120] In some embodiments, as Figure 3 shown, the control module 100 further has a second output terminal, and the amplification module 200 further has a second control terminal. The second output terminal of the control module 100 is connected to the second control terminal of the amplification module 200. The control module 100 performs a NOT operation on the second control signal EN2 to output a third control signal EN3, and the amplification module 200 is connected to the second power supply terminal under the control of the third control signal EN3 in the sense amplification stage T2.

[0121] In the above technical solution, the control module 100 delays the first control signal EN1 according to the temperature data of the storage unit 300 to adjust the level change moment of the first control signal EN1 and adjust the time for the amplification module 200 to connect to the first power supply terminal. The third control signal EN3 is obtained by performing a NOT operation on the second control signal EN2, so that the time for the amplification module 200 to connect to the second power supply terminal adapts to the time for the amplification module 200 to connect to the first power supply terminal. After the amplification module 200 connects to the first power supply terminal and the second power supply terminal, it amplifies the voltages on the bit line BL and the complementary bit line BLB, realizes adjusting the start moment of the sense amplification stage T2 according to the temperature data of the storage unit 300, and at the same time realizes adjusting the end moment of the charge sharing stage T1 according to the temperature data of the storage unit 300.

[0122] In some embodiments, the voltage VH of the first power supply terminal is greater than the voltage VL of the second power supply terminal, and the second power supply terminal is usually a ground terminal.

[0123] In some embodiments, as Figure 4 shown, the control module 100 includes a control unit 120, an adjustment unit 110, and a first inverter 130. The control module 100 has an output terminal, the adjustment unit 110 has an input terminal, an output terminal, and a control terminal, and the first inverter 130 has an input terminal and an output terminal.

[0124] The output terminal of the control unit 120 is connected to the control terminal of the adjustment unit 110, and the output terminal of the adjustment unit 110 is connected to the input terminal of the first inverter 130. The control unit 120 generates a delay adjustment signal according to the temperature data of the storage unit 300. The input terminal of the adjustment unit 110 receives a first control signal EN1, the control terminal of the adjustment unit 110 receives the delay adjustment signal, the adjustment unit 110 performs a delay process on the first control signal EN1 according to the delay adjustment signal and outputs a second control signal EN2, and the first inverter 130 performs a NOT operation on the second control signal EN2 and outputs a third control signal EN3.

[0125] In some embodiments, as Figure 4 shown, the control unit 120 includes a temperature sensor 121 and a temperature decoder 122. The temperature sensor 121 has an output terminal, and the temperature decoder 122 has an input terminal and an output terminal. The output terminal of the temperature sensor 121 is connected to the input terminal of the temperature decoder 122. The temperature sensor 121 detects the temperature data of the storage unit 300, and encodes the temperature data to generate temperature encoded data. The input terminal of the temperature decoder 122 is connected to the output terminal of the temperature sensor 121. The temperature decoder 122 decodes the temperature encoded data, compares the decoding result with each temperature range, determines the gear information corresponding to the temperature data, and generates a delay adjustment signal according to the gear information corresponding to the temperature data.

[0126] In some embodiments, as Figure 4 shown, the control unit 120 includes three output terminals, the delay adjustment signal includes three strobe signals, and the adjustment unit 110 includes a first adjustment subunit 111, a second adjustment subunit 112, a third adjustment subunit 113, and a selection unit 114. The selection unit 114 has three input terminals, which are sequentially marked as a first input terminal, a second input terminal, and a third input terminal.

[0127] The first adjustment subunit 111 has an input terminal and an output terminal. The output terminal of the first adjustment subunit 111 is connected to the first input terminal of the selection unit 114. The input terminal of the first adjustment subunit 111 receives the first control signal EN1, and performs a delay process on the first control signal EN1 and outputs a fourth control signal EN4.

[0128] The second regulating subunit 112 is provided with an input end and an output end. The output end of the second regulating subunit 112 is connected to the second input end of the selection unit 114. The input end of the second regulating subunit 112 receives the first control signal EN1 and delays the first control signal EN1 to output a fifth control signal EN5.

[0129] The third regulating subunit 113 is provided with an input end and an output end. The output end of the third regulating subunit 113 is connected to the third input end of the selection unit 114. The input end of the third regulating subunit 113 receives the first control signal EN1 and delays the first control signal EN1 to output a sixth control signal EN6.

[0130] Among them, the delay amounts of the fourth control signal EN4, the fifth control signal EN5, and the sixth control signal EN6 are all different, that is, the level change times of the fourth control signal EN4, the fifth control signal EN5, and the sixth control signal EN6 are all different.

[0131] Among them, when the fourth control signal EN4, the fifth control signal EN5, and the sixth control signal EN6 are all rising edge signals, the level change time is the rising edge time. When the fourth control signal EN4, the fifth control signal EN5, and the sixth control signal EN6 are all falling edge signals, the level change time is the falling edge time.

[0132] The selection unit 114 is further provided with three control ends, each control end is connected to the corresponding output end of the control unit 120. Each control end of the selection unit 114 receives the corresponding gating signal. The selection unit 114 selects one of the fourth control signal EN4, the fifth control signal EN5, and the sixth control signal EN6 for output under the control of the three gating signals. Among them, the output signal of the selection unit 114 controls the first control end of the amplification module 200.

[0133] In the above technical solution, the regulating unit 110 includes three regulating subunits, a selection unit 114, and a second inverter 140. The delay amounts of the output signals of the three regulating subunits relative to the first control signal EN1 are different, that is, the level change times of the output signals of the three regulating subunits are different. The selection unit 114 selects one of the output signals of the three regulating subunits for output according to the three gating signals. Whether the three gating signals are valid is determined according to the temperature data of the storage unit 300, so as to realize adjusting the level change time of the first control signal EN1 according to the temperature data of the storage unit 300, and using the output signal of the selection unit 114 to control the first control end of the amplification module 200, so as to realize adjusting the end time of the charge sharing stage T1 according to the temperature data of the storage unit 300.

[0134] In some embodiments, there are three temperature range gears, marked as the first temperature range, the second temperature range, and the third temperature range. The upper limit value of the first temperature range is less than or equal to the lower limit value of the second temperature range, and the upper limit value of the second temperature range is less than or equal to the lower limit value of the third temperature range. For example: the first temperature range is T ≤ 20°C, the second temperature range is 20°C < T ≤ 60°C, and the third temperature range is T > 60°C.

[0135] In some embodiments, the three gating signals output by the control unit 120 are marked as the first gating signal, the second gating signal, and the third gating signal. The first gating signal is used to control the selection unit 114 to select the fourth control signal EN4 for output. The second gating signal is used to control the selection unit 114 to select the fifth control signal EN5 for output. The third gating signal is used to control the selection unit 114 to select the sixth control signal EN6 for output.

[0136] In some embodiments, the delay amount of the fourth control signal EN4 is less than the delay amount of the fifth control signal EN5, and the delay of the fifth control signal EN5 is less than the delay amount of the sixth control signal EN6, that is, the level change moment of the fourth control signal EN4 is earlier than the level change moment of the fifth control signal EN5, and the level change moment of the fifth control signal EN5 is earlier than the level change moment of the sixth control signal EN6.

[0137] In some embodiments, when the temperature data is within the first temperature range, the first gating signal output by the control unit 120 is a valid value, and the second gating signal and the third gating signal output by the control unit 120 are invalid values. Under the control of the three gating signals, the selection unit 114 selects the fourth control signal EN4 for output.

[0138] When the temperature data is within the second temperature range, the second gating signal output by the control unit 120 is a valid value, and the first gating signal and the third gating signal output by the control unit 120 are invalid values. Under the control of the three gating signals, the selection unit 114 selects the fifth control signal EN5 for output.

[0139] When the temperature data is within the third temperature range, the third gating signal output by the control unit 120 is a valid value, and the first gating signal and the second gating signal output by the control unit 120 are invalid values. Under the control of the three gating signals, the selection unit 114 selects the sixth control signal EN6 for output.

[0140] In the above technical solution, that is, when the temperature of the storage unit 300 is higher, the selection unit 114 selects and outputs a control signal with a larger selection delay amount, that is, a control signal with a relatively late level change moment, so that the time of the charge sharing stage T1 is longer, and there is sufficient charge sharing time between the storage unit 300 and the bit line BL, so that the charge sharing voltage VCS on the bit line BL and the complementary bit line BLB is the largest at the end of the charge sharing stage T1.

[0141] In some embodiments, as Figure 5A shown, the first adjustment subunit 111 includes a first pulse generator 310, a first delay circuit 320, a second pulse generator 330, and a first latch 340.

[0142] Both the first pulse generator 310 and the second pulse generator 330 are provided with an input terminal and an output terminal. The first delay circuit 320 is provided with an input terminal and an output terminal. The first latch 340 is provided with a first input terminal, a second input terminal, and an output terminal.

[0143] The output terminal of the first pulse generator 310 is connected to the first input terminal In1 of the first latch 340. The input terminal of the second pulse generator 330 is connected to the output terminal of the first delay circuit 320. The output terminal of the second pulse generator 330 is connected to the second input terminal In2 of the first latch 340.

[0144] The input terminal of the first pulse generator 310 receives a first control signal EN1. The first pulse generator 310 generates a first pulse signal PL1 according to the first control signal EN1. The input terminal of the first delay circuit 320 also receives the first control signal EN1. The first delay circuit 320 performs a delay process on the first control signal EN1 and outputs a first delay signal. The second pulse generator 330 generates a second pulse signal PL2 according to the first delay signal. The first input terminal In1 of the first latch 340 receives the first pulse signal PL1. The second input terminal In2 of the first latch 340 receives the second pulse signal PL2. The first latch 340 generates a fourth control signal EN4 according to the first pulse signal PL1 and the second pulse signal PL2, and outputs it via the output terminal Out1.

[0145] In some embodiments, the first pulse generator 310 includes a first NAND gate 311 and an odd number of third inverters 312. The odd number of third inverters 312 are connected in cascade. That is, the input terminal of the first-stage third inverter 312 receives the first control signal EN1, and the input terminal of the second-stage third inverter 312 is connected to the output terminal of the first-stage third inverter 312. And so on, the input terminal of the last-stage third inverter 312 is connected to the output terminal of the penultimate-stage third inverter 312.

[0146] As Figure 5BAs shown, the first control signal EN1 is a rising-edge signal. After the first control signal EN1 undergoes an odd number of NOT operations, the output signal of the last-stage third inverter 312 is a falling-edge signal, and the rising-edge time t1 of the first control signal EN1 is earlier than the falling-edge time t3 of the output signal of the last-stage third inverter 312.

[0147] The first input terminal R1 of the first NAND gate 311 receives the first control signal EN1. The output terminal of the last-stage third inverter 312 is connected to the second input terminal R2 of the first NAND gate 311. After the first NAND gate 311 performs a NAND operation on the first control signal EN1 and the output signal of the last-stage third inverter 312, it outputs the first pulse signal PL1 through its output terminal, and the pulse width of the first pulse signal PL1 is smaller than the pulse width of the first control signal EN1.

[0148] In some embodiments, as Figure 5A shown, the first delay circuit 320 includes a first buffer 321 and a second buffer 322. The input terminal of the second buffer 322 is connected to the output terminal of the first buffer 321. The input terminal of the first buffer 321 receives the first control signal EN1, and the output terminal of the second buffer 322 outputs a first delay signal. When the first control signal EN1 is a rising-edge signal, after two signal delays, the rising-edge time t2 of the first delay signal is later than the rising-edge time t1 of the first control signal EN1.

[0149] In some embodiments, the first pulse generator 310 and the second pulse generator 330 have the same structure. Continuing to refer to Figure 5A , the second pulse generator 330 includes a fourth NAND gate 331 and an odd number of fourth inverters 332. The first input terminal R3 of the fourth NAND gate 331 receives the first delay signal. The first-stage fourth inverter 332 receives the first delay signal and inputs it to the second input terminal R4 of the fourth NAND gate 331 after an odd number of NOT operations. The fourth NAND gate 331 performs a NAND operation on the first delay signal and the first delay signal after an odd number of NOT operations, and then outputs the second pulse signal PL2 through the output terminal.

[0150] As Figure 5BAs shown, the first control signal EN1 and the first delay signal are both rising-edge signals, and the rising-edge time t1 of the first control signal EN1 is earlier than the rising-edge time t2 of the first delay signal. Then, the pulse start time t1 of the first pulse signal PL1 is earlier than the pulse start time t2 of the second pulse signal PL2, and the time difference △τ1 between the pulse start time of the second pulse signal PL2 and the pulse start time of the first pulse signal PL1 is equal to the time difference △τ1 between the rising-edge time of the first delay signal and the rising-edge time of the first control signal EN1. The pulse levels of the first pulse signal PL1 and the second pulse signal PL2 are the same, and the pulse widths are also the same.

[0151] In some embodiments, with continued reference to Figure 5A , the first latch 340 includes a second NAND gate 341 and a third NAND gate 342. The first input terminal of the second NAND gate 341 serves as the first input terminal In1 of the first latch 340. The second input terminal of the second NAND gate 341 is connected to the output terminal of the third NAND gate 342. The output terminal of the second NAND gate 341 is connected to the first input terminal of the third NAND gate 342. The second input terminal of the third NAND gate 342 serves as the second input terminal In2 of the first latch 340. The output terminal of the second NAND gate 341 serves as the output terminal Out1 of the first latch 340.

[0152] As Figure 5C shown, when the first control signal EN1 is a rising-edge signal and the first pulse signal PL1 and the second pulse signal PL2 are both low-level pulses, the first input terminal In1 of the first latch 340 first receives a low-level pulse, and the second input terminal In2 of the first latch 340 then receives a low-level pulse. The output terminal of the first latch 340 outputs a low level at the pulse start time t1 of the first pulse signal PL1 and maintains the low level. The output terminal of the first latch 340 outputs a high level at the pulse start time t2 of the second pulse signal PL2 and maintains the high level. That is, the fourth control signal EN4 output by the output terminal Out1 of the first latch 340 is still a rising-edge signal. The rising-edge time of the fourth control signal EN4 is determined by the pulse start time t2 of the second pulse signal PL2.

[0153] In some embodiments, as Figure 6A shown, the second adjustment subunit 112 includes a third pulse generator 410, a second delay circuit 420, a fourth pulse generator 430, and a second latch 440.

[0154] Both the third pulse generator 410 and the fourth pulse generator 430 are provided with input terminals and output terminals. The second delay circuit 420 is provided with an input terminal and an output terminal. The second latch 440 is provided with a first input terminal In3, a second input terminal In4, and an output terminal Out2.

[0155] The output terminal of the second delay circuit 420 is connected to the input terminal of the fourth pulse generator 430, and the output terminal of the third pulse generator 410 is connected to the first input terminal In3 of the second latch 440. The output terminal of the fourth pulse generator 430 is connected to the second input terminal In4 of the second latch 440.

[0156] The input terminal of the third pulse generator 410 receives the first control signal EN1, and the third pulse generator 410 generates a third pulse signal PL3 according to the first control signal EN1. The input terminal of the second delay circuit 420 receives the first control signal EN1, and the second delay circuit 420 performs a delay process on the first control signal EN1 and outputs a second delay signal. The input terminal of the fourth pulse generator 430 receives the second delay signal, and the fourth pulse generator 43 generates a fourth pulse signal PL4 according to the second delay signal. The first input terminal In3 of the second latch 440 receives the third pulse signal PL3, the second input terminal In4 of the second latch 440 receives the fourth pulse signal PL4, and the second latch 440 generates a fifth control signal EN5 according to the third pulse signal PL3 and the fourth pulse signal PL4, and outputs the fifth control signal EN5 via the output terminal Out2.

[0157] Wherein, the delay amount of the second delay circuit 420 is greater than that of the first delay circuit 320. That is, the level change moment of the second delay signal output by the second delay circuit 420 is later than that of the first delay signal output by the first delay circuit 320. When both the first delay signal and the second delay signal are rising edge signals, the level change moment is the rising edge moment. When both the first delay signal and the second delay signal are falling edge signals, the level change moment is the falling edge moment.

[0158] In some embodiments, as Figure 6A shown, the second delay circuit 420 includes a third buffer 421, a fourth buffer 422, a fifth buffer 423, and a sixth buffer 424. The input terminal of the third buffer 421 receives the first control signal EN1, the output terminal of the third buffer 421 is connected to the input terminal of the fourth buffer 422, the output terminal of the fourth buffer 422 is connected to the input terminal of the fifth buffer 423, the output terminal of the fifth buffer 423 is connected to the input terminal of the sixth buffer 424, and the first control signal EN1 outputs a second delay signal after four delay processes. Compared with the first delay signal obtained through two delays, the level change moment of the second delay signal obtained through four delays is later than that of the first delay signal.

[0159] The structure of the third pulse generator 410 is the same as that of the first pulse generator 310. The third pulse generator 410 includes a fifth NAND gate 411 and an odd number of cascaded fifth inverters 412. The connection relationship between the fifth NAND gate 411 and the odd number of cascaded fifth inverters 412 is similar to that in the first pulse generator 310, which will not be elaborated here. The structure of the fourth pulse generator 430 is the same as that of the first pulse generator 310. The fourth pulse generator 430 includes a sixth NAND gate 431 and an odd number of cascaded sixth inverters 432. The connection relationship between the sixth NAND gate 431 and the odd number of cascaded sixth inverters 432 is similar to that in the first pulse generator 310, which will not be elaborated here. The principle of the third pulse generator 410 generating the third pulse signal PL3 and the fourth pulse generator 430 generating the fourth pulse signal PL4 is the same as that of the first pulse generator 310 generating the first pulse signal PL1.

[0160] As Figure 6B shown, the pulse levels of the third pulse signal PL3 and the fourth pulse signal PL4 are the same, and the pulse widths are also the same. The pulse start time t6 of the fourth pulse signal PL4 is later than the pulse start time t5 of the third pulse signal PL3, and the time difference between the pulse start time t6 of the fourth pulse signal PL4 and the pulse start time t5 of the third pulse signal PL3 is the same as the time difference between the level change time of the second delay signal and the level change time of the first control signal EN1.

[0161] As Figure 6A shown, the structure of the second latch 440 is the same as that of the first latch 340. The second latch 440 includes a seventh NAND gate 441 and an eighth NAND gate 442. The connection relationship between the seventh NAND gate 441 and the eighth NAND gate 442 is similar to that in the first latch 340, which will not be elaborated here. The principle of the second latch 440 generating the fifth control signal EN5 is the same as that of the first latch 340 generating the fourth control signal EN4.

[0162] As Figure 6B shown, the output terminal Out2 of the second latch 440 outputs a low level at the pulse start time t5 of the third pulse signal PL3 and maintains the low level. The output terminal Out2 of the second latch 440 outputs a high level at the pulse start time t6 of the fourth pulse signal PL4 and maintains the high level. That is, the fifth control signal EN5 output by the second latch 440 is a rising edge signal. The rising edge time of the fifth control signal EN5 is determined by the pulse start time t6 of the fourth pulse signal PL4.

[0163] Due to the time difference between the level change moment of the second delay signal and the level change moment of the first control signal EN1 being greater than the time difference between the level change moment of the first delay signal and the level change moment of the first control signal EN1, the time difference between the pulse start moment t6 of the fourth pulse signal PL4 and the pulse start moment t5 of the third pulse signal PL3 is greater than the time difference between the pulse start moment t2 of the second pulse signal PL2 and the pulse start moment t1 of the first pulse signal PL1. Then, the rising edge moment t6 of the fifth control signal EN5 is later than the rising edge moment t1 of the fourth control signal EN4.

[0164] In some embodiments, as Figure 7A shown, the third adjustment sub-unit 113 includes a fifth pulse generator 510, a third delay circuit 520, a sixth pulse generator 530, and a third latch 540.

[0165] Both the fifth pulse generator 510 and the sixth pulse generator 530 are provided with an input end and an output end. The third delay circuit 520 is provided with an input end and an output end. The third latch 540 is provided with a first input end In5, a second input end In6, and an output end Out3.

[0166] The output end of the third delay circuit 520 is connected to the input end of the sixth pulse generator 530. The output end of the fifth pulse generator 510 is connected to the first input end In5 of the third latch 540. The output end of the sixth pulse generator 530 is connected to the second input end In6 of the third latch 540.

[0167] The input end of the fifth pulse generator 510 receives the first control signal EN1, and the fifth pulse generator 510 generates a fifth pulse signal PL5 according to the first control signal EN1. The input end of the third delay circuit 520 receives the first control signal EN1, and the third delay circuit 520 performs delay processing on the first control signal EN1 and outputs a third delay signal. The input end of the sixth pulse generator 530 receives the third delay signal, and the sixth pulse generator 530 generates a sixth pulse signal PL6 according to the third delay signal. The first input end In5 of the third latch 540 receives the fifth pulse signal PL5, the second input end In6 of the third latch 540 receives the sixth pulse signal PL6, and the third latch 540 generates a sixth control signal EN6 according to the fifth pulse signal PL5 and the sixth pulse signal PL6 and outputs it via the output end Out3.

[0168] Among them, the delay amount of the third delay circuit 520 is greater than that of the second delay circuit 420. That is, the level change moment of the third delay signal output by the third delay circuit 520 is later than that of the second delay signal output by the second delay circuit 420. When both the second delay signal and the third delay signal are rising edge signals, the level change moment is the rising edge moment. When both the second delay signal and the third delay signal are falling edge signals, the level change moment is the falling edge moment.

[0169] In some embodiments, as Figure 7A shown, the third delay circuit 520 includes a seventh buffer 521, an eighth buffer 522, a ninth buffer 523, a tenth buffer 524, an eleventh buffer 525, and a twelfth buffer 526. The input end of the seventh buffer 521 receives the first control signal EN1. The input end of the eighth buffer 522 is connected to the output end of the seventh buffer 521. The input end of the ninth buffer 523 is connected to the output end of the eighth buffer 522. The input end of the tenth buffer 524 is connected to the output end of the ninth buffer 523. The input end of the eleventh buffer 525 is connected to the output end of the tenth buffer 524. The input end of the twelfth buffer 526 is connected to the output end of the eleventh buffer 525. The output end of the twelfth buffer 526 outputs the third delay signal. The first control signal EN1 outputs the third delay signal after six delay processes. Through six delays, the level change moment of the third delay signal is later than that of the second delay signal.

[0170] As Figure 7A shown, the structure of the fifth pulse generator 510 is the same as that of the first pulse generator 310. The fifth pulse generator 510 includes a ninth NAND gate 511 and an odd number of cascaded seventh inverters 512. The connection relationship between the ninth NAND gate 511 and the odd number of cascaded seventh inverters 512 is similar to that in the first pulse generator 310 and will not be elaborated here. The structure of the sixth pulse generator 530 is the same as that of the first pulse generator 310. The sixth pulse generator 530 includes a tenth NAND gate 531 and an odd number of cascaded eighth inverters 532. The connection relationship between the tenth NAND gate 531 and the odd number of cascaded eighth inverters 532 is similar to that in the first pulse generator 310 and will not be elaborated here. The principles of the fifth pulse generator 510 generating the fifth pulse signal PL5 and the sixth pulse generator 530 generating the sixth pulse signal PL6 are the same as the principle of the first pulse generator 310 generating the first pulse signal PL1 and will not be elaborated here.

[0171] As Figure 7BAs shown, the pulse levels of the fifth pulse signal PL5 and the sixth pulse signal PL6 are the same, and the pulse widths are also the same. The pulse start time t8 of the sixth pulse signal PL6 is later than the pulse start time t7 of the fifth pulse signal PL5, and the time difference between the pulse start time t8 of the sixth pulse signal PL6 and the pulse start time t7 of the fifth pulse signal PL5 is the same as the time difference between the level change time of the third delay signal and the level change time of the first control signal EN1.

[0172] As Figure 7A shown, the structure of the third latch 540 is the same as that of the first latch 340. The third latch 540 includes an eleventh NAND gate 541 and a twelfth NAND gate 542. The connection relationship between the eleventh NAND gate 541 and the twelfth NAND gate 542 is similar to that in the first latch 340, and will not be elaborated here. The principle of the third latch 540 generating the sixth control signal EN6 is the same as the principle of the first latch 340 generating the fourth control signal EN4.

[0173] As Figure 7B shown, the output terminal Out3 of the third latch 540 outputs a low level at the pulse start time t7 of the fifth pulse signal PL5 and maintains the low level. The output terminal of the third latch 540 outputs a high level at the pulse start time t8 of the sixth pulse signal PL6 and maintains the high level. That is, the sixth control signal EN6 output by the third latch 540 is a rising edge signal. The rising edge time of the sixth control signal EN6 is determined by the pulse start time t8 of the sixth pulse signal PL6.

[0174] Since the time difference between the level change time of the third delay signal and the level change time of the first control signal EN1 is greater than the time difference between the level change time of the second delay signal and the level change time of the first control signal EN1, the time difference between the pulse start time t8 of the sixth pulse signal PL6 and the pulse start time t7 of the fifth pulse signal PL5 is greater than the time difference between the pulse start time t6 of the fourth pulse signal PL4 and the pulse start time t5 of the third pulse signal PL3. Then, the rising edge time t8 of the sixth control signal EN6 is later than the rising edge time t6 of the fifth control signal EN5.

[0175] In some embodiments, such as Figure 4As shown, the control unit 120 further includes a second inverter 140. The input terminal of the second inverter 140 is connected to the output terminal of the selection unit 114. The second inverter 140 is used to perform a NOT operation on the output signal of the selection unit 114, and the output signal of the second inverter 140 is used to control the first control terminal of the amplification module 200. When the control unit 120 outputs a rising edge signal, the second inverter 140 outputs a falling edge signal, and the first inverter 130 outputs a rising edge signal. The falling edge signal output by the second inverter 140 controls the amplification module 200 to turn on the first power supply terminal during the sense amplification stage T2, and the rising edge signal output by the first inverter 130 controls the amplification module 200 to turn on the second power supply terminal during the sense amplification stage T2.

[0176] In some embodiments, as Figure 3 shown, the amplification module 200 includes a first P-type transistor P1, a second P-type transistor P2, a third P-type transistor P3, a first N-type transistor N1, a second N-type transistor N2, and a third N-type transistor N3. The connection relationship of the transistors in the amplification module 200 has been described in Figure 1 and will not be elaborated here.

[0177] Among them, the gate of the third P-type transistor P3 serves as the first control terminal of the amplification module 200, and the gate of the third N-type transistor N3 serves as the second control terminal of the amplification module 200.

[0178] In some embodiments, the second control signal EN2 is valid for a falling edge signal, and the third control signal EN3 is valid for a rising edge signal.

[0179] In some embodiments, the first control signal EN1 is a rising edge signal. The gate of the third P-type transistor P3 is connected to the second inverter 140 and receives the second control signal EN2 output by the second inverter 140 as a falling edge signal. The gate of the third N-type transistor N3 is connected to the first inverter 130 and receives the third control signal EN3 output by the first inverter 130 as a rising edge signal.

[0180] Next, in combination with Figure 8A 、 Figure 8B and Figure 8C , taking the storage unit 300 storing data as "1" and writing data as "0", the working timing when writing data into the storage unit 300 is described as follows:

[0181] During the charge sharing stage T1, the word line signal on the word line WL is at a high level, the control transistor SN in the storage unit 300 is turned on, the storage capacitor Cs in the storage unit 300 shares charge with the bit line BL, and the voltage of the bit line BL increases.

[0182] As Figure 8AAs shown, when the temperature data of the storage unit 300 is relatively low and within the first temperature range, the selection unit 114 selects the fourth control signal EN4 output by the first adjustment subunit 111 for output. Compared with the fifth control signal EN5 and the sixth control signal EN6, the rising edge time of the fourth control signal EN4 is earlier. The time when the second control signal EN2 is at a high level is relatively short, the time when the third control signal EN3 is at a low level is relatively short, the time when the third N-type transistor N3 and the third P-type transistor P3 are in a cut-off state is relatively short, and the time when the amplification module 200 is disconnected from the first power supply terminal and the second power supply terminal is relatively short. Then, the time for the storage capacitor Cs in the storage unit 300 to share charge with the bit line BL is shorter. Since the voltage driving ability of the storage unit 300 is stronger at a lower temperature, it is ensured that the third N-type transistor N3 and the third P-type transistor P3 are turned on when the charge sharing voltage on the bit line BL and the complementary bit line BLB reaches the maximum value, and the sensing and amplification stage T2 is entered in a timely manner.

[0183] As Figure 8B shown, when the temperature data of the storage unit 300 rises and is within the second temperature range, the selection unit 114 selects the fifth control signal EN5 output by the second adjustment subunit 112 for output. Compared with the fourth control signal EN4, the rising edge time of the fifth control signal EN5 is later. The time when the second control signal EN2 is at a high level is extended, the time when the third control signal EN3 is at a low level is extended, the time when the third N-type transistor N3 and the third P-type transistor P3 are in a cut-off state is extended, and the time when the amplification module 200 is disconnected from the first power supply terminal and the second power supply terminal is extended. Then, the time for the storage capacitor Cs in the storage unit 300 to share charge with the bit line BL is extended. Since the voltage driving ability of the storage unit 300 becomes weaker after the temperature rises, by extending the charge sharing time, it is ensured that the charge sharing voltage on the bit line BL and the complementary bit line BLB reaches the maximum value at the end of the charge sharing stage T1.

[0184] As Figure 8CAs shown, when the temperature data of the storage unit 300 continues to rise and is in the third temperature range, the selection unit 114 selects and outputs the sixth control signal EN6 output by the third adjustment subunit 113. Compared with the fifth control signal EN5, the rising edge of the sixth control signal EN6 is later. The time when the second control signal EN2 is at a high level is further extended, and the time when the third control signal EN3 is at a low level is further extended. The time when the third N-type transistor N3 and the third P-type transistor P3 are in a cut-off state is further extended, and the time when the amplification module 200 is disconnected from the first power supply terminal and the second power supply terminal is further extended. Then, the time for the storage capacitor Cs in the storage unit 300 to share charge with the bit line BL is further extended. Since the voltage driving ability of the storage unit 300 becomes weaker after the temperature rises, by further extending the charge sharing time, it is ensured that the charge sharing voltage on the bit line BL and the complementary bit line BLB reaches the maximum value at the end of the charge sharing stage T1.

[0185] In the sense amplification stage T2, the gate of the third P-type transistor P3 receives that the second control signal EN2 becomes low, and the gate of the third N-type transistor N3 receives that the third control signal EN3 becomes high. The amplification module 200 is connected to both the first power supply terminal and the second power supply terminal. The amplification module 200 further drives the voltages on the bit line BL and the complementary bit line BLB to form a larger voltage difference between the bit line BL and the complementary bit line BLB.

[0186] In the above technical solution, the control unit 120 performs a delay process on the first control signal EN1 according to the temperature data of the storage unit 300 to adjust the falling edge time of the second control signal EN2, so as to realize adjusting the end time of the charge sharing stage T1 according to the temperature data of the storage unit 300, compensate for the change in the voltage driving ability of the storage unit 300 due to the increase in temperature data, ensure that the charge sharing voltage VCS on the bit line BL and the complementary bit line BLB is the maximum value at the end of the charge sharing stage T1, and realize accurately amplifying the voltages on the bit line BL and the complementary bit line BLB in the sense amplification stage T2.

[0187] An embodiment of the present disclosure provides a semiconductor memory, including the sense amplifier involved in the above embodiment.

[0188] Those skilled in the art will readily think of other implementations of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses, or adaptations of the present disclosure, which follow the general principles of the present disclosure and include the common general knowledge or conventional technical means in the technical field not disclosed in the present disclosure. The specification and embodiments are only regarded as exemplary, and the true scope and spirit of the present disclosure are pointed out by the following claims.

[0189] It should be understood that the present disclosure is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present disclosure is only limited by the appended claims.

Claims

1. A sense amplifier, characterized in that, Comprising: A control module, which is provided with an input end and a first output end, is used to obtain the temperature data of the storage unit, delay-process the first control signal received at its input end according to the temperature data of the storage unit to generate a second control signal, adjust the time for the amplification module to connect to the first power supply end, and adjust the charge sharing time between the bit line or the complementary bit line and the storage unit; An amplification module, whose first control end is connected to the first output end of the control module, is used to connect to the first power supply end under the control of the second control signal during the sense amplification stage, and amplify the voltage difference between the bit line and the complementary bit line under the drive of the first power supply end; The control module includes: A control unit, which is provided with an output end, and is used to generate a delay adjustment signal according to the temperature data of the storage unit; An adjustment unit, which is provided with an input end, an output end and a control end, its control end is connected to the output end of the control unit, its input end receives the first control signal, and delays the first control signal according to the delay adjustment signal to output the second control signal; The control unit includes three output ends, the delay adjustment signal includes three gating signals, and the adjustment unit includes: A first adjustment sub-unit, whose output end is connected to the first input end of the selection unit, and is used to delay-process the first control signal to output a fourth control signal; A second adjustment sub-unit, whose output end is connected to the second input end of the selection unit, and is used to delay-process the first control signal to output a fifth control signal; A third adjustment sub-unit, whose output end is connected to the third input end of the selection unit, and is used to delay-process the first control signal to output a sixth control signal; wherein, the delay amounts of the fourth control signal, the fifth control signal and the sixth control signal are all different; The selection unit, which is also provided with an output end and three control ends, each control end is connected to the corresponding output end of the control unit and receives the corresponding gating signal; is used to select one of the fourth control signal, the fifth control signal and the sixth control signal for output under the control of the three gating signals; the output signal of the selection unit is used to control the first control end of the amplification module; The first adjustment sub-unit includes: A first pulse generator, whose input end receives the first control signal, and is used to generate a first pulse signal according to the first control signal; A first delay circuit, whose input end receives the first control signal, delays the first control signal and then outputs a first delay signal; A second pulse generator, whose input end is connected to the output end of the first delay circuit, and is used to generate a second pulse signal according to the first delay signal; A first latch, whose first input end is connected to the first pulse generator, and whose second input end is connected to the second pulse generator, and is used to generate the fourth control signal according to the first pulse signal and the second pulse signal.

2. The sense amplifier according to claim 1, characterized in that, The control module is further provided with a second output end, and is also used to perform a NOT operation on the second control signal to generate a third control signal; The amplification module further has a second control terminal; the second control terminal is connected to the second output terminal of the control module and is used to connect to the second power supply terminal under the control of the third control signal. Among them, the voltage of the first power supply terminal is greater than the voltage of the second power supply terminal.

3. The sense amplifier according to claim 1, characterized in that, The control module further includes: A first inverter, whose input terminal is connected to the output terminal of the adjustment unit, is used to perform a NOT operation on the second control signal and output a third control signal.

4. The sense amplifier according to claim 1, characterized in that, The adjustment unit further includes: A second inverter, whose input terminal is connected to the output terminal of the selection unit, is used to perform a NOT operation on the output signal of the selection unit and then output; the output signal of the second inverter is used to control the first control terminal of the amplification module.

5. The sense amplifier according to claim 1, characterized in that, The control unit is used for: When the temperature data is within the first temperature range, the first strobe signal output is a valid value, and the second strobe signal and the third strobe signal output are invalid values; control the selection unit to select the fourth control signal for output. When the temperature data is within the second temperature range, the second strobe signal output is a valid value, and the first strobe signal and the third strobe signal output are invalid values; control the selection unit to select the fifth control signal for output. When the temperature data is within the third temperature range, the third strobe signal output is a valid value, and the first strobe signal and the second strobe signal output are invalid values; control the selection unit to select the sixth control signal for output. Among them, the upper limit value of the first temperature range is less than or equal to the lower limit value of the second temperature range, and the upper limit value of the second temperature range is less than or equal to the lower limit value of the third temperature range; the delay amount of the fourth control signal is less than the delay amount of the fifth control signal, and the delay amount of the fifth control signal is less than the delay amount of the sixth control signal.

6. The sense amplifier according to claim 1, characterized in that, The second adjustment sub-unit includes: A third pulse generator, whose input terminal receives the first control signal, is used to generate a third pulse signal according to the first control signal. A second delay circuit, whose input terminal receives the first control signal, performs a delay process on the first control signal and then outputs a second delay signal, and the delay amount of the second delay circuit is greater than the delay amount of the first delay circuit. A fourth pulse generator, whose input terminal is connected to the output terminal of the second delay circuit, is used to generate a fourth pulse signal according to the second delay signal. A second latch, whose first input terminal is connected to the third pulse generator, whose second input terminal is connected to the fourth pulse generator, and is used to generate the fifth control signal according to the third pulse signal and the fourth pulse signal.

7. The sense amplifier according to claim 6, wherein The third adjustment sub-unit includes: A fifth pulse generator, whose input terminal receives the first control signal, is used to generate a fifth pulse signal according to the first control signal. A third delay circuit, whose input terminal receives the first control signal, performs a delay process on the first control signal and then outputs a third delay signal, and the delay amount of the third delay circuit is greater than the delay amount of the second delay circuit. A sixth pulse generator, whose input terminal is connected to the output terminal of the third delay circuit, is configured to generate a sixth pulse signal according to the third delay signal; A third latch, whose first input terminal is connected to the fifth pulse generator, whose second input terminal is connected to the sixth pulse generator, and is configured to generate the sixth control signal according to the fifth pulse signal and the sixth pulse signal.

8. The sense amplifier according to claim 1, wherein The structures of the first pulse generator, the second pulse generator, the third pulse generator, the fourth pulse generator, the fifth pulse generator, and the sixth pulse generator are the same.

9. The sense amplifier according to claim 8, wherein The first pulse generator includes: An odd number of third inverters, the output terminal of the upper-level third inverter is connected to the input terminal of the lower-level third inverter; the input terminal of the first-level third inverter receives the first control signal, and the output terminal of the last-level third inverter is connected to the second input terminal of the first NAND gate; The first NAND gate, whose first input terminal receives the first control signal, and whose output terminal outputs the first pulse signal.

10. The sense amplifier according to claim 1, wherein The structures of the first latch, the second latch, and the third latch are the same. The first latch includes: A second NAND gate; its first input terminal serves as the first input terminal of the first latch, its second input terminal is connected to the output terminal of the third NAND gate, and its output terminal is connected to the first input terminal of the third NAND gate; The third NAND gate; the second input terminal serves as the second input terminal of the first latch, and its output terminal serves as the output terminal of the first latch.

11. The sense amplifier according to claim 1, wherein The first delay circuit includes: A first buffer, whose input terminal receives the first control signal; A second buffer, whose input terminal is connected to the output terminal of the first buffer, and whose output terminal outputs the first delay signal.

12. The sense amplifier according to claim 6, wherein The second delay circuit includes: A third buffer, whose input terminal receives the first control signal; A fourth buffer, whose input terminal is connected to the output terminal of the third buffer; A fifth buffer, whose input terminal is connected to the output terminal of the fourth buffer; A sixth buffer, whose input terminal is connected to the output terminal of the fifth buffer, and whose output terminal outputs the second delay signal.

13. The sense amplifier according to claim 7, wherein The third delay circuit includes: A seventh buffer, whose input terminal receives the first control signal; An eighth buffer, whose input terminal is connected to the output terminal of the seventh buffer; A ninth buffer, whose input terminal is connected to the output terminal of the eighth buffer; A tenth buffer, whose input terminal is connected to the output terminal of the ninth buffer; An eleventh buffer, whose input terminal is connected to the output terminal of the tenth buffer; A twelfth buffer, whose input terminal is connected to the output terminal of the eleventh buffer, and whose output terminal outputs the third delay signal.

14. The sense amplifier according to claim 1, wherein The control unit includes: A temperature sensor, which is configured to detect the temperature data of the storage unit and generate temperature encoded data according to the temperature data; A temperature decoder, whose input terminal is connected to the output terminal of the temperature sensor, and is configured to generate the delay adjustment signal according to the temperature encoded data.

15. The sense amplifier according to claim 1, wherein The amplification module includes: A third P-type transistor, whose source electrode is connected to the first power supply terminal, and whose gate electrode serves as the first control terminal of the amplification module; The first P-type transistor, whose source is connected to the drain of the third P-type transistor, and whose gate is connected to the drain of the second P-type transistor; The second P-type transistor, whose source is connected to the source of the first P-type transistor, and whose gate is connected to the drain of the first P-type transistor; The first N-type transistor, whose drain is connected to the drain of the first P-type transistor, whose gate is connected to the second N-type transistor, whose gate is connected to the complementary bit line, and whose source is indirectly coupled to the second power supply terminal; The second N-type transistor, whose drain is connected to the drain of the second P-type transistor, whose gate is connected to the first N-type transistor, whose gate is connected to the bit line, and whose source is connected to the source of the first N-type transistor.

16. The sense amplifier according to claim 15, wherein The amplification module includes: The third N-type transistor, whose source is connected to the second power supply terminal, whose gate serves as the second control terminal of the amplification module, and whose drain is connected to the source of the first N-type transistor.

17. A semiconductor memory, wherein A sense amplifier including any one of claims 1 to 16.

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