Simulation implementation method and device of solid state disk abnormal power-off and computer equipment

Abstract

The application relates to a simulation implementation method and device for abnormal power-off of a solid state disk, computer equipment and a storage medium, wherein the method comprises the following steps: obtaining a simulation implementation request for abnormal power-off of a solid state disk; according to the request, the running of each module in the SSD firmware and the running of each NAND particle processing unit are simulated in a multithreading mode; when an abnormal power-off is triggered by a test case, the running of all threads is ended to simulate the sudden stop of each module in the SSD firmware and the NAND particle processing unit and various execution states generated; when power-on is triggered by a test case, all threads are restarted to simulate the re-running of each module in the SSD firmware and the NAND particle processing unit. The application adopts a software simulation mode to simulate an abnormal power-off scene method, is more in line with an actual application scene, and can simulate various phenomena generated during abnormal power-off to facilitate debugging.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of solid state disks, and particularly relates to a simulation implementation method and device for abnormal power-off of a solid state disk, computer equipment and a storage medium. BACKGROUND

[0002] As a new type of storage medium, an SSD (Solid State Drive) uses NAND particles for data storage and has been widely applied to various fields such as PCs, notebooks and servers and gradually replaces HDDs (Hard Disk Drives) to become a mainstream application product in the storage field. The biggest advantage of the SSD is high read-write performance.

[0003] When a user uses the SSD, an abnormal power-off situation may occur. After the abnormal power-off, the SSD needs to ensure normal use after power-on, so the abnormal power-off scenario needs to be tested and debugged. In the existing method, one method is to use the SSD disk to test power-off and power-on, which will cause wear of the SSD disk, is high in cost and difficult to debug. Another method is to use a software simulation method to simulate the abnormal power-off scenario by reinitializing the modules, which has certain differences between the simulated scenario and the actual scenario, cannot simulate the sudden interruption of the SSD firmware and the different processing states of the NAND request and the scenario of incomplete single operation of the NAND in the abnormal power-off. SUMMARY

[0004] Therefore, it is necessary to provide a simulation implementation method and device for abnormal power-off of a solid state disk, computer equipment and a storage medium in view of the above technical problems.

[0005] A simulation implementation method for abnormal power-off of a solid state disk, the method comprising:

[0006] obtaining a simulation implementation request for abnormal power-off of the solid state disk;

[0007] simulating running of each module in the SSD firmware and running of each NAND particle processing unit in a multi-thread mode according to the request;

[0008] when the test case triggers abnormal power-off, ending running of all threads to simulate sudden stop of the SSD firmware modules and the NAND particle processing units and various execution states generated thereby;

[0009] when the test case triggers power-on, restarting all threads to simulate re-running of the SSD firmware modules and the NAND particle processing units.

[0010] In one of the embodiments, the step of simulating the running of each module in the SSD firmware and the running of each NAND grain processing unit in a multi-thread mode according to the request comprises:

[0011] Each module in the SSD firmware, each processing unit of the NAND grain and the host command processing are respectively created to run in a separate thread to simulate the parallel processing among the modules and the concurrent processing of each processing unit of the NAND grain, wherein the processing unit of the NAND grain simulates the read, write and erase operations on the NAND grain.

[0012] In one of the embodiments, the method further comprises:

[0013] The SSD firmware backend module and each NAND grain processing unit communicate in a message queue mode;

[0014] For each NAND grain processing unit, the SSD firmware backend module has a message queue for sending command messages, and all the NAND grain processing units use the same message queue to return command responses to the SSD firmware backend module.

[0015] In one of the embodiments, the step of ending the running of all threads to simulate the sudden stop of each module in the SSD firmware and each processing unit of the NAND grain and the various execution states generated when the test case triggers an abnormal power-off further comprises:

[0016] When the host thread triggers an abnormal power-off, all the NAND grain processing unit threads are ended;

[0017] When the NAND grain processing unit thread is ended, if the thread is processing a NAND write or erase request command at this time and the command is not processed, the scenario of the uncompleted NAND write or erase operation when the abnormal power-off occurs can be simulated.

[0018] A simulation implementation device of a solid state disk abnormal power-off, the simulation implementation device of the solid state disk abnormal power-off comprises:

[0019] An acquisition module, the acquisition module is used to acquire a simulation implementation request of a solid state disk abnormal power-off;

[0020] A running module, the running module is used to simulate the running of each module in the SSD firmware and the running of each NAND grain processing unit in a multi-thread mode according to the request;

[0021] A first simulation module, the first simulation module is used to end the running of all threads to simulate the sudden stop of each module in the SSD firmware and each processing unit of the NAND grain and the various execution states generated when the test case triggers an abnormal power-off;

[0022] a second simulation module, configured to restart all threads to simulate re-running of each module of the SSD firmware and the NAND processing unit when a test case triggers power-on.

[0023] In one of the embodiments, the running module is further configured to:

[0024] create separate threads for running each module of the SSD firmware, each processing unit of the NAND, and the host command processing, to simulate parallel processing among the modules and concurrent processing of each processing unit of the NAND; and

[0025] In one of the embodiments, the apparatus further comprises a communication module, configured to:

[0026] the SSD firmware backend module and each processing unit of the NAND communicate in a message queue manner;

[0027] For each processing unit of the NAND, the SSD firmware backend module has a message queue for sending command messages, and all processing units of the NAND use the same message queue to return command responses to the SSD firmware backend module.

[0028] In one of the embodiments, the first simulation module is further configured to:

[0029] when the host thread triggers an abnormal power-off, all processing unit threads of the NAND are ended;

[0030] when the processing unit threads of the NAND are ended, if the thread is processing a NAND write or erase request command and the command is not processed, a scenario of an abnormal power-off when a NAND write or erase operation is not completed can be simulated.

[0031] A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of any of the above methods when executing the computer program.

[0032] A computer readable storage medium, having a computer program stored thereon, wherein the computer program is executable by a processor to implement the steps of any of the above methods.

[0033] The simulation implementation method, device, computer equipment and storage medium of the abnormal power-off of the solid state disk, acquire a simulation implementation request of the abnormal power-off of the solid state disk; simulate the running of each module in the SSD firmware and the running of each NAND particle processing unit in a multi-thread mode according to the request; when the test case triggers the abnormal power-off, end the running of all threads to simulate the sudden stop of the SSD firmware and the NAND particle processing unit and the various execution states generated; when the test case triggers the power-on, restart all threads to simulate the re-running of the SSD firmware and the NAND particle processing unit. The application adopts a software simulation method to simulate the abnormal power-off scene, which is more in line with the actual application scene and can simulate various phenomena generated during the abnormal power-off to facilitate debugging. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 The flowchart of the simulation implementation method of the abnormal power-off of the solid state disk in one embodiment;

[0035] Figure 2 The flowchart of the simulation implementation method of the abnormal power-off of the solid state disk in another embodiment;

[0036] Figure 3 The architecture diagram of the software simulation module in one embodiment;

[0037] Figure 4 The interaction diagram of the back-end module and the NAND particle in one embodiment;

[0038] Figure 5 The structural block diagram of the simulation implementation device of the abnormal power-off of the solid state disk in one embodiment;

[0039] Figure 6 The structural block diagram of the simulation implementation device of the abnormal power-off of the solid state disk in another embodiment;

[0040] Figure 7 The internal structure diagram of the computer equipment in one embodiment. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical scheme and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0042] Currently, the existing abnormal power-off test method mainly includes the following two kinds, one is to use the SSD disk to test the power-off and power-on method, this method will have loss to the SSD disk, the cost is higher and not easy to debug. The other is to use the software simulation method, which uses module reinitialization to simulate the scene of abnormal power-off, which has certain difference between the simulated scene and the actual scene, and cannot simulate the sudden interruption of SSD firmware and the different processing state of NAND request and the scene of incomplete single operation of NAND during abnormal power-off.

[0043] Based on this, the present application provides a simulation implementation method of solid state disk abnormal power-off, which can be more consistent with the actual application scene and can simulate various phenomena generated during abnormal power-off to facilitate debugging.

[0044] In one embodiment, as shown in Figure 1 A simulation implementation method of solid state disk abnormal power-off is provided, which comprises:

[0045] Step 102, obtaining a simulation implementation request of solid state disk abnormal power-off;

[0046] Step 104, according to the request, simulating the running of each module in the SSD firmware and the running of each NAND particle processing unit by using multi-thread mode;

[0047] Step 106, when the test case triggers abnormal power-off, ending the running of all threads to simulate the sudden stop of each module of the SSD firmware and the NAND particle processing unit and the various execution states generated;

[0048] Step 108, when the test case triggers power-on, restarting all threads to simulate the re-running of each module of the SSD firmware and the NAND particle processing unit.

[0049] In this embodiment, a simulation implementation method of solid state disk abnormal power-off is provided, which is realized by software simulation. Specifically, first, a simulation implementation request of solid state disk abnormal power-off is obtained; and then, according to the request, the running of each module in the SSD firmware and the running of each NAND particle processing unit are simulated by using multi-thread mode.

[0050] In one embodiment, the step of simulating the running of each module in the SSD firmware and the running of each NAND particle processing unit by using multi-thread mode according to the request comprises: creating separate threads for running each module in the SSD firmware, each processing unit of the NAND particle and the host command processing to simulate the parallel processing between each module and the concurrent processing of each processing unit of the NAND particle; wherein the NAND particle processing unit simulates the read, write and erase operations on the NAND particle.

[0051] In particular, reference can be made to Figure 3 As shown in the architecture diagram of the software simulation module, each module in the SSD firmware, each processing unit of the NAND grain, and the host command processing are respectively created to run in a separate thread to simulate the parallel processing between the modules and the concurrent processing of each processing unit of the NAND grain. Among them, the NAND grain processing unit simulates the read, write and erase operations on the NAND grain.

[0052] When an abnormal power failure occurs, the running of each module of the SSD firmware is ended. Specifically, when the host thread triggers an abnormal power failure, the threads of each module of the SSD firmware and each processing unit of the NAND grain are ended to simulate the sudden interruption of the running of the SSD firmware when an abnormal power failure occurs. When the host thread triggers a power-on, the threads of each module are re-created and run to simulate the process of starting the SSD firmware.

[0053] The application scenarios of the simulation include: simulating the scenario that some NAND requests are not processed when an abnormal power failure occurs; simulating the scenario that some NAND requests are being processed but not completed when an abnormal power failure occurs; simulating the scenario that some NAND requests have been processed but the SSD firmware backend module has not received a response when an abnormal power failure occurs; simulating the scenario that a NAND write or erase operation is not completed when an abnormal power failure occurs.

[0054] In the above embodiment, a simulation implementation request of an abnormal power failure of a solid state disk is obtained; the running of each module in the SSD firmware and the running of each NAND grain processing unit are simulated in a multi-thread mode according to the request; when a test case triggers an abnormal power failure, the running of all threads is ended to simulate the sudden stop of each module of the SSD firmware and each NAND grain processing unit and various execution states generated thereby; when the test case triggers a power-on, all threads are restarted to simulate the re-running of each module of the SSD firmware and each NAND grain processing unit. The present scheme simulates the abnormal power failure scenario by using a software simulation mode, which is more consistent with the actual application scenario and can simulate various phenomena generated when an abnormal power failure occurs to facilitate debugging.

[0055] In one embodiment, as Figure 2 shown, a simulation implementation method of an abnormal power failure of a solid state disk is provided, and the method further includes:

[0056] In step 202, the SSD firmware backend module and each NAND grain processing unit communicate in a message queue mode.

[0057] In step 204, for each NAND grain processing unit, the SSD firmware backend module has a message queue for sending command messages, and all NAND grain processing units use the same message queue to return command responses to the SSD firmware backend module.

[0058] In this embodiment, a simulation method for abnormal power loss of a solid-state drive is provided. In this method, when an abnormal power loss is simulated, the processing of the current NAND flash memory is interrupted and terminated.

[0059] Specifically, refer to Figure 4 As shown, the SSD firmware backend module communicates with the processing units of each NAND flash memory chip via message queues. For each NAND flash memory chip's processing unit, the SSD firmware backend module has a message queue for sending command messages (message queues 1-4). All NAND flash memory chip processing units use the same message queue (message queue 5) to return command responses to the SSD firmware backend module.

[0060] In one embodiment, when a test case triggers an abnormal power failure, the step of ending the operation of all threads to simulate the sudden stop of various modules of the SSD firmware and the NAND flash memory processing unit and the resulting various execution states further includes: when the host thread triggers an abnormal power failure, all NAND flash memory processing unit threads will be terminated; when the NAND flash memory processing unit threads are terminated, if the thread is currently processing a NAND write or erase request command and the command has not been completed, the scenario where the NAND write or erase operation is not completed during the abnormal power failure can be simulated.

[0061] Specifically, when the host thread triggers an abnormal power loss, all NAND flash memory processing unit threads will be terminated. If there are still command messages in message queues 1-4 at this time, it simulates a scenario where some NAND requests are not processed during the abnormal power loss. If the NAND flash memory processing unit thread is currently processing a command message, it simulates a scenario where some NAND requests are being processed but not yet completed during the abnormal power loss. If there are still command messages in message queue 5, it simulates a scenario where some NAND requests have been completed during the abnormal power loss, but the SSD firmware backend module has not received a response. When the NAND flash memory processing unit thread is terminated, if the thread is currently processing a NAND write or erase request command, and the command has not been completed, it simulates a scenario where the NAND write or erase operation is incomplete during the abnormal power loss.

[0062] In the above embodiments, the method can simulate various power failure scenarios, and the simulation of abnormal power failure is more in line with real-world scenarios. Specific power failure scenarios include: simulating a scenario where the operation of each module of the SSD firmware is suddenly terminated during an abnormal power failure; simulating a scenario where the concurrent processing of each processing unit of the NAND flash memory chip is performed; simulating a scenario where different processing states of multiple NAND requests are performed; and simulating a scenario where the write or erase request command currently being processed by the NAND flash memory chip is interrupted during an abnormal power failure, resulting in partial write or erase operations.

[0063] It should be understood that, althoughFigures 1-4 The steps in the flowchart are shown in sequence according to the arrows, but the steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, the steps are not strictly limited in sequence, and the steps can be executed in other sequences. Moreover, Figures 1-4 At least a part of the steps in the flowchart can include multiple sub-steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution sequence of the sub-steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least a part of other steps or sub-steps or stages of other steps.

[0064] In one embodiment, as shown in Figure 5 An abnormal power-off simulation implementation device 500 of a solid state disk is provided, and the device comprises:

[0065] An acquisition module 501 is configured to acquire a simulation implementation request for abnormal power-off of a solid state disk.

[0066] A running module 502 is configured to simulate running of each module in the SSD firmware and running of each NAND particle processing unit in a multi-threaded manner according to the request.

[0067] A first simulation module 503 is configured to, when an abnormal power-off is triggered by a test case, end running of all threads to simulate sudden stop of the SSD firmware modules and the NAND particle processing units and various execution states generated thereby.

[0068] A second simulation module 504 is configured to, when power-on is triggered by a test case, restart running of all threads to simulate re-running of the SSD firmware modules and the NAND particle processing units.

[0069] In one embodiment, the running module 502 is further configured to:

[0070] Create separate threads for running of each module in the SSD firmware, each processing unit of the NAND particles, and host command processing, respectively, to simulate parallel processing among the modules and concurrent processing of each processing unit of the NAND particles; wherein the NAND particle processing units simulate read, write, and erase operations on the NAND particles.

[0071] In one embodiment, as shown in Figure 6 The abnormal power-off simulation implementation device 500 of the solid state disk further comprises a communication module 505, configured to:

[0072] The SSD firmware backend module communicates with each NAND grain processing unit in a message queue manner;

[0073] For each NAND grain processing unit, the SSD firmware backend module has a message queue for sending command messages, and all NAND grain processing units use the same message queue to return command responses to the SSD firmware backend module.

[0074] In an embodiment, the first simulation module 503 is further configured to:

[0075] When the host thread triggers an abnormal power-off, all NAND grain processing unit threads are ended;

[0076] When the NAND grain processing unit thread is ended, if the thread is processing a NAND write or erase request command at this time and the command is not processed, a scenario of an uncompleted NAND write or erase operation in an abnormal power-off can be simulated.

[0077] The specific limitations of the simulation implementation device for the abnormal power-off of the solid state disk can be referred to the limitations of the simulation implementation method for the abnormal power-off of the solid state disk in the foregoing, and will not be described here.

[0078] In an embodiment, a computer device is provided, and an internal structure diagram of the computer device can be as shown in Figure 7 The computer device includes a processor, a memory, and a network interface connected through a system bus. The processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operating system and the computer program in the non-volatile storage medium to run. The network interface of the computer device is configured to communicate with an external terminal through a network connection. The computer program is executed by the processor to implement a simulation implementation method for an abnormal power-off of a solid state disk.

[0079] Those skilled in the art can understand that Figure 7 The structure shown in the figure is only a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the computer device to which the scheme of the present application is applied. The specific computer device can include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0080] In an embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor. The processor implements the steps in each of the above method embodiments when executing the computer program.

[0081] In one embodiment, a computer readable storage medium is provided, having stored thereon a computer program, which, when executed by a processor, implements the steps of any of the above method embodiments.

[0082] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by a computer program instructing related hardware, and the computer program can be stored in a non-volatile computer readable storage medium. When the computer program is executed, the processes of the above-mentioned embodiments can be included. Any reference to memory, storage, database or other medium used in each embodiment provided by the present application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0083] Any combination of the technical features of the above embodiments can be made. In order to make the description simple, all possible combinations of the technical features in the above embodiments are not described, however, as long as the combination of the technical features does not exist, it should be considered as the scope of the present application.

[0084] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, some modifications and improvements can be made, which are all within the scope of the present application. Therefore, the scope of the patent protection of the present application should be subject to the appended claims.

Claims

1. A method for simulating a solid state disk (SSD) abnormal power-off, the method comprising: obtaining a request for simulating the SSD abnormal power-off; simulating, according to the request, running of each module in an SSD firmware and running of each NAND processing unit in a multi-thread mode; when an abnormal power-off is triggered by a test case, ending running of all threads to simulate sudden stop of each module in the SSD firmware and the NAND processing unit and various execution states generated thereby; and when a power-on is triggered by the test case, restarting running of all threads to simulate re-running of each module in the SSD firmware and the NAND processing unit. The step of simulating, according to the request, running of each module in the SSD firmware and running of each NAND processing unit in the multi-thread mode comprises: creating separate threads for running of each module in the SSD firmware, each NAND processing unit and a host command processing to simulate parallel processing among the modules and concurrent processing of each NAND processing unit, wherein the NAND processing unit simulates read, write and erase operations on a NAND. The method further comprises: communicating between a back-end module of the SSD firmware and each NAND processing unit in a message queue mode; for each NAND processing unit, the back-end module of the SSD firmware has a message queue for sending command messages, and all the NAND processing units use a same message queue to return command responses to the back-end module of the SSD firmware. The step of, when the abnormal power-off is triggered by the test case, ending running of all threads to simulate sudden stop of each module in the SSD firmware and the NAND processing unit and various execution states generated thereby further comprises: when the abnormal power-off is triggered by a host thread, all the NAND processing unit threads are ended; and when the NAND processing unit threads are ended, if the threads are processing a NAND write or erase request command and the command is not processed, a scenario of an uncompleted NAND write or erase operation at the abnormal power-off can be simulated. The device for simulating the SSD abnormal power-off comprises: an obtaining module configured to obtain a request for simulating the SSD abnormal power-off; a running module configured to simulate, according to the request, running of each module in an SSD firmware and running of each NAND processing unit in a multi-thread mode; a first simulation module configured to, when an abnormal power-off is triggered by a test case, end running of all threads to simulate sudden stop of each module in the SSD firmware and the NAND processing unit and various execution states generated thereby; and a second simulation module configured to, when a power-on is triggered by the test case, restart running of all threads to simulate re-running of each module in the SSD firmware and the NAND processing unit.

2. The method of claim 1, wherein the method further comprises: The running module is further configured to: ​ 3. The method of claim 2, wherein the method further comprises: ​ ​ ​ 4. The method of claim 3, wherein the method further comprises: ​ ​ ​ 5. A simulation device for abnormal power loss of a solid-state drive, characterized in that, ​ ​ ​ ​ ​ 6. The device for simulating implementation of abnormal power-off of a solid state drive according to claim 5, wherein, ​ Each module in the SSD firmware, each processing unit of the NAND grain and the host command processing are respectively created into separate threads to run to simulate the parallel processing among the modules and the concurrent processing of each processing unit of the NAND grain; wherein the processing unit of the NAND grain simulates the read, write and erase operations on the NAND grain.

7. The device for simulating implementation of abnormal power-off of a solid state drive according to claim 6, characterized in that, The device further comprises a communication module, which is configured to: The SSD firmware backend module communicates with each processing unit of the NAND grain in a message queue mode; For each processing unit of the NAND grain, the SSD firmware backend module has a message queue for sending command messages, and all the processing units of the NAND grain use the same message queue to return command responses to the SSD firmware backend module.

8. The device for simulating implementation of abnormal power-off of a solid state drive according to claim 7, characterized in that, The first simulation module is further configured to: When the host thread triggers an abnormal power-off, all the processing unit threads of the NAND grain are ended; When the processing unit thread of the NAND grain is ended, if the thread is processing a NAND write or erase request command and the command is not processed, the scenario that the NAND write or erase operation is not completed when the abnormal power-off occurs can be simulated.

9. A computer device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor executes the computer program to implement the steps of the method in any one of claims 1 to 4.

10. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the method in any one of claims 1 to 4.

Images