LDMOS device and method of manufacturing the same

Abstract

The application provides an LDMOS device and a manufacturing method thereof, a side wall with stepped side walls is formed on the sidewall of a field oxide layer, and a field plate with a stepped part is formed based on the side wall with the stepped side walls, the surface electric field of a drift region near the field oxide layer can be further optimized by the stepped part of the field plate, the side wall with the stepped side walls can avoid the polycrystal silicon at the bottom of the drift region from being broken down, more effective RESURF results are provided, and higher breakdown voltage and lower on-resistance can be realized. In addition, the side wall with the stepped side walls is manufactured by using a corresponding etching process in each direction of a plurality of stacked dielectric layers, the process is simple, and is self-aligned, and no overlay dimension is needed.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing technology, and in particular to an LDMOS device and its manufacturing method. Background Technology

[0002] Laterally diffused metal-oxide transistors (LDMOS) have advantages such as high voltage withstand capability, high gain, and low distortion, and are more compatible with complementary metal-oxide transistor (CMOS) processes, thus they are widely used in integrated circuits.

[0003] For LDMOS devices, a high breakdown voltage (BV) and low on-resistance (Rsp) are required. The mainstream approach is to improve the breakdown voltage using RESURF (Reduced Surface Field) technology. For details, please refer to... Figure 1 After forming a well region 101 in the substrate 100, a drain drift region 102 is added to the substrate 100, and a mask layer is added for material deposition, photolithography, and etching. A ROX (RESURF oxide) structure 103 is formed on the surface of the drain drift region 102. Then, a gate oxide (GOX, not shown) and polysilicon are deposited. The ROX structure 103 allows the polysilicon to extend laterally from the channel to the drain drift region 102. After further etching of the polysilicon and the gate oxide, a field plate 104 is formed. The field plate changes the electric field distribution of the drain drift region and does not break down at the bottom of the polysilicon, thus achieving a higher breakdown voltage. Summary of the Invention

[0004] The purpose of this invention is to provide an LDMOS device and its manufacturing method, which can achieve better RESURF effect, thereby increasing the breakdown voltage of the device and reducing the on-resistance.

[0005] To achieve the above objectives, the present invention provides a method for manufacturing an LDMOS device, comprising:

[0006] A substrate is provided, and a field oxide layer is formed on a portion of the substrate;

[0007] Conformal deposition of multiple dielectric layers on the field oxide layer and its exposed substrate;

[0008] The multilayer dielectric layers are sequentially anisotropically etched to form sidewalls formed by stacking the multilayer dielectric layers on the sidewalls of the field oxide layer.

[0009] Remove the upper medium layer in the sidewall to form a stepped sidewall;

[0010] A conformal deposition of a polycrystalline silicon layer is performed on the field oxide layer, the sidewalls, and the substrate surrounding the sidewalls;

[0011] The excess polysilicon layer is etched away to form a field electrode plate with a stepped portion, the stepped portion of the field electrode plate covering the stepped sidewall and extending continuously to the top of a portion of the field oxide layer.

[0012] Optionally, the method for manufacturing the LDMOS device further includes, before forming the field oxide layer on a portion of the substrate, or after forming the field electrode:

[0013] Ion implantation is performed on a portion of the substrate to form a well region of a first conductivity type;

[0014] Ion implantation is performed on a portion of the substrate outside the well region to form a drift region of a second conductivity type.

[0015] Optionally, the multilayer dielectric layer includes a first dielectric layer, a second dielectric layer, and a third dielectric layer stacked sequentially from bottom to top, wherein the material of the second dielectric layer is different from that of the first dielectric layer and the third dielectric layer, and the third dielectric layer is the upper dielectric layer.

[0016] Optionally, the step of sequentially performing anisotropic etching on the multilayer dielectric layers to form the sidewalls includes:

[0017] Using the second dielectric layer as the etching stop layer, anisotropic etching is performed on the third dielectric layer to form a first sidewall on the top sidewall of the second dielectric layer.

[0018] Using the first dielectric layer as the etching stop layer, the second dielectric layer is anisotropically etched to form a second sidewall whose sidewall is aligned with the first sidewall.

[0019] Optionally, during the process of anisotropically etching the second dielectric layer to form the second sidewall, the first sidewall is simultaneously anisotropically etched to thin the first sidewall, such that the top of the first sidewall and the top of the second sidewall are flush and not higher than the top of the first dielectric layer on the top of the field oxide layer.

[0020] Optionally, the step of removing the upper dielectric layer in the sidewall to form a stepped sidewall includes: removing the first dielectric layer exposed in the first sidewall and the second sidewall.

[0021] The method for manufacturing the LDMOS device further includes: forming a gate dielectric layer after forming the stepped sidewalls and before conformally depositing a polysilicon layer, the gate dielectric layer being in contact with the sidewalls and covering a portion of the substrate surrounding the sidewalls.

[0022] Optionally, the step of removing the upper dielectric layer in the sidewall to form a stepped sidewall includes: removing the first sidewall and retaining the first dielectric layer;

[0023] The method for manufacturing the LDMOS device further includes: after etching away excess polysilicon layer to form a field electrode plate with stepped portion, using the field electrode plate and the second sidewall as a mask, etching away excess first dielectric layer, wherein the first dielectric layer between the field electrode plate and the substrate is used as a gate dielectric layer.

[0024] Based on the same inventive concept, the present invention also provides an LDMOS device, comprising:

[0025] Substrate;

[0026] A field oxide layer is formed on a portion of the substrate;

[0027] A sidewall with stepped sidewalls, the sidewalls being formed on the sidewalls of the field oxide layer;

[0028] A field electrode plate having a stepped portion, the stepped portion of the field electrode plate covering the stepped sidewall and continuously extending to the top of a portion of the field oxide layer.

[0029] Optionally, the sidewall includes a first medium layer and a second medium layer stacked sequentially from bottom to top, wherein the material of the second medium layer is different from that of the first medium layer.

[0030] Optionally, the first dielectric layer also extends laterally from the bottom of the stepped sidewall to between the field electrode and the substrate at the periphery of the sidewall, to serve as a gate dielectric layer;

[0031] Alternatively, the outer wall of the first dielectric layer is aligned with the outer wall of the second dielectric layer, and the LDMOS device further includes a gate dielectric layer, which is connected to the sidewall and located between the field plate and a portion of the substrate surrounding the sidewall.

[0032] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0033] 1. A sidewall with stepped sidewalls is formed on the sidewall of the field oxide layer. By utilizing the gradual thickness change of the sidewall with stepped sidewalls, the electric field strength at the interface between the thicker field oxide layer in the drift region and the thinner gate dielectric layer around the sidewall can be reduced, thereby improving the breakdown voltage of the device.

[0034] 2. The polycrystalline silicon field electrode forms a stepped portion by conformally covering the stepped sidewall, thereby utilizing the stepped portion of the field electrode to further optimize the surface electric field of the drift region near the field oxide layer. Furthermore, the sidewall with the stepped sidewall can prevent the polycrystalline silicon from breaking down at the bottom of the drift region, providing a more effective RESURF result, and thus achieving higher breakdown voltage and lower on-resistance.

[0035] 3. Using multi-layered dielectric layers for corresponding anisotropic etching processes to fabricate sidewalls with stepped sidewalls is a simple and self-aligning process that does not require overlay dimensions. Compared to directly etching the sidewalls of the field oxide layer to shape them into stepped sidewalls, it avoids the formation of birdbeak structures between the field oxide layer and the polysilicon layer, thus preventing the tip effect problem. It is suitable for the fabrication of 6V~300V LDMOS devices. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of the cross-sectional structure of an existing LDMOS device.

[0037] Figure 2 A schematic flowchart illustrating the manufacturing method of an LDMOS device according to a specific embodiment of the present invention.

[0038] Figures 3 to 12 This is a cross-sectional structural diagram of the manufacturing method of the LDMOS device according to a specific embodiment of the present invention. Detailed Implementation

[0039] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid confusion with the invention. It should be understood that the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make the disclosure thorough and complete, and to fully convey the scope of the invention to those skilled in the art. The same reference numerals denote the same elements throughout. It should be understood that when a layer is referred to as being formed on other layers, it may be formed directly on the other layers, or an intervening film layer may be present. The terms “upper,” “lower,” “top,” “bottom,” “inner,” “middle,” “longitudinal,” and “lateral,” etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are used only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. “Longitudinal” can be understood as a direction perpendicular to the substrate surface, and “lateral” can be understood as a direction parallel to the substrate surface. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term “comprising” is used to determine the presence of possible features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items. The terms “identical” and “consistent” include the meaning of being completely equal and identical, and may also include the meaning of being approximately identical or approximately equal within permissible process tolerances. The terms "first," "second," etc., used in this specification are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronological sequence. It should be understood that these terms, used so in this way, may be replaced where appropriate, for example, to allow embodiments of the invention described herein to operate in a different order than that described or shown herein. Similarly, if the methods described herein comprise a series of steps, and the order of these steps presented herein is not necessarily the only possible order in which these steps can be performed, and some described steps may be omitted and / or some other steps not described herein may be added to the method. If a component in one figure is identical to a component in another figure, although these components are readily identifiable in all figures, this specification will not label all identical components in every figure for the sake of clarity.

[0040] The technical solution proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0041] Please refer to Figures 2 to 12 An embodiment of the present invention provides a method for manufacturing an LDMOS device, comprising:

[0042] S1, providing a substrate, forming a field oxide layer on a portion of the substrate;

[0043] S2, conformal deposition of a multilayer dielectric layer on the field oxide layer and its exposed substrate;

[0044] S3, sequentially perform anisotropic etching on the multilayer dielectric layers to form a sidewall formed by stacking the multilayer dielectric layers on the sidewall of the field oxide layer;

[0045] S4, Remove the upper medium layer in the sidewall to form a stepped sidewall;

[0046] S5, a polycrystalline silicon layer is deposited conformally on the field oxide layer, the sidewall, and the substrate surrounding the sidewall;

[0047] S6, Etch away excess polysilicon layer to form a field electrode plate with stepped portion, the stepped portion of the field electrode plate covering the stepped sidewall and extending continuously to the top of a portion of the field oxide layer.

[0048] Please refer to Figure 3 The substrate 200 provided in step S1 can be any suitable substrate material, such as silicon, silicon-on-insulator, germanium, silicon carbide, silicon germanide, etc., or a substrate material on which a semiconductor epitaxial layer such as silicon carbide is epitaxially grown. The conductivity type of the substrate is, for example, the second conductivity type.

[0049] In step S1, a drift region 204 is further formed in the substrate 200, and a field oxide layer 205 is formed on a portion of the drift region 204. The specific process includes the following steps:

[0050] S1.1, please refer to Figure 3 A photoresist (PR) layer 201 is coated on the substrate 200. The photoresist layer 201 is photolithographically etched (including exposure and development) to expose the surface of a portion of the substrate 200 (i.e. the area to be formed as the well region 202). Then, using the photolithographically etched photoresist layer 201 as a mask, ion implantation is performed on the exposed area of ​​the substrate 200 to form a well region 202 of the first conductivity type.

[0051] S1.2, please refer to Figure 4 The photoresist layer 201 is removed, and a photoresist material is recoated on the substrate 200 to form a photoresist layer 203. The photoresist layer 203 is photolithographically etched (including exposure and development) to mask the well region 202 and expose a portion of the substrate 200 outside the well region 202 (i.e., the region where the drift region 204 is to be formed). Then, using the photolithographically etched photoresist layer 203 as a mask, ion implantation is performed on the exposed area of ​​the substrate 200 to form a drift region 204 of the second conductivity type, which serves as the voltage withstand region of the LDMOS device.

[0052] S1.3, please refer to Figure 5 The photoresist layer 203 is removed, and an oxide layer (e.g., silicon oxide) is deposited on the surface of the substrate 200 by a suitable deposition process such as chemical vapor deposition. The deposited oxide layer covers the surfaces of the well region 202 and the drift region 204. A photoresist (not shown) is coated and photolithographically etched on the photoresist using a mask layer. Using the photolithographically etched photoresist layer as a mask, the oxide layer is etched until the surfaces of the well region 202 and the drift region 204 are exposed, forming a field oxide layer (ROX) 205 on a portion of the surface of the drift region 204.

[0053] In steps S1.1 and S1.2, annealing can be performed during ion implantation, or annealing can be performed after ion implantation in step S1.2, so that the implanted ions in the well region 202 and the drift region 204 diffuse to the required extent in both the lateral and longitudinal directions. In the longitudinal direction, the depth of the drift region 204 can be equal to, greater than, or less than the depth of the well region 202; in the lateral direction, the drift region 204 can be connected to or spaced apart from the well region 202.

[0054] As an example, both the substrate 200 and the well region 202 are of a first conductivity type, specifically P-type, and the second conductivity type is N-type. In other embodiments of the invention, the first conductivity type may be N-type, and the second conductivity type may be P-type.

[0055] Furthermore, the ion doping concentrations of drift region 204 and well region 202, as well as the film thickness of field oxide layer 205, need to be rationally designed based on the breakdown voltage and on-resistance requirements of the LDMOS device. For example, the film thickness of field oxide layer 205 (i.e., the deposition thickness of the oxide layer) is...

[0056] Please refer to Figure 6In step S2, a first dielectric layer 206, a second dielectric layer 207, and a third dielectric layer 208 are sequentially deposited on the substrate 200 using a suitable process such as chemical vapor deposition. The first dielectric layer 206, the second dielectric layer 207, and the third dielectric layer 208 are all conformally covered on the surfaces of the well region 202, the field oxide layer 205, and the drift region 204. Thus, the first dielectric layer 206, the second dielectric layer 207, and the third dielectric layer 208 form steps (or staircases) as they extend continuously from the top of the well region 202 to the top of the field oxide layer 205.

[0057] In this embodiment, the first dielectric layer 206 and the third dielectric layer 208 are made of the same material, while the second dielectric layer 207 is made of a different material than the first dielectric layer 206 and the third dielectric layer 208. The thickness of the first dielectric layer 206 is less than the thickness of the second dielectric layer 207 and the third dielectric layer 208, respectively, and serves as a protective layer for the surfaces of the trap region 202 and the drift region 204, as well as a stop layer during the etching of the second dielectric layer 207, while also shortening the process time during subsequent etching removal. As an example, the first dielectric layer 206 and the third dielectric layer 208 are both made of silicon dioxide, and the second dielectric layer 207 is made of silicon nitride. The thicknesses of the first dielectric layer 206, the second dielectric layer 207, and the third dielectric layer 208 are respectively...

[0058] In step S3, firstly, please refer to... Figure 7 Using the second dielectric layer 207 as the etching stop layer, anisotropic etching (i.e., sidewall etching) is performed on the third dielectric layer 208 to remove the third dielectric layer 208 above the top of the field oxide layer 205 and most of the third dielectric layer 208 around the sidewall of the field oxide layer 205 (including the third dielectric layer 208 above the well region 202 and part of the drift region 204). The remaining third dielectric layer 208 is retained on the top sidewall of the second dielectric layer 207, forming the first sidewall 208a. Next, please refer to... Figure 7 and Figure 8 Using the first sidewall 208a as a mask and the first dielectric layer 206 as an etch stop layer, anisotropic etching (i.e., sidewall etching) is performed on the second dielectric layer 207 to remove the second dielectric layer 207 above the top of the field oxide layer 205 and most of the second dielectric layer 207 around the sidewall of the field oxide layer 205 (including the second dielectric layer 207 above the well region 202 and part of the drift region 204) to form a second sidewall 207a aligned with the first sidewall 208b. Thus, the first sidewall 208b and the second sidewall 207a form the sidewall of the field oxide layer 205. The first dielectric layer 206 protects the surface of the substrate 200, including the well region 202 and the drift region 204, during this process.

[0059] In this embodiment, during the etching of the second dielectric layer 207 to form the second sidewall 207a, by selecting a reasonable etchant, the etching process can thin the first sidewall 208a, reducing its top height and lateral width. The remaining first sidewall 208a is eventually thinned into the first sidewall 208b. The remaining second dielectric layer 207 not only has its sidewalls aligned with the first sidewall 208b, but its top is also aligned with the first sidewall 208b, preventing the top height of the sidewall from exceeding the surface of the first dielectric layer 206 on top of the oxide layer 205. At the same time, since the thickness of the remaining first sidewall 208b is relatively close to the film thickness of the first dielectric layer 206, the first dielectric layer 206 exposed by the first sidewall 208b and the second sidewall 207a can be removed in the subsequent step S4, simplifying the process.

[0060] In step S4, please refer to Figure 8 and Figure 9 Suitable etching processes, such as dry etching (anisotropic etching) or wet etching (isotropic etching), can be used to remove the first dielectric layer 206 exposed by the first sidewall 208b and the second sidewall 207a in one pass. This forms a sidewall consisting of the second sidewall 207a and the remaining first dielectric layer 206a below it. The sidewall has a stepped sidewall, which is composed of the surface of the second sidewall 207a exposed after the removal of the first sidewall 208b and the sidewall originally exposed by the first sidewall 208b. That is, the second sidewall 207a is approximately "L"-shaped, and the vertical portion 207b adjacent to the sidewall of the field oxide layer 205 has a longitudinal film thickness d2 that is greater than the longitudinal film thickness d1 of the horizontal portion 207c extending laterally outward from the bottom of this portion.

[0061] It should be noted that the etching processes in steps S3 and S4 are self-aligned, requiring no additional mask and no overlay dimensions. The process is simple, and compared to the method of directly etching the sidewalls of the field oxide layer to shape them into stepped sidewalls, it does not cause the field oxide layer to produce a bird's beak structure, thus avoiding the problem of tip effect.

[0062] In step S5, please refer to Figure 9 and Figure 10 First, a gate dielectric layer (GOX) 209 is grown on the well region 202 and the drift region 204 through a thermal oxidation process. Then, a polysilicon layer 210 is deposited on the gate dielectric layer 209 and the exposed sidewalls and field oxide layer 205 through processes such as chemical vapor deposition. The deposited polysilicon layer 210 forms a stepped portion 210a by conformally covering the stepped sidewalls of the sidewalls.

[0063] The thickness of the gate dielectric layer 209 is less than the superposition of the thickness of the horizontal portion 207c of the second sidewall 207a and the thickness of the first dielectric layer 206, so as to ensure that when the polysilicon layer 210 can extend from the surface of the gate dielectric layer 209 to the top surface of the horizontal portion 207c of the second sidewall 207a, it can also form a stepped shape (i.e., a first step constituting the stepped portion 210a).

[0064] In step S6, please continue to refer to Figure 9 and Figure 10 The excess polysilicon layer 210 and the gate dielectric layer 209 below it are etched away. The remaining polysilicon layer 210 is located above the well region 202 and extends laterally to the bottom of the sidewall of the sidewall. The gate dielectric layer 209 is sandwiched between the well region 202 and the corresponding drift region 204, forming the gate (unmarked) of the LDMOS device. The other part is connected to the gate and extends along the stepped sidewall of the sidewall and laterally to the top of the field oxide layer 205, forming a field plate (unmarked) with a stepped portion 210a.

[0065] Next, please refer to Figure 11 The LDMOS device manufacturing method of this embodiment allows for subsequent conventional processes after the formation of the field electrode to complete the manufacturing of the LDMOS device. For example, it includes: first, performing source / drain ion implantation on the well region 202 on one side of the polysilicon layer 210 and the drift region 204 on the other side to form a source region 212 in the well region 202 and a drain region 213 in the drift region 204, both of which are of the second conductivity type; then, performing body ion implantation on the well region 202 outside the source region 212 to form a body region 211 of the first conductivity type; subsequently, performing a high-temperature annealing treatment between 800°C and 1000°C to fully activate the ions (i.e., impurities) in the substrate 200; next, depositing an interlayer dielectric layer and performing contact hole photolithography and etching to form gate contact holes, source contact holes, and drain contact holes; further depositing metal to fill the contact holes and form metal wiring, etc.

[0066] The LDMOS device manufacturing method of this embodiment forms a sidewall that is self-aligned with the sidewall of the field oxide layer by depositing and etching multiple dielectric layers on the sidewall of the field oxide layer. It is desirable that the sidewall has a stepped sidewall, thereby forming a field electrode plate with a stepped portion through the sidewall with the stepped sidewall. Then, the electric field distribution in the drift region is optimized by using the field electrode plate to improve the breakdown voltage of the device. Under the condition of having the same breakdown voltage as existing LDMOS devices, the on-resistance of the device can be reduced, and the process is simple and easy to implement.

[0067] It should be understood that the technical solution of the present invention is not limited to the manufacturing method of the LDMOS device in the above embodiments. Those skilled in the art can make any reasonable modifications based on the above embodiments to obtain other embodiments of the present invention.

[0068] For example, in another embodiment of the invention, in step S1, before depositing the oxide material for forming the field oxide layer 205, the drift region 204 is formed first, and then the trap region 202 is formed.

[0069] For example, in another embodiment of the present invention, before depositing the oxide material for forming the field oxide layer 205 in step S1, the well region 202 and the drift region 204 are not formed first, but after the field electrode is formed in step S6, the well region 202 and the drift region 204 are formed in the substrate 200.

[0070] For example, in other embodiments of the present invention, in step S6, a gate dielectric layer 209 is formed by a deposition process, and after etching the polysilicon layer 210 to form a field electrode, the gate dielectric layer is further etched to remove excess gate dielectric layer 209. The remaining gate dielectric layer is covered by the remaining polysilicon layer 210, that is, a portion of the remaining gate dielectric layer covers the surface of the sidewall and extends to the top of a portion of the field oxide layer 205.

[0071] For example, in yet another embodiment of the invention, please refer to Figure 12 In step S2, the first dielectric layer 206 and the third dielectric layer 207 deposited are made of different materials, and the deposited first dielectric layer 206 can be used as a subsequent gate dielectric layer. Therefore, in step S4, the first dielectric layer 206 is retained when the first sidewall 208b is removed. After etching the polysilicon layer 210 in step S6, the first dielectric layer 206 is etched using the remaining polysilicon layer 210 as a mask. The remaining first dielectric layer 206 is covered by the remaining polysilicon layer 210 and the second sidewall 207a. That is, the portion of the remaining first dielectric layer 206 directly sandwiched between the polysilicon layer 210 and the substrate 200 is used as the gate dielectric layer 206b between the gate and the substrate 200, and the other portion is directly covered by the second sidewall 207a and used as part of the sidewall 206a.

[0072] Based on the same inventive concept, one embodiment of the present invention also provides an LDMOS device, which can be formed using the manufacturing method of the LDMOS device described in any of the above embodiments. Please refer to [link / reference]. Figure 11 The LDMOS device includes a substrate 200, a field oxide layer 205, sidewalls with stepped sidewalls, and a field electrode with stepped portions. The materials used for the substrate 200, field oxide layer 205, sidewalls with stepped sidewalls, and field electrode with stepped portions are as described above and will not be repeated here.

[0073] A well region 202 of a first conductivity type and a drift region 204 of a second conductivity type are formed in the substrate 200. A body region 211 of a first conductivity type and a source region 212 of a second conductivity type are formed in the well region 202, and a drain region 213 of a second conductivity type is formed in the drift region 204.

[0074] A field oxide layer 205 is formed on a portion of the drift region 204 and exposes the leak region 213.

[0075] The sidewall with stepped sidewalls includes a first dielectric layer 206a (i.e., the bottom sidewall) and a second dielectric layer (i.e., the second sidewall 207a mentioned above) that are sequentially stacked on the sidewall of the field oxide layer 205.

[0076] The stepped portion of the field electrode plate covers the stepped sidewall of the sidewall and extends continuously to the top of part of the field oxide layer 205.

[0077] The LDMOS device in this embodiment also has a gate, which is formed with the same polysilicon layer as the field plate. The gate extends laterally from the side of the field plate away from the drain region 213 to the top of a portion of the well region 202. A gate dielectric layer 209 is sandwiched between the gate, the well region 202, and the drift region 204.

[0078] As an example, the gate dielectric layer 209 and the first dielectric layer 206a are formed using the same dielectric layer. In other words, the first dielectric layer also extends laterally from the bottom of the stepped sidewall to the space between the field plate and the substrate at the periphery of the sidewall, so as to serve as the gate dielectric layer.

[0079] As another example, the gate dielectric layer 209 and the first dielectric layer 206a are formed using different film layers. In this case, the outer wall of the first dielectric layer 206a is aligned with the outer wall of the second dielectric layer, and the gate dielectric layer 209 is in contact with the sidewall and located between the field electrode plate and a portion of the substrate surrounding the sidewall.

[0080] In summary, the LDMOS device and its manufacturing method of the present invention form a sidewall with stepped sidewalls on the sidewalls of the field oxide layer. Utilizing the gradual thickness variation of these stepped sidewalls, the electric field strength at the interface between the thicker field oxide layer in the drift region and the thinner gate dielectric layer around the sidewalls can be reduced, thereby improving the device's breakdown voltage. Simultaneously, the polysilicon field plate, conformally covering the stepped sidewalls, forms a stepped portion, further optimizing the surface electric field of the drift region near the field oxide layer. Furthermore, the stepped sidewalls prevent polysilicon breakdown at the bottom of the drift region, providing a more effective RESURF result, and ultimately achieving higher breakdown voltage and lower on-resistance. Furthermore, using multilayered dielectric layers for corresponding anisotropic etching processes to fabricate sidewalls with stepped sidewalls is a simple and self-aligning process that does not require overlay dimensions. Compared to directly etching the sidewalls of the field oxide layer to shape them into stepped sidewalls, this method avoids the formation of birdbeak structures in the field oxide layer and prevents the tip effect problem. It is suitable for the fabrication of 6V to 300V LDMOS devices.

[0081] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the present invention.

Claims

1. A method for manufacturing an LDMOS device, characterized in that, include: A substrate is provided, and a field oxide layer is formed on a portion of the substrate; Conformal deposition of multiple dielectric layers on the field oxide layer and its exposed substrate; The multilayer dielectric layers are sequentially anisotropically etched to form sidewalls formed by stacking the multilayer dielectric layers on the sidewalls of the field oxide layer. Remove the upper medium layer in the sidewall to form a stepped sidewall; A conformal deposition of a polycrystalline silicon layer is performed on the field oxide layer, the sidewalls, and the substrate surrounding the sidewalls; The excess polysilicon layer is etched away to form a field electrode plate with a stepped portion, the stepped portion of the field electrode plate covering the stepped sidewall and extending continuously to the top of a portion of the field oxide layer.

2. The method for manufacturing an LDMOS device as described in claim 1, characterized in that, Before forming the field oxide layer on a portion of the substrate, or after forming the field electrode, the method further includes: Ion implantation is performed on a portion of the substrate to form a well region of a first conductivity type; Ion implantation is performed on a portion of the substrate outside the well region to form a drift region of a second conductivity type.

3. The method for manufacturing an LDMOS device as described in claim 1, characterized in that, The multilayer dielectric layer includes a first dielectric layer, a second dielectric layer, and a third dielectric layer stacked sequentially from bottom to top. The material of the second dielectric layer is different from that of the first dielectric layer and the third dielectric layer. The third dielectric layer is the upper dielectric layer.

4. The method for manufacturing an LDMOS device as described in claim 3, characterized in that, The step of sequentially performing anisotropic etching on the multilayer dielectric layers to form the sidewalls includes: Using the second dielectric layer as the etching stop layer, anisotropic etching is performed on the third dielectric layer to form a first sidewall on the top sidewall of the second dielectric layer. Using the first dielectric layer as the etching stop layer, the second dielectric layer is anisotropically etched to form a second sidewall whose sidewall is aligned with the first sidewall.

5. The method for manufacturing an LDMOS device as described in claim 4, characterized in that, During the process of anisotropically etching the second dielectric layer to form the second sidewall, the first sidewall is simultaneously anisotropically etched to thin it so that the top of the first sidewall is flush with the top of the second sidewall and not higher than the top of the first dielectric layer on the top of the field oxide layer.

6. The method for manufacturing an LDMOS device as described in claim 4, characterized in that, The step of removing the upper dielectric layer in the sidewall to form a stepped sidewall includes: removing the first dielectric layer exposed in the first sidewall and the second sidewall; The method for manufacturing the LDMOS device further includes: forming a gate dielectric layer after forming the stepped sidewalls and before conformally depositing a polysilicon layer, the gate dielectric layer being in contact with the sidewalls and covering a portion of the substrate surrounding the sidewalls.

7. The method for manufacturing an LDMOS device as described in claim 4, characterized in that, The step of removing the upper medium layer in the sidewall to form a stepped sidewall includes: removing the first sidewall and retaining the first medium layer; The method for manufacturing the LDMOS device further includes: after etching away excess polysilicon layer to form a field electrode plate with stepped portion, using the field electrode plate and the second sidewall as a mask, etching away excess first dielectric layer, wherein the first dielectric layer between the field electrode plate and the substrate is used as a gate dielectric layer.

8. An LDMOS device, characterized in that, It is formed using the manufacturing method of an LDMOS device as described in any one of claims 1-7, and includes: Substrate; A field oxide layer is formed on a portion of the substrate; A sidewall with stepped sidewalls, the sidewalls being formed on the sidewalls of the field oxide layer; A field electrode plate having a stepped portion, the stepped portion of the field electrode plate covering the stepped sidewall and continuously extending to the top of a portion of the field oxide layer.

9. The LDMOS device as described in claim 8, characterized in that, The sidewall comprises a first medium layer and a second medium layer stacked sequentially from bottom to top, wherein the material of the second medium layer is different from that of the first medium layer.

10. The LDMOS device as claimed in claim 9, characterized in that, The first dielectric layer also extends laterally from the bottom of the stepped sidewall to between the field electrode and the substrate at the periphery of the sidewall, to serve as a gate dielectric layer; Alternatively, the outer wall of the first dielectric layer is aligned with the outer wall of the second dielectric layer, and the LDMOS device further includes a gate dielectric layer, which is connected to the sidewall and located between the field plate and a portion of the substrate surrounding the sidewall.

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