A power semiconductor module package structure

Abstract

The application discloses a power semiconductor module packaging structure. The structure comprises a first heat sink, a first chip module and a second chip module; the first chip module and the second chip module are symmetrically arranged on the two sides of the first heat sink; the first chip module comprises a first substrate, a first power chip, a second power chip, a first positive power input terminal, a first negative power input terminal and a first phase power output terminal; the second chip module comprises a second substrate, a third power chip, a fourth power chip, a second positive power input terminal, a second negative power input terminal and a second phase power output terminal; the first substrate, the first power chip, the second power chip, the first positive power input terminal, the first negative power output terminal and the first phase power output terminal are symmetrically arranged with the second substrate, the fourth power chip, the third power chip, the second negative power input terminal, the second positive power output terminal and the second phase power output terminal, so that the commutation paths are completely overlapped.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to semiconductor packaging technology, and in particular, to a power semiconductor module packaging structure. BACKGROUND

[0002] The semiconductor power module packaging technology is mainly developing towards small size and large power. At present, the conventional power module packaging adopts the way of arranging multiple chips in plane, which leads to large area of chip circuit commutation loop, large stray inductance parameter, easy to cause large voltage and current overshoot in switching process, poor device safety, large loss and poor EMC performance, especially for SiC devices, the switching characteristic is hard, the voltage overshoot is more serious, and the electromagnetic interference problem is serious. SUMMARY

[0003] The present application provides a power semiconductor module packaging structure, so that the commutation path is completely overlapped, thereby reducing the stray inductance parameter of the power semiconductor module and improving the switching safety of the module.

[0004] Embodiments of the present application provide a power semiconductor module packaging structure, which comprises:

[0005] A first heat sink, the first heat sink comprising a first surface and a second surface arranged oppositely;

[0006] A first chip module, the first chip module being arranged on one side of the first surface of the first heat sink, the first chip module comprising a first substrate, a first power chip, a second power chip, a first positive power input terminal, a first negative power output terminal and a first phase power output terminal, the first substrate comprising a first electrode part, a second electrode part and a third electrode part, one end of the first electrode part being welded to the first positive power input terminal, one end of the second electrode part being welded to the first negative power input terminal, one end of the third electrode part being welded to the first phase power output terminal, the first power chip being welded to the first electrode part, the second power chip being welded to the third electrode part, the first power chip being electrically connected to the third electrode part through a binding wire, the second power chip being electrically connected to the second electrode part through a binding wire;

[0007] A second chip module is arranged on the second surface of the first heat sink; the second chip module comprises a second substrate, a third power chip, a fourth power chip, a second positive power input terminal, a second negative power input terminal and a second phase power output terminal; the second substrate comprises a fourth electrode part, a fifth electrode part and a sixth electrode part; one end of the fourth electrode part is welded to the second positive power input terminal; one end of the fifth electrode part is welded to the second negative power input terminal; one end of the sixth electrode part is welded to the second phase power output terminal; the third power chip is welded to the sixth electrode part; the fourth power chip is welded to the fifth electrode part; the third power chip is electrically connected to the fourth electrode part through a binding wire; the fourth power chip is electrically connected to the sixth electrode part through a binding wire.

[0008] The first phase power output terminal is electrically connected to the first phase power output terminal through a load; the third power chip and the second power chip are symmetrically arranged; the fourth power chip and the first power chip are symmetrically arranged.

[0009] Optionally, the first positive power input terminal and the second negative power input terminal have different extension lengths.

[0010] The second positive power input terminal and the first negative power input terminal have different extension lengths.

[0011] The first phase output terminal and the second phase output terminal have different extension lengths.

[0012] Optionally, the third substrate, a second heat sink, a fourth substrate and a third heat sink are further included.

[0013] The third substrate is arranged on the side of the first chip module away from the first heat sink; the second heat sink is arranged on the side of the third substrate away from the first chip module, and the second heat sink covers the first heat sink in the projection part of the first heat sink.

[0014] The fourth substrate is arranged on the side of the second chip module away from the first heat sink; the third heat sink is arranged on the side of the fourth substrate away from the second chip module; the fourth heat sink covers the first heat sink in the projection part of the first heat sink.

[0015] Optionally, the second heat sink comprises a first water-cooled substrate and a first heat dissipation pin; the first water-cooled substrate is arranged between the first heat dissipation pin and the third substrate.

[0016] The third heat dissipation plate comprises a second water-cooled base plate and a second heat dissipation pin; the second water-cooled base plate is arranged between the second heat dissipation pin and the fourth base plate.

[0017] Optionally, the package layer is further included.

[0018] The package layer, the second heat dissipation plate and the third heat dissipation plate form a sealed cavity, and the sealed cavity is filled with a sealing material.

[0019] Optionally, the first heat dissipation plate comprises a first water-cooled flat plate, a heat dissipation cavity and a second water-cooled flat plate; the heat dissipation cavity is arranged between the first water-cooled flat plate and the second water-cooled flat plate.

[0020] Optionally, the first heat dissipation plate comprises a heat dissipation metal plate.

[0021] Optionally, the first power chip, the second power chip, the third power chip and the fourth power chip each comprise a plurality of parallel semiconductor chips.

[0022] Optionally, the first base plate further comprises a first control signal terminal solder joint; the first control signal terminal solder joint is electrically connected to the first power chip and the second power chip through a binding wire.

[0023] The second base plate further comprises a second control signal terminal solder joint; the second control signal terminal solder joint is electrically connected to the third power chip and the fourth power chip through a binding wire.

[0024] Optionally, the first base plate and the second base plate are both double-sided copper-clad ceramic base plates; the third base plate and the fourth base plate are both double-sided copper-clad ceramic base plates.

[0025] The embodiment of the present application is characterized in that one end of the first electrode part in the first substrate is welded with the first positive power input terminal, one end of the second electrode part is welded with the first negative power input terminal, one end of the third electrode part is welded with the first phase power output terminal, the first power chip is welded on the first electrode part, the second power chip is welded on the third electrode part, the first power chip is electrically connected with the third electrode part through the binding wire, the second power chip is electrically connected with the second electrode block through the binding wire, one end of the fourth electrode part in the second substrate is welded with the second positive power input terminal, one end of the fifth electrode part is welded with the second negative power input terminal, one end of the sixth electrode part is welded with the second phase power output terminal, the third power chip is welded on the sixth electrode part, the fourth power chip is welded on the fifth electrode part, the third power chip is electrically connected with the fourth electrode part through the binding wire, the fourth power chip is electrically connected with the sixth electrode part through the binding wire, the first phase power output terminal is electrically connected with the first phase power output terminal through the load, the third power chip and the second power chip are symmetrically arranged, and the fourth power chip and the first power chip are symmetrically arranged, so that the packaging structure adopts the completely symmetrical layout and wiring structure, the switching current path is completely overlapped, the stray inductance parameter of the power semiconductor module is reduced, and the switching safety of the module is improved. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 is a front view and a back view of a power semiconductor module packaging structure provided by the embodiment of the present application;

[0027] Figure 2 is a front view and a back view of a power semiconductor module packaging structure provided by the embodiment of the present application; Figure 1 is a sectional structure schematic view of the power semiconductor module packaging structure along the sectional line AB;

[0028] Figure 3 is an electrical connection schematic view of a power semiconductor module provided by the embodiment of the present application;

[0029] Figure 4 is a front view and a back view of another power semiconductor module packaging structure provided by the embodiment of the present application;

[0030] Figure 5 is a front view and a back view of another power semiconductor module packaging structure provided by the embodiment of the present application; Figure 4 is a sectional structure schematic view of the power semiconductor module packaging structure along the sectional line AB;

[0031] Figure 6 is a whole structure schematic view of a power semiconductor module packaging structure provided by the embodiment of the present application. DETAILED DESCRIPTION

[0032] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0033] Figure 1 These are a front top view and a back top view of a power semiconductor module packaging structure provided in an embodiment of the present invention; Figure 2 It is along Figure 1 A cross-sectional schematic diagram of a power semiconductor module packaging structure with section line AB; as shown. Figure 1 and Figure 2 As shown, the power semiconductor module packaging structure includes: a first heat sink 10; the first heat sink 10 includes a first surface 11 and a second surface 12 disposed opposite to each other; a first chip module 20; the first chip module 20 is disposed on one side of the first surface 11 of the first heat sink 10; the first chip module 20 includes a first substrate 21, a first power chip 22, a second power chip 23, a first positive power input terminal 24, a first negative power input terminal 25, and a first phase power output terminal 26; the first substrate 21 includes a first electrode portion 211, a second electrode portion 212, and a third electrode portion 213; one end of the first electrode portion 211 is soldered to the first positive power input terminal 24; one end of the second electrode portion 212 is soldered to the first negative power input terminal 25; the third electrode portion 213... The first phase power output terminal 26 is soldered to the first electrode portion 211; the first power chip 22 is soldered to the first electrode portion 211; the second power chip 23 is soldered to the third electrode portion 213; the first power chip 22 is electrically connected to the third electrode portion 213 via a bonding wire; the second power chip 23 is electrically connected to the second electrode portion 212 via a bonding wire; optionally, the first substrate 21 is a double-sided copper-clad ceramic substrate; the first substrate 21 also includes a first intermediate ceramic insulating layer 215 and a first copper layer 216; the first intermediate ceramic insulating layer 215 serves to insulate the first electrode portion 211, the second electrode portion 212 and the third electrode portion 213 from the first heat sink 10, and the first copper layer 216 serves to solder the first substrate 21 to the first heat sink 10.

[0034] The second chip module 30 is arranged on the second surface 12 of the first heat dissipation plate 10; the second chip module 30 comprises a second substrate 31, a third power chip 32, a fourth power chip 33, a second positive power input terminal 34, a second negative power input terminal 35 and a second phase power output terminal 36; the second substrate 31 comprises a fourth electrode part 311, a fifth electrode part 312 and a sixth electrode part 313; one end of the fourth electrode part 311 is welded with the second positive power input terminal 34; one end of the fifth electrode part 312 is welded with the second negative power input terminal 35; one end of the sixth electrode part 313 is welded with the second phase power output terminal 36; the third power chip 32 is welded on the sixth electrode part 313; the fourth power chip 33 is welded on the fifth electrode part 312; the third power chip 32 is electrically connected with the fourth electrode part 311 through a binding wire; the fourth power chip 33 is electrically connected with the sixth electrode part 313 through a binding wire; wherein the first phase power output terminal 26 is electrically connected with the first phase power output terminal 36 through a load; the third power chip 32 is symmetrically arranged with the second power chip 23; the fourth power chip 33 is symmetrically arranged with the first power chip 22; optionally, the second substrate 31 is a double-sided copper clad ceramic substrate; the second substrate 31 further comprises a second intermediate ceramic insulating layer 315 and a second copper skin layer 316; the second intermediate ceramic insulating layer 315 plays a role of insulation between the third electrode part 311, the fourth electrode part 312 and the fifth electrode part 313 and the first heat dissipation plate 10; the second copper skin layer 316 plays a role of welding the second substrate 31 on the first heat dissipation plate 10.

[0035] wherein, Figure 3 is an electrical connection diagram of a power semiconductor module provided by an embodiment of the present application, as Figure 3 shown, the power semiconductor module comprises four power switching devices Q1, Q2, Q3 and Q4; the power switching devices Q1, Q2, Q3 and Q4 can be IGBTs or MOSFETs; when the power semiconductor module outputs power, Q1 and Q2 cannot be turned on at the same time, and Q3 and Q4 cannot be turned on at the same time; when Q1 and Q4 are turned on and Q2 and Q3 are turned off, a load flows through a forward current, forming a commutation loop; when Q1 and Q4 are turned off and Q2 and Q3 are turned on, the load flows through a reverse current, forming another commutation loop; thus, the four power switching devices Q1-Q4 work alternately to convert direct current into alternating current. As Figure 1 and Figure 2 shown, the actual diagram of the power semiconductor module and the electrical connection Figure 1When the first positive power input terminal 24 receives the input DC positive input current signal, the first electrode part 211 is welded to the first positive power input terminal 24 at one end, the first power chip 22 is welded to the first electrode part 211, the first power chip 22 is electrically connected to the third electrode part 213 through a binding wire, the third electrode part 213 is welded to the first phase power output terminal 26 at one end, and the first phase power output terminal 26 is electrically connected to the first phase power output terminal 36 through a load. This is equivalent to that the DC positive input current signal is transmitted to the load through the first power chip 22, and the positive input current signal flowing out of the load is transmitted to the second phase power output terminal 36. Meanwhile, the sixth electrode part 313 is welded to the second phase power output terminal 36 at one end, and the fourth power chip 33 is electrically connected to the sixth electrode part 313 through a binding wire. The fourth power chip 33 is welded to the fifth electrode part 312. The fifth electrode part 312 is welded to the second negative power input terminal 35 at one end. Thus, the positive input current signal flowing out of the load is transmitted to the second phase power output terminal 36, and then transmitted to the fourth power chip 33, and finally flows back to the second negative power input terminal 35, thereby forming a forward commutation loop.

[0036] Similarly, when the second positive power input terminal 34 receives the input DC positive input current signal, the fourth electrode part 311 is welded to the second positive power input terminal 34 at one end, the third power chip 32 is electrically connected to the fourth electrode part 311 through a binding wire, the third power chip 32 is welded to the sixth electrode part 313, the sixth electrode part 313 is welded to the second phase power output terminal 36 at one end, and the second phase power output terminal 36 is electrically connected to the first phase power output terminal 26 through a load. This is equivalent to that the DC positive input current signal is transmitted to the load through the third power chip 32, and the positive input current signal flowing out of the load is transmitted to the first phase power output terminal 26. Meanwhile, the third electrode part 213 is welded to the first phase power output terminal 26 at one end, the second power chip 23 is welded to the third electrode part 213, the second power chip 23 is electrically connected to the second electrode part 212 through a binding wire, and the second electrode part 212 is welded to the first negative power input terminal 25 at one end. Thus, the positive input current signal flowing out of the load is transmitted to the first phase power output terminal 26, and then transmitted to the second power chip 23, and finally flows back to the first negative power input terminal 25, thereby forming a negative commutation loop. Thus, the third power chip 32 and the second power chip 23 are symmetrically arranged, the fourth power chip 33 and the first power chip 22 are symmetrically arranged, and the upper and lower layers adopt a completely symmetrical layout structure. The forward commutation loop formed by the fourth power chip 33 and the first power chip 22 and the other negative commutation loop formed by the third power chip 32 and the second power chip 23 completely overlap, thereby reducing the stray inductance parameter of the power semiconductor module and improving the switching safety of the module.

[0037] Optionally, Figure 4is a front view and a back view of another power semiconductor module packaging structure provided by the embodiment of the present application; Figure 5 is a cross-sectional structure of the power semiconductor module packaging structure along the cross-sectional line AB; as shown in Figure 4 Figure 4 and Figure 5 The semiconductor module packaging structure further comprises a third substrate 40, a second heat sink 50, a fourth substrate 60 and a third heat sink 70; the third substrate 40 is arranged on the side of the first chip module 20 away from the first heat sink 10; the second heat sink 50 is arranged on the side of the third substrate 40 away from the first chip module 20; the second heat sink 50 covers the first heat sink 10 in the projection part of the first heat sink 10; the fourth substrate 60 is arranged on the side of the second chip module 30 away from the first heat sink 10; and the third heat sink 70 is arranged on the side of the fourth substrate 60 away from the second chip module 30. The third heat sink 70 covers the first heat sink 10 in the projection part of the first heat sink 10; wherein the third substrate 40 is a double-sided copper-clad ceramic substrate, the third substrate 40 comprises two copper layers and an insulating layer between the two copper layers, a copper layer is arranged on the first surface of the third substrate 40 and used for welding and fixing the first power chip 22 and the second power chip 23, another copper layer is arranged on the second surface of the third substrate 40 and used for welding and fixing the second heat sink 50, and the insulating layer in the third substrate 40 well insulates the first power chip 22, the second power chip 23 and the second heat sink 50. The fourth substrate 60 is also a double-sided copper-clad ceramic substrate, and similarly, the fourth substrate 60 comprises two copper layers and an insulating layer between the two copper layers, a copper layer is arranged on the first surface of the fourth substrate 60 and used for welding and fixing the third power chip 32 and the fourth power chip 33, another copper layer is arranged on the second surface of the fourth substrate 60 and used for fixing and welding the third heat sink 70, and the insulating layer in the fourth substrate 60 well insulates the third power chip 32, the fourth power chip 33 and the third heat sink 70. In addition, the upper and lower double-layer heat dissipation of the second heat sink 50 and the third heat sink 70 can effectively realize the simultaneous heat dissipation of the upper and lower surfaces of the module, the heat dissipation effect is good, and the volume of the module can be effectively reduced.

[0038] Optionally, continuing to refer to Figure 5 The structure further comprises a packaging layer 80; the packaging layer 80, the second heat sink 50 and the third heat sink 70 form a sealed cavity, the sealed cavity is filled with a sealing material, and exemplarily, the sealed cavity is filled with potting epoxy resin to form a complete power semiconductor module.

[0039] Optionally, referring to Figure 4 and Figure 5 ​The second heat dissipation plate 50 comprises a first water-cooled base plate and a first heat dissipation pin; the first water-cooled base plate is arranged between the first heat dissipation pin and the third base plate 40; the third heat dissipation plate 70 comprises a second water-cooled base plate and a second heat dissipation pin; the second water-cooled base plate is arranged between the second heat dissipation pin and the fourth base plate 60. The first water-cooled base plate can be used for welding and fixing the third base plate 40; the second water-cooled base plate can be used for welding and fixing the fourth base plate 60; the first heat dissipation pin and the second heat dissipation pin can increase the contact area with the external cooling liquid, so as to effectively improve the heat dissipation efficiency of the whole module; it can be understood that the structure of the second heat dissipation plate 50 and the third heat dissipation plate 70 can also be other forms, and any heat sink with a weldable flat surface meets the design, and the structure of the second heat dissipation plate 50 and the third heat dissipation plate 70 is not limited here.

[0040] Optionally, as shown in Figure 4 and Figure 5 , the first heat dissipation plate 10 comprises a first water-cooled flat plate, a heat dissipation cavity and a second water-cooled flat plate; the heat dissipation cavity is arranged between the first water-cooled flat plate and the second water-cooled flat plate. The first water-cooled flat plate and the second water-cooled flat plate are respectively used for welding and fixing the first base plate 21 and the second base plate 31; the heat dissipation cavity is used for increasing the contact area with the cooling liquid and improving the heat dissipation efficiency; it can be understood that the structure of the first heat dissipation plate can also be other forms, and any heat sink with a weldable flat surface meets the design, and the structure of the first heat dissipation plate is not limited here.

[0041] Optionally, as shown in Figure 4 , the first heat dissipation plate 10 comprises a heat dissipation metal plate, which can be directly welded on the first base plate 21 and the second base plate 31. The heat dissipation metal plate can play a role of heat dissipation, and can also effectively reduce the volume of the module.

[0042] Optionally, Figure 6 is a whole structure schematic diagram of a power semiconductor module packaging structure provided by an embodiment of the present application, referring to Figure 2 and Figure 6The extension length of the first positive power input terminal 24 is different from that of the second negative power input terminal 35; the extension length of the second positive power input terminal 25 is different from that of the first negative power input terminal 34; and the extension length of the first phase output terminal 26 is different from that of the second phase output terminal 36. The first positive power input terminal 24 and the second negative power input terminal 35 are arranged in a stack, and the extension length of the second negative power input terminal 35 is greater than that of the first positive power input terminal 24; the second positive power input terminal 25 and the first negative power input terminal 34 are arranged in a stack, and the extension length of the first negative power input terminal 34 is greater than that of the second positive power input terminal 25; and the first phase output terminal 26 and the second phase output terminal 36 are arranged in a stack, and the extension length of the second phase output terminal 36 is greater than that of the first phase output terminal 26. In this way, the lower second negative power input terminal 35, the first negative power input terminal 34 and the second phase output terminal 36 and the upper first positive power input terminal 24, the second positive power input terminal 25 and the first phase output terminal 26 can be welded with the external copper bar at the same time, thereby improving the welding efficiency of the module and the external copper bar.

[0043] In addition, the first positive power input terminal 24 and the second negative power input terminal 35 are arranged in a longitudinal vertical manner; the second positive power input terminal 25 and the first negative power input terminal 34 are arranged in a longitudinal vertical manner; and the first phase output terminal 26 and the second phase output terminal 36 are arranged in a longitudinal vertical manner. In this way, the positive and negative currents completely overlap, so that the connection stray inductance parameter with the external motor and the capacitor is also as small as possible.

[0044] Optionally, as shown in Figure 1 , the first power chip 22, the second power chip 23, the third power chip 32 and the fourth power chip 33 each include a plurality of parallel semiconductor chips. The number of parallel semiconductor chips of each power chip can be set according to actual power needs. The parallel arrangement of the plurality of semiconductor chips can improve the scalability of the power. In addition, the uniform arrangement of the semiconductor chips is conducive to improving the consistency of the switching characteristics of the entire module.

[0045] Optionally, as shown in Figure 1 , 3 and 4, the first substrate 21 further includes a first control signal terminal solder joint 27; the first control signal terminal solder joint 27 is electrically connected to the first power chip 22 and the second power chip 23 through a binding wire; the second substrate 31 further includes a second control signal terminal solder joint 37; the second control signal terminal solder joint 37 is electrically connected to the third power chip 32 and the fourth power chip 33 through a binding wire.

[0046] The first control signal terminal solder joint 27 and the second control signal terminal solder joint 37 can receive control signals, so that the power device is in an open or closed state; in the actual layout, the first control signal terminal solder joint 27 and the second control signal terminal solder joint 37 are arranged in a row and concentrated on one side, so that the control lines are conveniently led out.

[0047] It should be noted that the above only describes the preferred embodiments of the present application and the principles of the applied technology. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and that various obvious changes, re-adjustments and substitutions can be made by those skilled in the art without departing from the scope of the present application. Therefore, although the present application has been described in more detail through the above embodiments, the present application is not limited to the above embodiments, and can include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the appended claims.

Claims

1. A power semiconductor module package structure, characterized by, The utility model relates to a chip module and a heat dissipation device, and relates to the technical field of chip module and heat dissipation device. It comprises: A first heat dissipation plate; The first heat dissipation plate comprises a first surface and a second surface arranged oppositely; A first chip module; The first chip module is arranged on one side of the first surface of the first heat dissipation plate; the first chip module comprises a first substrate, a first power chip, a second power chip, a first positive power input terminal, a first negative power output terminal and a first phase power output terminal; the first substrate comprises a first electrode part, a second electrode part and a third electrode part; one end of the first electrode part is welded to the first positive power input terminal; one end of the second electrode part is welded to the first negative power input terminal; one end of the third electrode part is welded to the first phase power output terminal; the first power chip is welded to the first electrode part; the second power chip is welded to the third electrode part; the first power chip is electrically connected to the third electrode part through a binding wire; the second power chip is electrically connected to the second electrode part through a binding wire; A second chip module; The second chip module is arranged on one side of the second surface of the first heat dissipation plate; the second chip module comprises a second substrate, a third power chip, a fourth power chip, a second positive power input terminal, a second negative power input terminal and a second phase power output terminal; the second substrate comprises a fourth electrode part, a fifth electrode part and a sixth electrode part; one end of the fourth electrode part is welded to the second positive power input terminal; one end of the fifth electrode part is welded to the second negative power input terminal; one end of the sixth electrode part is welded to the second phase power output terminal; the third power chip is welded to the sixth electrode part; the fourth power chip is welded to the fifth electrode part; the third power chip is electrically connected to the fourth electrode part through a binding wire; the fourth power chip is electrically connected to the sixth electrode part through a binding wire; Wherein, the first phase power output terminal is electrically connected to the second phase power output terminal through a load; the third power chip and the second power chip are symmetrically arranged; the fourth power chip and the first power chip are symmetrically arranged; The extension length of the first positive power input terminal is different from that of the second negative power input terminal; The extension length of the second positive power input terminal is different from that of the first negative power input terminal; 2. The power semiconductor module package structure according to claim 1, characterized by, The extension length of the first phase power output terminal is different from that of the second phase power output terminal. It further comprises: A third substrate, a second heat dissipation plate, a fourth substrate and a third heat dissipation plate; The third substrate is arranged on the side of the first chip module away from the first heat dissipation plate; The second heat dissipation plate is arranged on the side of the third substrate away from the first chip module, and the second heat dissipation plate covers the first heat dissipation plate in the projection part of the first heat dissipation plate; The fourth substrate is arranged on the side of the second chip module away from the first heat dissipation plate; The third heat dissipation plate is arranged on the side of the fourth substrate away from the second chip module; the third heat dissipation plate covers the first heat dissipation plate in the projection part of the first heat dissipation plate.

3. The power semiconductor module package structure according to claim 2, characterized by, The second heat dissipation plate comprises a first water-cooled base plate and a first heat dissipation pin; the first water-cooled base plate is arranged between the first heat dissipation pin and the third base plate; The third heat dissipation plate comprises a second water-cooled base plate and a second heat dissipation pin; the second water-cooled base plate is arranged between the second heat dissipation pin and the fourth base plate.

4. The power semiconductor module package structure according to claim 2, characterized by, Further comprising: a packaging layer; The packaging layer, the second heat dissipation plate and the third heat dissipation plate form a sealed cavity, and the sealed cavity is filled with a sealing material.

5. The power semiconductor module package structure according to claim 1, characterized by, The first heat dissipation plate comprises a first water-cooled flat plate, a heat dissipation cavity and a second water-cooled flat plate; the heat dissipation cavity is arranged between the first water-cooled flat plate and the second water-cooled flat plate.

6. The power semiconductor module package structure of claim 1, wherein, The first heat dissipation plate comprises a heat dissipation metal plate.

7. The power semiconductor module package structure of claim 1, wherein, The first power chip, the second power chip, the third power chip and the fourth power chip each comprise a plurality of parallel semiconductor chips.

8. The power semiconductor module package structure of claim 1, wherein, The first base plate further comprises a first control signal terminal solder joint; the first control signal terminal solder joint is electrically connected to the first power chip and the second power chip through a binding wire; The second base plate further comprises a second control signal terminal solder joint; the second control signal terminal solder joint is electrically connected to the third power chip and the fourth power chip through a binding wire.

9. The power semiconductor module package structure according to claim 2, characterized by, The first base plate and the second base plate are both double-sided copper-clad ceramic base plates; The third base plate and the fourth base plate are both double-sided copper-clad ceramic base plates.

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