IGBT and method for manufacturing the same

Abstract

The present disclosure relates to an IGBT and a manufacturing method thereof. The IGBT comprises, from bottom to top, a collector region (109), a buffer layer (108), a substrate (101), a field oxide layer (102), an insulating medium layer (106) and a metal layer (107), and further comprises a main junction region (103) of a first conductive type and a cutoff ring region (104) of a second conductive type formed by diffusion in the substrate. A polysilicon layer is arranged between the field oxide layer and the insulating medium layer, and the polysilicon layer comprises m first conductive type doped regions (p1-pm) and m second conductive type doped regions (n1-nm) arranged alternately in a horizontal direction, m≥2. The metal layer above the main junction region and the first conductive type doped region (p1) closest to the main junction region are in contact through a hole in the insulating medium layer, and the metal layer above the cutoff ring region and the second conductive type doped region (nm) closest to the cutoff ring region are in contact through a hole in the insulating medium layer. The present scheme improves the consistency and stability of the breakdown voltage of the device.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to an IGBT and a method for manufacturing the same. Background Technology

[0002] An Insulated Gate Bipolar Transistor (IGBT) is a power device composed of a Bipolar Junction Transistor (BJT) and a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). It is primarily used in high-power applications requiring high voltage and high current. Breakdown voltage is one of its most important parameters, and it, along with maximum current capacity, determines the device's rated power.

[0003] The ideal device breakdown voltage refers to the case where the PN junction is a parallel planar junction. Since the junction termination effect is not considered, the breakdown voltage is determined only by device parameters such as doping concentration and substrate thickness. However, due to the realities of actual devices and the influence of certain factors in the manufacturing process, the breakdown voltage of actual devices is lower than that of an ideal parallel planar junction. Therefore, in practical device design, to achieve higher device breakdown voltages, we must consider the impact of the termination effect and design a better termination structure.

[0004] Commonly used device termination structures include: junction extension termination (JTE), lateral variable doping (VLD), field confinement ring (FLR), field confinement ring combined with field plate, and high-resistivity semiconductor polycrystalline silicon (SIPOS) termination structure. Summary of the Invention

[0005] The purpose of this disclosure is to provide an IGBT with high breakdown voltage consistency and stability, and a method for manufacturing the same.

[0006] To achieve the above objectives, this disclosure provides an IGBT, which, from bottom to top, comprises a collector region, a buffer layer, a substrate, a field oxide layer, an insulating dielectric layer, and a metal layer. The IGBT further includes a main junction region of a first conductivity type and a cutoff ring region of a second conductivity type diffused into the substrate. A polysilicon layer is disposed between the field oxide layer and the insulating dielectric layer. The polysilicon layer includes m doped regions of the first conductivity type and m doped regions of the second conductivity type arranged alternately in a horizontal direction, where m ≥ 2. The metal layer above the main junction region and the first conductivity type doped region closest to the main junction region are in contact through holes in the insulating dielectric layer, and the metal layer above the cutoff ring region and the second conductivity type doped region closest to the cutoff ring region are in contact through holes in the insulating dielectric layer.

[0007] Optionally, the IGBT further includes q-1 ring regions of a first conductivity type diffused in the substrate, where q≥2. On the field oxide layer between the main junction region and the ring region adjacent to the main junction region, between two adjacent ring regions, and between the cutoff ring region and the ring region adjacent to the cutoff ring region, m first conductivity type doped regions and m second conductivity type doped regions are alternately arranged in the horizontal direction. The metal layer above each ring region and the first conductivity type doped region and the second conductivity type doped region closest to that ring region are in contact through holes in the insulating dielectric layer.

[0008] Optionally, the doping dose of the first conductivity type doped region and the second conductivity type doped region is 10. 13 ~10 15 / cm 2 .

[0009] Optionally, the doping dose of the main junction region is 10. 13 ~10 15 / cm 2 .

[0010] Optionally, the injection energy of the main junction region is 50–120 keV.

[0011] This disclosure also provides a method for manufacturing an IGBT, the method comprising:

[0012] A field oxide layer is grown on the substrate;

[0013] The substrate is exposed by photolithography on the field oxide layer, and impurities of a first conductivity type are implanted into the substrate to form a main junction region;

[0014] The substrate is exposed by photolithography on the field oxide layer, and impurities of a second conductivity type are implanted into the substrate to form a cutoff ring region;

[0015] Gate oxide is grown on the field oxide layer, and a polycrystalline silicon layer is deposited.

[0016] By photolithography, impurities of a first conductivity type and impurities of a second conductivity type are implanted into the polysilicon layer to generate m doped regions of the first conductivity type and m doped regions of the second conductivity type arranged alternately in the horizontal direction, where m≥2;

[0017] Deposit insulating dielectric layer;

[0018] Photolithography exposes the main junction region and the cutoff ring region. Photolithography is used to create holes in the insulating dielectric layer above the first conductivity type doped region closest to the main junction region, and photolithography is used to create holes in the insulating dielectric layer above the second conductivity type doped region closest to the cutoff ring region.

[0019] Metal layers are deposited on the main junction region, the cutoff ring region, the first conductivity type doped region closest to the main junction region, and the second conductivity type doped region closest to the cutoff ring region;

[0020] A buffer layer and a current collection area are formed on the back side.

[0021] Optionally, after growing a field oxide layer on the substrate, the method further includes: photolithographically exposing the substrate on the field oxide layer, implanting impurities of a first conductivity type into the substrate to form q-1 ring regions of the first conductivity type, where q≥2;

[0022] Implanting impurities of a first conductivity type and a second conductivity type onto the polysilicon layer by photolithography includes: implanting impurities of a first conductivity type and a second conductivity type onto the polysilicon layer by photolithography, so as to generate m first conductivity type doped regions and m second conductivity type doped regions alternately arranged in the horizontal direction on the field oxide layer between the main junction region and the ring region adjacent to the main junction region, between two adjacent ring regions, and between the cutoff ring region and the ring region adjacent to the cutoff ring region;

[0023] After depositing the insulating dielectric layer, the method further includes: photolithographically exposing the ring regions; photolithographically drilling holes on the insulating dielectric layer above the first conductivity type doped region and the second conductivity type doped region closest to each ring region; and depositing a metal layer on the ring regions, the first conductivity type doped region and the second conductivity type doped region closest to each ring region.

[0024] Optionally, the doping dose of the first conductivity type doped region and the second conductivity type doped region is 10. 13 ~10 15 / cm 2 .

[0025] Optionally, the doping dose of the main junction region is 10. 13 ~10 15 / cm 2 .

[0026] Optionally, the injection energy of the main junction region is 50–120 keV.

[0027] The above technical solution involves depositing a polysilicon structure on the field oxide layer of the terminal, based on the field-limiting ring termination structure. Multiple continuous PNPN junctions are then formed on the polysilicon by implanting impurities. The mutual depletion of these PNPN junctions creates linear and stepped potential barrier distributions, resulting in a uniform electric field distribution. By modulating the uniform distribution of the electric field on the terminal surface through the capacitance effect, the influence of interface charge can be effectively eliminated, improving the device's avalanche capability. Furthermore, this PNPN structure has lower process requirements, is easier to control, and exhibits high termination efficiency, achieving a high breakdown voltage with a smaller termination area. Additionally, this PNPN structure has lower high-temperature leakage current, better stability, higher electric field modulation efficiency, and a more uniform electric field, thus significantly improving the consistency and stability of the device's breakdown voltage.

[0028] Other features and advantages of this disclosure will be described in detail in the following detailed description section. Attached Figure Description

[0029] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings:

[0030] Figure 1 This is a schematic diagram of the structure of an IGBT provided in an exemplary embodiment;

[0031] Figure 2 This is an exemplary embodiment provided. Figure 1 A flowchart illustrating the manufacturing process of IGBTs;

[0032] Figures 3a-3f This is an exemplary embodiment provided. Figure 1 A schematic diagram of the IGBT manufacturing process;

[0033] Figure 4 This is a schematic diagram of the IGBT structure provided in another exemplary embodiment;

[0034] Figure 5 This is an exemplary embodiment provided. Figure 4 A flowchart illustrating the manufacturing process of IGBTs;

[0035] Figures 6a-6f This is an exemplary embodiment provided. Figure 4 A schematic diagram of the manufacturing process of IGBTs.

[0036] Explanation of reference numerals in the attached figures

[0037] 101 Substrate 102 Field Oxide Layer 103 Main Junction Region

[0038] 104 Cut-off ring region 105 Polysilicon layer 106 Insulating dielectric layer

[0039] 107 Metal layer 108 Buffer layer 109 Collector area

[0040] p1~pm First conductivity type doped region 10³⁻²~10³⁻q ring region

[0041] n1~nm Second conductivity type doped region Detailed Implementation

[0042] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0043] In this disclosure, those skilled in the art will understand that, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to directions relative to the IGBT manufacturing process. Furthermore, the terms "upper," "lower," and "horizontal," etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are used only for the convenience of describing this disclosure and for simplification, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0044] The field-limiting ring termination structure is a commonly used termination structure for IGBT devices. It utilizes implanted doping to form multiple ring regions with the same impurities as the main junction doped (e.g., p-type). Under reverse voltage, each ring region is depleted by the main junction depletion layer, forming an electric field opposite to the original electric field, thereby weakening the electric field in that region and achieving a balanced distribution of the overall electric field. This disclosure makes some improvements to the IGBT device termination structure based on the field-limiting ring termination structure, which are described in detail below.

[0045] Figure 1 This is a schematic diagram of the structure of an IGBT provided in an exemplary embodiment. For example... Figure 1 As shown, the IGBT can be sequentially comprised from bottom to top of a collector region 109, a buffer layer 108, a substrate 101, a field oxide layer 102, an insulating dielectric layer 106, and a metal layer 107. The IGBT also includes a main junction region 103 of a first conductivity type and a cutoff ring region 104 of a second conductivity type, diffused and formed in the substrate 101.

[0046] A polysilicon layer is disposed between the field oxide layer 102 and the insulating dielectric layer 106. The polysilicon layer includes m first conductivity type doped regions p1 to pm and m second conductivity type doped regions n1 to nm arranged alternately in the horizontal direction, where m ≥ 2.

[0047] The metal layer 107 above the main junction region 103 and the first conductivity type doped region p1 closest to the main junction region 103 are in contact through holes in the insulating dielectric layer 106. The metal layer 107 above the stop ring region 104 and the second conductivity type doped region nm closest to the stop ring region 104 are in contact through holes in the insulating dielectric layer 106.

[0048] For example, the first conductivity type is P-type, and the second conductivity type is N-type. From the main junction region 103 to the cutoff ring region 104, the polysilicon layer starts from the first conductivity type doped region p1 and sequentially arranges the second conductivity type doped region n1, the first conductivity type doped region p2, the second conductivity type doped region n2, the first conductivity type doped region p3, ..., the first conductivity type doped region pm, and the second conductivity type doped region nm in the horizontal direction, thus forming multiple continuous PNPN structures. The number of PN junctions is greater than or equal to 2, and this structure plays a role in modulating the surface electric field.

[0049] The above technical solution involves depositing a polysilicon structure on the field oxide layer of the terminal, based on the field-limiting ring termination structure. Multiple continuous PNPN junctions are then formed on the polysilicon by implanting impurities. The mutual depletion of these PNPN junctions creates linear and stepped potential barrier distributions, resulting in a uniform electric field distribution. By modulating the uniform distribution of the electric field on the terminal surface through the capacitance effect, the influence of interface charge can be effectively eliminated, improving the device's avalanche capability. Furthermore, this PNPN structure has lower process requirements, is easier to control, and exhibits high termination efficiency, achieving a high breakdown voltage with a smaller termination area. Additionally, this PNPN structure has lower high-temperature leakage current, better stability, higher electric field modulation efficiency, and a more uniform electric field, thus significantly improving the consistency and stability of the device's breakdown voltage.

[0050] Figure 2 This is an exemplary embodiment provided. Figure 1 A flowchart illustrating the manufacturing process of IGBTs. Figures 3a-3f This is an exemplary embodiment provided. Figure 1 A schematic diagram of the IGBT manufacturing process. (Example) Figure 2 As shown, the method may include the following steps.

[0051] Step S11, a field oxide layer 102 is grown on the substrate 101, such as... Figure 3aAs shown. For example, a lightly doped N-type single-crystal semiconductor substrate material with a crystal orientation of 100 / 110 / 111 can be selected, and the appropriate resistivity and thickness can be chosen according to the device's breakdown voltage. A field oxide layer 102 of a certain thickness can be grown by thermal oxidation.

[0052] Step S12: Photolithography is performed on the field oxide layer 102 to expose the substrate 101. Impurities of the first conductivity type are implanted into the substrate 101 to form the main junction region 103, as shown below. Figure 3b As shown. For example, an opening is photolithographically formed on the field oxide layer 102 and a P-type impurity is implanted, followed by high-temperature diffusion to form the terminal structure main junction region 103. The doping dose of the main junction region 103 can be 10. 13 ~10 15 / cm 2 The injection energy in the main junction region 103 can be 50–120 keV.

[0053] Step S13: Photolithography is performed on the field oxide layer 102 to expose the substrate 101. Impurities of a second conductivity type are implanted into the substrate 101 to form a cutoff ring region 104, as shown below. Figure 3c As shown. For example, an opening is made by photolithography and N-type impurities are implanted, and a terminal structure N-type cutoff ring region 104 is formed by high-temperature push-bonding.

[0054] Step S14: A gate oxide layer is grown on the field oxide layer 102, and a polysilicon layer 105 is deposited, as shown below. Figure 3d As shown. For example, a thin and dense gate oxide layer is thermally grown on the field oxide layer 102, and a polycrystalline silicon layer 105 of a certain thickness is deposited by chemical vapor deposition.

[0055] Step S15: By photolithography, impurities of a first conductivity type and impurities of a second conductivity type are implanted into the polysilicon layer 105 to generate m first conductivity type doped regions p1 to pm and m second conductivity type doped regions n1 to nm arranged alternately in the horizontal direction, where m ≥ 2. Figure 3e As shown. The doping dose of the first conductivity type doped region p1 to pm and the second conductivity type doped region n1 to nm can be 10. 13 ~10 15 / cm 2 For example, implanting doping doses of 10... 13 ~10 15 / cm 2 The boron and doping dose is 10 13 ~10 15 / cm 2 Phosphorus forms a continuous PNPN region structure.

[0056] Step S16: Deposit insulating dielectric layer 106, and perform high-temperature annealing and planarization, as shown. Figure 3f As shown.

[0057] Step S17: Photolithography exposes the main junction region 103 and the cutoff ring region 104. Photolithography is performed on the insulating dielectric layer 106 above the first conductivity type doped region p1, which is closest to the main junction region 103. Photolithography is also performed on the insulating dielectric layer 106 above the second conductivity type doped region nm, which is closest to the cutoff ring region 104. Figure 3f As shown.

[0058] Step S18: Deposit metal layers 107 on the main junction region 103, the stop ring region 104, the first conductivity type doped region p1 closest to the main junction region 103, and the second conductivity type doped region nm closest to the stop ring region 104 to form alloy ohmic contacts and terminal metal electrodes or field plates, such as... Figure 3f As shown.

[0059] Step S19, a buffer layer 108 and a collector area 109 are formed on the back side, as shown below. Figure 3f As shown. For example, after depositing a passivation layer on the front side, N-type impurities can be implanted after thinning on the back side to form an N-type buffer layer 108. Then, P-type impurities are implanted and activated by laser annealing, and the back side metal is deposited by evaporation to form a current collector region 109.

[0060] Figure 4 This is a schematic diagram of the IGBT structure provided in another exemplary embodiment. For example... Figure 4 As shown, in Figure 1 Based on this, the IGBT also includes q-1 ring regions 103-2 to 103-q of a first conductivity type diffused in the substrate 101, where q ≥ 2. Figure 4 In the embodiment, q = 3.

[0061] Between the main junction region 103 and the adjacent ring region 103-2, between two adjacent ring regions 103-2 and 103-3, and between the cutoff ring region 104 and the adjacent ring region 103-q. Figure 4 The field oxide layer 102 between the ring regions 103-3) is provided with m first conductivity type doped regions p1 to pm and m second conductivity type doped regions n1 to nm arranged alternately in the horizontal direction. The metal layer 107 above each ring region and the first conductivity type doped region and the second conductivity type doped region closest to the ring region are in contact through the holes in the insulating dielectric layer 106.

[0062] For example, the metal layer 107 above the ring region 103-2 and Figure 4 The second conductivity type doped region nm on the left and the first conductivity type doped region p1 on the right are in contact through holes in the insulating dielectric layer 106.

[0063] Figure 5 This is an exemplary embodiment provided. Figure 4 A flowchart illustrating the manufacturing process of an IGBT. (e.g.) Figure 5 As shown, in Figure 2 Based on this, after growing a field oxide layer 102 on the substrate 101 (step S11), the method further includes step S131: exposing the substrate 101 by photolithography on the field oxide layer 102, and implanting impurities of a first conductivity type into the substrate 101 to form q-1 ring regions of the first conductivity type 103-2 to 103-q, where q≥2. Figure 5 In this context, step S131 follows steps S12 and S13. As those skilled in the art will understand, in other embodiments, steps S131, S12, and S13 can be executed in any order or simultaneously.

[0064] exist Figure 2 Based on this, by photolithography, impurities of the first conductivity type and impurities of the second conductivity type are implanted on the polysilicon layer 105 respectively (step S15). This may include step S151: by photolithography, impurities of the first conductivity type and impurities of the second conductivity type are implanted on the polysilicon layer 105 respectively, so that m first conductivity type doped regions p1 to pm and m second conductivity type doped regions n1 to nm are generated alternately in the horizontal direction on the field oxide layer 102 between the main junction region 103 and the ring region 103-2 adjacent to the main junction region 103, between two adjacent ring regions, and between the cutoff ring region 104 and the ring region 103-q adjacent to the cutoff ring region 104.

[0065] exist Figure 2 Based on the deposition of insulating dielectric layer 106 (step S16), the method further includes:

[0066] Step S171: Photolithography exposes the ring regions 103-2 to 103-q, and photolithography drills holes on the insulating dielectric layer 106 above the first conductivity type doped region p1 and the second conductivity type doped region nm that are closest to each ring region.

[0067] Step S181: Deposit metal layer 107 on ring regions 103-2 to 103-q, the first conductivity type doped region p1 closest to each ring region, and the second conductivity type doped region nm closest to each ring region.

[0068] Those skilled in the art will understand that in other embodiments, step S171 may be performed simultaneously with step S17, and step S181 may be performed simultaneously with step S18.

[0069] Figures 6a-6f This is an exemplary embodiment provided. Figure 4A schematic diagram of the IGBT manufacturing process is shown below. In this embodiment, the IGBT manufacturing process is as follows.

[0070] Step S11, grow a field oxide layer 102 on the substrate 101, such as Figure 6a As shown. For example, a lightly doped N-type single-crystal semiconductor substrate material with a crystal orientation of 100 / 110 / 111 can be selected, and the appropriate resistivity and thickness can be chosen according to the device's breakdown voltage. A field oxide layer 102 of a certain thickness can be grown by thermal oxidation.

[0071] Step S12: Photolithography is performed on the field oxide layer 102 to expose the substrate 101. Impurities of the first conductivity type are implanted into the substrate 101 to form the main junction region 103, as shown below. Figure 6b As shown. For example, an opening is photolithographically formed on the field oxide layer 102 and a P-type impurity is implanted, followed by high-temperature diffusion to form the main junction region 103 of the terminal structure. The doping dose of the main junction region 103 can be 10. 13 ~10 15 / cm 2 The injected energy can be 50–120 keV.

[0072] Step S131: Photolithography is performed on the field oxide layer 102 to expose the substrate 101. Impurities of a first conductivity type are implanted into the substrate 101 to form q-1 ring regions of the first conductivity type 103-2 to 103-q, where q ≥ 2. Figure 6b As shown, q = 3. For example, an opening is photolithographically formed on the field oxide layer 102 and a P-type impurity is implanted, followed by high-temperature diffusion to form the ring regions 103-2 to 103-q of the terminal structure. The doping dose of the ring regions 103-2 to 103-q can be 10. 13 ~10 15 / cm 2 The injected energy can be 50–120 keV.

[0073] Step S13: Photolithography is performed on the field oxide layer 102 to expose the substrate 101. Impurities of a second conductivity type are implanted into the substrate 101 to form a cutoff ring region 104, as shown below. Figure 6c As shown. For example, an opening is made by photolithography and N-type impurities are implanted, and a terminal structure N-type cutoff ring region 104 is formed by high-temperature push-bonding.

[0074] Step S14: A gate oxide layer is grown on the field oxide layer 102, and a polysilicon layer 105 is deposited, as shown below. Figure 6d As shown. For example, a thin and dense gate oxide layer is thermally grown on the field oxide layer 102, and a polycrystalline silicon layer 105 of a certain thickness is deposited by chemical vapor deposition.

[0075] Step S151: By photolithography, impurities of the first conductivity type and impurities of the second conductivity type are implanted into the polysilicon layer 105, respectively, to generate m horizontally alternating first conductivity type doped regions p1 to pm and m second conductivity type doped regions n1 to nm on the field oxide layer 102 between the main junction region 103 and the ring region 103-2 adjacent to the main junction region 103, between two adjacent ring regions, and between the cutoff ring region 104 and the ring region 103-q adjacent to the cutoff ring region 104, where m ≥ 2. Figure 6e As shown. For example, implanting doping doses of 10... 13 ~10 15 / cm 2 The boron content and doping dose are 10 13 ~10 15 / cm 2 Phosphorus forms a continuous PNPN region structure.

[0076] Step S16: Deposit insulating dielectric layer 106, and perform high-temperature annealing and planarization, as shown. Figure 6f As shown.

[0077] Step S17: Photolithography exposes the main junction region 103 and the cutoff ring region 104. Photolithography is performed on the insulating dielectric layer 106 above the first conductivity type doped region p1, which is closest to the main junction region 103. Photolithography is also performed on the insulating dielectric layer 106 above the second conductivity type doped region nm, which is closest to the cutoff ring region 104. Figure 6f As shown.

[0078] Step S171: Photolithography exposes the ring regions 103-2 to 103-q. Photolithography drills holes in the insulating dielectric layer 106 above the first conductivity type doped region p1 and the second conductivity type doped region nm, which are closest to each ring region. Figure 6f As shown.

[0079] Step S18: Deposit metal layers 107 on the main junction region 103, the stop ring region 104, the first conductivity type doped region p1 closest to the main junction region 103, and the second conductivity type doped region nm closest to the stop ring region 104 to form alloy ohmic contacts and terminal metal electrodes or field plates, such as... Figure 6f As shown.

[0080] Step S181: Deposit a metal layer 107 on the ring regions 103-2 to 103-q, the first conductivity type doped region p1 closest to each ring region, and the second conductivity type doped region nm closest to each ring region, as shown below. Figure 6f As shown.

[0081] Step S19, a buffer layer 108 and a collector area 109 are formed on the back side, as shown below. Figure 6fAs shown. For example, after depositing a passivation layer on the front side, N-type impurities can be implanted after thinning on the back side to form an N-type buffer layer 108. Then, P-type impurities are implanted and activated by laser annealing, and the back side metal is deposited by evaporation to form a current collector region 109.

[0082] The preferred embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. However, this disclosure is not limited to the specific details of the above embodiments. Within the scope of the technical concept of this disclosure, various simple modifications can be made to the technical solutions of this disclosure, and these simple modifications all fall within the protection scope of this disclosure.

[0083] It should also be noted that the various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, this disclosure will not describe the various possible combinations separately.

[0084] Furthermore, various different embodiments of this disclosure can be combined in any way, as long as they do not violate the spirit of this disclosure, they should also be regarded as the content disclosed in this disclosure.

Claims

1. An IGBT, comprising, from bottom to top, a collector region (109), a buffer layer (108), a substrate (101), a field oxide layer (102), an insulating dielectric layer (106), and a metal layer (107), wherein the IGBT further comprises a main junction region (103) of a first conductivity type and a stop ring region (104) of a second conductivity type diffused and formed in the substrate (101), characterized in that, A polysilicon layer (105) is disposed between the field oxide layer (102) and the insulating dielectric layer (106). The polysilicon layer (105) includes m first conductivity type doped regions (p1~pm) and m second conductivity type doped regions (n1~nm) arranged alternately in the horizontal direction, where m≥2. The metal layer (107) above the main junction region (103) and the first conductivity type doped region (p1) closest to the main junction region (103) are in contact through a hole in the insulating dielectric layer (106). The metal layer (107) above the stop ring region (104) and the second conductivity type doped region (nm) closest to the stop ring region (104) are in contact through a hole in the insulating dielectric layer (106). The IGBT also includes q-1... The first conductivity type ring regions (103-2~103-q) diffused in the substrate (101), q≥2, are provided on the field oxide layer (102) between the main junction region (103) and the ring region (103-2) adjacent to the main junction region (103), between two adjacent ring regions, and between the cutoff ring region (104) and the ring region (103-q) adjacent to the cutoff ring region (104). m first conductivity type doped regions (p1~pm) and m second conductivity type doped regions (n1~nm) are arranged alternately in the horizontal direction. The metal layer (107) above each ring region and the first conductivity type doped region and the second conductivity type doped region closest to the ring region are in contact through the holes in the insulating dielectric layer (106).

2. The IGBT according to claim 1, characterized in that, The doping dose of the first conductivity type doped region (p1~pm) and the second conductivity type doped region (n1~nm) is 10. 13 ~10 15 / cm 2 .

3. The IGBT according to claim 1, characterized in that, The doping dose of the main junction region (103) is 10. 13 ~10 15 / cm 2 .

4. The IGBT according to claim 1, characterized in that, The injection energy of the main junction region (103) is 50~120keV.

5. A method for manufacturing an IGBT as described in any one of claims 1-4, characterized in that, The method includes: A field oxide layer (102) is grown on the substrate (101); The substrate (101) is exposed by photolithography on the field oxide layer (102), and impurities of the first conductivity type are implanted into the substrate (101) to form a main junction region (103). The substrate (101) is exposed by photolithography on the field oxide layer (102), and impurities of a second conductivity type are implanted into the substrate (101) to form a cutoff ring region (104). Gate oxide is grown on the field oxide layer (102), and a polysilicon layer (105) is deposited. By photolithography, impurities of the first conductivity type and impurities of the second conductivity type are implanted into the polysilicon layer (105) to generate m first conductivity type doped regions (p1~pm) and m second conductivity type doped regions (n1~nm) arranged alternately in the horizontal direction, where m≥2; Deposit an insulating dielectric layer (106); Photolithography exposes the main junction region (103) and the cutoff ring region (104). Photolithography is used to create holes in the insulating dielectric layer (106) above the first conductivity type doped region (p1) closest to the main junction region (103). Photolithography is also used to create holes in the insulating dielectric layer (106) above the second conductivity type doped region (nm) closest to the cutoff ring region (104). Metal layers (107) are deposited on the main junction region (103), the cutoff ring region (104), the first conductivity type doped region (p1) closest to the main junction region (103), and the second conductivity type doped region (nm) closest to the cutoff ring region (104). A buffer layer (108) and a collector area (109) are formed on the back side.

6. The method according to claim 5, characterized in that, After growing a field oxide layer (102) on the substrate (101), the method further includes: photolithographically exposing the substrate (101) on the field oxide layer (102), and implanting impurities of a first conductivity type into the substrate (101) to form q-1 ring regions of the first conductivity type (103-2~103-q), where q≥2; By photolithography, impurities of a first conductivity type and impurities of a second conductivity type are implanted on the polysilicon layer (105), including: by photolithography, impurities of a first conductivity type and impurities of a second conductivity type are implanted on the polysilicon layer (105) to generate m first conductivity type doped regions (p1~pm) and m second conductivity type doped regions (n1~nm) arranged alternately in the horizontal direction on the field oxide layer (102) between the main junction region (103) and the ring region (103-2) adjacent to the main junction region (103), between two adjacent ring regions, and between the cutoff ring region (104) and the ring region (103-q) adjacent to the cutoff ring region (104). After depositing the insulating dielectric layer (106), the method further includes: photolithographically exposing the ring regions (103-2~103-q), photolithographically drilling holes on the insulating dielectric layer (106) above the first conductivity type doped region (p1) closest to each ring region and the second conductivity type doped region (nm) closest to each ring region; and depositing a metal layer (107) on the ring regions (103-2~103-q), the first conductivity type doped region (p1) closest to each ring region and the second conductivity type doped region (nm) closest to each ring region.

7. The method according to claim 5 or 6, characterized in that, The doping dose of the first conductivity type doped region (p1~pm) and the second conductivity type doped region (n1~nm) is 10. 13 ~10 15 / cm 2 .

8. The method according to claim 5 or 6, characterized in that, The doping dose of the main junction region (103) is 10. 13 ~10 15 / cm 2 .

9. The method according to claim 5 or 6, characterized in that, The injection energy of the main junction region (103) is 50~120keV.

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