Circuit structure for realizing motor lead-lag commutation

Abstract

This invention relates to a circuit structure for implementing phase lead-lag commutation in a motor. The circuit structure includes a Hall angle mapping module for receiving three Hall signals generated by an external motor's Hall module and configuring them into Hall synchronization angle values; a Hall angle update module for selecting an appropriate angle update mode based on the circuit structure's internal logic; a three-phase angle generation module for performing time-division calculations on the angles generated by the Hall angle update module to generate the current three-phase angle signal; an angle conversion module for performing corresponding angle conversions on the three-phase angle signal generated by the three-phase angle generation module; and a PWM generation module for generating a three-phase, six-channel complementary PWM waveform. The circuit structure of this invention only adds a few logic circuit modules, yet it can easily implement phase lead-lag operation and achieve smooth switching between square wave and sine wave control modes.

Description

Technical Field

[0001] This invention relates to the field of square wave motor commutation technology, and more particularly to the field of motor lead-lag commutation technology, specifically a circuit structure for realizing motor lead-lag commutation. Background Technology

[0002] Permanent magnet brushless motors (PMMBMs) have advantages such as simple structure, high power density, long service life, and easy maintenance, and are gaining an increasingly large share of the market, making them the first choice for motor design. Control systems for brushless motors often use position sensors to detect rotor position, including rotary transformers, encoders, and Hall sensors. Hall sensors, in particular, are widely used in scenarios where high control precision is not required due to their superior anti-interference capabilities and ease of installation. However, the presence of position sensors reduces motor reliability and increases motor size and cost. In recent years, with the development of control technology and the improvement of control chip performance, the application of sensorless high-speed PMMBMs has gradually increased. There are various methods for rotor position detection in sensorless brushless DC motors, such as flux linkage estimation, freewheeling diode current detection, and back EMF detection. Among these, the method based on winding back EMF is the most mature and widely used.

[0003] For the HALL method, as the load increases, magnetic field distortion occurs, leading to commutation signal lag and consequently commutation delay. To improve motor efficiency, leading commutation is essential. Regarding the winding back EMF, if the hardware delay of the back EMF signal caused by the delay of the filter components is small, the characteristic of a 30-degree leading commutation timing at the zero-crossing point of the back EMF can be utilized to achieve leading commutation by reducing the delay time. However, for circuits with severe hardware delay in the back EMF signal, leading commutation can only be achieved by delaying the back EMF signal of the previous phase, which increases code complexity.

[0004] Most of the non-sensory operation involves controlling the commutation signal at the software level. For example, Chinese patent document CN111264025, "Method for Running a Motor," uses the principle of FOC (Field Oriented Control, also known as vector control) in flux linkage control for lead-lag control. It requires a series of calculation operations in each PWM cycle, including current sampling, angle calculation, torque control, and PWM generation, to ensure that the lead angle of the controlled motor torque does not exceed the critical operating angle of the motor or generator. It can generate sine waves and trapezoidal waves. However, this series of calculation operations places high demands on the performance of the main control MCU, thus increasing the control cost. Chinese patent document CN201610542908.4, "A Control Method for a Permanent Magnet Brushless Motor," calculates the rotor flux linkage by detecting the phase voltage and phase current of the motor, and simultaneously integrates the phase current to obtain a current integral signal. The phase difference between this current integral signal and the rotor flux linkage is the phase difference between the phase current and the back EMF. Then, by detecting and compensating for the phase difference between the rotor flux linkage and the current integral signal, a closed-loop control is formed based on this phase difference. The output value of this closed loop is the commutation correction value, enabling the motor to operate at the optimal commutation point. Like the "Method for Running a Motor" mentioned above, this scheme faces the problem of high computational requirements for the main control MCU, thus increasing design costs. Chinese patent document CN104767435, "Real-time Correction Method for Commutation Phase of Sensorless Brushless Motor Based on Neutral Point Voltage," determines the current commutation phase error by collecting the voltage difference of a virtual neutral point 30 degrees before and after the commutation point. This voltage difference is used as the commutation error feedback quantity to achieve real-time correction of the trapezoidal wave commutation phase. However, this patent suffers from insufficient accuracy at low speeds. Chinese patent document CN106452225, "Real-time Correction System and Method for Commutation Phase of Sensorless Brushless DC Motor," compares the voltage sample value of the off-phase voltage Vt at time tx with half of the DC bus voltage Ud / 2 of the three-phase bridge inverter circuit. The commutation position correction angle Δθ is calculated based on the difference, and then the commutation phase of the sensorless brushless DC motor is corrected through PI control. Δθ≈arcsin((2Vt-Ud) / 2Ec), where Ec is the phase winding back electrodynamic type. Ec cannot be obtained directly. At high speeds, it is close to Ud and can be replaced by Ud, but the accuracy is affected. If higher accuracy is desired, Ec still needs to be calculated in real time at high speeds, which increases the burden on the main control chip and raises the requirements for chip performance. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a simple, efficient and convenient circuit structure for realizing motor lead-lag commutation.

[0006] To achieve the above objectives, the circuit structure of the present invention for realizing the leading and lagging commutation of the motor is as follows:

[0007] The main feature of this circuit structure for realizing the leading and lagging commutation of a motor is that the circuit structure includes:

[0008] The Hall angle mapping module is connected to the Hall module of the external motor. It is used to receive the three Hall signals generated by the Hall module and convert the three Hall signals into Hall synchronization angle values ​​respectively.

[0009] The Hall angle update module, connected to the Hall angle mapping module, is used to select the corresponding angle update mode according to the internal logic of the circuit structure.

[0010] The three-phase angle generation module is connected to the Hall angle update module and is used to perform time-division calculation on the angle generated by the Hall angle update module to generate the current three-phase angle signal of the three Hall signals.

[0011] An angle conversion module, connected to the three-phase angle generation module, is used to perform corresponding angle conversions on the three-phase angle signals generated by the three-phase angle generation module; and

[0012] The PWM generation module, connected to the angle conversion module, is used to generate the three-phase six-channel complementary PWM waveform of the circuit structure.

[0013] Preferably, the Hall angle mapping module uses a 3-8 decoder unit to compile and process the three Hall signals generated by the Hall module of the external motor to generate corresponding register configuration signals for setting the phase offset of the Hall signals. After each register configuration signal is processed by AND gates and OR gates, the Hall synchronization angle value corresponding to the three Hall signals is generated.

[0014] Preferably, the register configuration signal sets the phase offset of the Hall signal, specifically as follows:

[0015] The register configuration signal sets the phase offset of the corresponding Hall signal according to the placement position of the three Hall elements, specifically including:

[0016] Register 5 is configured to set the phase offset of the corresponding Hall signal to 0°.

[0017] Register 1 configuration signal is used to set the phase offset of the corresponding Hall signal to 60°;

[0018] Register 3 configuration signal is used to set the phase offset of the corresponding Hall signal to 120°;

[0019] Register 2 configuration signal is used to set the phase offset of the corresponding Hall signal to 180°;

[0020] Register 6 configuration signal is used to set the phase offset of the corresponding Hall signal to 240°;

[0021] Register 4 configuration signal is used to set the phase offset of the corresponding Hall signal to 300°;

[0022] Phase-leading commutation and phase-lag commutation can be achieved by changing the phase bias of the Hall signal.

[0023] Preferably, the Hall angle update module includes:

[0024] A first register, wherein the high-level input terminal of the first register is connected to the Hall synchronization angle value, the clock terminal of the first register is input with a clock signal clk, the S-input terminal of the first register is input with a state update signal HALL_change, and the output terminal of the first register outputs the processed unidirectional angle Degree_A; and

[0025] The first adder has a first input terminal that receives a unidirectional angle Degree_A for angle addition calculation, a second input terminal that receives an angle count increment signal Degree_in, and an output terminal that sends the angle variable generated after addition to the low-level input terminal of the first register for angle update processing.

[0026] Preferably, the three-phase angle generation module includes:

[0027] The second register has a high-level input terminal that receives the first timing input signal C0 and calculates the sine signal sin(Degree) at time C0. The clock terminal of the second register receives the system clock signal HCLK and the output terminal of the second register outputs the first synchronization increment signal Add_1 and calculates the sine signal sin(Degree+120°) at time Add_1.

[0028] The third register has a high-level input terminal connected to the first synchronization increment signal Add_1, a clock terminal connected to the system clock signal HCLK, and an output terminal connected to the second synchronization increment signal Add_2. The sine signal sin(Degree+240°) at time Add_2 is calculated.

[0029] The second adder receives the sinusoidal signals sin(Degree+120°) at time Add_1 and sin(Degree+240°) at time Add_2 after AND and OR gate processing, and inputs them to its first input terminal. The second input terminal receives the unidirectional angle Degree_A. The output terminal of the second adder, after addition processing, outputs the real-time signal Degree.

[0030] The first subtractor has its first input terminal connected to the real-time signal Degree, and its second input terminal connected to a 360° sine wave signal. The output terminal of the first subtractor performs subtraction on the input signal to generate the current three-phase angle output sine wave signal Sin_degree_pre of the circuit structure.

[0031] Preferably, the angle conversion module includes:

[0032] The first quadrant angle conversion module is used to convert the three-phase angle output sinusoidal signal Sin_degree_pre that meets the requirements into a first quadrant angle signal Degree_1_90, and then process the first quadrant angle signal Degree_1_90 and the current three-phase angle output sinusoidal signal Sin_degree_pre with AND gates and OR gates to generate a real-time sinusoidal signal Sin_degree.

[0033] The second quadrant angle conversion module is used to convert the three-phase angle output sinusoidal signal Sin_degree_pre that meets the requirements into a second quadrant angle signal Degree_91_180, and then perform AND and OR gate processing on the second quadrant angle signal Degree_91_180 and the current three-phase angle output sinusoidal signal 180°-Sin_degree_pre generated after angle conversion to generate a real-time sinusoidal signal Sin_degree.

[0034] The third quadrant angle conversion module is used to convert the required three-phase angle output sinusoidal signal Sin_degree_pre to a third quadrant angle signal Degree_181_270, and then perform AND and OR gate processing on the third quadrant angle signal Degree_181_270 and the currently converted three-phase angle output sinusoidal signal Sin_degree_pre - 180° to generate a real-time sinusoidal signal Sin_degree; and

[0035] The fourth quadrant angle conversion module is used to convert the three-phase angle output sinusoidal signal Sin_degree_pre that meets the requirements into a fourth quadrant angle signal Degree_271_360. Then, the fourth quadrant angle signal Degree_271_360 is processed with the current three-phase angle output sinusoidal signal 360°-Sin_degree_pre after angle conversion through AND and OR gates to generate the real-time sinusoidal signal Sin_degree.

[0036] Preferably, the PWM generation module includes:

[0037] The Sin function generator is used to input the real-time sine signal Sin_degree and, after processing, generates an output sine signal Sinout.

[0038] The second subtractor receives the output sine signal Sinout at its first input terminal and a 30° sine signal at its second input terminal. The second subtractor determines the sign bit of the input signal and outputs the result signal of the sign bit determination of the input signal at its output terminal.

[0039] The first trigger module receives the judgment result signal from the output of the second subtractor at its input terminal, and the clock terminal of the first trigger module receives the first timing input signal C0 and the system clock signal HCLK. The output terminal of the first trigger module is connected to the input terminal of the first inverter, the output terminal of the first inverter is connected to the first input terminal of the AND gate, the second input terminal of the AND gate receives the amplitude signal, and the conduction state of the upper and lower bridge arms of the corresponding Hall signal is determined according to the signal conduction timing.

[0040] The second trigger module has its first input terminal connected to the judgment result signal of the output terminal of the second subtractor, and its clock terminal inputs the first synchronous increment signal Add_1 and the system clock signal HCLK. The output terminal of the second trigger module is connected to the input terminal of the second inverter, and the output terminal of the second inverter is connected to the first input terminal of the AND gate. The second input terminal of the AND gate inputs an amplitude signal, and the conduction state of the upper and lower bridge arms of the corresponding Hall signal is determined according to the signal conduction timing.

[0041] The third trigger module has its first input connected to the judgment result signal of the output of the second subtractor, and its clock input includes the second synchronous increment signal Add_2 and the system clock signal HCLK. The output of the third trigger module is connected to the input of the third inverter, and the output of the third inverter is connected to the first input of the AND gate. The second input of the AND gate receives an amplitude signal, and the conduction status of the upper and lower bridge arms of the corresponding Hall signal is determined according to the signal conduction timing.

[0042] Preferably, the conduction state of the upper and lower bridge arms of the corresponding Hall signal changes according to the following rules:

[0043] When the conduction timing is in the first quadrant, that is, when the sinusoidal signal sin(Degree) at the unidirectional angles Degree_A and C0 is in the first quadrant, the upper arm sign bit Sign_sin of the corresponding Hall signal is 1 and the lower arm sign bit Sign_sin_n is 0, then the upper arm of the corresponding Hall signal is turned on.

[0044] When the conduction timing is in the second quadrant, that is, when the sinusoidal signal sin(Degree) at the unidirectional angles Degree_A and C0 is in the second quadrant, the upper arm sign bit Sign_sin of the corresponding Hall signal is 1 and the lower arm sign bit Sign_sin_n is 0, then the upper arm of the corresponding Hall signal is turned on.

[0045] When the conduction timing is in the third quadrant, that is, when the sinusoidal signal sin(Degree) at the unidirectional angles Degree_A and C0 is in the third quadrant, the upper arm sign bit Sign_sin of the corresponding Hall signal is 0 and the lower arm sign bit Sign_sin_n is 1, then the lower arm of the corresponding Hall signal is turned on.

[0046] When the conduction timing is in the fourth quadrant, that is, when the sinusoidal signal sin(Degree) at the unidirectional angles Degree_A and C0 is in the fourth quadrant, the upper arm sign bit Sign_sin of the corresponding Hall signal is 0 and the lower arm sign bit Sign_sin_n is 1, then the lower arm of the corresponding Hall signal is turned on.

[0047] The circuit structure of this invention for implementing lead-lag commutation in motors, compared to existing technologies, allows for simple and intuitive implementation of lead-lag settings for square wave motors by combining specific hardware structures. It integrates dedicated logic circuits for motors, requiring only a few register assignments for both speed acquisition and lead-lag commutation between phases, eliminating the need for multiplication, division, and interrupt operations, thus significantly reducing software workload. Furthermore, the lead and lag functions can use the same code, saving program space. In applications requiring switching between square wave and sine wave modes, this invention allows for direct switching without vibration or connection issues. Attached Figure Description

[0048] Figure 1 This is a schematic diagram illustrating the implementation principle of the circuit structure for realizing the motor's leading-lagging commutation according to the present invention.

[0049] Figure 2 This is a schematic diagram illustrating the working principle of the PWM generator used in the circuit structure for realizing motor lead-lag commutation according to the present invention.

[0050] Figure 3 This is a schematic diagram illustrating the working principle of the Hall angle mapping module of the present invention.

[0051] Figure 4 This is a schematic diagram illustrating the working principle of the Hall angle update module of the present invention.

[0052] Figure 5 This is a schematic diagram of the synchronous incremental signal generation of the three-phase angle generation module of the present invention.

[0053] Figure 6 This is a schematic diagram illustrating the working principle of the three-phase angle generation module of the present invention.

[0054] Figure 7 This is a schematic diagram illustrating the working principle of the angle conversion module of the present invention.

[0055] Figure 8 This is a schematic diagram illustrating the working principle of the PWM generation module of the present invention. Detailed Implementation

[0056] To more clearly describe the technical content of the present invention, the following description is provided in conjunction with specific embodiments.

[0057] Before describing the embodiments of the present invention in detail, it should be noted that, in the following, the terms “comprising,” “including,” or any other variations are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed or inherent to such process, method, article, or apparatus.

[0058] Please see Figure 1 As shown, the circuit structure for realizing the leading and lagging commutation of a motor includes:

[0059] The Hall angle mapping module is connected to the Hall module of the external motor. It is used to receive the three Hall signals generated by the Hall module and convert the three Hall signals into Hall synchronization angle values ​​respectively.

[0060] The Hall angle update module, connected to the Hall angle mapping module, is used to select the corresponding angle update mode according to the internal logic of the circuit structure.

[0061] The three-phase angle generation module is connected to the Hall angle update module and is used to perform time-division calculation on the angle generated by the Hall angle update module to generate the current three-phase angle signal of the three Hall signals.

[0062] An angle conversion module, connected to the three-phase angle generation module, is used to perform corresponding angle conversions on the three-phase angle signals generated by the three-phase angle generation module; and

[0063] The PWM generation module, connected to the angle conversion module, is used to generate the three-phase six-channel complementary PWM waveform of the circuit structure.

[0064] Please see Figure 3 As shown, in a preferred embodiment of the present invention, the Hall angle mapping module compiles and processes the three Hall signals generated by the Hall module of the external motor through a 3-8 decoder unit to generate corresponding register configuration signals for setting the phase offset of the Hall signals. After each register configuration signal is processed by AND gate and OR gate, the Hall synchronization angle value corresponding to the three Hall signals is generated.

[0065] In a preferred embodiment of the present invention, the register configuration signal sets the phase bias of the Hall signal, specifically as follows:

[0066] The register configuration signal sets the phase offset of the corresponding Hall signal according to the placement position of the three Hall elements, specifically including:

[0067] Register 5 is configured to set the phase offset of the corresponding Hall signal to 0°.

[0068] Register 1 configuration signal is used to set the phase offset of the corresponding Hall signal to 60°;

[0069] Register 3 configuration signal is used to set the phase offset of the corresponding Hall signal to 120°;

[0070] Register 2 configuration signal is used to set the phase offset of the corresponding Hall signal to 180°;

[0071] Register 6 configuration signal is used to set the phase offset of the corresponding Hall signal to 240°;

[0072] Register 4 configuration signal is used to set the phase offset of the corresponding Hall signal to 300°;

[0073] Phase-leading commutation and phase-lag commutation can be achieved by changing the phase bias of the Hall signal.

[0074] Please see Figure 4 As shown, in a preferred embodiment of the present invention, the Hall angle update module includes:

[0075] A first register, wherein the high-level input terminal of the first register is connected to the Hall synchronization angle value, the clock terminal of the first register is input with a clock signal clk, the S-input terminal of the first register is input with a state update signal HALL_change, and the output terminal of the first register outputs the processed unidirectional angle Degree_A; and

[0076] The first adder has a first input terminal that receives a unidirectional angle Degree_A for angle addition calculation, a second input terminal that receives an angle count increment signal Degree_in, and an output terminal that sends the angle variable generated after addition to the low-level input terminal of the first register for angle update processing.

[0077] Please see Figure 6 As shown, in a preferred embodiment of the present invention, the three-phase angle generation module includes:

[0078] The second register has a high-level input terminal that receives the first timing input signal C0 and calculates the sine signal sin(Degree) at time C0. The clock terminal of the second register receives the system clock signal HCLK and the output terminal of the second register outputs the first synchronization increment signal Add_1 and calculates the sine signal sin(Degree+120°) at time Add_1.

[0079] The third register has a high-level input terminal connected to the first synchronization increment signal Add_1, a clock terminal connected to the system clock signal HCLK, and an output terminal connected to the second synchronization increment signal Add_2. The sine signal sin(Degree+240°) at time Add_2 is calculated.

[0080] The second adder receives the sinusoidal signals sin(Degree+120°) at time Add_1 and sin(Degree+240°) at time Add_2 after AND and OR gate processing, and inputs them to its first input terminal. The second input terminal receives the unidirectional angle Degree_A. The output terminal of the second adder, after addition processing, outputs the real-time signal Degree.

[0081] The first subtractor has its first input terminal connected to the real-time signal Degree, and its second input terminal connected to a 360° sine wave signal. The output terminal of the first subtractor performs subtraction on the input signal to generate the current three-phase angle output sine wave signal Sin_degree_pre of the circuit structure.

[0082] Please see Figure 7 As shown, in a preferred embodiment of the present invention, the angle conversion module includes:

[0083] The first quadrant angle conversion module is used to convert the three-phase angle output sinusoidal signal Sin_degree_pre that meets the requirements into a first quadrant angle signal Degree_1_90, and then process the first quadrant angle signal Degree_1_90 and the current three-phase angle output sinusoidal signal Sin_degree_pre with AND gates and OR gates to generate a real-time sinusoidal signal Sin_degree.

[0084] The second quadrant angle conversion module is used to convert the three-phase angle output sinusoidal signal Sin_degree_pre that meets the requirements into a second quadrant angle signal Degree_91_180, and then perform AND and OR gate processing on the second quadrant angle signal Degree_91_180 and the current three-phase angle output sinusoidal signal 180°-Sin_degree_pre generated after angle conversion to generate a real-time sinusoidal signal Sin_degree.

[0085] The third quadrant angle conversion module is used to convert the required three-phase angle output sinusoidal signal Sin_degree_pre to a third quadrant angle signal Degree_181_270, and then perform AND and OR gate processing on the third quadrant angle signal Degree_181_270 and the currently converted three-phase angle output sinusoidal signal Sin_degree_pre - 180° to generate a real-time sinusoidal signal Sin_degree; and

[0086] The fourth quadrant angle conversion module is used to convert the three-phase angle output sinusoidal signal Sin_degree_pre that meets the requirements into a fourth quadrant angle signal Degree_271_360. Then, the fourth quadrant angle signal Degree_271_360 is processed with the current three-phase angle output sinusoidal signal 360°-Sin_degree_pre after angle conversion through AND and OR gates to generate the real-time sinusoidal signal Sin_degree.

[0087] Please see Figure 8 As shown, in a preferred embodiment of the present invention, the PWM generation module includes:

[0088] The Sin function generator is used to input the real-time sine signal Sin_degree and, after processing, generates an output sine signal Sinout.

[0089] The second subtractor receives the output sine signal Sinout at its first input terminal and a 30° sine signal at its second input terminal. The second subtractor determines the sign bit of the input signal and outputs the result signal of the sign bit determination of the input signal at its output terminal.

[0090] The first trigger module receives the judgment result signal from the output of the second subtractor at its input terminal, and the clock terminal of the first trigger module receives the first timing input signal C0 and the system clock signal HCLK. The output terminal of the first trigger module is connected to the input terminal of the first inverter, the output terminal of the first inverter is connected to the first input terminal of the AND gate, the second input terminal of the AND gate receives the amplitude signal, and the conduction state of the upper and lower bridge arms of the corresponding Hall signal is determined according to the signal conduction timing.

[0091] The second trigger module has its first input terminal connected to the judgment result signal of the output terminal of the second subtractor, and its clock terminal inputs the first synchronous increment signal Add_1 and the system clock signal HCLK. The output terminal of the second trigger module is connected to the input terminal of the second inverter, and the output terminal of the second inverter is connected to the first input terminal of the AND gate. The second input terminal of the AND gate inputs an amplitude signal, and the conduction state of the upper and lower bridge arms of the corresponding Hall signal is determined according to the signal conduction timing.

[0092] The third trigger module has its first input connected to the judgment result signal of the output of the second subtractor, and its clock input includes the second synchronous increment signal Add_2 and the system clock signal HCLK. The output of the third trigger module is connected to the input of the third inverter, and the output of the third inverter is connected to the first input of the AND gate. The second input of the AND gate receives an amplitude signal, and the conduction status of the upper and lower bridge arms of the corresponding Hall signal is determined according to the signal conduction timing.

[0093] In a preferred embodiment of the present invention, the conduction state of the upper and lower bridge arms of the corresponding Hall signal changes according to the following rules:

[0094] When the conduction timing is in the first quadrant, that is, when the sinusoidal signal sin(Degree) at the unidirectional angles Degree_A and C0 is in the first quadrant, the upper arm sign bit Sign_sin of the corresponding Hall signal is 1 and the lower arm sign bit Sign_sin_n is 0, then the upper arm of the corresponding Hall signal is turned on.

[0095] When the conduction timing is in the second quadrant, that is, when the sinusoidal signal sin(Degree) at the unidirectional angles Degree_A and C0 is in the second quadrant, the upper arm sign bit Sign_sin of the corresponding Hall signal is 1 and the lower arm sign bit Sign_sin_n is 0, then the upper arm of the corresponding Hall signal is turned on.

[0096] When the conduction timing is in the third quadrant, that is, when the sinusoidal signal sin(Degree) at the unidirectional angles Degree_A and C0 is in the third quadrant, the upper arm sign bit Sign_sin of the corresponding Hall signal is 0 and the lower arm sign bit Sign_sin_n is 1, then the lower arm of the corresponding Hall signal is turned on.

[0097] When the conduction timing is in the fourth quadrant, that is, when the sinusoidal signal sin(Degree) at the unidirectional angles Degree_A and C0 is in the fourth quadrant, the upper arm sign bit Sign_sin of the corresponding Hall signal is 0 and the lower arm sign bit Sign_sin_n is 1, then the lower arm of the corresponding Hall signal is turned on.

[0098] In one specific embodiment of the present invention, the workflow of this technical solution is as follows: The three-channel HALL signals generated by the Hall module of the external motor are converted into HALL synchronization angle values ​​according to the configuration of the Hall angle mapping module. The Hall angle update module selects whether to use the HALL synchronization angle or auto-increment based on Degree_inc according to its internal logic. Because there is only one sine function generator in this invention, and a three-phase motor is controlled, a three-phase angle generation module is used to perform time-division calculation on the single-phase angle Degree_A generated by the Hall angle update module to obtain the three-phase angle and generate Sin_degree_pre. Due to the various symmetries of the sine angle, only the angle in the first quadrant needs to be calculated. This invention adopts this approach, only calculating the phase value in the range of 0° to 90°. Therefore, the generated Sin_degree_pre needs to be converted, and the PWM generation module generates a three-phase six-channel complementary PWM waveform. The PWM generator and the system clock participate meticulously in the work of other modules.

[0099] In one specific embodiment of the present invention, please refer to Figure 2 As shown, the square wave control or sine wave control of the motor in this invention requires, as follows: Figure 2 The PWM generator shown in the figure has C0 as the starting point of the PWM signal. This invention configures the three-phase duty cycle by configuring only one amplitude register, and the lead-lag method is also incorporated into it.

[0100] In one specific embodiment of the present invention, the placement positions of different motor HALL components may vary slightly. This variation can be addressed by configuring the angle corresponding to the register, and by modifying... Figure 3 By configuring register x (x can be 1 to 6) in the register, this deviation can be corrected. Lead-lag control works on a similar principle; by biasing the entire register, lead or lag switching can be achieved.

[0101] For example:

[0102] Ideally, the signal difference between two consecutive phase signals is 60 degrees, as follows:

[0103] 5->0° 4->60° 6->120° 2->180° 3->240° 1->300°

[0104] However, if the test reveals some phase lag, the angle offset needs to be increased, for example, by 20 degrees.

[0105] 5->20° 4->80° 6->140° 2->200° 3->260° 1->320°

[0106] In this way, advanced commutation can be achieved.

[0107] Similarly, if phase lead is found at this point, the base offset needs to be reduced, or even offset in the negative direction, such as -10 degrees.

[0108] 5->350° 4->50° 6->110° 2->170° 3->230° 1->290°

[0109] This achieves delayed commutation.

[0110] Although the HALL signal has three lines, theoretically corresponding to eight states from 0b000 to 0b111, for three HALL components placed at an angle of 120 degrees apart, there are only six combinations of signals from 1 to 6. Moreover, depending on whether it is forward or reversed, its HALL value is either 5 4 6 2 3 1 or 5 1 3 2 6 4. This technical solution only provides an example of one of these combinations.

[0111] In one specific embodiment of the present invention, such as Figure 4 As shown, this invention is based on a sine wave generator to produce a square wave control signal. The calculation of the sine wave requires a higher angle accuracy than 60° (60° is the accuracy of square wave control). Therefore, the motor speed needs to be calculated based on the counter value N every 60°. The counting clock is a C0 signal (a higher accuracy can be set based on application requirements). 60° / N (degrees / PWM cycle) is then the angle count increment Degree_inc. This current angle increment Degree_inc is added to the previous single-phase angle Degree_A to obtain the current angle of the Hall signal. The aforementioned single-phase angle Degree_A is continuously incremented based on the angle increment. Simultaneously, the single-phase angle Degree_A can also change according to the state of HALL. When the signal indicating a state change in HALL_change is updated, the rotor position angle represented by HALL will be synchronized to the single-phase angle Degree_A in the form of an integer value, thus changing the angle itself. Figure 4The "HALL synchronization angle" input can be understood as follows: for a square wave, HALL means the commutation phase sequence itself. However, for this technical solution, the HALL value represents a synchronization angle. This angle plays the role of synchronization angle information when the HALL state changes, synchronizing the angle accumulated by the adder to the HALL synchronization angle.

[0112] In one specific embodiment of the present invention, there is only one sine function generator. For three-phase signals, the three-phase sine waves need to be calculated in a time-division manner. C0 is the first timing. The sine calculation used in this invention requires one HCLK clock (system clock). Therefore, this clock is used to synchronize the Add_1 signal, which is one HCLK phase different from C0, and the Add_2 signal, which is two HCLK phase different from C0 (see...). Figure 5 As shown), when the Add_1 signal is on its rising edge, and when the HALL information is updated (i.e., HALL_change is 1), the corresponding angle will be updated to Degree_A with the highest priority. For example:

[0113] 5->0° 4->60° 6->120° 2->180° 3->240° 1->300°;

[0114] Then the sine calculation begins, which is performed using time-sharing. At time C0, sin(Degree) is calculated; at time Add_1, sin(Degree+120°) is calculated; and at time Add_2, sin(Degree+240°) is calculated.

[0115] In one specific embodiment of the present invention, the sine calculation in the present invention can only calculate between 0° and 90°, therefore angle conversion is still required, such as... Figure 7 As shown, the sine value is calculated directly between 0° and 90°. Between 90° and 180°, the calculation is converted to sin(180° - degree). Between 180° and 270°, the calculation is converted to sin(degree - 180°). Between 270° and 360°, the calculation is converted to sin(360° - degree). For sine values ​​between 180° and 360° that are negative, the corresponding Sign_sin sign is 0; when the sine value is positive, Sign_sin is 1.

[0116] In one specific embodiment of the present invention, during square wave control, the conduction time of each phase is 120 degrees, followed by a 60-degree suspension, and finally conduction is initiated in the other arm of the same phase, as follows: Figure 8As shown, the output range of the sin function generator is 0 to 1ff, where 0x7f represents sin(30°) and 0x1ff represents sin(90°). When the sin_degree angle is between 30° and 90°, it is time for the circuit to be turned on. Whether the upper or lower bridge arm is turned on depends on the sign_sin bit. For the range of 0° to 360°, the upper bridge arm is turned on between 30° and 150°, and the lower bridge arm is turned on between 210° and 330°. The sign_sin bit is 1 between 0° and 180° and 0 between 180° and 360°, as shown in Table 1.

[0117] Table 1. Angle Conversion and Upper / Lower Arm Conductivity Comparison Table

[0118] Degree_A Sin_degree (0°~90°) Sign_sin Sign_sin_n Conduction timing upper and lower bridge arms conduction 0°～90° Degree_A 1 0 30°～90° Upper arm conduction 90°～180° 180-Degree_A 1 0 90°～150° Upper arm conduction 180°～270° Degree_A-180 0 1 210°～270° Lower arm conduction 270°～360° 360-Degree_A 0 1 270°～330° Lower arm conduction

[0119] Meanwhile, the examples of the modules listed above in this technical solution all use the Hall sensor mode as an example. In fact, the same principle applies to the non-sensor BEMF back-electromagnetic signal. By adjusting the configuration of the six registers in the Hall angle mapping module, lead and lag commutation can be achieved. The same or similar parts involved will not be elaborated here.

[0120] It should be understood that various parts of the present invention can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution device.

[0121] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0122] In the description of this specification, references to terms such as "an embodiment," "some embodiments," "example," "specific example," or "embodiment," "implementation," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0123] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

[0124] The circuit structure of this invention for implementing lead-lag commutation in motors, compared to existing technologies, allows for simple and intuitive implementation of lead-lag settings for square wave motors by combining specific hardware structures. It integrates dedicated logic circuits for motors, requiring only a few register assignments for both speed acquisition and lead-lag commutation between phases, eliminating the need for multiplication, division, and interrupt operations, thus significantly reducing software workload. Furthermore, the lead and lag functions can use the same code, saving program space. In applications requiring switching between square wave and sine wave modes, this invention allows for direct switching without vibration or connection issues.

[0125] In this specification, the invention has been described with reference to specific embodiments thereof. However, it will be apparent that various modifications and variations can be made without departing from the spirit and scope of the invention. Therefore, the specification and drawings should be considered illustrative rather than restrictive.

Claims

1. A circuit structure for realizing lead-lag commutation of a motor, characterized in that, The circuit structure includes: The Hall angle mapping module is connected to the Hall module of the external motor. It is used to receive the three Hall signals generated by the Hall module and convert the three Hall signals into Hall synchronization angle values ​​respectively. The Hall angle update module, connected to the Hall angle mapping module, is used to select the corresponding angle update mode according to the internal logic of the circuit structure. The three-phase angle generation module is connected to the Hall angle update module and is used to perform time-division calculation on the angle generated by the Hall angle update module to generate the current three-phase angle signal of the three Hall signals. An angle conversion module, connected to the three-phase angle generation module, is used to perform corresponding angle conversions on the three-phase angle signals generated by the three-phase angle generation module; and The PWM generation module, connected to the angle conversion module, is used to generate the three-phase six-channel complementary PWM waveform of the circuit structure. The Hall angle mapping module uses a 3-8 decoder unit to compile and process the three Hall signals generated by the Hall module of the external motor, generating corresponding register configuration signals for setting the phase offset of the Hall signals. After each register configuration signal is processed by AND and OR gates, the Hall synchronization angle value corresponding to the three Hall signals is generated. The register configuration signal sets the phase offset of the Hall signal, specifically as follows: The register configuration signal sets the phase offset of the corresponding Hall signal according to the placement position of the three Hall elements, specifically including: Register 5 is configured to set the phase offset of the corresponding Hall signal to 0°. Register 1 configuration signal is used to set the phase offset of the corresponding Hall signal to 60°; Register 3 configuration signal is used to set the phase offset of the corresponding Hall signal to 120°; Register 2 configuration signal is used to set the phase offset of the corresponding Hall signal to 180°; Register 6 configuration signal is used to set the phase offset of the corresponding Hall signal to 240°; Register 4 configuration signal is used to set the phase offset of the corresponding Hall signal to 300°; Phase-leading commutation and phase-lag commutation can be achieved by changing the phase bias of the Hall signal.

2. The circuit structure for realizing lead-lag commutation of a motor according to claim 1, characterized in that, The Hall angle update module includes: A first register, wherein the high-level input terminal of the first register is connected to the Hall synchronization angle value, the clock terminal of the first register is input with a clock signal clk, the S-input terminal of the first register is input with a state update signal HALL_change, and the output terminal of the first register outputs the processed unidirectional angle Degree_A; and The first adder has a first input terminal that receives a unidirectional angle Degree_A for angle addition calculation, a second input terminal that receives an angle count increment signal Degree_in, and an output terminal that sends the angle variable generated after addition to the low-level input terminal of the first register for angle update processing.

3. The circuit structure for realizing motor lead-lag commutation according to claim 2, characterized in that, The three-phase angle generation module includes: The second register has a high-level input terminal that receives the first timing input signal C0 and calculates the sine signal sin(Degree) at time C0. The clock terminal of the second register receives the system clock signal HCLK and the output terminal of the second register outputs the first synchronization increment signal Add_1 and calculates the sine signal sin(Degree +120°) at time Add_1. The third register has a high-level input terminal connected to the first synchronization increment signal Add_1, a clock terminal connected to the system clock signal HCLK, and an output terminal connected to the second synchronization increment signal Add_2. The sine signal sin(Degree +240°) at time Add_2 is calculated. The second adder receives the sinusoidal signals sin(Degree + 120°) at time Add_1 and sin(Degree + 240°) at time Add_2 after AND and OR gate processing, and inputs them to its first input terminal. The second input terminal receives the unidirectional angle Degree_A. The output terminal of the second adder, after addition processing, outputs the real-time signal Degree. The first subtractor has its first input terminal connected to the real-time signal Degree, and its second input terminal connected to a 360° sine wave signal. The output terminal of the first subtractor performs subtraction on the input signal to generate the current three-phase angle output sine wave signal Sin_degree_pre of the circuit structure.

4. The circuit structure for realizing motor lead-lag commutation according to claim 3, characterized in that, The angle conversion module includes: The first quadrant angle conversion module is used to convert the three-phase angle output sinusoidal signal Sin_degree_pre that meets the requirements into a first quadrant angle signal Degree_1_90, and then process the first quadrant angle signal Degree_1_90 and the current three-phase angle output sinusoidal signal Sin_degree_pre with AND gates and OR gates to generate a real-time sinusoidal signal Sin_degree. The second quadrant angle conversion module is used to convert the three-phase angle output sinusoidal signal Sin_degree_pre that meets the requirements into a second quadrant angle signal Degree_91_180, and then perform AND and OR gate processing on the second quadrant angle signal Degree_91_180 and the current three-phase angle output sinusoidal signal 180°-Sin_degree_pre generated after angle conversion to generate a real-time sinusoidal signal Sin_degree. The third quadrant angle conversion module is used to convert the required three-phase angle output sinusoidal signal Sin_degree_pre to a third quadrant angle signal Degree_181_270, and then perform AND and OR gate processing on the third quadrant angle signal Degree_181_270 and the currently converted three-phase angle output sinusoidal signal Sin_degree_pre - 180° to generate a real-time sinusoidal signal Sin_degree; and The fourth quadrant angle conversion module is used to convert the three-phase angle output sinusoidal signal Sin_degree_pre that meets the requirements into a fourth quadrant angle signal Degree_271_360. Then, the fourth quadrant angle signal Degree_271_360 is processed with the current three-phase angle output sinusoidal signal 360°-Sin_degree_pre after angle conversion through AND and OR gates to generate the real-time sinusoidal signal Sin_degree.

5. The circuit structure for realizing motor lead-lag commutation according to claim 4, characterized in that, The PWM generation module includes: The Sin function generator is used to input the real-time sine signal Sin_degree and, after processing, generates an output sine signal Sinout. The second subtractor receives the output sine signal Sinout at its first input terminal and a 30° sine signal at its second input terminal. The second subtractor determines the sign bit of the input signal and outputs the result signal of the sign bit determination of the input signal at its output terminal. The first trigger module receives the judgment result signal from the output of the second subtractor at its input terminal, and the clock terminal of the first trigger module receives the first timing input signal C0 and the system clock signal HCLK. The output terminal of the first trigger module is connected to the input terminal of the first inverter, the output terminal of the first inverter is connected to the first input terminal of the AND gate, the second input terminal of the AND gate receives the amplitude signal, and the conduction state of the upper and lower bridge arms of the corresponding Hall signal is determined according to the signal conduction timing. The second trigger module has its first input terminal connected to the judgment result signal of the output terminal of the second subtractor, and its clock terminal inputs the first synchronous increment signal Add_1 and the system clock signal HCLK. The output terminal of the second trigger module is connected to the input terminal of the second inverter, and the output terminal of the second inverter is connected to the first input terminal of the AND gate. The second input terminal of the AND gate inputs an amplitude signal, and the conduction state of the upper and lower bridge arms of the corresponding Hall signal is determined according to the signal conduction timing. The third trigger module has its first input connected to the judgment result signal of the output of the second subtractor, and its clock input includes the second synchronous increment signal Add_2 and the system clock signal HCLK. The output of the third trigger module is connected to the input of the third inverter, and the output of the third inverter is connected to the first input of the AND gate. The second input of the AND gate receives an amplitude signal, and the conduction status of the upper and lower bridge arms of the corresponding Hall signal is determined according to the signal conduction timing.

6. The circuit structure for realizing lead-lag commutation of a motor according to claim 5, characterized in that, The conduction states of the upper and lower bridge arms of the corresponding Hall signal change according to the following rules: When the conduction timing is in the first quadrant, that is, when the sinusoidal signal sin(Degree) at the unidirectional angles Degree_A and C0 is in the first quadrant, the upper arm sign bit Sign_sin of the corresponding Hall signal is 1 and the lower arm sign bit Sign_sin_n is 0, then the upper arm of the corresponding Hall signal is turned on. When the conduction timing is in the second quadrant, that is, when the sinusoidal signal sin(Degree) at the unidirectional angles Degree_A and C0 is in the second quadrant, the upper arm sign bit Sign_sin of the corresponding Hall signal is 1 and the lower arm sign bit Sign_sin_n is 0, then the upper arm of the corresponding Hall signal is turned on. When the conduction timing is in the third quadrant, that is, when the sinusoidal signal sin(Degree) at the unidirectional angles Degree_A and C0 is in the third quadrant, the upper arm sign bit Sign_sin of the corresponding Hall signal is 0 and the lower arm sign bit Sign_sin_n is 1, then the lower arm of the corresponding Hall signal is turned on. When the conduction timing is in the fourth quadrant, that is, when the sinusoidal signal sin(Degree) at the unidirectional angles Degree_A and C0 is in the fourth quadrant, the upper arm sign bit Sign_sin of the corresponding Hall signal is 0 and the lower arm sign bit Sign_sin_n is 1, then the lower arm of the corresponding Hall signal is turned on.

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