A frequency converter control method and device, electronic equipment and storage medium

Abstract

The application belongs to the technical field of converter control, and particularly relates to a frequency converter control method and device, electronic equipment and a storage medium. The frequency converter control method comprises the following steps: comparing the comparison values of the upper bridge arm switching tubes of each path, recording the comparison value in the middle size as a first comparison value; recording the PWM signal output by the upper bridge arm switching tube corresponding to the first comparison value as a to-be-flipped signal; and performing flipping processing on the to-be-flipped signal. The technical scheme can replace the zero vector with two basic vectors with a phase difference of 180 degrees, so as to eliminate the existence of the zero vector, ensure the realization of inverse variable modulation of the non-zero vector, reduce the impact of the bus current on the electrolytic capacitor, prolong the service life of the electrolytic capacitor, and improve the system stability.

Description

Technical Field

[0001] This invention belongs to the technical field of inverter control, specifically relating to an inverter control method, device, electronic equipment, and storage medium. Background Technology

[0002] With the development of microprocessors, space vector pulse width modulation (SVPWM), which boasts significant advantages such as easy digitization, high DC voltage utilization, and low harmonic content, has become a widely researched and applied PWM (Pulse Width Modulation) modulation technique. Space vector control is primarily used in motor drives, and the initial development of this control method was inextricably linked to the field-oriented control of motors. In the 1970s, to control AC motor loads, three-phase AC motor systems were transformed into two-phase coordinate systems through vector exchange for control. This transformation converted the originally strongly coupled three-phase AC motor system into an equivalent two-phase DC system, significantly reducing coupling and allowing control to be performed in a manner similar to that of a DC motor.

[0003] In the control system of a brushless DC motor, energy is mainly supplied to the downstream load through an AC-DC-AC frequency converter. For example... Figure 1 The AC-DC-AC inverter drive topology shown uses a single-phase uncontrolled rectifier 100 to rectify the mains frequency AC power into a constant DC voltage. A large-capacity electrolytic capacitor 110 then reduces DC voltage ripple, providing a stable DC voltage for the inverter unit 120. Each arm of the inverter unit 120 consists of two series-connected switching transistors, with the series connection point controlling one phase of the motor M. The SVPWM modulation process involves outputting SVPWM inverter signals to these switching transistors. This is primarily achieved by eight combined vectors controlling the switching transistors on different arms, six of which are base vectors and two are zero vectors. In digital signal processor (DSP) control applications, a seven-segment vector inverter is typically used. However, the presence of zero vectors in this configuration can cause severe fluctuations in the bus current, significantly reducing the lifespan of the electrolytic capacitors and impacting the reliability of the drive control system over time. Summary of the Invention

[0004] To address the issue of significant fluctuations in bus current caused by the presence of a zero vector during inverter operation, which can impact capacitors, this invention provides a frequency converter control method, device, electronic equipment, and storage medium. These methods ensure non-zero vector inverter modulation, thereby reducing the impact of bus current on electrolytic capacitors, extending their service life, and improving system stability.

[0005] In a first aspect, the present application provides a frequency converter control method, the method comprising:

[0006] determining a comparison value of each upper bridge arm switch according to a duty ratio of a PWM signal output by the upper bridge arm switch and a carrier period;

[0007] comparing the comparison values of the upper bridge arm switches, recording a comparison value in the middle as a first comparison value, and recording a PWM signal output by the upper bridge arm switch corresponding to the first comparison value as a signal to be flipped;

[0008] flipping the signal to be flipped.

[0009] In some embodiments of the present application, the flipping of the signal to be flipped comprises:

[0010] complementarily outputting the first comparison value to obtain a new first comparison value;

[0011] comparing an instantaneous value of the carrier with the new first comparison value within a period of the carrier to determine a level of the signal to be flipped after flipping.

[0012] In some embodiments of the present application, the complementarily outputting of the first comparison value to obtain a new first comparison value comprises determining the new first comparison value according to a difference between an amplitude of the carrier and the first comparison value.

[0013] In some embodiments of the present application, the comparing of the instantaneous value of the carrier with the new first comparison value within the period of the carrier to determine the level of the signal to be flipped after flipping comprises:

[0014] when the instantaneous value of the carrier is greater than the new first comparison value, the level of the signal to be flipped after flipping is a low level; and when the instantaneous value of the carrier is less than the new first comparison value, the level of the signal to be flipped after flipping is a high level.

[0015] In a second aspect, the present application provides a frequency converter control device, the device comprising:

[0016] a calculation module configured to determine a comparison value of each upper bridge arm switch according to a duty ratio of a PWM signal output by the upper bridge arm switch and a carrier period;

[0017] a comparison module configured to compare the comparison values of the upper bridge arm switches, record a comparison value in the middle as a first comparison value, and record a PWM signal output by the upper bridge arm switch corresponding to the first comparison value as a signal to be flipped;

[0018] The control module is configured to perform a flipping process on the signal to be flipped.

[0019] In some embodiments of the present application, the control module comprises:

[0020] The complementary output module is configured to output the first comparison value complementarily to obtain a new first comparison value.

[0021] The flipping module is configured to compare the instantaneous value of the carrier with the new first comparison value in a carrier generation period, and determine the level of the signal to be flipped after flipping.

[0022] In some embodiments of the present application, the complementary output module is configured to determine the new first comparison value according to the difference between the amplitude of the carrier and the first comparison value.

[0023] In some embodiments of the present application, the flipping module comprises:

[0024] The counting comparison module is configured to compare the instantaneous value of the carrier with the new first comparison value in the carrier generation period.

[0025] The action module is configured to determine the level of the signal to be flipped after flipping as a low level when the instantaneous value of the carrier is greater than the new first comparison value, and determine the level of the signal to be flipped after flipping as a high level when the instantaneous value of the carrier is less than the new first comparison value, in the carrier generation period.

[0026] In a third aspect, the present application provides an electronic device comprising a memory and a processor, wherein the memory stores a computer program, and the computer program is executed by the processor to implement the variable frequency converter control method according to any one of the first aspect.

[0027] In some embodiments of the present application, the electronic device comprises at least one of a refrigerator, a washing machine, and an air conditioner.

[0028] In a fourth aspect, the present application provides a storage medium storing a computer program, wherein the computer program is executed by one or more processors, and can be used to implement the variable frequency converter control method according to any one of the first aspect.

[0029] Compared with the prior art, one or more embodiments of the above solution can have the following advantages or beneficial effects:

[0030] The variable frequency converter control method provided by the application can replace the zero vector with two basic vectors with a phase difference of 180 degrees to eliminate the existence of the zero vector. In the motor control process, the voltage vectors of other sectors can follow the flip rule to ensure the realization of non-zero vector inversion modulation, reduce the impact of bus current on electrolytic capacitors, prolong the service life of electrolytic capacitors, and improve the stability of the system. BRIEF DESCRIPTION OF DRAWINGS

[0031] The scope of the present disclosure can be better understood by reading the following detailed description of exemplary embodiments in conjunction with the accompanying drawings. The drawings included in the present disclosure are as follows:

[0032] Figure 1 for AC-DC-AC variable frequency drive topology;

[0033] Figure 2 for the control system block diagram of the direct current brushless motor provided by the first embodiment of the application;

[0034] Figure 3 for the three PWM combination before flip and bus current waveform provided by the first embodiment of the application;

[0035] Figure 4 for the variable frequency converter control method implementation flowchart provided by the first embodiment of the application;

[0036] Figure 5 for the three PWM signals and bus current waveform provided by the first embodiment of the application after flip;

[0037] Figure 6 for the register rule schematic diagram provided by the second embodiment of the application;

[0038] Figure 7 for the structure schematic diagram of the variable frequency converter control device provided by the third embodiment of the application;

[0039] Figure 8 for the structure block diagram of the electronic device provided by the fourth embodiment of the application. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical scheme and advantages of the present application more clear, the following will combine the present application with the drawings to make further detailed description, the described embodiments should not be regarded as the limitation of the present application, all other embodiments obtained by the person skilled in the art without creative labor are within the scope of protection of the present application.

[0041] In the following description, "some embodiments" are related to a subset of all possible embodiments, but it can be understood that "some embodiments" can be the same subset or different subset of all possible embodiments, and can be combined with each other without conflict.

[0042] If the application file appears "first\second\third" similar description is added the following description, the term "first\second\third" involved in the following description is only to distinguish similar objects, not represent the specific order of the object, can be understood, "first\second\third" in the case of permission can be exchanged specific order or sequence, so that the application described herein can be implemented in addition to the order illustrated or described.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the specification herein is for describing the embodiments of the application only and is not intended to be limiting of the application.

[0044] Example One

[0045] The application is directed to a control system of a direct-current brushless motor, taking a three-phase motor as an example, as shown in the AC-DC-AC frequency conversion driving topology, including an inverter unit 120, a motor M and a microprocessor, a power frequency AC power supply is rectified into a constant voltage DC voltage through a single-phase uncontrolled rectifier 100, and then a large-capacity electrolytic capacitor 110 is used to reduce the DC voltage ripple to provide a stable DC voltage for the inverter unit 120. Each bridge arm of the inverter unit 120 is composed of two switch tubes connected in series, and the output of the series connection point controls one phase of the motor M. Figure 1 The control algorithm of the direct-current brushless motor is mainly implemented in the microprocessor, as shown in the control system block diagram of the direct-current brushless motor

[0046] Figure 2 The control algorithm of the direct-current brushless motor is mainly implemented in the microprocessor, as shown in the control system block diagram of the direct-current brushless motor d d q ​​​Subtracting, the result is obtained through the current loop 210 to get the Q-axis voltage command value Vqref; again through the iPark conversion module 230 the D-axis voltage command value Vdref and the Q-axis voltage command value Vqref in the two-phase rotating dq coordinate system are converted into the alpha-axis voltage V α and the beta-axis voltage V β .

[0047] Wherein, the iPark conversion formula is:

[0048]

[0049] Finally through the SVPWM module 240, the action time of each voltage vector of the motor M in a control cycle is calculated, and the voltage vector action time is optimized to generate the SVPWM inverter signal of the switching tube, and input to the inverter unit 120 to drive the motor M.

[0050] Suppose the alpha-axis voltage V α and the beta-axis voltage V β in the two-phase static αβ coordinate system corresponding to the voltage space vector are K and K / sqrt(3), respectively, and the angle θ of the motor rotor is 30°, the duty cycle of the PWM (Pulse Width Modulation) signal output by the upper bridge arm switching tube of the three roads is calculated through the SVPWM module 240, that is, the lower bridge arm and the upper bridge arm output complementarily. Among them, the specific calculation method of the duty cycle of the PWM signal is the common SVPWM control, that is, judging the interval position of the reference voltage vector, and then synthesizing the reference voltage vector by using the adjacent two voltage vectors in the sector and the appropriate zero vector. Among them, the calculation process of the voltages V A , V B , V C of the three roads of the motor A, B and C is:

[0051]

[0052] The SVPWM module 240 calculates the CMP values corresponding to the three upper bridge arm switching tubes according to the duty cycle of the PWM signal output by the three upper bridge arm switching tubes and the carrier cycle, which are CMPA, CMPB and CMPC, as shown in Figure 3 The three road PWM combination before flipping and the bus current waveform, at this time the voltage space vector is decomposed into the sum of 2 parts of 4 vectors (100) + 2 parts of 6 vectors (110) + 4 parts of zero vectors (000 and 111). At this time the bus current waveform is suddenly changed to 0 when passing through the zero vector, which will cause impact to the capacitor and affect its service life.

[0053] Therefore, the application provides a variable frequency converter control method, which can ensure the realization of inverse variable modulation of a non-zero vector, reduce the impact of bus current on an electrolytic capacitor, prolong the service life of the electrolytic capacitor, and improve system stability. The method is not limited to air conditioner products, and can be applied to devices using a variable frequency converter.

[0054] Figure 4 A variable frequency converter control method implementation flowchart provided by the embodiment of the application is shown in Figure 4 The method is applied to an electronic device 400, which can be a computer, a mobile terminal, or the like. The function realized by the variable frequency converter control method provided by the embodiment of the application can be realized by calling program code by a processor 402 in the electronic device 400, wherein the program code can be saved in a computer storage medium. The embodiment provides a variable frequency converter control method, which comprises the following steps.

[0055] In step S100, the comparison values of the upper bridge arm switching tubes of the respective paths are determined according to the duty ratios and carrier periods of the PWM signals output by the upper bridge arm switching tubes of the respective paths.

[0056] The comparison values of the upper bridge arm switching tubes of the respective paths are used to determine the duty ratios of the PWM signals output by the respective paths. The output rule before the PWM signals of the respective paths are flipped is as follows: in the period in which the carrier occurs, the instantaneous value of the carrier is compared with the comparison value of the upper bridge arm switching tube in size, and when the instantaneous value of the carrier is greater than the comparison value of the upper bridge arm switching tube, the PWM signal output is high; when the instantaneous value of the carrier is lower than the comparison value of the upper bridge arm switching tube, the PWM signal output is low, so as to determine the duty ratio of the PWM signal output by the respective paths before the PWM signals are flipped. Then, according to the comparison values of the upper bridge arm switching tubes of the respective paths, it is ensured that the duty ratio of the PWM signal after the flip does not change when the PWM signal is flipped subsequently.

[0057] In step S200, the comparison values of the upper bridge arm switching tubes of the respective paths are compared in size, the comparison value in the middle size is recorded as a first comparison value, and the PWM signal output by the upper bridge arm switching tube corresponding to the first comparison value is recorded as a to-be-flipped signal.

[0058] For example, taking a three-phase motor as an example, the comparison values CMP of the upper bridge arm switching tubes of three paths A, B, and C are CMPA, CMPB, and CMPC, respectively. As shown in Figure 3 the PWM signal output by the upper bridge arm switching tube of the path B is the to-be-flipped signal.

[0059] Step S300, the signal to be flipped is flipped. Here, the essence of the flip processing is to replace the zero vector with two basis vectors with a phase difference of 180° to eliminate the existence of the zero vector.

[0060] In some embodiments, in step S300 "the signal to be flipped is flipped", comprising:

[0061] Step S310, the first comparison value is complemented to obtain a new first comparison value.

[0062] Step S320, in the period of carrier generation, the instantaneous value of the carrier is compared with the new first comparison value to determine the level of the signal to be flipped after flipping.

[0063] In some embodiments, in step S310 "the first comparison value is complemented to obtain a new first comparison value", the complement output is: according to the difference between the amplitude of the carrier and the first comparison value, the new first comparison value is determined. The amplitude of the carrier is half of the quotient of the chip clock frequency and the switching frequency of the switch tube in the increment / decrement counting mode.

[0064] For example, the new first comparison value CMPB' is:

[0065] CMPD' = PRD - CMPD,

[0066] Where PRD is the amplitude of the carrier, and CMPB is the first comparison value.

[0067] The amplitude of the carrier PRD is:

[0068]

[0069] Because of the use of the comparison value complement principle, it can be ensured that the duty cycle of the flipped PWM signal is unchanged. As shown in Figure 3 The PWM signal of B output represents the signal to be flipped. In a carrier cycle, the time of B output PWM signal high level is 2*(PRD-CMPB). After flipping, as shown in Figure 5 The comparison value of B is the new first comparison value CMPB', CMPB' = PRD-CMPB. Obviously, before flipping, the PWM signal output by B is high before reaching the comparison value CMPB', and the time of B output high level in a carrier cycle is 2*CMPB' = 2*(PRD-CMPB), that is, the duty cycle of the PWM signal output by B before and after flipping is unchanged

[0070] In some embodiments, the step S320 "in a period in which the carrier occurs, comparing the instantaneous value of the carrier with the new first comparison value, and determining the level of the to-be-inverted signal after inversion" includes:

[0071] In the period in which the carrier occurs, when the instantaneous value of the carrier is greater than the new first comparison value, the level of the to-be-inverted signal after inversion is a low level; and when the instantaneous value of the carrier is less than the new first comparison value, the level of the to-be-inverted signal after inversion is a high level.

[0072] Figure 5 For the inverted three-path PWM signal and the bus current waveform, at this time, the voltage space vector is decomposed into the sum of 2 portions of 4 vectors (100) + 2 portions of 6 vectors (110) + 2 portions of 2 vectors (010) + 2 portions of 5 vectors (101). This processing mode essentially replaces the zero vector with two basic vectors with a phase difference of 180 degrees to eliminate the existence of the zero vector. In the motor control process, the voltage vectors of other sectors can follow the inversion rule to ensure the realization of non-zero vector inversion modulation, to reduce the impact of bus current on the electrolytic capacitor, prolong the service life of the electrolytic capacitor, and improve the system stability.

[0073] Example Two

[0074] On the basis of Embodiment One, this embodiment describes the method of Embodiment One through specific implementation cases. The microprocessor in the motor control system determines the comparison value of each upper bridge arm switch tube according to the duty ratio and carrier period of the PWM signal output by each upper bridge arm switch tube; compares the sizes of the comparison values of the three upper bridge arm switch tubes, records the comparison value in the middle size as the first comparison value; records the PWM signal output by the upper bridge arm switch tube corresponding to the first comparison value as the to-be-inverted signal; and then performs inversion processing on the to-be-inverted signal. to eliminate the existence of zero vectors.

[0075] In some embodiments, after the microprocessor compares the sizes of the comparison values of the three upper bridge arm switch tubes, records the comparison value in the middle size as the first comparison value; records the PWM signal output by the upper bridge arm switch tube corresponding to the first comparison value as the to-be-inverted signal, and then performs complementary output on the first comparison value to obtain a new first comparison value, and then compares the instantaneous value of the carrier with the new first comparison value in a period in which the carrier occurs, to determine the level of the to-be-inverted signal. Wherein, the performance form of complementary output is: determining the new first comparison value according to the difference between the amplitude of the carrier and the first comparison value. The amplitude of the carrier is half of the quotient of the chip clock frequency and the switching frequency of the switch tube in the increment / decrement counting mode.

[0076] Exemplarily, the comparison values CMP of the three bridge arm switch tubes on the A, B and C paths are CMPA, CMPB and CMPC respectively, wherein the comparison value CMPB of the bridge arm switch tube on the B path is of the middle size. The new first comparison value CMPB' is:

[0077] CMPB' = PRD - CMPB,

[0078] wherein PRD is the amplitude of the carrier, and CMPB is the first comparison value.

[0079] The amplitude PRD of the carrier is:

[0080]

[0081] In some embodiments, the comparison between the instantaneous value of the carrier and the new first comparison value in the period when the carrier occurs is used to determine the level of the signal to be flipped, including:

[0082] In the upper half cycle when the carrier occurs, if the instantaneous value of the carrier is greater than the new first comparison value, the signal to be flipped outputs a low level; in the lower half cycle when the carrier occurs, if the carrier is less than the new first comparison value, the signal to be flipped outputs a high level.

[0083] Exemplarily, taking the DSP control application as an example, referring to the register rule diagram shown in Figure 6 The A path PWM signal represents the PWM signal before flipping, and the comparison value CMPA is the comparison value of the bridge arm switch tube on the A path. The A path PWM signal adopts the output rule before flipping, i.e., when the instantaneous value of the carrier is greater than the comparison value CMPA of the bridge arm switch tube on the A path, the PWM signal output by the A path is a high level; when the instantaneous value of the carrier is less than the comparison value CMPA of the bridge arm switch tube on the A path, the PWM signal output by the A path is a low level. In the DSP control application, the output rule of the AQ action register corresponding to the A path PWM signal is to make the CAU bit register equal to 0x1 and the CAD bit register equal to 0x2.

[0084] The B-path PWM signal represents the flipped PWM signal. The comparison value CMPB' is the comparison value of the B-path upper arm switch tube, representing the comparison value of the PWM signal that needs to be flipped, i.e., representing the new first comparison value. The B-path PWM signal adopts the flipped output rule, i.e., when the instantaneous value of the carrier is greater than the comparison value CMPB' of the B-path upper arm switch tube, the PWM signal output by the B-path is low; when the instantaneous value of the carrier is less than the comparison value CMPB' of the B-path upper arm switch tube, the PWM signal output by the B-path is high. In a DSP control application, i.e., the output rule of the AQ action register corresponding to the B-path PWM signal is to set the CAU bit register to 0x1 and the CAD bit register to 0x2. As shown in FIG. 8, the PWM signal output by the B-path represents the signal to be flipped. The time for which the PWM signal output by the B-path is high in one carrier cycle is 2*(PRD-CMPB). Figure 3 As shown in FIG. 9, at this time, the comparison value of the B-path is the new first comparison value CMPB', CMPB' = PRD-CMPB. Obviously, after modifying the output rule of the AQ action register, the PWM signal output by the B-path is high before reaching the comparison value CMPB', and thus the time for which the PWM signal output by the B-path is high in one carrier cycle is 2*CMPB' = 2*(PRD-CMPB), i.e., the duty cycle of the PWM signal output by the B-path before and after flipping is unchanged. Figure 5

[0085] Example Three

[0086] Figure 7 FIG. 10 is a structural schematic diagram of a frequency converter control device provided in an embodiment of the present application. As shown in FIG. 10, the embodiment provides a frequency converter control device 300, which comprises: Figure 7

[0087] The calculation module 310 is configured to determine the comparison value of each upper arm switch tube according to the duty cycle of the PWM signal output by each upper arm switch tube and the carrier cycle.

[0088] The comparison value of each upper arm switch tube is used to determine the duty cycle of the PWM signal output by the corresponding path. The output rule of each PWM signal before flipping is that, in the carrier cycle, the instantaneous value of the carrier and the comparison value of the upper arm switch tube are compared, and when the instantaneous value of the carrier is greater than the comparison value of the upper arm switch tube, the PWM signal output is high; when the instantaneous value of the carrier is less than the comparison value of the upper arm switch tube, the PWM signal output is low. Thus, the duty cycle of the PWM signal output by the corresponding path before flipping is determined. The comparison value of each upper arm switch tube facilitates subsequent flipping processing of the PWM signal, and ensures that the duty cycle of the flipped PWM signal does not change.

[0089] ​​The comparison module 320 is configured to compare the comparison values of the upper arm switch tubes of the phases, record a comparison value with an intermediate value as a first comparison value, and record a PWM signal output by the upper arm switch tube corresponding to the first comparison value as a to-be-flipped signal.

[0090] The control module 330 is configured to perform flipping processing on the to-be-flipped signal. Here, the essence of the flipping processing is to replace the zero vector with two basic vectors with a phase difference of 180°, so as to eliminate the existence of the zero vector.

[0091] It should be noted that the calculation module 310 in this embodiment can be used to perform step S100 in the embodiment of the present application, the comparison module 320 in this embodiment can be used to perform step S200 in the embodiment of the present application, and the control module 330 in this embodiment can be used to perform step S300 in the embodiment of the present application.

[0092] The above modules and examples and application scenarios realized by the corresponding steps are the same, but are not limited to the contents disclosed in the above embodiments.

[0093] In some embodiments, the control module 330 includes:

[0094] The complementary output module is configured to complementally output the first comparison value to obtain a new first comparison value.

[0095] The flipping module is configured to compare the instantaneous value of the carrier with the new first comparison value in a carrier generation period, and determine the level of the to-be-flipped signal after flipping.

[0096] In some embodiments, the complementary output module is configured to determine the new first comparison value according to a difference between the amplitude of the carrier and the first comparison value, wherein the amplitude of the carrier is half of the quotient of the chip clock frequency and the switching frequency of the switch tube.

[0097] The new first comparison value CMPB' is:

[0098] CMPB' = PRD - CMPB,

[0099] wherein PRD is a period register setting value, and CMPB is the first comparison value.

[0100] The amplitude PRD of the carrier is:

[0101]

[0102] In some embodiments of the present application, the flipping module includes:

[0103] The counting comparison module is configured to compare the instantaneous value of the carrier with the new comparison value in the carrier generation period.

[0104] The action module is configured to determine the level of the to-be-inverted signal after inversion as a low level when the instantaneous value of the carrier is greater than the new first comparison value during the period in which the carrier occurs, and determine the level of the to-be-inverted signal after inversion as a high level when the instantaneous value of the carrier is less than the new first comparison value.

[0105] For example, the action module uses an AQ action register, and modifies the output rule of the AQ action register, i.e., the CAU bit register is equal to 0x1, and the CAD bit register is equal to 0x2, i.e., during the period in which the carrier occurs, when the instantaneous value of the carrier is greater than the new first comparison value CMPB', the AQ action register limits the level of the to-be-inverted signal after inversion as a low level; when the instantaneous value of the carrier is less than the new first comparison value CMPB', the AQ action register limits the level of the to-be-inverted signal after inversion as a high level.

[0106] Thanks to the use of the comparison value complement principle, the duty cycle of the inverted PWM signal can be ensured unchanged. The zero vector is replaced by two basic vectors with a phase difference of 180 degrees to eliminate the existence of the zero vector, and the non-zero vector inversion modulation is ensured to reduce the impact of bus current on the electrolytic capacitor, prolong the service life of the electrolytic capacitor, and improve the system stability.

[0107] Example Four

[0108] The embodiment of the application provides an electronic device 400, as shown in the structural block diagram of the electronic device provided by the embodiment, the electronic device 400 can be a mobile phone, a computer or a tablet computer, and the like, and comprises a memory 401 and a processor 402, the memory 401 stores a computer program, and the computer program is executed by the processor to realize the frequency converter control method in the embodiment. It can be understood that the electronic device 400 can further comprise a multimedia component, an input / output (I / O) interface, and a communication component. The electronic device 400 comprises at least one of a refrigerator, a washing machine and an air conditioner. Figure 8 The structural block diagram of the electronic device provided by the embodiment is shown, the electronic device 400 can be a mobile phone, a computer or a tablet computer, and the like, and comprises a memory 401 and a processor 402, the memory 401 stores a computer program, and the computer program is executed by the processor to realize the frequency converter control method in the embodiment. It can be understood that the electronic device 400 can further comprise a multimedia component, an input / output (I / O) interface, and a communication component. The electronic device 400 comprises at least one of a refrigerator, a washing machine and an air conditioner.

[0109] The processor 402 is configured to execute all or part of the steps in the data real-time display method in the embodiment. The memory is configured to store various types of data, which can include, for example, instructions of any application program or method in the electronic device 400, and application program related data.

[0110] The processor 402 can be an Application Specific Integrated Circuit (ASIC), a Digital Signal Processor (DSP), a Digital Signal Processing Device (DSPD), a Programmable Logic Device (PLD), a Field Programmable Gate Array (FPGA), a controller, a microcontroller, a microprocessor, or other electronic elements implementing the data real-time display method in the above embodiment one.

[0111] The memory 401 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as a Static Random Access Memory (SRAM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), an Erasable Programmable Read-Only Memory (EPROM), a Programmable Read-Only Memory (PROM), a Read-Only Memory (ROM), a magnetic storage, a flash memory, a magnetic disk, or an optical disk.

[0112] Example Five

[0113] The embodiment also provides a computer readable storage medium, such as a flash memory, a hard disk, a multimedia card, a card memory (for example, an SD or DX memory, etc.), a Random Access Memory (RAM), a Static Random Access Memory (SRAM), a Read-Only Memory (ROM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), a Programmable Read-Only Memory (PROM), a magnetic storage, a magnetic disk, an optical disk, a server, an App application store, etc., which stores a computer program, and the computer program can implement the following method steps when executed by the processor 402.

[0114] In step S100, the duty cycle and the carrier period of the PWM signal output by each upper bridge arm switch tube are determined to obtain a comparison value corresponding to each upper bridge arm switch tube.

[0115] Step S200, comparing the comparison values of the bridge arm switch tubes on each path, recording the comparison value in the middle as the first comparison value; recording the PWM signal output by the bridge arm switch tube corresponding to the first comparison value as the to-be-flipped signal.

[0116] Step S300, performing flipping processing on the to-be-flipped signal.

[0117] The specific embodiment process of the above method steps can be referred to Embodiment 1, which will not be repeated here.

[0118] To sum up, the application provides a frequency converter control method and device, electronic equipment and storage medium, the method can flip the PWM signal output by the path corresponding to the comparison value in the middle, and ensure that the duty cycle of the flipped PWM signal is unchanged, thereby realizing replacing the zero vector with two basic vectors with a phase difference of 180°, eliminating the existence of the zero vector, and realizing the inverter modulation of the non-zero vector in the motor control process, reducing the impact of bus current on the electrolytic capacitor, prolonging the service life of the electrolytic capacitor, and improving the system stability.

[0119] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer readable storage medium. When the computer program is executed, it can include the processes of the above-mentioned embodiments. In the embodiments provided by the application, any reference to the memory, storage, database or other medium can include at least one of the non-volatile and volatile memories. The non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory or optical memory. The volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, the RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM).

[0120] It should be understood that every feature, structure, or characteristic described herein is within a preferred embodiment of the present application. It should be noted that the foregoing embodiments are merely exemplary and are not to be construed as limiting the present application. It should also be noted that features from one embodiment can be combined with features from another embodiment. It should also be noted that the words "comprise," "comprising," "comprises," "include," "including," and "includes" when used in this specification and in the following claims are not to be interpreted so as to exclude other additives, components, elements or steps. It should be understood that the terms "a" or "an," as used herein, mean "one or more" when applied to any feature in the specification and claims.

[0121] It should be noted that, as used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a component" includes a plurality of such components. In this specification and in the claims, the term "on" or "onto" means "directly on or onto," unless otherwise indicated. The term "coupled" means either directly connected to or indirectly connected with the aid of one or more intervening components.

[0122] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The above-described device embodiments are merely illustrative, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the displayed or discussed components can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0123] The units described above as separate components can or can not be physically separate, and the components displayed as units can or can not be physical units; they can be located in one place or distributed on multiple network units; and some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0124] In addition, each functional unit in each embodiment of the present application can be integrated into one processing unit, or each unit can be a unit alone, or two or more units can be integrated into one unit; the integrated unit can be realized in the form of hardware or in the form of hardware plus software functional unit.

[0125] Those skilled in the art can understand that all or part of the steps of the above-mentioned method embodiments can be completed by program instruction related hardware, the foregoing program can be stored in a computer readable storage medium, and the program executes the steps of the method embodiments when executed.

[0126] Alternatively, the integrated units of the present application can be stored in a computer readable storage medium if they are realized in the form of software function modules and sold or used as independent products. Based on this understanding, the technical solutions of the embodiments of the present application can be embodied in the form of software products, and the computer software products are stored in a storage medium, including a plurality of instructions for causing a controller to execute all or part of the methods described in the embodiments of the present application. The foregoing storage medium includes mobile storage devices, ROM, magnetic discs or optical discs, and various media that can store program codes.

[0127] The above is only an embodiment of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A frequency converter control method, characterized in that, The method includes: The comparison value for each bridge arm switch is determined based on the duty cycle and carrier period of the PWM signal output by each bridge arm switch. Compare the comparison values ​​of the switching transistors of each bridge arm, and record the comparison value in the middle as the first comparison value; record the PWM signal output by the bridge arm switching transistor corresponding to the first comparison value as the signal to be toggled. The signal to be flipped is flipped; The step of performing the flipping process on the signal to be flipped includes: The first comparison value is output as a complement to obtain a new first comparison value; During the period of carrier occurrence, the instantaneous value of the carrier is compared with the new first comparison value to determine the level of the signal to be flipped after flipping.

2. The method according to claim 1, characterized in that, The step of outputting the first comparison value in a complementary manner to obtain a new first comparison value includes: determining the new first comparison value based on the difference between the amplitude of the carrier wave and the first comparison value.

3. The method according to claim 1, characterized in that, The step of comparing the instantaneous value of the carrier with the new first comparison value during the period of carrier generation to determine the level of the signal to be flipped after flipping includes: During the period of the carrier wave, if the instantaneous value of the carrier wave is greater than the new first comparison value, the level of the signal to be flipped after flipping is low; if the instantaneous value of the carrier wave is less than the new first comparison value, the level of the signal to be flipped after flipping is high.

4. A frequency converter control device, characterized in that, The device includes: The calculation module is used to determine the comparison value of each bridge arm switch based on the duty cycle and carrier period of the PWM signal output by each bridge arm switch. The comparison module is used to compare the comparison values ​​of the switching transistors of each bridge arm, and the comparison value in the middle is recorded as the first comparison value; the PWM signal output by the bridge arm switching transistor corresponding to the first comparison value is recorded as the signal to be flipped. The control module is used to perform flipping processing on the signal to be flipped; The control module includes: The complementary output module is used to output the first comparison value in a complementary manner to obtain a new first comparison value; The flipping module is used to compare the instantaneous value of the carrier with the new first comparison value during the period of carrier occurrence to determine the level of the signal to be flipped.

5. The apparatus according to claim 4, characterized in that, The complementary output module is used to determine the new first comparison value based on the difference between the amplitude of the carrier and the first comparison value.

6. The apparatus according to claim 4, characterized in that, The flipping module includes: The counting comparison module is used to compare the instantaneous value of the carrier with the new first comparison value during the carrier generation period; The action module is configured to determine that the level of the signal to be flipped is low when the instantaneous value of the carrier is greater than the new first comparison value during the period of the carrier occurrence; and to determine that the level of the signal to be flipped is high when the instantaneous value of the carrier is less than the new first comparison value.

7. An electronic device, characterized in that, It includes a memory and a processor, wherein the memory stores a computer program, which, when executed by the processor, performs a frequency converter control method as described in any one of claims 1 to 3.

8. The electronic device according to claim 7, characterized in that, The electronic device includes at least one of a refrigerator, a washing machine, and an air conditioner.

9. A storage medium, characterized in that, The computer program stored in the storage medium can be executed by one or more processors, and the computer program can be used to implement a frequency converter control method as described in any one of claims 1 to 3.

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