Unified Material-to-System Simulation and Verification for Semiconductor Design and Manufacturing

Abstract

A complete, unified method for materials-to-system simulation, design, and verification in semiconductor design and manufacturing may include evaluating the impact of semiconductor material or process variations on software algorithms. The method may include: converting the material or process variations into a property database; using the property database to generate an original circuit structure; performing electrical characterization on the original circuit structure; providing the output of the electrical characterization to a script to generate a compact model; generating a trimmed-down version of a standard cell; generating a digital system based on the trimmed-down version of the standard cell; and evaluating the performance of the software algorithms on the digital system to determine the impact of the material or process variations for semiconductor manufacturing processes.

Description

[0001] This application claims the benefit of priority of U.S. Patent Application No. 16 / 781,980, filed on February 4, 2020, the content of which is incorporated herein by reference in its entirety for all purposes. Technical Field

[0002] This application generally describes processes for software and hardware tools that connect various stages of integrated circuit design and manufacturing processes. Specifically, the present disclosure describes tools for propagating the effects of material or process variations into the execution of software algorithms on digital systems. Background Art

[0003] In the past few decades, circuit architectures have used scaling techniques to meet the demands of increasing workloads. Scaling has traditionally reduced the feature size of integrated circuit elements (e.g., from 10 nm to 7 nm, to 5 nm, etc.). However, due to reaching the physical limits of silicon structures, the physical limits of silicon structures have greatly slowed the gains that scaling techniques might provide in recent years. Additionally, with the recent emergence of artificial intelligence and machine learning algorithms (AI / ML), the amount of data to be processed and the diversity of different workload types have begun to exceed the gains provided by scaling techniques. Hardware computing requirements are growing exponentially and may require new circuit manufacturing advancements to keep pace. Thus, the growing processing demands from AI / ML technologies, combined with the decreasing performance gains achieved through traditional circuit scaling, may require other technologies to improve performance. Summary of the Invention

[0004] In some embodiments, a method for complete, unified material-to-system simulation, design, and verification for semiconductor design and manufacturing may include evaluating the impact of semiconductor material or process variations on software algorithms. The method may include: converting the material or process variations into a property database; using the property database to generate an original circuit structure; performing electrical characterization on the original circuit structure; providing the output of the electrical characterization to a script to generate a compact model; generating a trimmed-down version of a standard cell; generating a digital system based on the trimmed-down version of the standard cell; and evaluating the performance of a software algorithm on the digital system to determine the impact of the material or process variations for semiconductor manufacturing processes.

[0005] In some embodiments, the system may include one or more processors and one or more memory devices. The one or more memory devices may include instructions that, when executed by the one or more processors, cause the one or more processors to perform operations, the operations including: receiving a material or process variation for a semiconductor manufacturing process; converting the material or process variation into a property database; using the property database to generate an original circuit structure; performing electrical characterization on the original circuit structure; providing the output of the electrical characterization to a script to generate a compact model; generating a reduced version of a standard cell; generating a digital system based on the reduced version of the standard cell; and evaluating the performance of a software algorithm on the digital system to determine the impact of the material or process variation for the semiconductor manufacturing process.

[0006] In some embodiments, a non-transitory computer-readable medium may include instructions that, when executed by one or more processors, cause the one or more processors to perform operations, the operations including: receiving a material or process variation for a semiconductor manufacturing process; converting the material or process variation into a property database; using the property database to generate an original circuit structure; performing electrical characterization on the original circuit structure; providing the output of the electrical characterization to a script to generate a compact model; generating a reduced version of a standard cell; generating a digital system based on the reduced version of the standard cell; and evaluating the performance of a software algorithm on the digital system to determine the impact of the material or process variation for the semiconductor manufacturing process.

[0007] In any embodiment, any of the following features may be implemented in any combination and without limitation. The original circuit structure may include transistors. Performing electrical characterization of the original circuit structure may include: generating current and voltage characteristics of the transistors. The method / operation may also include: performing TCAD simulation of the original circuit structure; generating a circuit model of the original circuit structure using a characteristics database and TCAD simulation; performing circuit simulation on the circuit model; and / or determining whether a material or process variation of a semiconductor manufacturing process is acceptable based on the circuit simulation results of the circuit model. The method / operation may also include: receiving a plurality of material or process variations for a semiconductor manufacturing process; converting the plurality of material or process variations into a characteristics database; generating additional original circuit structures for each of the plurality of material or process variations using the characteristics database; simulating the additional original circuit structures; and identifying acceptable material or process variations among the plurality of material or process variations based on the results of simulating the original circuit structures. The original circuit structure may include a memory film stack. The trimmed standard cell may include a memory array. The compact model may include a ring oscillator. The method / operation may also include: testing the performance of the ring oscillator to determine PPAC characteristics; and determining that the performance of the ring oscillator is acceptable before generating the trimmed standard cell. The trimmed standard cell may omit features not required by the digital system. The software algorithm may include an AI / ML algorithm. The method / operation may also include: generating a trimmed process design kit (PDK) using the trimmed standard cell. The cells in the PDK may use abstract values extracted from the characteristics database. The trimmed PDK may include only the cells affected by the material or process variations used for the semiconductor manufacturing process. The digital system may be a processor. The method / operation may also include: performing at least two short-loop optimization tests before generating the digital system to test the PPAC characteristics of the original circuit structure and the trimmed standard cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] A further understanding of the nature and advantages of various embodiments can be realized by reference to the remainder of the specification and the drawings, in which like reference numerals are used throughout the drawings to refer to like components. In some cases, sub-labels are associated with the reference numerals to denote one of a plurality of like components. When a reference numeral is cited without specification

[0009] Figure 1 FIG. shows a process flow of different operations that may be performed to evaluate how material or process variations affect an entire electronic circuit system according to some embodiments.

[0010] Figure 2 FIG. shows a unified process flow of operations that may be performed in a single workflow to evaluate how material or process variations affect an entire system according to some embodiments.

[0011] Figure 3 A flowchart of a method for performing a full system evaluation according to some embodiments is shown, where the full system evaluation is used to evaluate material / process changes at progressive stages with short-loop sub-evaluations.

[0012] Figure 4 An example of short-loop optimization of an integration test workflow described above in Figure 3 is shown.

[0013] Figure 5 An example of a second short-loop optimization according to some embodiments that converts technical features into design rules and then into a trimmed PDK library is shown.

[0014] Figure 6 An exemplary computer system in which various embodiments may be implemented is shown. DETAILED DESCRIPTION

[0015] In the past few decades, circuit architectures have used scaling techniques to meet the demands of increasing workloads. Scaling has traditionally reduced the feature size of integrated circuit elements (e.g., from 10 nm to 7 nm, to 5 nm, etc.). However, in recent years, the physical limits of silicon structures have significantly slowed the gains achievable with scaling techniques. Additionally, with the emergence of artificial intelligence and machine learning algorithms (AI / ML), the amount of data to be processed and the diversity of different workload types have started to exceed the gains achieved with scaling techniques. Hardware computing demands are growing exponentially, and new circuit manufacturing advancements may be needed to keep pace. Thus, the growing processing demands from AI / ML technologies, combined with the decreasing performance gains achieved through traditional circuit scaling, may require other technologies to improve performance. One alternative technology for improving performance is material / process innovation by device manufacturers.

[0016] Material innovation includes (e.g.) any change to various physical aspects of a semiconductor device, such as the size of source / drain contacts, the type of isolation between transistors, gate oxide materials, work function metals, source / drain region doping, contact materials, liners in contact materials, and / or any other parameter of the semiconductor device. At the early stages of the semiconductor design cycle, the impact of these types of changes on large processors and / or systems-on-chip (SoCs) employing different software algorithms may not be clear. For example, the power-performance-area-cost (PPAC) improvements from material engineering innovations may seem small, but can multiply at the SoC level and vice versa.

[0017] Despite the potentially encouraging benefits of material innovation, the difficulties and inherent limitations of existing tools, processes, and systems make it difficult to implement material innovation in practice without a broad, multi-year design validation process. Due to the complexity inherent in designing, testing, implementing, and manufacturing complex circuit-based systems, design processes have traditionally been separated among different entities in the semiconductor ecosystem. For example, device manufacturers will introduce the use of semiconductor-grade materials or process variations. Subsequently, the material variations will be implemented in a simple device structure in a semiconductor foundry or wafer fab using a compact model. The process design kit (PDK), standard cell library, and embedded memory for the process design kit (PDK) are developed by integrated circuit design entities that provide electronic design automation (EDA) software. "Fabless" device design entities or integrated device manufacturers (IDMs) use the standard cells / memory in the PDK to generate block-level designs, complete SoCs, and system-level devices. Finally, software designers will use the fabricated IC devices to run complex software designs and algorithms. Each of these different stages of the IC design and manufacturing pipeline is performed by different entities, each using different software / hardware tools to perform their part of the process.

[0018] Currently, there is little connection between the different stages in this process. For example, the simple devices and / or compact models designed by the wafer fab are tested against their own internal benchmarks to determine that the corresponding simple circuit devices meet their technical requirements. The simple devices and / or compact models are then passed to an integrated circuit (IC) design entity, which will use the compact model to design a complete PDK, standard cells, and memory cells for the EDA software. Similarly, the IC design entity will test the standard cells against its own internal technical requirements. Finally, the standard cells will be used to design a complete IC system, and the IC system will be tested again against its own software benchmarks. Due to the lack of connectivity between each of the different entities and software / hardware tools, the full ramifications of changes made to the process or materials by the device vendor are not known when these changes propagate through the semiconductor ecosystem to the entire AI / ML system.

[0019] Note that the lack of connectivity between the various parts of IC design and manufacturing processes is the result of technical issues (rather than business requirements). Existing software / hardware tools do not support integrating these different processes into a single workflow that can be implemented by a single computer system. The embodiments described herein help solve this and other technical issues by providing connection software tools between the various stages of existing IC design and manufacturing processes. The embodiments described herein also change the existing design tool flow such that these existing design tool flows can quickly implement and test minor changes to materials or processes without the design of a complete library of standard cells and memory arrays. Finally, the embodiments described herein greatly reduce the time required to evaluate material / process changes by aggregating each stage of the process, from materials to a complete system, into a single software workflow. This combination of advantages provided by these embodiments reduces the previous multi-year process for evaluating material / process changes at a device manufacturer to at most a few days or weeks.

[0020] Figure 1 A process flow is shown that can be executed, according to some embodiments, to evaluate how changes to materials or processes affect different operations of an entire electronic circuit system. The first entity involved in this process may include a semiconductor device manufacturer (“device manufacturer”) 102 that designs devices for manufacturing electronic circuits on semiconductor wafers. An example of device manufacturer 102 may include Applied (Applied ). Generally, device manufacturer 102 may make material / process changes to change how the device manufacturer manufactures semiconductor devices. These changes may include any changes to various physical aspects of the semiconductor device, such as the size of source / drain contacts, the type of isolation between transistors, the gate oxide material, the work function metal, the source / drain region doping, the contact material, the liner in the contact material, and / or any other parameters of the semiconductor device. Note that in the Figure 1 process flow, device manufacturer 102 may initiate material / process change 110, but device manufacturer 102 generally will not know the downstream impact of these material / process changes 110 until other entities and software / hardware tools perform their respective operations as described below. Although device manufacturer 102 may test material / process changes, device manufacturer 102 can only verify the consequences of the changes at a very small scale level for individual features or small devices. Device manufacturer 102 does not have software / hardware tools to evaluate the consequences of material / process changes 110 at the system level, especially for chip systems running AI / ML software.

[0021] Next, device manufacturer 104 (i.e., a wafer foundry) that purchases devices from device manufacturer 102 will design simple device structures 112 that will be used on semiconductor manufacturing equipment to design an entire semiconductor system. These simple device structures 112 can include circuit designs and layouts for transistors, diodes, capacitors, and other semiconductor devices. Device manufacturer 104 will then test the electrical characteristics of these individual devices. For example, device manufacturer 102 typically tests characteristic parameters such as the resistance of vias, the on-current of transistors, and other smaller-scale measurements for each semiconductor device. Generally, these tests can include both hardware tests and technology computer-aided design (TCAD) software tests, which can automate and model semiconductor manufacturing and semiconductor device operation. TCAD tools can model processing steps and the behavior of electrical devices based on the fundamental physics of semiconductor layouts. Device manufacturer 102 can also create a compact model 116 (such as a SPICE transistor model) of the semiconductor device, which captures the behavior of the simple device structure for use in designing larger circuits that use these semiconductor devices.

[0022] After the compact model 116 is generated, the compact model 116 can be used to build circuits for standard cells. This step can be performed by device manufacturer 104 and / or integrated circuit design entity 106. These two entities can work together or can handle different parts of the steps assigned to IC design entity 106. For example, when the compact models of individual transistors are combined, other aspects of circuit performance may be affected based on the connections between these transistors. Capacitances and dielectrics form between the compact model transistors as these capacitances and dielectrics are combined into a larger, multi-transistor circuit. At this level, standard circuits 118 can be designed in EDA software and tested at the circuit level rather than at the transistor level. For example, standard circuits 118 can be benchmarked for power consumption, frequency, and / or other simple electrical characteristics. As described above, material / process variations 110 can affect the operation of standard circuits 118, but these effects are not discovered until during simulation and using EDA software and SPICE simulation, etc., when the material / process variations 110 have propagated down to IC design entity 106. Figure 1

[0023] One of the most time-consuming aspects of the process is generating a complete PDK library and standard cells / memories. The PDK library can include symbols, device parameters, parametric cells, design rules, circuit layout verification rules, electrical rules, and layers, among other things. When the device manufacturer 102 makes a material / process change 110, the PDK library 120, which includes standard circuit elements and cells, is typically redesigned by the device manufacturer 104 and / or the IC design entity 106. This is a time-consuming process because the PDK ensures that designs created in the EDA software can be manufactured by the device manufacturer 104 at a predetermined yield.

[0024] Finally, the system design entity 108 can use the PDK to design and run large circuit systems. The system design entity 108 can include a fabless design company that designs circuit-based systems for manufacturing at a manufacturing entity. Additionally, an integrated device manufacturer (IDM) can include a semiconductor company that designs, manufactures, and sells integrated circuit products. Any of these system design entities 108 can use various design tools to design block-level designs 122, including processors, memory blocks, multiply-accumulators (MACs), digital signal processors (DSPs), and other design blocks. These design blocks can be tested to determine if performance, power, area, and / or cost requirements (PPAC) have been met. The system design entity 108 can also design a complete SoC design 124 that integrates multiple design blocks into a single system-on-chip. The complete SoC design 124 can also be tested to meet PPAC requirements. In some cases, the complete SoC design 124 can also be tested when running a software algorithm 126 on the manufactured chip. The speed and efficiency of the software algorithm 126 can then be used to make a final determination on whether the material / process change 110 is effective.

[0025] Because the processes shown above in Figure 1 can take years to fully evaluate the material / process change 110, the embodiments described herein describe a single workflow system such that the device manufacturer 102 can evaluate the impact of the material / process change 110 on the complete SoC 124 and / or the algorithm 126 in about a few days or about a few weeks (instead of about a few years). Some existing software tools can be used, but other scripts have been designed to link these tools together, and the new process reduces the number of PDK components and standard cells that need to be designed to perform this evaluation.

[0026] Figure 2 A unified process flow 200 is shown that can be executed in a single workflow to evaluate how a material or process change affects the operation of an entire system, according to some embodiments. This process flow 200 is similar to the one shown above in Figure 1The process flow 100 shown therein. However, the process flow 200 is executed by a single workflow, and this single workflow is executed by a single entity. Instead of passing the design between different software tools operating at different locations, on different computer systems, and by different entities; these embodiments execute each operation as part of a single workflow, such that the entire process can be executed by a single entity and / or a single computer system. This reduces the time required to perform a complete material-to-system evaluation for the material / process change 110 (from years to weeks or days).

[0027] The process flow 200 also includes additional blocks 230, 232, 234, which add new processes to the method, and these new processes enable various tools / processes to operate as part of a single workflow executed by the device manufacturer 102. After the material / process change 110 has been implemented, the new process in block 230 can be executed. First, the method can read and transform 202 the material / process change 110 to generate a database including a process library 204 and / or a material library 206. For example, some embodiments can store the material / process information in a table. The system can read and transform 202 the table and extract the process changes from the spreadsheets or tables that have been made during the current design iteration. Reading and transforming 202 can characterize the material by extracting all relevant properties of the material (such as properties from process-related changes and properties from material-related changes). The process information can include information related to a specific technology node, a specific device, a transistor type, transistor parameters, material thickness, feature length, channel, and / or the like. The material information can include the materials used in the device, the liner type / material, the material resistivity, the material properties, and / or other characteristics. This information can be stored in the process library 204 and / or the material library 206. The process library 204 and / or the material library 206 can be pre-built at the start of the process and can be used throughout the remainder of the process. The process library 204 and / or the material library 206 can be stored in a database, which serves as a lookup function for subsequent steps in the process.

[0028] At various stages of the process, the information in the database can be referred to later to fill in the missing parameters for building the model. When building the simple device structure 112, the system can use many pre-built, predefined structures with missing parameters. The process can then query the database including the process library 204, and the material library 206 can be used as a lookup table to extract the relevant parameters, which can then be inserted into the simple device structure. The simple device structure can include lines, vias, and simple transistors for building the above simple device structure. The simple device structure can also be referred to as the "original" device structure or the original circuit structure. Note that some embodiments use logic devices, while other embodiments can use memory devices. For memory embodiments, the simple device structure can include a memory film stack.

[0029] After constructing the simple device, electrical characteristics 114 can be extracted. As described below with reference to Figure 4 those described, a TCAD model and / or a SPICE model can be generated based on the characteristics extracted from the database, and these models can be simulated to generate electrical characteristics 114 for the simple device structure. At this stage, a first assessment can be made of how the material / process variation 110 affects the electrical characteristics 114. If the effect is already negative, different material / process variations can be used instead, and the process can be restarted using these different material / process variations.

[0030] The second new processing block 232 can include new processing for converting the simple device structure into compact models that can be used to construct standard cell circuits 118. For example, if a specific type of 7nm transistor made of a specific material is specified, these parameters can be provided as input to the database to look up the relevant parameters to insert into the device model. Additionally, the electrical characteristics 114 can be fed into this processing to generate the compact models. The values provided can be approximate compact model extractions. Thus, the read and conversion processing 208 can extract information from the material library 206 in the database and / or the electrical characteristics 114, and convert this information into the values required to construct the compact models for the corresponding device type. This can include converting the properties from the database into the approximate values required for the compact models. The conversion processing can be designed differently for each specific tool used to generate the compact models, and the conversion processing can include converting the data in the database and the electrical characteristics 114 into values and formats that can be read by the specific tool. At this point, the compact models 210 can be automatically extracted for use in constructing the standard cell circuits 118. As described above, the standard cell circuits 118 can include NAND gates, inverters, and / or any other simple circuit configurations.

[0031] At this stage of the automated process, the system can construct the standard cell circuits 118 and evaluate the performance of the standard cell circuits 118. At this point, the entire process can be automated such that the material / process variation 110 propagates all the way to the standard cell circuits 118. The standard cell circuits 118 can then be processed to measure the PPAC characteristics of the cells 118 and determine whether the process / material variation 110 has positively or negatively affected the operating characteristics of the standard cell 118. For example, the oscillation frequency and power usage of a ring oscillator can be tested at this time to determine whether the material / process variation 110 has a positive or negative effect on these operating characteristics. If the effect is positive, the remainder of the process can continue, while if the process is negative, the process can be stopped and different material / process variations 110 can be used. For embodiments using memory devices, a memory array can be constructed and measured instead of a ring oscillator or other logic device.

[0032] After testing the standard cells, a "trimmed" version of the PDK library can be generated. The previously recognized process for generating the PDK library was very manual and time-consuming. The embodiments described herein use an automated process in which the abstract values of a given technology can be used to generate elements of a "trimmed" PDK library that are only affected by material / process variations 110. For example, the "abstract" values can be derived by considering a sequence of process conditions or process steps (e.g., lithography, etching, and deposition, etc.) to be abstracted into a set of design rules (e.g., tip-to-tip and enclosure rules, etc.). These abstracted and compacted values can be used in such a way that there is no loss of accuracy in the simulation. These values can be abstracted, compacted, and / or propagated to each subsequent stage. The abstracted and compacted values vary according to different execution stages. For example, the material / process variations can be abstracted at the material level to represent the relationship between resistivity and thickness. At the small structure or transistor level, these values can then be abstracted into I / V and C / V characteristics. Next, at the standard cell level, the abstract values can be used to generate cell characteristics such as functionality, power, drive strength, and fan-out, etc. Finally, when generating the trimmed version of the PDK library, these abstract values can generate relevant design rules such as the spacing between lines, tip-to-tip spacing, etc. At each stage, these abstract values can be stored in the material / process database when they are generated and inserted into the models and simulations. The standard cell and PDK characteristics can be captured in the trimmed version of the standard cells and the trimmed PDK definition, and / or the standard cell and PDK characteristics can be captured in the material / process database.

[0033] For example, the previous process for generating the PDK library involved a foundry moving from different technology nodes (e.g., moving from 7nm to 5nm). The foundry would start with an earlier version of the 7nm PDK along with all its associated overhead. It should also be noted that the version of the 7nm PDK might be layered on top of the previous 10nm PDK library, such that each additional iteration of the PDK library adds additional layers and / or design rules to the existing library. The foundry would manually obtain the results of physical experiments from the 7nm PDK to shrink certain parameters in the cell library. The foundry would then communicate with the EDA vendor to integrate the new PDK library with the new technology. After several months, the EDA software would be available to fabless designers and IDMs to actually implement and design software algorithms on the technology hardware.

[0034] These embodiments simplify this entire process for testing at the device manufacturer. Thus, a full PDK library is not required to perform this test. Instead, a small, trimmed-down set of PDK cells 212 can be designed to test the effects of the material / process variations 110. Since the material / process variations 110 have only relatively few changes, the corresponding changes required in the existing PDK library are relatively few. The software can map the changes to the existing cells resulting from the material / process variations 110, rather than building on top of an inflated PDK library. Then, a trimmed-down version of the PDK cells can be used, which has only a few changes related to specific parameters affected by the material / process variations 110. Some embodiments can use abstract values of a given device without losing accuracy in the final result simulation.

[0035] The same process can be used to generate a standard cell library from the trimmed-down PDK cells. Instead of months of manual processing to design a standard cell library, a "trimmed-down" version of the relevant standard cells can be generated. Again, abstract values from the process library 204 and / or the material library 206 can be used to generate the trimmed-down standard cells. For example, the material library can include values related to material properties, such as the dielectric constant and resistivity of different materials. The process library can include process conditions, such as deposition thickness and annealing temperature. These values from the material / process libraries can be abstracted to delays, power, rise and fall times, and / or other cell characteristics at the standard cell level. Then, these new standard cells can replace the block-level design 122 and the full-chip SoC design 124, and PPAC verification can be performed to determine how the material / process variations 110 affect the system-level design. Additionally, some embodiments can also test various algorithms 126 (such as AI / ML algorithms) to determine the impact of the material / process variations 110 on software operation. The trimmed-down standard cells and / or the trimmed-down PDK library may be limited to the features required for this early exploration. For example, the trimmed-down library can be generated to include only the cells affected by the material / process variations and required in the system / SoC design. These cells can be generated as simple cells with only the required characteristics, rather than layered on top of a full set of cells from a previous PDK library. It should be emphasized that it is possible to simulate material / process innovations up to the system level and algorithm verification without significantly reducing accuracy. It has been found that using abstract values to generate compact models, trimmed-down standard cells, and trimmed-down PDK libraries produces very accurate results at the system level.

[0036] It should be understood that Figure 2 the specific steps shown provide a particular method for evaluating variations according to various embodiments, which evaluate material / process variations in semiconductor manufacturing processes. According to alternative embodiments, other step sequences can also be performed. For example, alternative embodiments can perform the steps outlined above in a different order. Additionally, Figure 2Each of the steps illustrated may include a plurality of sub - steps, and these sub - steps may be executed in various orders suitable for each step. Additionally, depending on the particular application, additional steps may be added or removed. Those of ordinary skill in the art will recognize many variations, modifications, and alternatives.

[0037] Figure 3 FIG. 300 is a flow chart of a method for performing a full - system evaluation according to some embodiments. This full - system evaluation is used to evaluate material / process changes at progressive stages using short - loop sub - evaluations. This method includes a number of short - loop validations that test material / process changes at each stage of the manufacturing and circuit - design pipelines in a single process. This allows the method to determine at each important checkpoint whether the changes have caused the original / simple device, PDK library, standard cell, circuit, and / or system to exhibit unsatisfactory performance, for example, with respect to PPAC requirements. In each short - loop validation, the system can determine whether the current material / process change is acceptable or whether new changes should be iterated.

[0038] As described above, the method may first convert any material / process change into a value stored in the material / process database 302. The remaining steps of the method may be derived from the material / process database 302 to retrieve these values needed for the evaluation process. The database may include characteristics of materials and processes for constructing small test structures. The method may then calculate performance metrics 304 for the small test structures. At this point, a first evaluation may be performed to determine whether the material / process change stored in the material / process database 302 has caused the small test structures to perform according to an acceptable threshold. For example, the method may test characteristics such as voltage, current, capacitance, etc. of the small test structures. The test structures may include transistors, ring oscillators, NAND gates, and / or other simple circuits. The process may then iterate other material / process changes or other test - structure devices and perform a similar evaluation process on each. This short - loop optimization allows a determination to be made early in the process as to whether the proposed material / process changes will be acceptable. This short - loop optimization also allows new materials to be tested quickly and continuously as alternative materials.

[0039] As described above, for a material / process change that has passed the evaluation of the small test structure, a trimmed standard cell library or a trimmed embedded memory structure can be automatically generated from the material / process database 302. To continue the overall system test process, the method can include generating any necessary components (310) for synthesis, floorplanning, placement and routing, clock tree synthesis, and circuit timing, etc. These can be used to generate custom circuits, such as analog, digital, and mixed-signal circuits (312). For memory elements, a memory array can be generated together with the macro cell design (314). Finally, any or all of these components can be assembled into a complete chip integration design, and the design can be evaluated for compliance with the PPAC requirements (316). At this stage, another short-loop optimization decision can be made to determine whether the impact of the material / process change on the larger system is within an acceptable range. If not, a decision 320 can be made to iterate to a different material / process change. Multiple designs can be tested (318) until each design has been verified using the new material / process change. The database 324 can store the results and / or designs of the systems that have passed the PPAC requirements. Multiple material / process changes can be evaluated, and a set of candidate or acceptable material / process changes can be saved for continued evaluation.

[0040] Finally, a third optimization loop can be performed by implementing a software algorithm on the digital system. Various software algorithms can be retrieved from the database 326 and mapped to the design of the system under test 328. System-level traffic can be generated to test the algorithm 330, and the system can calculate the accuracy and performance of the circuit (332). Similarly, the performance of the algorithm can be verified by comparing it with multiple metrics, including the PPAC requirements. If the performance of the algorithm is not satisfactory, this final optimization loop can iterate multiple algorithms (336), multiple system designs (338), and / or multiple material / process changes (340). This step can also compare the results from multiple designs to determine the best material / process change from a set of proposed material / process changes.

[0041] It should be understood that Figure 3 the specific steps shown in Figure 3 provide a specific method for evaluating changes (evaluating material / process changes in semiconductor manufacturing processes) according to various embodiments. According to alternative embodiments, other step sequences can also be executed. For example, alternative embodiments can execute the steps outlined above in a different order. In addition,

[0042] Figure 4 illustrates an example of short - loop optimization using the integration test workflow described above in Figure 3 . In this example, the short - loop optimization cycle may not end until small - circuit testing of a circuit such as a transistor is performed. First, a TCAD model 402 can be generated, which includes all the resistances and capacitances generated by connecting the original devices / structures together. For example, when the source, drain, gate, and oxide, etc., are connected to form a transistor circuit, they may generate parasitic capacitances. The TCAD model 402 captures these capacitances in the silicon layout. This model can be built in TCAD using rules applicable to each of the technology iterations such as N, N + 1, N + 2, etc. (e.g., 7nm, 5nm, 3nm, etc.).

[0043] Next, the TCAD model 402 can be used to generate a SPICE model. The above - mentioned compact model can be used as part of a SPICE simulation to simulate the performance of a circuit (e.g., a transistor) and generate current, voltage, timing, and other electrical characteristics for the circuit. At this point, the simulations in both TCAD and SPICE can be used as the first checkpoint to determine whether material / process variations have affected the circuit performance in an acceptable manner. In some embodiments, the simulation data from TCAD can be used as a standard, and the SPICE simulation data can be compared with the TCAD simulation data. If the SPICE simulation data is close to the TCAD simulation data within a threshold amount, then this SPICE simulation can be used to test the circuit later. For example, for evaluation purposes, test data 406 can be generated from either of the models 402, 404.

[0044] Note that the TCAD model 402 shows the material depositions on the various levels that can be used to form a transistor. This can include the metal 1 layer (M1), via 1 layer (V1), and contact layer (CT), etc. The TCAD model 402 captures all the resistances and capacitances that can be generated by the layout of the circuit. This allows the device manufacturer to change the layout of the circuit. For example, in Figure 4 , at least five different sets of test data have been generated, as shown in the optimization diagram 408. The first experiment uses the conventional design of the transistor, and each subsequent experiment (e.g., experiment 1 and experiment 2, etc.) has implemented one or more material / process variations for generating the TCAD model 402 and / or the SPICE model 404. The final experiment (experiment 3+) shows the maximum improvement in delay caused by the CT layer of the circuit. By performing multiple tests using different types of material / process variations, this short - loop optimization cycle can uncover the best variations for small - circuit performance. This can also uncover at an early stage the material / process variations that may have the greatest impact on system - level performance later in the process.

[0045] Figure 5Shows an example of converting technical features to design rules and then to a trimmed PDK library for second short circuit optimization according to some embodiments. Different technologies affect design rules implemented in different ways. In this example, the system can propose two different design rules for evaluation. The "Technology A" design rule 502a can be compared with the "Technology B" design rule 502b. By comparison, the "Technology B" design rule 502b provides more stringent back-end-of-line (BEOL) design rules due to the proposed improved material design, process optimization, and integration in the initial steps of this process described above.

[0046] For each of the design rules 502a and 502b, the impact on the design rules and interconnect models can be captured in the corresponding PDK 504. For each of these design rules 502a and 502b, a trimmed version of the PDK can be generated, which includes compact models, design rules, and interconnect models for generating each circuit element in EDA software. Next, the system can automatically generate a set of trimmed standard cells 508. Different standard cells can be generated for each different technology being tested. As described above, changes in the design rules can be used to make small changes to existing standard cells to generate the trimmed standard cells 508.

[0047] Next, a circuit using the standard cells 508 can be generated, and the placement and routing 506 for each different technology can be generated. In this example, the interconnects of Technology B are more dense, and the thermal diagram shown for the placement and routing 506 in Figure 5 shows the relative density between Technology A and Technology B. This allows the circuit of Technology B to be implemented in a much smaller footprint in the semiconductor circuit. Next, the PPA metrics 510 can be compared to determine which technology is more efficient through comparison. As Figure 5 shown, the PPA metrics 510 indicate that Technology B can reduce the circuit area by 20% without significantly negatively impacting the performance or power metrics of the circuit. The error results 512 can also be compared between the two technologies. In this example, Technology B results in fewer design rule check (DRC) errors compared to Technology A. Similarly, this short circuit optimization can quickly evaluate the impact of material / process changes in the technology, as the material / process changes propagate forward through the design process to the physically placed, routed, and implemented system.

[0048] Figure 6Illustrates an exemplary computer system 600 in which various embodiments may be implemented. System 600 can be used to implement any of the above computer systems. As shown, computer system 600 includes a processing unit 604 that communicates with a plurality of peripheral subsystems via a bus subsystem 602. These peripheral subsystems can include a processing acceleration unit 606, an I / O subsystem 608, a storage subsystem 618, and a communication subsystem 624. Storage subsystem 618 includes a tangible computer-readable storage medium 622 and a system memory 610.

[0049] Bus subsystem 602 provides a mechanism for enabling the various components and subsystems of computer system 600 to communicate with each other as desired. Although bus subsystem 602 is schematically shown as a single bus, alternative embodiments of the bus subsystem may utilize multiple buses. Bus subsystem 602 can be any one of a variety of bus structures, including a memory bus or memory controller, a peripheral device bus, and a local bus using any one of a variety of bus architectures. For example, these architectures can include an Industry Standard Architecture (ISA) bus, a Micro Channel Architecture (MCA) bus, an Enhanced ISA (EISA) bus, a Video Electronics Standards Association (VESA) local bus, and a Peripheral Component Interconnect (PCI) bus, which can be implemented as a Mezzanine bus manufactured in accordance with the IEEE P1386.1 standard.

[0050] The processing unit 604, which can be implemented as one or more integrated circuits (e.g., a conventional microprocessor or microcontroller), controls the operation of computer system 600. One or more processors can be included in processing unit 604. These processors can include a single-core processor or a multi-core processor. In certain embodiments, processing unit 604 can be implemented as one or more independent processing units 632 and / or 634, each of which includes a single-core processor or a multi-core processor. In other embodiments, processing unit 604 can also be implemented as a quad-core processing unit formed by integrating two dual-core processors into a single chip.

[0051] In various embodiments, processing unit 604 can execute various programs in response to program code and can maintain multiple concurrently executing programs or processes. At any given time, some or all of the program code to be executed can reside in (one or more) processors 604 and / or storage subsystem 618. Through appropriate programming, (one or more) processors 604 can provide the various functions described above. Computer system 600 can additionally include a processing acceleration unit 606, which can include a digital signal processor (DSP), a dedicated processor, and / or a similar processor.

[0052] The I / O subsystem 608 may include a user interface input device and a user interface output device. The user interface input device may include a keyboard, a pointing device such as a mouse or a trackball, a touchpad or a touchscreen incorporated into a display, a scroll wheel, a click wheel, a jog dial, buttons, switches, a keypad, an audio input device having a voice command recognition system, a microphone, and other types of input devices. The user interface input device may include, for example, motion sensing and / or gesture recognition devices (such as Microsoft motion sensors), which allow a user to control and interact with an input device (such as a Microsoft Xbox 360 game controller) through a natural user interface using gestures and voice commands. The user interface input device may also include eye movement recognition devices (such as Google Blink Detector), which can detect a user's eye activity (such as "blinking" when taking a picture and / or making a menu selection) and convert the eye movement into an input to the input device (such as Google ). Additionally, the user interface input device may include voice recognition sensing devices, which allow a user to interact with a voice recognition system (such as, a navigator) through voice commands.

[0053] The user interface input device may further include, but is not limited to, a three-dimensional (3D) mouse, a joystick or a pointing stick, a gamepad, and a graphics tablet, and audio / video devices such as speakers, digital cameras, digital video cameras, portable multimedia players, webcams, image scanners, fingerprint scanners, barcode readers, 3D scanners, 3D printers, laser rangefinders, and eye tracking devices. Additionally, the user interface input device may include, for example, medical imaging input devices such as computed tomography, magnetic resonance imaging, positron emission tomography, and medical ultrasound devices. The user interface input device may also include, for example, audio input devices such as MIDI keyboards and digital musical instruments.

[0054] The user interface output device may include a display subsystem, an indicator light, or a non-visual display such as an audio output device. The display subsystem may be a cathode ray tube (CRT), a flat panel device (such as a device using a liquid crystal display (LCD) or a plasma display), a projection device, and a touchscreen. Generally, the use of the term "output device" is intended to include all possible types of devices and mechanisms for outputting information from the computer system 600 to a user or another computer. For example, the user interface output device may include, but is not limited to, various display devices that visually convey text, graphics, and audio / video information, such as screens, printers, speakers, headphones, automotive navigation systems, plotters, voice output devices, and modems.

[0055] The computer system 600 may include a storage subsystem 618 that includes software elements shown as currently residing within system memory 610. The system memory 610 may store program instructions that can be loaded and executed on the processing unit 604 and data generated during the execution of these programs.

[0056] Depending on the configuration and type of the computer system 600, the system memory 610 may be volatile (such as random access memory (RAM)) and / or non-volatile (such as read-only memory (ROM) and flash memory, etc.). RAM typically includes data and / or program modules that can be immediately accessed by the processing unit 604 and / or are currently being operated on and executed by the processing unit 604. In some embodiments, the system memory 610 may include various different types of memory, such as static random access memory (SRAM) or dynamic random access memory (DRAM). In some embodiments, a basic input / output system (BIOS) including basic routines may typically be stored in the ROM, and these basic routines help transfer information between elements within the computer system 600 during, for example, startup. By way of example and not limitation, the system memory 610 also shows an application program 612; the application program 612 may include client applications, web browsers, middle-tier applications, relational database management systems (RDBMS), etc., program data 614, and an operating system 616. For example, the operating system 616 may include various versions of Microsoft Apple and / or Linux operating systems, various commercially available or UNIX-like operating systems (which include but are not limited to various GNU / Linux operating systems, Google OS, etc.) and / or mobile device operating systems, such as iOS, Phone, OS, 10 OS, and OS operating systems.

[0057] The storage subsystem 618 may also provide a tangible computer-readable storage medium for storing the basic program instructions and data constructs that provide the functionality of some embodiments. The software (programs, code modules, instructions) that provides the above functionality when executed by a processor may be stored in the storage subsystem 618. These software modules or instructions may be executed by the processing unit 604. The storage subsystem 618 may also provide a repository for storing data used in accordance with various embodiments.

[0058] The storage subsystem 600 may also include a computer-readable storage medium reader 620; this computer-readable storage medium reader 620 may be further connected to a computer-readable storage medium 622. The computer-readable storage medium 622 may be together with and optionally in combination with the system memory 610; the computer-readable storage medium 622 may comprehensively represent remote, local, fixed, and / or removable storage devices and storage media for temporarily and / or more permanently including, storing, transmitting, and retrieving computer-readable information.

[0059] The computer-readable storage medium 622 including code or portions of code may also include any suitable media known or used in the art; any such suitable media includes storage media and communication media, such as but not limited to volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing and / or transmitting information. This may include tangible computer-readable storage media such as RAM, ROM, electronically erasable programmable ROM (EEPROM), flash memory, or other memory technologies, CD-ROM, digital versatile disc (DVD), or other optical memory, magnetic tape cassettes, magnetic tape, disk storage, or other magnetic storage devices, or other tangible computer-readable media. This may also include intangible computer-readable media such as data signals, data transmissions, or any other medium that can be used to transmit the required information and can be accessed by the computing system 600.

[0060] For example, the computer-readable storage medium 622 may include a hard disk drive that reads from or writes to a non-removable non-volatile magnetic medium, a disk drive that reads from or writes to a removable non-volatile disk, and an optical disk drive that reads from or writes to a removable non-volatile optical disk (such as CD ROM, DVD, and Blu- ray disk and other optical media). The computer-readable storage medium 622 may include but is not limited to: Drives, flash memory cards, universal serial bus (USB) flash drives, secure digital (SD) cards, DVD discs, digital video tapes, etc. The computer-readable storage medium 622 may also include solid-state drives (SSDs) based on non-volatile memory and SSDs based on volatile memory. These non-volatile memory-based SSDs such as flash-based SSDs, enterprise flash drives, and solid-state ROMs, etc. These volatile memory-based SSDs such as solid-state RAM, dynamic RAM, static RAM, DRAM-based SSDs, magnetoresistive RAM (MRAM) SSDs, and hybrid SSDs using a combination of DRAM and flash-based SSDs. The disk drive and its associated computer-readable medium may provide non-volatile storage of computer-readable instructions, data structures, program modules, and other data for the computer system 600.

[0061] The communication subsystem 624 provides an interface to other computer systems and networks. The communication subsystem 624 serves as an interface for receiving data from the computer system 600 and sending data to other systems. For example, the communication subsystem 624 may enable the computer system 600 to connect to one or more devices via the Internet. In some embodiments, the communication subsystem 624 may include radio frequency (RF) transceiver components for accessing wireless voice and / or accessing data networks (e.g., using cellular phone technology, advanced data network technologies such as 3G, 4G, or EDGE (Enhanced Data Rates for Global Evolution)), WiFi (IEEE 802.11 home standards or other mobile communication technologies or any combination thereof), global positioning system (GPS) receiver components, and / or other components. In some embodiments, the communication subsystem 624 may provide wired network connectivity (e.g., Ethernet) as a supplement or alternative to the wireless interface.

[0062] In some embodiments, the communication subsystem 624 may also receive input communications on behalf of one or more users of the computer system 600 in the form of structured and / or unstructured data feeds 626, event streams 628, event updates 630, etc.

[0063] For example, the communication subsystem 624 may be configured to receive data feeds 626 in real time from users of social networks and / or other communication services, such as feed, update, web feeds such as Rich Site Summary (RSS) feeds, and / or real-time updates from one or more third-party information sources.

[0064] In addition, communication subsystem 624 may also be configured to receive data in the form of continuous data streams, which may include event stream 628 and / or event updates 630 of real-time events. These continuous data streams may be continuous or unbounded in nature without a clear end point. Examples of applications that generate continuous data may include, for example, sensor data applications, financial tickers, network performance measurement tools (e.g., network monitoring and traffic management applications), clickstream analysis tools, and automotive traffic monitoring, etc.

[0065] Communication subsystem 624 may also be configured to output structured and / or unstructured data feeds 626, event stream 628, event updates 630, etc. to one or more databases that may communicate with one or more stream data source computers (which are coupled to computer system 600).

[0066] Computer system 600 may be one of various types; these various types include handheld portable devices (e.g., cellular phones, computing tablet computers, PDAs), wearable devices (e.g., Google head-mounted displays), PCs, workstations, mainframes, kiosks, and rack-mounted servers, or any other data processing system.

[0067] Due to the ever-changing nature of computers and networks, the description of computer system 600 depicted in the figure is only intended as a specific example. Many other configurations with more or fewer components than the system depicted in the figure are possible. For example, specific elements may also be implemented using custom hardware and / or available hardware, firmware, software (including small applications), or combinations thereof. In addition, connections to other computing devices, such as network input / output devices, may be employed. Based on the disclosure and teachings provided herein, those of ordinary skill in the art will understand other ways and / or methods of implementing various embodiments.

[0068] In the foregoing description, for purposes of explanation, numerous specific details were set forth in order to provide a thorough understanding of the various embodiments. However, it will be apparent to those skilled in the art that some of these specific details may not be required to practice the embodiments. In other instances, well-known structures and devices are shown in block diagram form.

[0069] The foregoing description provides only exemplary embodiments, and the foregoing description is not intended to limit the scope, applicability, or configuration of the present disclosure. On the contrary, the foregoing description of the exemplary embodiments will provide those skilled in the art with an enabling description for practicing the exemplary embodiments. It should be understood that various changes may be made to the function and arrangement of the elements without departing from the spirit and scope of the various embodiments set forth in the appended claims.

[0070] In the foregoing description, specific details are given to provide a thorough understanding of the embodiments. However, those of ordinary skill in the art will understand that the embodiments may be practiced without these specific details. For example, circuits, systems, networks, processes, and other components may have been shown in block diagram form as components so as not to obscure the embodiments with unnecessary details. In other instances, well-known circuits, processes, algorithms, structures, and techniques may have been shown without unnecessary detail to avoid obscuring the embodiments.

[0071] In addition, it should be noted that the various embodiments may have been described as a process depicted as a flowchart, a flow diagram, a data flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe operations as sequential processing, many operations may be performed in parallel or simultaneously. In addition, the order of the operations may be rearranged. The processing terminates when the operations of the processing are completed, but the processing may have other steps not shown in the figure. The processing may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc. When the processing corresponds to a function, the termination of the processing may correspond to a return of the function to the calling function or the main function.

[0072] The term "computer-readable medium" includes, but is not limited to, portable or fixed storage devices, optical storage devices, wireless channels, and various other media that can store, include, or carry instructions and / or data. A code segment or machine-executable instruction can represent a process, a function, a subroutine, a program, a routine, a subroutine, a module, a software package, a class, or any combination of instructions, data structures, or program statements. A code segment can be coupled to another code segment or a hardware circuit by passing and / or receiving information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc. can be passed, forwarded, or transmitted in any suitable manner, which includes memory sharing, message passing, token passing, network transmission, etc.

[0073] Furthermore, the embodiments may be implemented by hardware, software, firmware, middleware, microcode, a hardware description language, or any combination thereof. When implemented in software, firmware, middleware, or microcode, the program code or code segments for performing the necessary tasks can be stored in a machine-readable medium. A processor or processors can execute the necessary tasks.

[0074] In the foregoing specification, various aspects of the various embodiments have been described with reference to specific embodiments of the various embodiments, but those skilled in the art will recognize that not all embodiments are limited thereto. The various features and aspects of the above embodiments can be used alone or in combination. In addition, the embodiments can be used in any number of environments and applications beyond those described herein without departing from the broader spirit and scope of this specification. Accordingly, the specification and the drawings should be regarded as illustrative rather than restrictive.

[0075] Additionally, for illustrative purposes, the methods are described in a particular order. It should be understood that in alternative embodiments, the methods may be performed in an order different from that described. It should also be understood that the above methods may be performed by hardware components or may be embodied as a sequence of machine-executable instructions that may be used to cause a machine, such as a general or special-purpose processor, or logic circuitry programmed with instructions, to perform these methods. These machine-executable instructions may be stored on one or more machine-readable media, such as a CD-ROM or other type of optical disc, a floppy disc, a ROM, a RAM, an EPROM, an EEPROM, a magnetic or optical card, a flash memory, or other type of machine-readable media suitable for storing electronic instructions. Alternatively, the methods may be performed by a combination of hardware and software.

Claims

1. A method for evaluating the impact of semiconductor material or process variations on a software algorithm, the method comprising the following steps: Receiving, by one or more computer systems, material or process variations for a semiconductor manufacturing process; Converting, by the one or more computer systems, the material or process variations into a characteristic database; Generating, by the one or more computer systems, an original circuit structure using the characteristic database; Performing, by the one or more computer systems, electrical characterization on the original circuit structure; Providing, by the one or more computer systems, the output of the electrical characterization to a script to generate a compact model; Generating, by the one or more computer systems, a trimmed-down standard cell using the compact model; Generating, by the one or more computer systems, a digital system based on the trimmed-down standard cell; and Evaluating, by the one or more computer systems, the performance of a software algorithm on the digital system to determine whether the material or process variations for the semiconductor manufacturing process are acceptable.

2. The method according to claim 1, wherein the original circuit structure includes transistors.

3. The method according to claim 2, wherein the step of performing the electrical characterization on the original circuit structure comprises: Generating current and voltage characteristics of the transistors.

4. The method according to claim 1, further comprising: Performing, by the one or more computer systems, technology computer-aided design (TCAD) simulation of the original circuit structure.

5. The method according to claim 4, further comprising: Generating, by the one or more computer systems, a circuit model of the original circuit structure using the characteristic database and the technology computer-aided design (TCAD) simulation; and Performing, by the one or more computer systems, circuit simulation of the circuit model.

6. The method according to claim 5, further comprising: Determining, by the one or more computer systems, based on the results of the circuit simulation of the circuit model, that the material or process variations for the semiconductor manufacturing process are acceptable.

7. The method according to claim 1, further comprising: Receiving, by the one or more computer systems, multiple material or process variations for the semiconductor manufacturing process; Converting, by the one or more computer systems, the multiple material or process variations into the characteristic database; Generating, by the one or more computer systems, additional original circuit structures for each of the multiple material or process variations using the characteristic database; Simulating, by the one or more computer systems, the additional original circuit structures; and Identifying, by the one or more computer systems, acceptable material or process variations among the multiple material or process variations based on the results of simulating the original circuit structure.

8. A system, comprising: One or more processors; One or more memory devices including instructions that, when executed by the one or more processors, cause the one or more processors to perform operations, the operations including: Receiving material or process variations for a semiconductor manufacturing process; Convert the material or process variation into a characteristic database; Generate an original circuit structure using the characteristic database; Perform electrical characterization on the original circuit structure; Provide the output of the electrical characterization to a script to generate a compact model; Generate a trimmed-down version of a standard cell using the compact model; Generate a digital system based on the trimmed-down version of the standard cell; and Evaluate the performance of a software algorithm on the digital system to determine whether the material or process variation for the semiconductor manufacturing process is acceptable.

9. The system of claim 8, wherein the original circuit structure includes a memory film stack.

10. The system of claim 9, wherein the trimmed-down version of the standard cell includes a memory array.

11. The system of claim 8, wherein the compact model includes a ring oscillator.

12. The system of claim 11, wherein the operation further includes: Test the performance of the ring oscillator to determine power-performance-area-cost (PPAC) characteristics; and Before generating the trimmed-down version of the standard cell, determine that the performance of the ring oscillator is acceptable.

13. The system of claim 8, wherein the trimmed-down version of the standard cell omits features not required by the digital system.

14. The system of claim 8, wherein the software algorithm includes an artificial intelligence (AI) and / or machine learning (ML) algorithm.

15. A non-transitory computer-readable medium including instructions that, when executed by one or more processors, cause the one or more processors to perform operations, the operations include: Receive a material or process variation for a semiconductor manufacturing process; Convert the material or process variation into a characteristic database; Generate an original circuit structure using the characteristic database; Perform electrical characterization on the original circuit structure; Provide the output of the electrical characterization to a script to generate a compact model; Generate a trimmed-down version of a standard cell using the compact model; Generate a digital system based on the trimmed-down version of the standard cell; and Evaluate the performance of a software algorithm on the digital system to determine whether the material or process variation for the semiconductor manufacturing process is acceptable.

16. The non-transitory computer-readable medium of claim 15, wherein the operation further includes: Generate a trimmed-down version of a process design kit (PDK) using the trimmed-down version of the standard cell.

17. The non-transitory computer-readable medium of claim 16, wherein the cells in the process design kit (PDK) use abstract values extracted from the characteristic database.

18. The non-transitory computer-readable medium of claim 16, wherein the trimmed-down version of the process design kit (PDK) may include only the cells affected by the material or process variation for the semiconductor manufacturing process.

19. The non-transitory computer-readable medium of claim 15, wherein the digital system includes a processor.

20. The non-transitory computer-readable medium of claim 15, wherein the operation further includes: Before generating the digital system, at least two short-circuit optimization tests are performed to test the power-performance-area-cost (PPAC) characteristics of the original circuit structure and the standard cells of the trimmed version.

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