Multi-chip stacked device

Abstract

Examples described herein generally relate to multi-chip devices with stacked chips. In one example, a multi-chip device includes a chip stack including chips. Adjacent chips are connected to each other. A plurality of the chips collectively include columns of interrupt via pillars and bridges. Each of the plurality of chips has an interrupt via pillar in each column. The interrupt via pillar has first and second contiguous via pillar portions aligned in a direction that is perpendicular to a side of a semiconductor substrate of the respective chip. The first contiguous via pillar portion is not connected to the second contiguous via pillar portion within the interrupt via pillar. Each of the plurality of chips has one or more of the bridges. Within the respective chip, each bridge connects a first contiguous via pillar portion in one column and a second contiguous via pillar portion in another column.

Description

Technical Field

[0001] Examples of the present disclosure generally relate to multi-chip stack devices including stacked chips. Background Art

[0002] Devices have been developed that include multiple integrated circuit chips, including modules and / or packages. These devices come in a variety of forms. By forming such devices, electronic devices can integrate multiple chips to form a device, where each chip can be manufactured using standard semiconductor processes and then assembled and packaged to form a larger multifunctional device. In some cases, by having different chips, semiconductor processes that are difficult to integrate can be separated, such as when parts of one chip require different processes than another chip.

[0003] Another aspect is the ability to combine devices with chips of different functions (e.g., some field programmable gate array (FPGA) chips and some memory chips) into the same device, resulting in a smaller device size, more functionality, and lower power consumption. Semiconductor processes used for chips can be more focused on giving the device greater advantages in areas such as increasing chip performance, reducing costs, and improving manufacturing yields. Other benefits can be achieved through such devices. Summary of the Invention

[0004] The examples described herein generally relate to multi-chip devices with vertically stacked chips. More specifically, the various chips of the chip stack can include interrupted via columns aligned in columns across multiple chips, where the bridges between the columns can form staggered via columns. The staggered via columns can form a communication path between, for example, a base chip of the chip stack and another chip, with any number of chips inserted between the base chip and the other chip. This example can implement non-programmable, non-volatile structures and communication paths as staggered via columns. Programming of the structures and communication paths can be avoided. These structures can be used in high-voltage operations and can be used in power-up sequences. The same hardware layout can be implemented for the middle chip and / or remote chips in the chip stack, which can reduce the number of tape-outs to implement the chip stack and can reduce the cost of developing the chip stack.

[0005] The example described herein is a multi-chip device. The multi-chip device includes a chip stack. The chip stack includes chips. Adjacent chips in the chips are connected to each other. The plurality of chips collectively include columns and bridges of interrupted via posts. Each chip in the plurality of chips has an interrupted via post in each of the columns. The interrupted via post has a first continuous via post portion and a second continuous via post portion aligned in a direction perpendicular to a side of a semiconductor substrate of the respective chip. The first continuous via post portion is not connected to the second continuous via post portion within the interrupted via post. Each chip in the plurality of chips has one or more bridges in the bridges. Within the respective chip, each of the bridges connects a first continuous via post portion in one of the columns to a second continuous via post portion in another of the columns.

[0006] Another example described herein is a method of operating a multi-chip device. Signals are communicated between a first chip and a second chip. The first chip and the second chip are in a chip stack. One or more intermediate chips are arranged in the chip stack between the first chip and the second chip. At each of the one or more intermediate chips, communicating signals includes communicating signals from one interrupted via post column to another interrupted via post column. Each of the interrupted via post columns in the interrupted via post columns extends through the one or more intermediate chips. Each of the interrupted via post columns in the interrupted via post columns at each of the one or more intermediate chips includes a first continuous via post portion and a second continuous via post portion arranged in the corresponding chip. Within the corresponding interrupted via post column, the first continuous via post portion is not connected to the second continuous via post portion.

[0007] Another example described herein is a multi-chip device. The multi-chip device includes a chip stack. The chip stack includes a chip. A first chip of the chip stack includes a first continuous via post portion, a second continuous via post portion, a third continuous via post portion, and a bridge. The first continuous via post portion has a first solder pad at an interface between the first chip and a lower chip of the chip stack. The first continuous via post portion is connected to active circuitry of the first chip via an interconnect. The second continuous via post portion has a second solder pad at an interface between the first chip and an overlying chip of the chip stack. The second solder pad is aligned with the first solder pad. The second continuous via post portion is not connected to the first continuous via post portion. The third continuous via post portion has a third solder pad at an interface between the first chip and the lower chip. The bridge connects the third continuous via post portion and the second continuous via post portion.

[0008] These and other aspects can be understood with reference to the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order that the manner in which the above features are understood in detail, a more particular description, briefly summarized above, may be obtained by reference to example embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings illustrate only typical example embodiments and are therefore not to be considered as limiting the scope thereof.

[0010] Figure 1 is a structure of a multi-chip device with chip stacking according to some examples.

[0011] Figure 2 is a block diagram of a circuit schematic according to some examples, depicting Figure 1 A multi-chip device is a stack of chips containing integrated circuits.

[0012] Figure 3 Depicts some examples Figure 1 A chip stack having a simplified structure of at least a corresponding portion of the Z-interface of the chip.

[0013] Figure 4 Depicted is another chip stack with a simplified structure of at least a corresponding portion of a Z-interface of the chip, according to some examples.

[0014] Figure 5 Based on some examples Figure 1 A flow chart of a method for a multi-chip device.

[0015] Figure 6 is a flow chart of a method of operating a multi-chip device according to some examples.

[0016] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements of one example may be beneficially incorporated in other examples. DETAILED DESCRIPTION

[0017] The examples described herein generally relate to multi-chip devices with vertically stacked chips. More specifically, some examples described herein relate to structures within a chip of the stacked chips for communicating signals between the chips. Typically, a chip stack can include a base chip, one or more intermediate chips, and a remote chip, wherein the one or more intermediate chips are arranged between the base chip and the remote chip. A column of interrupted via posts is formed through the one or more intermediate chips and in some examples, the column of interrupted via posts is formed into the remote chip. Within each column in a column in each of the chips through which the corresponding column extends, the corresponding column includes a first continuous via post portion and a second continuous via post portion aligned within the column (e.g., in a direction perpendicular to the front side of the semiconductor substrate of the corresponding chip). Within the corresponding column, the first continuous via post portion and the second continuous via post portion are not connected to each other. Within each of these chips, a bridge extends between the first continuous via post portion of one column and the second continuous via post portion of another column and connects the two portions. The first continuous via post portion of one column and the second continuous via post portion of another column are connected by a bridge to form an intersecting via post that passes through the corresponding chip.

[0018] Each chip in the (multiple) intermediate chips and the remote chips may include active circuits. Each active circuit of the corresponding chip can be connected to the same column of interrupted via posts for communicating signals between the corresponding active circuit and the base chip. The base chip may have interfaces, such as interfaces of bonding pads, that are connected to different columns of interrupted via posts. The base chip may have circuits configured to communicate with different active circuits of other chips. At the base chip, signals can be communicated to target active circuits on different chips through different columns. At each chip between the base chip and the chip including the target active circuit, the signal can be converted from one column to another. This conversion may cause the signal to communicate with the active circuit through the same column (although on different chips).

[0019] For example, stacking chips in a three-dimensional integrated circuit (3DIC) can create multiple and larger final products with different chip combinations. If chips with the same hardware layout are implemented in a chip stack, this can reduce the number of tapeouts required and can reduce product development costs. Larger products (e.g., field programmable gate arrays (FPGAs), systems on chips (SoCs), processors, and / or application-specific integrated circuits (ASICs)) can be created by stacking chips with the same hardware layout, thereby utilizing fewer (e.g., one) tapeouts. When the chips used in a chip stack have the same hardware layout, costs can be saved because, for example, research and development can be reduced due to fewer tapeouts.

[0020] One challenge with stacking chips, where multiple chips have the same hardware layout, is communicating signals between the chips. Because each chip with the same hardware layout receives or transmits signals at the same physical location within the corresponding chip, signals intended for one chip are also received at every chip with the same hardware layout. Various previous solutions have addressed this issue by programming the active circuitry to control the communication of signals between the different active circuits. However, challenges with these previous solutions are that, for example, programmability can create reliability issues and / or controls may not be programmable prior to power-up, which can prevent certain signals from being communicated during the power-up sequence.

[0021] To address these challenges, in some examples described herein, staggered via columns can be implemented in chips with the same hardware layout so that signals communicating with active circuits on different chips in the chip can be transmitted or received at the same physical location (e.g., through the same column) at the corresponding chip. Signals communicating with active circuits of different chips can be communicated through, for example, different columns at the base chip. Thus, signals can communicate with the base chip through different columns at the base chip, can be converted to other columns at any intermediate chip, and communicate with active circuits of different chips through the same column at the corresponding chip. This example can implement non-programmable, non-volatile structures and communication paths as staggered via columns. Therefore, programming of structures and communication paths can be avoided. These structures can be used in high-voltage operations and can be used in power-up sequences. In addition, the same hardware layout can be implemented for intermediate chips and / or remote chips, which can reduce the number of tape-outs to implement chip stacking and can reduce the cost of developing chip stacking.

[0022] Various features are described below with reference to the accompanying drawings. It should be noted that the drawings may be drawn to scale or not, and throughout the drawings, elements with similar structures or functions are represented by similar reference numerals. It should be noted that the drawings are intended only to facilitate the description of the features. They are not intended to be an exhaustive description of the claimed invention or to limit the scope of the claimed invention. In addition, the illustrated examples do not necessarily have all the aspects or advantages shown. The aspects or advantages described in conjunction with a particular example are not necessarily limited to that example and can be practiced in any other example, even if not illustrated or explicitly described as such. In addition, the methods described herein can be described in a specific order of operations, but other methods according to other examples can be implemented in various other orders with more or fewer operations (for example, including different serial or parallel executions of various operations). Various components described as "first component", "second component", etc. in a component do not mean or imply any structure or position generated by "first", "second", etc. "First", "second", etc. are used herein to easily refer to different components.

[0023] Figure 1 is a structure of a multi-chip device according to some examples. Figure 1 The multi-chip device includes a chip stack including a base chip 102 and fabric chips 104, 106, and 108. The base chip 102 and the fabric chips 104-108 are described herein as examples. Although the different chips are described herein as or including various integrated circuits (ICs) or components (e.g., fabric, base, programmable logic, etc.), the aspects described herein can be generally applicable to chips of a multi-chip device having any type of IC or component.

[0024] exist Figure 1 In some multi-chip devices, the fabric chips 104-108 are arranged with their active sides or front sides facing down toward the base chip 102, with the base chip 102 arranged with its active side or front sides facing up toward the fabric chips 104-108. In other multi-chip devices, the middle fabric chips are arranged with their active sides or front sides facing up away from the base chip 102, and the distal fabric chips are arranged with their active sides or front sides facing down toward the base chip 102, with the base chip 102 arranged with its active side or front sides facing up toward the fabric chips 104-108. Various other multi-chip devices may have different structures, different numbers of chips, additional components, etc.

[0025] Typically, chips 102-108 are stacked and form a chip stack in a multi-chip device. In some examples, chips 102-108 are stacked to form an active die on active die (AoA) device. Each chip in chips 102-108 may include an active IC. In some examples, more or fewer chips may be included in the chip stack. For example, a multi-chip device may have two chips, such as a base chip and a fabric chip, or two fabric chips. In other examples, a multi-chip device may have three chips, four chips, five chips, etc.

[0026] Each of the chips 102-108 includes a respective semiconductor substrate 112, 114, 116, 118 and includes a respective front dielectric layer 122, 124, 126, 128 on the front side of the respective semiconductor substrate 112-118. The front dielectric layers 122-128 include metallization (e.g., metal lines and / or vias) formed therein (illustrated but not specifically numbered), which can electrically connect various components in the IC. Each of the chips 102-106 includes a respective back dielectric layer 132, 134, 136 on the back side of the respective semiconductor substrate 112-116. The back dielectric layers 132-136 include metallization (e.g., metal lines and / or vias) formed therein (illustrated but not specifically numbered), which can electrically connect various components in the IC. As illustrated, the metallization in the front-side dielectric layers 124, 126, 128 of the fabric chips 104, 106, 108 is connected to corresponding circuit regions 143, 145, 147 of the fabric chips 104, 106, 108, where corresponding active circuits may be formed. Such connections and example active circuits will be described in more detail below in the context of subsequent figures.

[0027] Each semiconductor substrate 112-118 of chips 102-108 includes, for example, transistors 142, 144, 146, 148 formed on and / or in the front-side surface of the respective semiconductor substrate 112-118. Transistors 142-148 and any other components may be connected to metallization in the front-side dielectric layers 122-128. Transistors 144, 146, 148 are illustrated as being in respective circuit regions 143, 145, 147 of the fabric chips 104, 106, 108; however, transistors 144, 146, 148 and / or other transistors may be outside of circuit regions 143, 145, 147. Each semiconductor substrate 112 - 116 of a respective chip 102 - 106 has a backside through-substrate via (TSV) 162 , 164 , 166 therethrough that may connect metallization in the frontside dielectric layer 122 - 126 to metallization in the backside dielectric layer 132 - 136 of the respective chip 102 - 106 .

[0028] Front side bonding pads 152, 154, 156, 158 (e.g., metal (e.g., Cu) bonding pads) are formed in the respective front side dielectric layers 122-128 of the chips 102-108 at outer surfaces remote from the respective semiconductor substrates 112-118. The front side bonding pads 152-158 can be arranged to form respective chip-to-chip interfaces. The front side bonding pads 152-158 are connected to the metallization in the respective front side dielectric layers 122-128. Back side bonding pads 174, 176 (e.g., metal (e.g., Cu) bonding pads) are formed in the respective back side dielectric layers 134, 136 of the structure chips 104, 106 at outer surfaces remote from the respective semiconductor substrates 114, 116. The back side bonding pads 174, 176 can be arranged to form respective chip-to-chip interfaces. The backside bond pads 174 , 176 are connected to the metallization in the respective backside dielectric layers 134 , 136 .

[0029] External connector backside pads 172 (e.g., metal (e.g., aluminum) pads) are formed in the backside dielectric layer 132 of the base chip 102 at an outer surface of the semiconductor substrate 112 remote from the base chip 102. The external connector backside pads 172 are connected to the metallization in the backside dielectric layer 132 of the base chip 102. A passivation layer 180 is formed on an outer surface of the semiconductor substrate 112 remote from the base chip 102, having corresponding openings therethrough that expose the external connector backside pads 172. External connectors 182 (e.g., controlled collapse chip connections (C4), microbumps, etc.) are formed on corresponding external connector backside pads 172 through the openings in the passivation layer 180.

[0030] External connector 182 can be attached to the package substrate. The package substrate can be further attached to, for example, a printed circuit board (PCB) to attach the package substrate (and therefore the multi-chip device) to the PCB. Various other components can be included in the multi-chip device. For example, the multi-chip device can include an interposer, an encapsulant (such as a mold compound (MUF), etc.). A person of ordinary skill in the art will readily appreciate the various modifications that can be made to the multi-chip device.

[0031] The chips 102-108 are bonded together (e.g., using a hybrid bonding method of metal-metal and oxide-oxide bonding) to form a chip stack. The base chip 102 is bonded to the structure chip 104 from front to front, such that the front bonding pads 152 of the base chip 102 and the outer surface of the front dielectric layer 122 are bonded to the front bonding pads 154 and the outer surface of the front dielectric layer 124 of the structure chip 104. The structure chip 104 is bonded to the structure chip 106 from back to front, such that the back bonding pads 174 of the structure chip 104 and the outer surface of the back dielectric layer 134 are bonded to the front bonding pads 156 and the outer surface of the front dielectric layer 126 of the structure chip 106. The structure chip 106 is bonded to the structure chip 108 from back side to front side such that back side bonding pads 176 of the structure chip 106 and the outer surface of the back side dielectric layer 136 are bonded to front side bonding pads 158 of the structure chip 108 and the outer surface of the front side dielectric layer 128 .

[0032] Other bonding arrangements can be implemented. For example, the base chip 102 can be bonded to the structure chip 104 from front to back, such that the front bonding pads 152 of the base chip 102 and the outer surface of the front dielectric layer 122 are bonded to the back bonding pads 174 and the outer surface of the back dielectric layer 134 of the structure chip 104. The structure chip 104 can be bonded to the structure chip 106 from front to back, such that the front bonding pads 154 of the structure chip 104 and the outer surface of the front dielectric layer 124 are bonded to the back bonding pads 176 and the outer surface of the back dielectric layer 136 of the structure chip 106. The structure chip 106 can be bonded to the structure chip 108 from front to front, such that the front bonding pads 156 of the structure chip 106 and the outer surface of the front dielectric layer 126 are bonded to the front bonding pads 158 of the structure chip 108 and the outer surface of the front dielectric layer 128.

[0033] In other examples, chips 102-108 can be attached together using external connectors such as microbumps, solder, etc. In some examples, some of chips 102-108 can be attached together using external connectors, while other chips can be bonded together without using external connectors. Any arrangement of bonding and use of external connectors can be implemented.

[0034] Any chip in the chip stack may include a Z-interface circuit. The Z-interface circuit can enable communication of signals between chips in the chip stack. The Z-interface circuit may include staggered via posts. Each staggered via post includes a first continuous via post portion (e.g., which includes a TSV) in a first interrupted via post and a second continuous via post portion (e.g., which does not include a TSV) in a second interrupted via post, wherein a bridge (e.g., a metal line) extends between the first continuous via post portion and the second continuous via post portion and connects the two portions.

[0035] Each interrupted via post includes metal lines / pads and vias in a corresponding front dielectric layer, TSVs passing through a corresponding semiconductor substrate, and metal lines / pads and / or vias in a corresponding back dielectric layer, wherein the metal lines / pads, vias, and TSVs are generally aligned in a direction perpendicular to the front side of the corresponding semiconductor substrate. A continuous via post portion of the interrupted via post is formed by metal lines / pads and vias in the corresponding back dielectric layer, TSVs, and at least some of the metal lines / pads and vias in the corresponding front dielectric layer, and another continuous via post portion of the interrupted via post is formed by at least some of the metal lines / pads and vias in the corresponding front dielectric layer. In the interrupted via post, different continuous via post portions in the interrupted via post are not connected to each other (e.g., metal features such as vias or metal lines / pads are omitted at the metal layer in the interrupted via post).

[0036] Columns of interrupted via posts can be arranged and aligned across multiple chips in a chip stack, such as across fabric chips 104-108. Each column can include one or more interrupted via posts in each of the multiple chips. Thus, interdigitated via posts in a chip can be bridged across two columns in the multiple chips. In this configuration, each of the multiple chips can transmit signals to or receive signals from the same column. When a signal propagates through any intermediate chip, the signal is converted to another column at each intermediate chip through a bridge of interdigitated via posts. Additional details of the Z-interface circuit are described below. Any of the chips 102-108 can include a Z-interface circuit, but in some examples, the remote fabric chip 108 can omit TSVs and / or metallization in the back dielectric layer because the remote fabric chip 108 may not undergo backside processing.

[0037] In some examples, each of the fabric chips 104-108 includes a processing IC. The processing IC may generally include any circuit configured or configurable to process any data and / or signal and output the data and / or signal generated by the processing, and is not limited to any circuits of the memory and auxiliary memory (e.g., address decoders, memory controllers, etc.). The processing ICs of the fabric chips 104-108 are generally the same IC. In some examples, the hardware topology, architecture, and layout of the fabric chips 104-108 are the same, except that the remote fabric chip 108 may omit components formed by backside processing, such as backside TSVs, backside dielectric layers, and / or metallization in the backside dielectric layers. In some examples, the processing ICs of the fabric chips 104-108 include one or more programmable logic regions (e.g., the structure of an FPGA), and the processing ICs have the same hardware topology, architecture, and layout between the fabric chips 104-108. Having a Z-interface in the fabric chips 104-108 allows chips that undergo the same front side processing to be integrated into a multi-chip device.

[0038] In other examples, chips 102-108 may each be or include a different IC, or may have any arrangement including the same IC and / or different ICs. For example, any of fabric chips 104-108 may be or include a processing IC or memory. In some examples, chip 108 is an ASIC. Any of chips 102-108 may be collectively referred to as an active chip.

[0039] Figure 2 is a block diagram of a circuit schematic according to some examples, which depicts Figure 1 The multi-chip device is a multi-chip programmable device. For example, the circuit diagram can be implemented in Figure 1 In a multi-chip device, regardless of the orientation of the fabric chips 104, 106.

[0040] In the example shown, the base chip 102 includes a base IC on the base chip 102, which may be a SoC. The fabric chips 104, 106, 108 include corresponding programmable logic (PL) ICs 224, 226, 228. In some examples, the ICs 224, 226, 228 are identical ICs and have the same hardware layout and topology. These ICs are provided as example implementations. Other ICs (e.g., with other hard IP blocks) may be implemented in the chip. The fabric chips 104, 106, 108 also include corresponding Z-interfaces 234, 236, 238.

[0041] The basic IC on the basic chip 102 includes a processing system 202, input / output circuits (IO) 204, IP core circuits 206, a network on chip (NoC) 210, and a Z-interface 232. The processing system 202 can be or include any of a variety of different processor types and numbers of processor cores. For example, the processing system 202 can be implemented as a separate processor, such as a single core capable of executing program instruction codes. In another example, the processing system 202 can be implemented as a multi-core processor. The processing system 202 can be implemented using any of a variety of different types of architectures. Example architectures that can be used to implement the processing system 202 may include an ARM processor architecture, an x86 processor architecture, a graphics processing unit (GPU) architecture, a mobile processor architecture, a reduced instruction set computer (RISC) architecture (e.g., RISC-V), or other suitable architectures capable of executing computer-readable program instruction codes.

[0042] The input / output circuitry 204 may include extreme performance input / output (XPIO), multi-gigabit transceivers (MGTs), high bandwidth memory (HBM) interfaces, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), or any other input / output blocks. The input / output circuitry 204 may be configured to receive and / or transmit signals from and / or to circuits external to the multi-chip device. The IP core circuitry 206 may include a memory controller (such as a double data rate (DDR) memory controller, a high bandwidth memory (HBM) memory controller, etc.), a peripheral component interconnect express (PCIe) interface, a cache coherent interconnect for accelerators (CCIX) interface, an Ethernet core (such as a media address controller (MAC), etc.), a forward error correction (FEC) block, and / or any other hardened circuitry. Any of the input / output circuitry 204 and / or the IP core circuitry 206 may be programmable.

[0043] NoC 210 includes a programmable network 212 and a NoC peripheral interconnect (NPI) 214. Programmable network 212 communicatively couples the subsystems of the base ICs and any other circuits on base chip 102. Programmable network 212 includes NoC packet switches and interconnects connecting the NoC packet switches. Each NoC packet switch performs NoC packet switching within programmable network 212. At the edge of programmable network 212, programmable network 212 has interface circuits. The interface circuits include NoC master units (NMUs) and NoC slave units (NSUs). Each NMU is an ingress circuit connecting a master circuit to programmable network 212, and each NSU is an egress circuit connecting programmable network 212 to a slave endpoint circuit. The NMUs are communicatively coupled to the NSUs via the NoC packet switches and interconnects of programmable network 212. The NoC packet switches are connected to each other and to the NMUs and NSUs via interconnects to implement multiple physical channels within programmable network 212. The NoC packet switch, NMU, and NSU include a register block that determines the operation of the corresponding NoC packet switch, NMU, or NSU.

[0044] The NPI 214 includes circuitry for writing register blocks that determine the functionality of the NMU, NSU, and NoC packet switches. The NPI 214 includes peripheral interconnects coupled to the register blocks for programming them to set functionality. The register blocks in the NMU, NSU, and NoC packet switches of the programmable network 212 support interrupts, quality of service (QoS), error handling and reporting, transaction control, power management, and address mapping control. The NPI 214 may include an NPI root node residing on the processing system 202 (e.g., the platform management controller (PMC) of the processing system 202), interconnected NPI switches connected to the NPI root node, and protocol blocks connected to the interconnected NPI switches and corresponding register blocks. The NPI 214 can be used to program any programmable circuit of the base IC on the base chip 102. For example, the NPI 214 can be used to program any programmable input / output circuit 204 and / or IP core circuit 206.

[0045] The Z-interface 232 may include active circuits, such as buffers for driving signals. The Z-interface 232 provides an interface (including through-metal lines / pads and vias in the metallization layers) to connect the processing system 202, input / output circuitry 204, IP core circuitry 206, and programmable network 212 of the NoC 210 to the chip covering the base chip 102 and / or the substrate (e.g., a package substrate) beneath the base chip 102. In addition, the Z-interface 232 may provide a direct interface through the base chip 102.

[0046] The various subsystems and circuits of the base IC on base chip 102 can be communicatively coupled. As illustrated, processing system 202, input / output circuitry 204, and IP core circuitry 206 are connected to NoC 210 (e.g., to programmable network 212) and, therefore, are communicatively coupled to one another. Processing system 202 is also connected to NPI 214 for communicating configuration data to the various programmable components on base chip 102. Processing system 202 is also connected to programmable network 212 of NoC 210 for communicating configuration data to chips overlying base chip 102. Programmable network 212 of NoC 210 is connected to Z-interface 232 so that data, such as transaction data and configuration data, can be communicated to another chip via Z-interface 232. Each of processing system 202, input / output circuitry 204, and IP core circuitry 206 is connected to Z-interface 232 for communicating with programmable logic in, for example, PL ICs 224, 226, 228 in overlying fabric chips 104, 106. Other communication mechanisms between the various subsystems and circuits may be implemented, such as direct connections.

[0047] The PL ICs 224-228 on each of the fabric chips 104-108 include one or more programmable logic regions. A programmable logic region is a logic circuit system that can be programmed to perform a specified function. A programmable logic region can include any number or arrangement of programmable blocks. As an example, a programmable logic region can be implemented as a structure of an FPGA. For example, a programmable logic region can include any number of configurable logic blocks (CLBs), lookup tables (LUTs), digital signal processing blocks (DSPs), random access memory blocks (BRAMs), etc. Each programmable block in the programmable blocks (e.g., CLBs, LUTs, DSPs, BRAMs, etc.) can include one or more programmable interconnect elements. For example, various corresponding types of programmable blocks can be arranged in rows and / or columns, and associated programmable interconnect elements can be connected to adjacent programmable logic elements in the same columns and rows. The programmable interconnect elements can form an interconnect network of programmable logic regions. Any logic and connection can be implemented by the programmable logic region by programming or configuring any programmable block in the programmable logic region.

[0048] The Z-interface 234-238 on each of the fabric chips 104-108 may include active circuits, such as buffers and / or selection circuits for driving signals. The Z-interface 234-238 provides an interface (including vias through metal lines and metallization layers) to enable the corresponding PL IC 224-228 to communicate with the chip above and / or below the corresponding fabric chip 104-108. In addition, the Z-interface 234-238 can provide a direct interface through the corresponding fabric chip 104-108. An example of a column of interrupted via posts with intersecting via posts that can implement a direct interface is described in more detail below. For example, configuration data for the PL IC 224-228 can be transmitted via a passive connection through the Z-interface 234-238.

[0049] Each PL IC 224-228 may also include a configuration interconnect that includes a configuration frame (CFRAME) driver. The CFRAME driver may be or include control logic to communicate configuration data (such as a bitstream) to configure the programmable logic. Each programmable logic region is configurable or programmable via configuration data received via the Z-interface 232, the corresponding Z-interface 234-238 of the corresponding fabric chip 104-108, and any intermediate Z-interfaces 234, 236. For example, the processing system 202 (e.g., the PMC of the processing system 202) may transmit configuration data to the corresponding PL IC 224-228 via the programmable network 212 of the NoC 210 and the Z-interface 232. In some examples, the configuration interconnect (e.g., including the CFRAME driver) may direct the configuration data to the appropriate programmable block and may control the configuration of such programmable block.

[0050] Figure 3 The diagram shows some examples Figure 1 The chip stack has a simplified structure of at least corresponding portions of the Z-interfaces 234, 236, 238 of the fabric chips 104, 106, 108. Although described with respect to the fabric chips 104, 106, 108, aspects of the described Z-interfaces may be applicable to the Z-interface 232 of the base chip 102. Figure 3 The structure chips 104 - 108 are illustrated with their front sides oriented toward the base chip 102 .

[0051] The Z-interface 234 of the structure chip 104 includes: a first interrupted via post, which includes a first continuous via post portion 304-11 and a second continuous via post portion 304-12; a second interrupted via post, which includes a first continuous via post portion 304-21 and a second continuous via post portion 304-22; a third interrupted via post, which includes a first continuous via post portion 304-31 and a second continuous via post portion 304-32; and a fourth interrupted via post, which includes a first continuous via post portion 304-41 and a second continuous via post portion 304-42. Although not shown in FIG. Figure 3 Although specifically marked, reference is made to the first interrupted via column 304-1, the second interrupted via column 304-2, the third interrupted via column 304-3 and the fourth interrupted via column 304-4.

[0052] The first continuous via post portion 304-11 of the first interrupted via post 304-1 includes metal lines / pads (including backside bonding pad 174-1) in the backside dielectric layer 134, a backside TSV 164-1 extending through the semiconductor substrate 114, and metal lines / pads in the frontside dielectric layer 124. The second continuous via post portion 304-12 of the first interrupted via post 304-1 includes metal lines / pads (including frontside bonding pad 154-1) in the frontside dielectric layer 124. The first continuous via post portion 304-21 of the second interrupted via post 304-2 includes metal lines / pads (including backside bonding pad 174-2) in the backside dielectric layer 134, a backside TSV 164-2 extending through the semiconductor substrate 114, and metal lines / pads in the frontside dielectric layer 124. The second continuous via post portion 304-22 of the second interrupted via post 304-2 includes metal lines / pads (including the front bonding pad 154-2) in the front dielectric layer 124. The first continuous via post portion 304-31 of the third interrupted via post 304-3 includes metal lines / pads (including the back bonding pad 174-3) in the back dielectric layer 134, the back TSV 164-3 passing through the semiconductor substrate 114, and the metal lines / pads in the front dielectric layer 124. The second continuous via post portion 304-32 of the third interrupted via post 304-3 includes metal lines / pads (including the front bonding pad 154-3) in the front dielectric layer 124. A first continuous via post portion 304-41 of the fourth interrupted via post 304-4 includes metal lines / pads (including backside bonding pad 174-4) in the backside dielectric layer 134, a backside TSV 164-4 passing through the semiconductor substrate 114, and metal lines / pads in the frontside dielectric layer 124. A second continuous via post portion 304-42 of the fourth interrupted via post 304-4 includes metal lines / pads (including frontside bonding pad 154-4) in the frontside dielectric layer 124.

[0053] The metal lines / pads, vias, and TSVs (including in the corresponding first continuous via post portion and the corresponding second continuous via post portion) in each interrupted via post 304-1, 304-2, 304-3, 304-4 are aligned within the corresponding interrupted via post in a direction perpendicular to the front surface of the semiconductor substrate 114. Even more generally, the first continuous via post portion and the second continuous via post portion of the corresponding interrupted via post 304-1, 304-2, 304-3, 304-4 are aligned within the corresponding interrupted via post in a direction perpendicular to the front surface of the semiconductor substrate 114. In this example, the first continuous via post portion typically includes a vertically stacked back bonding pad, a metal line and / or via in the back dielectric layer, a TSV, and a metal line and / or via in the front dielectric layer, which are continuously connected together. In this example, the second continuous via post portion generally includes vertically stacked metal lines and / or vias in the front-side dielectric layer and the front-side bond pads, which are continuously connected together.

[0054] Within the respective interrupted via posts 304-1, 304-2, 304-3, 304-4, a first continuous via post portion is not connected to a second continuous via post portion. Typically, each of the interrupted via posts 304-1, 304-2, 304-3, 304-4 is not continuously connected through the metallization of the respective front-side dielectric layer 124 of the fabric chip 104. More specifically, the respective first continuous via post portions 304-11, 304-21, 304-31, 304-41 of the interrupted via posts 304-1, 304-2, 304-3, 304-4 are not connected to the respective second continuous via post portions 304-12, 304-22, 304-32, 304-42 of the interrupted via posts 304-1, 304-2, 304-3, 304-4. For example, no metal features (such as vias) are directly connected to the bridges 314-21, 314-32 in the second interrupted via column 304-2 and no metal features are between the bridges 314-21, 314-32, and no metal features (such as vias) are directly connected to the bridges 314-32, 314-43 in the third interrupted via column 304-3 and no metal features are between the bridges 314-32, 314-43.

[0055] The Z-interfaces 236 and 238 of the fabric chips 106 and 108 include interrupted via posts similar to the Z-interface 234 of the fabric chip 104. The Z-interface 236 of the fabric chip 106 includes: a first interrupted via post including a first continuous via post portion 306-11 and a second continuous via post portion 306-12; a second interrupted via post including a first continuous via post portion 306-21 and a second continuous via post portion 306-22; a third interrupted via post including a first continuous via post portion 306-31 and a second continuous via post portion 306-32; and a fourth interrupted via post including a first continuous via post portion 306-41 and a second continuous via post portion 306-42. Although not described in Figure 3 Specific reference is made to the first interrupted via post 306-1, the second interrupted via post 306-2, the third interrupted via post 306-3, and the fourth interrupted via post 306-4. The interrupted via posts 306-1, 306-2, 306-3, and 306-4 are configured in the fabric chip 106 in the same manner as the interrupted via posts 304-1, 304-2, 304-3, and 304-4 are configured in the fabric chip 104.

[0056] The Z-interface 238 of the structure chip 108 includes: a first interrupted via post, which includes a first continuous via post portion 308-11 and a second continuous via post portion 308-12; a second interrupted via post, which includes a first continuous via post portion 308-21 and a second continuous via post portion 308-22; a third interrupted via post, which includes a first continuous via post portion 308-31 and a second continuous via post portion 308-32; and a fourth interrupted via post, which includes a first continuous via post portion 308-41 and a second continuous via post portion 308-42. Although not shown in FIG. Figure 3 8. Specifically identified in FIG. 1 , reference is made to the first interrupted via post 308-1, the second interrupted via post 308-2, the third interrupted via post 308-3, and the fourth interrupted via post 308-4. The interrupted via posts 308-1, 308-2, 308-3, 308-4 are configured in the fabric chip 108 in the same manner as the interrupted via posts 304-1, 304-2, 304-3, 304-4 are configured in the fabric chip 104, except that there are no corresponding TSVs and metal lines / pads and vias in the backside dielectric layer because the fabric chip 108 does not undergo backside processing. One of ordinary skill in the art will readily appreciate the similarities and differences between the previous discussion and the components of the fabric chip 104. Figure 3 The relationship between the components of the fabric chips 106, 108 is shown in FIG.

[0057] The interrupted via pillars are aligned in columns across the fabric chips 104-108. The first interrupted via pillars 304-1, 306-1, 308-1 in the fabric chip 104-108 are aligned in the first column. The second interrupted via pillars 304-2, 306-2, 308-2 in the fabric chip 104-108 are aligned in the second column. The third interrupted via pillars 304-3, 306-3, 308-3 in the fabric chip 104-108 are aligned in the third column. The fourth interrupted via pillars 304-4, 306-4, 308-4 in the fabric chip 104-108 are aligned in the fourth column.

[0058] Utilizing this alignment, various continuous via post sections on different chips are connected via bond pads bonded together at a bonding interface. A first continuous via post section 304-11 on fabric chip 104 is connected to a second continuous via post section 306-12 on fabric chip 106 by bonding backside bond pad 174-1 to frontside bond pad 156-1. A first continuous via post section 304-21 on fabric chip 104 is connected to a second continuous via post section 306-22 on fabric chip 106 by bonding backside bond pad 174-2 to frontside bond pad 156-2. A first continuous via post section 304-31 on fabric chip 104 is connected to a second continuous via post section 306-32 on fabric chip 106 by bonding backside bond pad 174-3 to frontside bond pad 156-3. The first continuous via post portion 304 - 41 on the fabric chip 104 is connected to the second continuous via post portion 306 - 42 on the fabric chip 106 by bonding the backside bond pad 174 - 4 to the frontside bond pad 156 - 4 .

[0059] By bonding the backside bonding pad 176-1 to the frontside bonding pad 158-1, the first continuous via post portion 306-11 on the fabric chip 106 is connected to the second continuous via post portion 308-12 on the fabric chip 108. By bonding the backside bonding pad 176-2 to the frontside bonding pad 158-2, the first continuous via post portion 306-21 on the fabric chip 106 is connected to the second continuous via post portion 308-22 on the fabric chip 108. By bonding the backside bonding pad 176-3 to the frontside bonding pad 158-3, the first continuous via post portion 306-31 on the fabric chip 106 is connected to the second continuous via post portion 308-32 on the fabric chip 108. The first continuous via post portion 306 - 41 on the fabric chip 106 is connected to the second continuous via post portion 308 - 42 on the fabric chip 108 by bonding the backside bond pad 176 - 4 to the frontside bond pad 158 - 4 .

[0060] The respective bridges are arranged to extend between a first continuous via post portion of a corresponding interrupted via post in one column within the chip and a second continuous via post portion of a corresponding different interrupted via post in a different column within the chip, and connect the two portions. Each bridge in the illustrated example is a metal line arranged in a corresponding front-side dielectric layer. For example, the bridge can include multiple lines / pads and / or vias and can be arranged in the back-side dielectric layer.

[0061] The second-to-first bridge 314-21 forms the second continuous via column portion 304-22 of the second interrupted via column 304-2 and at least the corresponding portion of the first continuous via column portion 304-11 of the first interrupted via column 304-1, extending between the two portions and connecting the two portions. The third-to-second bridge 314-32 forms the second continuous via column portion 304-32 of the third interrupted via column 304-3 and at least the corresponding portion of the first continuous via column portion 304-21 of the second interrupted via column 304-2, extending between the two portions and connecting the two portions. The fourth-to-third bridge 314-43 forms the second continuous via column portion 304-42 of the fourth interrupted via column 304-4 and at least the corresponding portion of the first continuous via column portion 304-31 of the third interrupted via column 304-3, extending between the two portions and connecting the two portions.

[0062] The second-to-first bridge 316-21 forms the second continuous via column portion 306-22 of the second interrupted via column 306-2 and at least the corresponding portion of the first continuous via column portion 306-11 of the first interrupted via column 306-1, extending between the two portions, and connecting the two portions. The third-to-second bridge 316-32 forms the second continuous via column portion 306-32 of the third interrupted via column 306-3 and at least the corresponding portion of the first continuous via column portion 306-21 of the second interrupted via column 306-2, extending between the two portions, and connecting the two portions. The fourth-to-third bridge 316-43 forms the second continuous via column portion 306-42 of the fourth interrupted via column 306-4 and at least the corresponding portion of the first continuous via column portion 306-31 of the third interrupted via column 306-3, extending between the two portions, and connecting the two portions.

[0063] The second-to-first bridge 318-21 forms the second continuous via column portion 308-22 of the second interrupted via column 308-2 and at least the corresponding portion of the first continuous via column portion 308-11 of the first interrupted via column 308-1, extending between the two portions, and connecting the two portions. The third-to-second bridge 318-32 forms the second continuous via column portion 308-32 of the third interrupted via column 308-3 and at least the corresponding portion of the first continuous via column portion 308-21 of the second interrupted via column 308-2, extending between the two portions, and connecting the two portions. The fourth-to-third bridge 318-43 forms the second continuous via column portion 308-42 of the fourth interrupted via column 308-4 and at least the corresponding portion of the first continuous via column portion 308-31 of the third interrupted via column 308-3, extending between the two portions, and connecting the two portions.

[0064] Each first continuous via post portion and second continuous via post portion connected together by a bridge forms an intersecting via post within the corresponding chip. The first continuous via post portion 304-11, the second to first bridge 314-21, and the second continuous via post portion 304-22 form an intersecting via post. The first continuous via post portion 304-21, the third to second bridge 314-32, and the second continuous via post portion 304-32 form an intersecting via post. The first continuous via post portion 304-31, the fourth to third bridge 314-43, and the second continuous via post portion 304-42 form an intersecting via post.

[0065] The first continuous via post portion 306-11, the second to first bridge 316-21, and the second continuous via post portion 306-22 form an intersecting via post. The first continuous via post portion 306-21, the third to second bridge 316-32, and the second continuous via post portion 306-32 form an intersecting via post. The first continuous via post portion 306-31, the fourth to third bridge 316-43, and the second continuous via post portion 306-42 form an intersecting via post.

[0066] The first continuous via post portion 308-11, the second to first bridge 318-21, and the second continuous via post portion 308-22 form an intersecting via post. The first continuous via post portion 308-21, the third to second bridge 318-32, and the second continuous via post portion 308-32 form an intersecting via post. The first continuous via post portion 308-31, the fourth to third bridge 318-43, and the second continuous via post portion 308-42 form an intersecting via post.

[0067] Furthermore, second-to-first bridges 314-21, 316-21, and 318-21 are connected to input or output nodes of active circuits (e.g., PL ICs 224, 226, and 228) of corresponding fabric chips 104-108. As illustrated, second-to-first bridge 314-21 is connected to PL IC 224 via interconnect 324 (e.g., metal wires / pads and / or vias); second-to-first bridge 316-21 is connected to PL IC 226 via interconnect 326; and second-to-first bridge 318-21 is connected to PL IC 228 via interconnect 328. The nodes of the active circuits to which the second-to-first bridges are connected can be input nodes, output nodes, or bidirectional nodes. Thus, signals can be received by the active circuits and / or output to the second-to-first bridges.

[0068] The base chip 102 is capable of transmitting and / or receiving signals from active circuits (e.g., PL ICs 224-228) on the fabric chips 104-108 via the front side bonding pads 152-2, 152-3, and 152-4. Based on the hardware configuration of the fabric chips 104-108, the front side bonding pads 152-2, 152-3, and 152-4 to which a signal is transmitted or received can determine which circuit on the fabric chip 104-108 receives or transmits the signal. In the example shown, a first signal 334 on the front side bonding pad 152-2 communicates with the PL IC 224 on the fabric chip 104; a second signal 336 on the front side bonding pad 152-3 communicates with the PL IC 226 on the fabric chip 106; and a third signal 338 on the front side bonding pad 152-4 communicates with the PL IC 228 on the fabric chip 108.

[0069] Front side bonding pad 152-2 is connected to front side bonding pad 154-2, which is part of the second column and is also part of the second continuous via post portion 304-22 of the second interrupted via post 304-2. Front side bonding pad 152-3 is connected to front side bonding pad 154-3, which is part of the third column and is also part of the second continuous via post portion 304-32 of the third interrupted via post 304-3. Front side bonding pad 152-4 is connected to front side bonding pad 154-4, which is part of the fourth column and is also part of the second continuous via post portion 304-42 of the fourth interrupted via post 304-4.

[0070] The circuitry of the base chip 102 can transmit or receive a first signal 334 at the front side bonding pad 152-2. The first signal 334 is communicated to the PL IC 224 through the second column (e.g., the second continuous via post portion 304-22 of the second interrupted via post 304-2), the second to first bridge 314-21, and the interconnect 324. The first signal 334 can be further communicated to the circuitry of the fabric chip 106 through the first column (e.g., through the first continuous via post portion 304-11 of the first interrupted via post 304-1 and the second continuous via post portion 306-12 of the first interrupted via post 306-1). In some examples, the first column of the first interrupted via posts 304-1, 306-1, 308-1 can be omitted. In such an example, the first signal 334 is not communicated to the fabric chip 106 through the first continuous via post portion 304-11 and the second continuous via post portion 306-12.

[0071] The circuitry of the base chip 102 can transmit or receive a second signal 336 at the front side bond pad 152-3. The second signal 336 is communicated through the third column (e.g., the second continuous via post portion 304-32 of the third interrupted via post 304-3), the third-to-second bridge 314-32, and the second column (e.g., the first continuous via post portion 304-21 of the second interrupted via post 304-2) within the fabric chip 104. Thus, the second signal 336 is communicated and converted from the third column to the second column through the interleaved via posts in the fabric chip 104. The second signal 336 is further communicated to the PL IC 226 through the second column (e.g., the second continuous via post portion 306-22 of the second interrupted via post 306-2), the second-to-first bridge 316-21, and the interconnect 326. The second signal 336 can further be communicated to the circuitry of the fabric chip 108 through the first column (e.g., through the first continuous via post portion 306-11 of the first interrupted via post 306-1 and the second continuous via post portion 308-12 of the first interrupted via post 308-1). In some examples, the first column of the first interrupted via posts 304-1, 306-1, 308-1 can be omitted. In such an example, the second signal 336 is not communicated to the fabric chip 108 through the first continuous via post portion 306-11 and the second continuous via post portion 308-12.

[0072] The circuitry of the base chip 102 can transmit or receive a third signal 338 at the front side bonding pad 152-4. The third signal 338 is communicated through the fourth column (e.g., the second continuous via post portion 304-42 of the fourth interrupted via post 304-4), the fourth-to-third bridge 314-43, and the third column (e.g., the first continuous via post portion 304-31 of the third interrupted via post 304-3) within the fabric chip 104. Thus, the third signal 338 is communicated and converted from the fourth column to the third column through the interleaved via posts in the fabric chip 104. The third signal 338 is further communicated through the third column (e.g., the second continuous via post portion 306-32 of the third interrupted via post 306-3), the third-to-second bridge 316-32, and the second column (e.g., the first continuous via post portion 306-21 of the second interrupted via post 306-2) within the fabric chip 106. Thus, the third signal 338 is communicated and converted from the third column to the second column through the interleaved via pillars in the fabric chip 106. The third signal 338 is further communicated to the PL IC 228 through the second column (e.g., the second continuous via pillar portion 308-22 of the second interrupted via pillar 308-2), the second-to-first bridge 318-21, and the interconnect 328.

[0073] As previously described, each of the active circuits (e.g., the PL ICs 224-228) receives a signal from or transmits a signal to the base chip 102 through the same second column of second interrupted via pillars 304-2, 306-2, 308-2 within the corresponding fabric chip 104-108. Thus, the PL ICs 224-228 can have the same hardware layout, wherein the PL ICs 224-228 communicate different signals with the base chip 102 at the same corresponding locations within the corresponding fabric chip 104-108 without any other PL IC 224-228 also receiving the signal.

[0074] Staggered via pillars can enable different chips in a chip stack to have the same IC and hardware, which can reduce the number of chip variants to be designed and tape-out. Furthermore, in some examples, programming of communication interfaces between chips can be avoided by implementing staggered via pillars.

[0075] It will be readily understood by those skilled in the art that Figure 3The description is simplified. In some examples, the front-side dielectric layers 122-128 of the respective chips 102-108 are each or each include a set of dielectric layers, such as more than 18 dielectric layers, for example, depending on the technology node of the chips 102-108. In addition, in some examples, the front-side dielectric layers 122-128 can each have or include 18 metal layers (e.g., M0 to M17 layers), but the number of metal layers can vary, such as depending on the technology node of the chip. In some examples, the various bridges and / or metal lines can be in any of the metal layers.

[0076] Figure 4 The diagram illustrates a chip stack according to some examples having a simplified structure of at least a portion of the Z-interfaces 234, 236, 238 of the fabric chips 104, 106, 108. Although described with respect to the fabric chips 104, 106, 108, aspects of the described Z-interfaces may be applicable to the Z-interface 232 of the base chip 102. Figure 4 The diagram shows the intermediate structure chips 104 , 106 with their front surfaces oriented away from the base chip 102 , and the distal structure chip 108 with its front surface oriented toward the base chip 102 .

[0077] Those skilled in the art will readily understand the above description (regarding Figure 3 )right Figure 4 Therefore, Figure 4 The detailed description may be omitted in some aspects.

[0078] Typically, the Z-interfaces 234, 236 of the fabric chips 104, 106 include interrupted via posts. The Z-interface 234 of the fabric chip 104 includes: a first interrupted via post including a first continuous via post portion 404-11 and a second continuous via post portion 404-12; a second interrupted via post including a first continuous via post portion 404-21 and a second continuous via post portion 404-22; a third interrupted via post including a first continuous via post portion 404-31 and a second continuous via post portion 404-32; and a fourth interrupted via post including a first continuous via post portion 404-41 and a second continuous via post portion 404-42. Although not described in Figure 4 Although specifically marked, reference is made to the first interrupted via column 404-1, the second interrupted via column 404-2, the third interrupted via column 404-3 and the fourth interrupted via column 404-4.

[0079] The Z-interface 236 of the structure chip 106 includes: a first interrupted via post, which includes a first continuous via post portion 406-11 and a second continuous via post portion 406-12; a second interrupted via post, which includes a first continuous via post portion 406-21 and a second continuous via post portion 406-22; a third interrupted via post, which includes a first continuous via post portion 406-31 and a second continuous via post portion 406-32; and a fourth interrupted via post, which includes a first continuous via post portion 406-41 and a second continuous via post portion 406-42. Although not shown in FIG. Figure 4 Specifically marked, but reference is made to the first interrupted via column 406-1, the second interrupted via column 406-2, the third interrupted via column 406-3 and the fourth interrupted via column 406-4.

[0080] The interrupted via pillars are aligned in columns across the fabric chips 104-108. The first interrupted via pillars 404-1, 406-1, 308-1 in the fabric chip 104-108 are aligned in the first column. The second interrupted via pillars 404-2, 406-2, 308-2 in the fabric chip 104-108 are aligned in the second column. The third interrupted via pillars 404-3, 406-3, 308-3 in the fabric chip 104-108 are aligned in the third column. The fourth interrupted via pillars 404-4, 406-4, 308-4 in the fabric chip 104-108 are aligned in the fourth column.

[0081] The corresponding bridge is arranged to extend between the first continuous via post portion of the corresponding interrupted via post in one column within the chip and the second continuous via post portion of the corresponding different interrupted via post in a different column, and connect the two portions. The second-to-first bridge 414-21 forms the first continuous via post portion 404-21 of the second interrupted via post 404-2 and at least the corresponding portion of the second continuous via post portion 404-12 of the first interrupted via post 404-1, extending between the two portions, and connecting the two portions. The third-to-second bridge 414-32 forms the first continuous via post portion 404-31 of the third interrupted via post 404-3 and at least the corresponding portion of the second continuous via post portion 404-22 of the second interrupted via post 404-2, extending between the two portions, and connecting the two portions. The fourth to third bridge 414 - 43 forms at least corresponding portions of the first continuous via post portion 404 - 41 of the fourth interrupted via post 404 - 4 and the second continuous via post portion 404 - 32 of the third interrupted via post 404 - 3 , extends between the two portions, and connects the two portions.

[0082] The second-to-first bridge 416-21 forms the first continuous via column portion 406-21 of the second interrupted via column 406-2 and at least the corresponding portion of the second continuous via column portion 406-12 of the first interrupted via column 406-1, extending between the two portions, and connecting the two portions. The third-to-second bridge 416-32 forms the first continuous via column portion 406-31 of the third interrupted via column 406-3 and at least the corresponding portion of the second continuous via column portion 406-22 of the second interrupted via column 406-2, extending between the two portions, and connecting the two portions. The fourth-to-third bridge 416-43 forms the first continuous via column portion 406-41 of the fourth interrupted via column 406-4 and at least the corresponding portion of the second continuous via column portion 406-32 of the third interrupted via column 406-3, extending between the two portions, and connecting the two portions.

[0083] Each first continuous via post portion and second continuous via post portion connected together by a bridge forms an intersecting via post within the corresponding chip. The second continuous via post portion 404-12, the second to first bridge 414-21, and the first continuous via post portion 404-21 form an intersecting via post. The second continuous via post portion 404-22, the third to second bridge 414-32, and the first continuous via post portion 404-31 form an intersecting via post. The second continuous via post portion 404-32, the fourth to third bridge 414-43, and the first continuous via post portion 404-41 form an intersecting via post. The second continuous via post portion 406-12, the second to first bridge 416-21, and the first continuous via post portion 406-21 form an intersecting via post. The second continuous via post portion 406-22, the third to second bridge 416-32, and the first continuous via post portion 406-31 form an intersecting via post. The second continuous via post portion 406 - 32 , the fourth to third bridges 416 - 43 and the first continuous via post portion 406 - 41 form a crossed via post.

[0084] Furthermore, the second-to-first bridges 414-21 and 416-21 are connected to input nodes or output nodes of active circuits (e.g., PL ICs 224 and 226) of the respective fabric chips 104 and 106. As illustrated, the second-to-first bridge 414-21 is connected to the PL IC 224 via an interconnect 424 (e.g., a metal line / pad and / or via), and the second-to-first bridge 416-21 is connected to the PL IC 226 via an interconnect 426. The node of the active circuit to which the second-to-first bridge is connected can be an input node, an output node, or a bidirectional node. Thus, signals can be received by the active circuit and / or output to the second-to-first bridge.

[0085] Figure 5 Based on some examples Figure 1 and Figure 3 A flowchart of a method 500 for implementing a multi-chip device of the present invention. A person skilled in the art will readily understand methods for implementing other multi-chip devices such as Figure 4 ). Figure 5 The processing of method 500 is generally described, and a person skilled in the art will readily understand the more specific processing that can be performed. The more specific processing can be based on any semiconductor process used to form an IC on a substrate that is to be singulated into chips. For the purposes of this description, the wafer on which one or more base chips 102 are formed is referred to as a base wafer, and the wafer on which one or more structure chips 104, 106, 108 are formed is referred to as a structure wafer. Any wafer can be of any shape and / or size.

[0086] At block 502, front-side processing is performed on the chips on the respective wafers. For example, the front-side processing of each semiconductor substrate 112, 114, 116, 118 (e.g., wafer) may include forming devices (e.g., transistors 142, 144, 146, 148) in and / or on the front side of the semiconductor substrates 112, 114, 116, 118, and forming a front-side dielectric layer 122, 124, 126, 128 with metallization and front-side bonding pads 152, 154, 156, 158 on the front side of the semiconductor substrates 112, 114, 116, 118. A plurality of base chips 102 may be formed on the base wafer. A plurality of structure chips 104, 106, or 108 may be formed on each of the plurality of structure wafers. For example, the front-side processing may form portions of interrupted via posts of a Z-interface on and / or in the respective semiconductor substrates and front-side dielectric layers.

[0087] At block 504, a base wafer is bonded to a first structure wafer, such as Figure 1 As a result of the bonding, the front side of the base chip 102 is bonded to the front side of the structure chip 104, as shown in FIG. Figure 1 The bonding may be hybrid bonding, such as bonding the front side bonding pads 152 on the base wafer to the front side bonding pads 154 on the first structure wafer, and bonding the outer surface of the front side dielectric layer 122 on the base wafer to the outer surface of the front side dielectric layer 124 on the first structure wafer.

[0088] At block 506, the semiconductor substrate of the first structure wafer is thinned from the back side of the first structure wafer. Figure 1 As shown in FIG, the semiconductor substrate 114 of the structure chip 104 is thinned from the back. The thinning can be performed by chemical mechanical polishing (CMP) or other suitable processes. At block 508, the structure chip on the first structure wafer is processed from the back. Figure 1As shown, the backside processing may include forming backside TSVs 164 that pass through the semiconductor substrate 114 of the first structure wafer and connect to the metallization in the frontside dielectric layer 124 on the first structure wafer. The backside processing may further include forming a backside dielectric layer 134 having metallization and backside bonding pads 174 on the backside of the semiconductor substrate 114. The metallization in the backside dielectric layer 134 may be connected to the metallization in the frontside dielectric layer 124 through the backside TSVs 164. Generally, the formation of the backside TSVs and the metallization in the backside dielectric layer may form interrupted via posts of a Z-interface on and / or in the respective semiconductor substrates and backside dielectric layers.

[0089] At block 510, a first structure wafer is bonded to a second structure wafer, such as Figure 1 As a result of the bonding, the back side of the fabric chip 104 is bonded to the front side of the fabric chip 106, as shown in FIG. Figure 1 The bonding may be a hybrid bonding, such as bonding the backside bonding pads 174 on the first structure wafer to the frontside bonding pads 156 on the second structure wafer, and bonding the outer surface of the backside dielectric layer 134 on the first structure wafer to the outer surface of the frontside dielectric layer 126 on the second structure wafer.

[0090] At block 512, the semiconductor substrate of the second structure wafer is thinned from the back side of the second structure wafer, as described with respect to block 506. Figure 1 As shown in FIG, the semiconductor substrate 116 of the structure chip 106 is thinned from the back side.

[0091] At block 514, backside processing is performed on the fabric chips on the second fabrication wafer, as described with respect to block 508. Figure 1 As shown, the backside processing may include forming backside TSVs 166 that pass through the semiconductor substrate 116 of the second structure wafer and connect to the metallization in the frontside dielectric layer 126 on the second structure wafer. The backside processing may further include forming a backside dielectric layer 136 having metallization and backside bonding pads 176 on the backside of the semiconductor substrate 116. The metallization in the backside dielectric layer 136 may connect to the metallization in the frontside dielectric layer 126 through the backside TSVs 166.

[0092] At block 516, the second structure wafer is bonded to a third structure wafer, such as Figure 1 As a result of the bonding, the back side of the fabric chip 106 is bonded to the front side of the fabric chip 108, as shown in FIG. Figure 1The bonding may be hybrid bonding, such as bonding the backside bonding pads 176 on the second structure wafer to the frontside bonding pads 158 on the third structure wafer, and bonding the outer surface of the backside dielectric layer 136 on the second structure wafer to the outer surface of the frontside dielectric layer 128 on the third structure wafer.

[0093] At block 518, the semiconductor substrate of the base wafer is thinned from the back side of the base wafer, as described with respect to block 506. Figure 1 As shown in FIG, the semiconductor substrate 112 of the base chip 102 is thinned from the back side.

[0094] At block 520, backside processing is performed on the base chips on the base wafer, as described with respect to block 508. Figure 1 As shown, the back side processing may include forming back side TSVs 162 that pass through the semiconductor substrate 112 of the base wafer and connect to the metallization in the front side dielectric layer 122 on the base wafer. The back side processing may further include forming a back side dielectric layer 132 having metallization and external connector back side pads 172 on the back side of the semiconductor substrate 112. The metallization in the back side dielectric layer 132 may be connected to the metallization in the front side dielectric layer 122 through the back side TSVs 162. The back side processing of the base chip 102 may further include forming a passivation layer 180 and external connectors 182. At block 522, the bonded wafers are singulated (e.g., by sawing) to separate the individual multi-chip devices that have been formed. Each multi-chip device in the multi-chip device may be as shown. Figure 1 As shown in .

[0095] Various operations of the blocks of method 500 may be repeated and / or omitted to form various multi-chip devices. Method 500 is provided as an example of how to form some multi-chip devices. In other examples, some operations may be performed in parallel. For example, multiple different wafer stacks may be formed in parallel (e.g., by bonding and processing the respective wafers) before the multiple different wafer stacks are bonded together and further processed to form the multi-chip device. Based on the above description of method 500, one of ordinary skill in the art will readily understand how to form other multi-chip devices.

[0096] Figure 6 is a flow chart of a method 600 of operating a multi-chip device according to some examples. For example, a multi-chip device may be configured as follows: Figures 1 to 4 For illustrative purposes, Figure 3 The various operations of method 600 are described in the context of a multi-chip device. One of ordinary skill in the art will readily appreciate that such operations may be similarly performed in other multi-chip devices such as Figure 4 to execute or copy on a multi-chip device).

[0097] Method 600 describes communicating signals between the base chip 102 and the fabric chips 104-108. Method 600 is described in terms of directionality, where signals are transmitted from the base chip 102 and received at the fabric chips 104-108. One skilled in the art will readily appreciate that method 600 can similarly be performed in reverse order, where signals are transmitted from the fabric chips 104-108 and received at the base chip 102. Any interleaved studs can be implemented for unidirectional communication from the base chip 102 to the fabric chips 104-108, for unidirectional communication from the fabric chips 104-108 to the base chip 102, or for bidirectional communication between the base chip 102 and the fabric chips 104-108.

[0098] At block 602, at a base chip, signals are routed to different columns, where the signals target active circuits on different fabricated chips. Figure 3 , signals 334-338 are transmitted to different columns of interrupted via pillars. For example, first signal 334 is transmitted to the second column of second interrupted via pillars 304-2, 306-2, 308-2 via frontside bonding pad 152-2; second signal 336 is transmitted to the third column of third interrupted via pillars 304-3, 306-3, 308-3 via frontside bonding pad 152-3; and third signal 338 is transmitted to the fourth column of fourth interrupted via pillars 304-4, 306-4, 308-4 via frontside bonding pad 152-4. First signal 334 is targeted to active circuitry on fabric chip 104 (e.g., PL IC 224). Second signal 336 is targeted to active circuitry on fabric chip 106 (e.g., PL IC 226). Third signal 338 is targeted to active circuitry on fabric chip 108 (e.g., PL IC 228).

[0099] At block 604, at each intermediate fabric chip between the base chip and the fabric chip having the target active circuit, the corresponding signal is converted to another column. Figure 3A second signal 336 destined for active circuitry on the fabric chip 106 is converted from the third column of third interruption via pillars 304-3, 306-3, and 308-3 to the second column of second interruption via pillars 304-2, 306-2, and 308-2 via the third-to-second bridge 314-32 in the intermediate fabric chip 104. A third signal 338 destined for active circuitry on the fabric chip 108 is converted from the fourth column of fourth interruption via pillars 304-4, 306-4, and 308-4 to the third column of third interruption via pillars 304-3, 306-3, and 308-3 via the fourth-to-third bridge 314-43 in the intermediate fabric chip 104. A third signal 338 destined for active circuitry on the fabric chip 108 is further converted in the intermediate fabric chip 106 from the third column of third interrupted via posts 304-3, 306-3, 308-3 to the second column of second interrupted via posts 304-2, 306-2, 308-2 through the third to second bridge 316-32.

[0100] At block 606, at a fabric chip having a target active circuit, a corresponding signal is received at the target active circuit via the same column. Figure 3 The first signal 334 is received at the active circuit (e.g., PL IC 224) of the fabric chip 104 through the second column of the second interrupted via pillars 304-2, 306-2, 308-2 (e.g., through the second continuous via pillar portion 304-22) and further through the second-to-first bridge 314-21 and the interconnect 324. The second signal 336 is received at the active circuit (e.g., PL IC 224) of the fabric chip 106 through the second column of the second interrupted via pillars 304-2, 306-2, 308-2 (e.g., through the second continuous via pillar portion 306-22) and further through the second-to-first bridge 316-21 and the interconnect 326. The third signal 338 is received at active circuitry (e.g., PLIC 228) of the fabric chip 108 through the second column of second interrupted via pillars 304-2, 306-2, 308-2 (e.g., through the second continuous via pillar portion 308-22), and further through the second-to-first bridge 318-21 and the interconnect 328.

[0101] While the foregoing is directed to particular examples, other and further examples may be devised without departing from the basic scope thereof, and the scope of the same is determined by the claims that follow.

Claims

1. A multi-chip device comprising: A chip stack comprising chips, wherein adjacent chips are connected to each other, and the plurality of chips collectively comprise: an interrupted via post column, each chip of the plurality of chips having an interrupted via post in each of the columns, the interrupted via post having a first continuous via post portion and a second continuous via post portion aligned in a direction perpendicular to a side of a semiconductor substrate of the corresponding chip, the first continuous via post portion not being connected to the second continuous via post portion within the interrupted via post; and bridges, each chip of the plurality of chips having one or more of the bridges, each of the bridges connecting the first continuous via post portion in one of the columns with the second continuous via post portion in another of the columns within the corresponding chip; Each chip in the plurality of chips includes an active circuit, and the active circuit in the plurality of chips is connected to the same first continuous via post portion of a corresponding column in the column within the corresponding chip, and the same second continuous via post portion of another corresponding column in the column.

2. A multi-chip device according to claim 1, wherein at each interface between adjacent chips of the plurality of chips and in each column of the columns, the first continuous via column portion of the corresponding column and in one chip of the corresponding adjacent chips is connected to the second continuous via column portion of the corresponding column and in another chip of the corresponding adjacent chip.

3. A multi-chip device according to claim 1, wherein the chip includes a base chip, the base chip includes a first pad at an interface with one of the multiple chips, the one of the multiple chips includes a second pad at the interface, each of the columns includes a corresponding pad of the second pads, and the corresponding pad is connected to the corresponding pad of the first pads. 4 . The multi-chip device of claim 1 , wherein the first continuous via pillar portion in one or more of the chips each comprises a through-substrate via (TSV) passing through the semiconductor substrate of the corresponding chip.

5. A method of operating a multi-chip device, the method comprising: communicating signals between a first chip and a second chip, the first chip and the second chip being in a chip stack, one or more intermediate chips being arranged in the chip stack between the first chip and the second chip, wherein: At each of the one or more intermediate chips, communicating the signal comprises communicating the signal from an interrupted via post column to another interrupted via post column, each of the interrupted via post columns extending across the one or more intermediate chips; and Each of the interrupted via post columns at each of the one or more intermediate chips comprises a first continuous via post portion and a second continuous via post portion arranged in the corresponding chip, wherein the first continuous via post portion is not connected to the second continuous via post portion within the corresponding interrupted via post column; Each of the second chip and the intermediate chip includes an active circuit, which is connected to the same first continuous via column portion of a corresponding column in the column within the corresponding chip, and the same second continuous via column portion of another corresponding column in the column.

6. A method according to claim 5, wherein at each intermediate chip of the one or more intermediate chips, a bridge is arranged within the corresponding chip and connects the first continuous via column portion of the interrupted via column column to the second continuous via column portion of the other interrupted via column column.

7. The method according to claim 5, further comprising: Respective signals are communicated between the first chip and each of the one or more intermediate chips.

8. The method of claim 7, wherein the first chip includes solder pads, each of the solder pads being connected to a different column of interrupted via posts, and each of the signals communicated between the first chip and the second chip and between the first chip and the one or more intermediate chips being communicated through a different one of the solder pads. 9 . The method of claim 5 , wherein each of the first continuous via post portions comprises a through-substrate via (TSV) passing through a semiconductor substrate of the corresponding chip.

10. A multi-chip device comprising: A chip stack comprising chips, wherein a first chip of the chip stack comprises: a first continuous via post portion having a first pad at an interface between the first chip and a lower chip of the chip stack, the first continuous via post portion being connected to an active circuit of the first chip through an interconnect and a first bridge; a second continuous via post portion having a second pad at an interface between the first chip and an overlying chip of the chip stack, the second pad being aligned with the first pad, the second continuous via post portion being unconnected to the first continuous via post portion; a third continuous via column portion having a third pad at the interface between the first chip and the lower chip; a second bridge connecting the third continuous via column portion and the second continuous via column portion; and An additional continuous via post portion has an additional pad at the interface between the first chip and the overlying chip, the additional continuous via post portion being connected to the active circuit of the first chip through the interconnect and the first bridge.

11. The multi-chip device of claim 10 , wherein the first chip further comprises: a fourth continuous via column portion having a fourth pad at the interface between the first chip and the overlying chip, the fourth pad being aligned with the third pad, and the fourth continuous via column portion being not connected to the third continuous via column portion; a fifth continuous via column portion having a fifth pad at the interface between the first chip and the lower chip; as well as A third bridge connects the fifth continuous via column portion and the fourth continuous via column portion.

12. The multi-chip device of claim 10, wherein: The first chip further includes a fourth continuous via column portion, the fourth continuous via column portion having a fourth pad at the interface between the first chip and the overlying chip, the fourth pad being aligned with the third pad, and the fourth continuous via column portion not being connected to the third continuous via column portion; The overlying chip comprises: a fifth continuous via column portion having a fifth pad at the interface between the first chip and the overlying chip, the fifth pad being connected to the second pad, the fifth continuous via column portion being connected to an active circuit of the overlying chip through an interconnect; a sixth continuous via column portion, aligned with the fifth continuous via column portion, the sixth continuous via column portion not being connected to the fifth continuous via column portion; a seventh continuous via column portion, having a seventh pad at the interface between the first chip and the overlying chip, the seventh pad being connected to the fourth pad; an eighth continuous via post portion aligned with the seventh continuous via post portion, the eighth continuous via post portion not being connected to the seventh continuous via post portion; and a third bridge connecting the seventh continuous via column portion and the sixth continuous via column portion; The first continuous via post portion, the second continuous via post portion, the fifth continuous via post portion, and the sixth continuous via post portion are aligned in a first interrupted via post column; and The third continuous via post portion, the fourth continuous via post portion, the seventh continuous via post portion, and the eighth continuous via post portion are aligned in a second interrupted via post column. 13 . The multi-chip device of claim 10 , wherein the lower chip is configured to communicate signals with the first chip through the first pads and to communicate signals with the overlying chip through the third pads.

14. The multi-chip device of claim 1 or 10, wherein each chip in the stack of chips has the same hardware layout.

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