Display substrate and manufacturing method thereof, and display device

Abstract

A display substrate and a preparation method thereof, and a display device. The display substrate includes a display area and a binding area located on one side of the display area, the binding area at least including a lead area; the display area includes a plurality of data lines and a plurality of data fan-out lines, the lead area includes a plurality of lead lines, and the orthographic projections of the plurality of data lines and the plurality of data fan-out lines on the display substrate plane at least partially overlap; at least one lead line is connected to the data line through the data fan-out line; in the lead area, the orthographic projection of any lead line on the display substrate plane has no overlapping area with the orthographic projections of other lead lines on the display substrate plane.

Description

[0001] This application claims priority to PCT application No. PCT / CN2021 / 074469, filed on January 29, 2021, with application number PCT / CN2021 / 074469 and invention name “Display Substrate and Display Device”, the content of which should be understood as incorporated into this application by reference. Technical Field

[0002] The present disclosure relates to but is not limited to the field of display technology, and in particular to a display substrate and a preparation method thereof, and a display device. Background Art

[0003] Organic Light Emitting Diode (OLED) is an active light-emitting display device with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, and extremely high response speed. With the continuous development of display technology, display devices using OLED as a light-emitting device and thin film transistors (TFT) for signal control have become the mainstream products in the current display field. Summary of the invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] On the one hand, an exemplary embodiment of the present disclosure provides a display substrate, comprising a display area and a binding area located on one side of the display area, the binding area at least comprising a lead area; the display area comprises a plurality of data lines and a plurality of data fan-out lines, the lead area comprises a plurality of lead lines, and the orthographic projections of the plurality of data lines and the plurality of data fan-out lines on the plane of the display substrate at least partially overlap; at least one lead line is connected to the data line through the data fan-out line; in the lead area, the orthographic projection of any lead line on the plane of the display substrate has no overlapping area with the orthographic projections of other lead lines on the plane of the display substrate.

[0006] In an exemplary embodiment, at least one lead line is directly connected to the data line.

[0007] In an exemplary embodiment, the number of the data lines is greater than the number of the data fan-out lines.

[0008] In an exemplary embodiment, at least one data fan-out line includes a first line segment, a second line segment and a third line segment; the first end of the first line segment is connected to the lead line, and the second end of the first line segment is connected to the first end of the second line segment after extending in a direction away from the lead area; the second end of the second line segment is connected to the first end of the third line segment after extending along a second direction or a direction opposite to the second direction; the second end of the third line segment is connected to the data line through a via after extending in a direction close to the lead area; the second direction intersects the first direction, and the first direction is parallel to the data line.

[0009] In an exemplary embodiment, the third line segment includes an extension segment and a connecting segment; the first end of the extension segment is located within the display area and is connected to the second end of the second line segment, the second end of the extension segment extends toward the direction close to the lead area to the edge of the display area, and is connected to the first end of the connecting segment, the second end of the connecting segment extends toward the direction away from the display area, and is connected to the data line extending to the lead area through a via hole; the edge of the display area is the edge of the display area on the side close to the lead area.

[0010] In an exemplary embodiment, a plurality of via holes connecting the data fan-out lines to the data lines are at the same distance from the edge of the display area.

[0011] In an exemplary embodiment, the first line segment is parallel to the first direction, and the extended section of the third line segment is parallel to the first direction.

[0012] In an exemplary embodiment, a spacing between adjacent first line segments is the same as a spacing between adjacent data lines, and a spacing between protruding segments of adjacent third line segments is the same as a spacing between adjacent data lines.

[0013] The first line segment is parallel to the first direction, and there is a first angle between the first line segment and the first direction, and / or there is a second angle between the extended segment of the third line segment and the first direction, and the first angle is 20° to 70°, and the second angle is 20° to 70°.

[0014] In an exemplary embodiment, the first line segment includes a first straight line segment and a first oblique line segment; the first end of the first straight line segment is connected to the lead wire, and the second end of the first straight line segment is connected to the first end of the first oblique line segment after extending in a direction away from the lead area; the first oblique line segment is connected to the first end of the second line segment after extending in a direction away from the lead area; the first oblique line segment has a first angle with the first direction, the first angle is 20° to 70°, and the second end of the first straight line segment is at a first distance from the edge of the display area; and / or the extended section of the third line segment includes a third oblique line segment and a third straight line segment; the first end of the third oblique line segment is connected to the second end of the second line segment, the second end of the third oblique line segment is connected to the first end of the third straight line segment after extending in a direction close to the lead area, and the second end of the third straight line segment is connected to the first end of the connecting section after extending in a direction close to the lead area to the edge of the display area; the third oblique line segment has a second angle with the first direction, the second angle is 20° to 70°, and the first end of the third straight line segment is at a second distance from the edge of the display area.

[0015] In an exemplary embodiment, the second line segment includes a plurality of sub-line segments, the plurality of sub-line segments are interwoven to form a plurality of grid patterns, and the plurality of grid patterns are repeatedly and continuously arranged in the first direction and / or the second direction.

[0016] In an exemplary embodiment, at least one data fan-out line includes a first line segment and a second line segment; the first end of the first line segment is connected to the lead-out line, and the second end of the first line segment is connected to the first end of the second line segment after extending in a direction away from the lead area; the second end of the second line segment is connected to the data line through a via after extending along a second direction or a direction opposite to the second direction; the second direction intersects the first direction, and the first direction is parallel to the data line.

[0017] In an exemplary embodiment, a plurality of vias connecting the data fan-out lines to the data lines have different distances from an edge of the display area; the edge of the display area is an edge of the display area close to a lead area.

[0018] In an exemplary embodiment, at least one data fan-out line includes a first line segment and a second line segment; a first end of the first line segment is connected to the lead-out line, and a second end of the first line segment is connected to the second line segment after extending in a direction away from the lead-out area; the second line segment includes a plurality of sub-line segments, the plurality of sub-line segments are interwoven to form a plurality of grid patterns, the plurality of grid patterns are repeated and continuously arranged in a first direction and / or a second direction, and at least one sub-line segment is connected to the data line through a via; the second direction intersects with the first direction, and the first direction is parallel to the data line.

[0019] In an exemplary embodiment, the plurality of lead lines in the lead area have the same width and the spacing between adjacent lead lines is the same; the width and spacing are dimensions in a second direction that intersects the first direction and is parallel to the data line.

[0020] In an exemplary embodiment, in a plane parallel to the display substrate, the display substrate has a center line, the center line extends along a first direction and bisects the pixel column of the display area, the first direction is parallel to the data line; on one side of the center line, the plurality of data lines include a first data line group and a second data line group, the plurality of lead lines include a first lead line group and a second lead line group; the first data line group includes a first data line, a second data line, ..., an Mth data line sequentially arranged along the second direction, the second data line group is arranged on one side of the first data line group in the second direction, the second data line group includes an (M+1)th data line, an (M+2)th data line, and a (M+3)th data line sequentially arranged along the second direction. line, ..., the Nth data line, the second direction intersects with the first direction; the first lead group includes a first lead line, a second lead line, ..., the Mth lead line arranged in sequence along the opposite direction of the second direction, the second lead group includes an (M+1)th lead line, a (M+2)th lead line, ..., the Nth lead line arranged in sequence along the second direction, the lead lines of the first lead group and the lead lines of the second lead group are arranged alternately; M, N are positive integers greater than 2, and M is less than N; the lead lines in the first lead group are connected to the data lines in the first data line group through the data fan-out lines, and the lead lines in the second lead group are directly connected to the data lines in the second data line group.

[0021] In an exemplary embodiment, in a plane perpendicular to the display substrate, the display substrate includes a first conductive layer, a second conductive layer and a third conductive layer, and an insulating layer is provided between the first conductive layer and the second conductive layer and between the second conductive layer and the third conductive layer; the data line and the data fan-out line are provided in different conductive layers.

[0022] In an exemplary embodiment, the data fan-out lines include odd data fan-out lines and even data fan-out lines, the odd data fan-out lines are connected to the data lines of odd columns in the first data line group, and the even data fan-out lines are connected to the data lines of even columns in the first data line group; the odd data fan-out lines and the even data fan-out lines are arranged in different conductive layers.

[0023] In an exemplary embodiment, the lead-out lines include odd lead-out lines and even lead-out lines; the odd lead-out lines are connected to the data lines of odd columns in the first data line group through the odd data fan-out lines, or are directly connected to the data lines of odd columns in the second data line group; the even lead-out lines are connected to the data lines of even columns in the first data line group through the even data fan-out lines, or are directly connected to the data lines of even columns in the second data line group; the odd lead-out lines and the odd data fan-out lines are arranged on the same layer and are an integrated structure connected to each other, and the even lead-out lines and the even data fan-out lines are arranged on the same layer and are an integrated structure connected to each other.

[0024] In an exemplary embodiment, the odd data fan-out lines are arranged in the first conductive layer, the even data fan-out lines are arranged in the second conductive layer, and the data lines are arranged in the third conductive layer; or, the even data fan-out lines are arranged in the first conductive layer, the odd data fan-out lines are arranged in the second conductive layer, and the data lines are arranged in the third conductive layer.

[0025] In an exemplary embodiment, a material of the first conductive layer and a material of the second conductive layer are the same.

[0026] On the other hand, an exemplary embodiment of the present disclosure further provides a display device, comprising any one of the above-mentioned display substrates.

[0027] In another aspect, the exemplary embodiments of the present disclosure further provide a method for preparing a display substrate, wherein the display substrate comprises a display area and a binding area located on one side of the display area, wherein the binding area comprises at least a lead area; the preparation method comprises:

[0028] A plurality of data lines and a plurality of data fan-out lines are formed in the display area, and a plurality of lead-out lines are formed in the lead area, wherein the orthographic projections of the plurality of data lines and the plurality of data fan-out lines on the display substrate plane at least partially overlap; at least one lead-out line is connected to the data line through the data fan-out line; and in the lead area, the orthographic projection of any lead-out line on the display substrate plane has no overlapping area with the orthographic projections of other lead-out lines on the display substrate plane.

[0029] Other aspects will become apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure. The shapes and sizes of the components in the accompanying drawings do not reflect the actual proportions and are only intended to illustrate the contents of the present disclosure.

[0031] Figure 1 is a structural schematic diagram of a display device;

[0032] Figure 2 It is a schematic diagram of a planar structure of a display substrate;

[0033] Figure 3 It is a schematic diagram of the planar structure of a display area in a display substrate;

[0034] Figure 4 A schematic diagram of the cross-sectional structure of a display area in a display substrate;

[0035] Figure 5 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0036] Figure 6 is a working timing diagram of a pixel driving circuit;

[0037] Figure 7 A schematic diagram of a planar structure showing a binding region in a substrate;

[0038] Figure 8 A schematic diagram of a data fan-out line in a binding area;

[0039] Fig. 9 A schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0040] Fig.10 for Fig. 9 A side view of the substrate is shown in FIG.

[0041] Fig.11 A schematic diagram of the structure of a lead-out line and a data fan-out line according to an exemplary embodiment of the present disclosure;

[0042] Fig.12 for Fig.11 Enlarged view of the middle C1 region;

[0043] Fig.13 for Fig.12 Enlarged view of the middle C2 region;

[0044] Fig.14 for Fig.13 Sectional view along AA direction;

[0045] Fig.15 It is a schematic diagram of the structure of another lead-out line and a data fan-out line of an exemplary embodiment of the present disclosure;

[0046] Fig.16 for Fig.15 Enlarged view of the middle C3 region;

[0047] Fig.17It is a structural schematic diagram of another lead-out line and a data fan-out line of an exemplary embodiment of the present disclosure;

[0048] Fig.18 It is a structural schematic diagram of another lead-out line and a data fan-out line of an exemplary embodiment of the present disclosure;

[0049] Fig.19 for Fig.18 Enlarged view of the middle C4 region;

[0050] Fig. 20 It is a structural schematic diagram of another lead-out line and a data fan-out line of an exemplary embodiment of the present disclosure;

[0051] Fig.21 for Fig. 20 Enlarged view of the middle C5 region;

[0052] Fig. 22 It is a structural schematic diagram of another lead-out line and a data fan-out line of an exemplary embodiment of the present disclosure;

[0053] Fig.23 for Fig. 22 Enlarged view of the middle C6 region;

[0054] Fig.24 It is a structural schematic diagram of another lead-out line and a data fan-out line of an exemplary embodiment of the present disclosure;

[0055] Fig.25 for Fig.24 Enlarged view of the middle C7 region;

[0056] Fig.26 It is a schematic structural diagram of another lead-out line and a data fan-out line according to an exemplary embodiment of the present disclosure.

[0057] Description of reference numerals:

[0058] 10—display substrate; 11—first insulating layer; 12—second insulating layer;

[0059] 13—third insulating layer; 14—fourth insulating layer; 20—integrated circuit;

[0060] 30—flexible circuit board; 100—display area; 101—substrate;

[0061] 102—driving circuit layer; 102A—transistor; 102B—storage capacitor;

[0062] 200—binding area; 201—first fan-out area; 202—bending area;

[0063] 203—second fan-out area; 204—antistatic area; 205—driver chip area;

[0064] 206—binding pin area; 300—frame area; 301—anode;

[0065] 302—pixel definition layer; 303—organic light emitting layer; 304—cathode;

[0066] 401—first encapsulation layer; 402—second encapsulation layer; 403—third encapsulation layer;

[0067] 500—binding area; 501—lead area; 502—bending area;

[0068] 503—composite circuit area; 600—lead-out line; 700—data fan-out line. DETAILED DESCRIPTION

[0069] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail in conjunction with the accompanying drawings hereinafter. Note that the embodiments can be implemented in a number of different forms. A person of ordinary skill in the relevant technical field can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of some known functions and known components. The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0070] In the drawings, the size of each component, the thickness of a layer, or the area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to this size, and the shape and size of each component in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0071] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0072] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0073] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0074] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0075] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged.

[0076] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0077] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0078] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".

[0079] The term "about" in the present disclosure refers to a numerical value that is not strictly limited to allow for process and measurement errors.

[0080] Figure 1 FIG. 1 is a schematic diagram of the structure of a display device. Figure 1As shown, the OLED display device may include a timing controller, a data signal driver, a scan signal driver, a light emitting signal driver, and a pixel array, and the pixel array may include a plurality of scan signal lines (S1 to Sm), a plurality of data lines (D1 to Dn), a plurality of light emitting signal lines (E1 to Eo), and a plurality of sub-pixels Pxij. In an exemplary embodiment, the timing controller may provide a grayscale value and a control signal suitable for the specification of the data signal driver to the data signal driver, a clock signal suitable for the specification of the scan signal driver, a scan start signal, etc. to the scan signal driver, and a clock signal suitable for the specification of the light emitting signal driver, an emission stop signal, etc. to the light emitting signal driver. The data signal driver may generate a data voltage to be provided to the data lines D1, D2, D3, ... and Dn using the grayscale value and the control signal received from the timing controller. For example, the data signal driver may sample the grayscale value using the clock signal, and apply the data voltage corresponding to the grayscale value to the data lines D1 to Dn in units of pixel rows, where n may be a natural number. The scan signal driver may generate a scan signal to be provided to the scan signal lines S1, S2, S3, ... and Sm by receiving a clock signal, a scan start signal, etc. from a timing controller. For example, the scan signal driver may sequentially provide a scan signal having an on-level pulse to the scan signal lines S1 to Sm. For example, the scan signal driver may be constructed in the form of a shift register, and may generate a scan signal in a manner that sequentially transmits a scan start signal provided in the form of an on-level pulse to a next-level circuit under the control of a clock signal, and m may be a natural number. The luminous signal driver may generate an emission signal to be provided to the luminous signal lines E1, E2, E3, ... and Eo by receiving a clock signal, an emission stop signal, etc. from a timing controller. For example, the luminous signal driver may sequentially provide an emission signal having an off-level pulse to the luminous signal lines E1 to Eo. For example, the luminous signal driver may be constructed in the form of a shift register, and may sequentially transmit a luminous stop signal provided in the form of an off-level pulse to a next-level circuit under the control of a clock signal, and o may be a natural number. The pixel array may include a plurality of sub-pixels Pxij, each of which may be connected to a corresponding data line, a corresponding scan signal line, and a corresponding light emitting signal line, and i and j may be natural numbers. The sub-pixel Pxij may refer to a sub-pixel in which a transistor is connected to the i-th scan signal line and to the j-th data line.

[0081] Figure 2 FIG. 1 is a schematic diagram of a planar structure of a display substrate. Figure 2As shown, the display substrate may include a display area 100, a binding area 200 located on one side of the display area 100, and a frame area 300 located on the other side of the display area 100. The display area 100 may include a plurality of sub-pixels configured to display dynamic pictures or still images, the binding area 200 may include connection lines and circuits for connecting a plurality of data lines to an integrated circuit, the frame area 300 may include a power line for transmitting a voltage signal, the binding area 200 and the frame area 300 may include an isolation dam of a ring structure, at least one side of the frame area 300 may be a curled area formed by bending, or the display area 100 and the frame area 300 may both be bent or curved areas, which is not limited in the present disclosure.

[0082] In an exemplary embodiment, the display area may include a plurality of pixel units arranged in a matrix manner. Figure 3 FIG. 1 is a schematic diagram of a planar structure of a display area in a display substrate. Figure 3 As shown, the display substrate may include a plurality of pixel units P arranged in a matrix, at least one of the plurality of pixel units P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light, and the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 each include a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the scanning signal line, the data line, and the light-emitting signal line, and the pixel driving circuit is configured to receive the data voltage transmitted by the data line under the control of the scanning signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting devices in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the pixel driving circuits of the sub-pixels in which they are located, and the light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which they are located.

[0083] In an exemplary embodiment, the pixel unit P may include a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel, or may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, which is not limited in the present disclosure. In an exemplary embodiment, the shape of the sub-pixel in the pixel unit may be a rectangle, a rhombus, a pentagon, or a hexagon. When the pixel unit includes three sub-pixels, the three sub-pixels may be arranged in a horizontal parallel, vertical parallel, or in a triangular manner. When the pixel unit includes four sub-pixels, the four sub-pixels may be arranged in a horizontal parallel, vertical parallel, or square manner, which is not limited in the present disclosure.

[0084] Figure 4 FIG. 1 is a schematic diagram of a cross-sectional structure of a display area in a display substrate, illustrating the structure of three sub-pixels of an OLED display substrate. Figure 4 As shown, on a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 102 disposed on a substrate 101, a light emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101, and an encapsulation layer 104 disposed on a side of the light emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as spacers, etc., which are not limited in the present disclosure.

[0085] In an exemplary embodiment, the substrate 101 may be a flexible substrate, or may be a rigid substrate. The driving circuit layer 102 of each sub-pixel may include a plurality of transistors and storage capacitors constituting a pixel driving circuit. Figure 4 Only one transistor 102A and one storage capacitor 102B are taken as examples. The light-emitting structure layer 103 may include an anode 301, a pixel definition layer 302, an organic light-emitting layer 303 and a cathode 304. The anode 301 is connected to the drain electrode of the driving transistor 210 through a via, the organic light-emitting layer 303 is connected to the anode 301, and the cathode 304 is connected to the organic light-emitting layer 303. The organic light-emitting layer 303 emits light of corresponding colors under the drive of the anode 301 and the cathode 304. The encapsulation layer 104 may include a first encapsulation layer 401, a second encapsulation layer 402 and a third encapsulation layer 403 stacked together. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, and the second encapsulation layer 402 may be made of organic materials. The second encapsulation layer 402 is arranged between the first encapsulation layer 401 and the third encapsulation layer 403, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0086] In an exemplary embodiment, the organic light emitting layer 303 may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), an emitting layer (EML), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the electron transport layers of all sub-pixels may be a common layer connected together, the hole blocking layers of all sub-pixels may be a common layer connected together, the emitting layers of adjacent sub-pixels may have a small overlap, or may be isolated, and the electron blocking layers of adjacent sub-pixels may have a small overlap, or may be isolated.

[0087] In exemplary embodiments, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C structure. Figure 5 FIG. 1 is a schematic diagram of an equivalent circuit of a pixel driving circuit. Figure 5 As shown, the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7), 1 storage capacitor C and 7 signal lines (data line D, first scanning signal line S1, second scanning signal line S2, light emitting signal line E, initial signal line INIT, first power line VDD and second power line VSS).

[0088] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first power line VDD, and a second end of the storage capacitor C is connected to the second node N2 , ie, the second end of the storage capacitor C is connected to the control electrode of the third transistor T3 .

[0089] The control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2. When the on-level scan signal is applied to the second scan signal line S2, the first transistor T1 transmits the initialization voltage to the control electrode of the third transistor T3, so that the charge amount of the control electrode of the third transistor T3 is initialized.

[0090] The control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When the on-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.

[0091] The control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C, the first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called a driving transistor, and the third transistor T3 determines the amount of driving current flowing between the first power line VDD and the second power line VSS according to the potential difference between its control electrode and the first electrode.

[0092] The control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be called a switching transistor, a scan transistor, etc. When the on-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 enables the data voltage of the data line D to be input to the pixel driving circuit.

[0093] The control electrode of the fifth transistor T5 is connected to the light emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device. The fifth transistor T5 and the sixth transistor T6 can be called light emitting transistors. When the on-level light emitting signal is applied to the light emitting signal line E, the fifth transistor T5 and the sixth transistor T6 form a driving current path between the first power line VDD and the second power line VSS to make the light emitting device emit light.

[0094] The control electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device. When the on-level scan signal is applied to the first scan signal line S1, the seventh transistor T7 transmits the initialization voltage to the first electrode of the light emitting device to initialize or release the charge accumulated in the first electrode of the light emitting device.

[0095] In an exemplary embodiment, the second electrode of the light emitting device is connected to the second power line VSS, the signal of the second power line VSS is a low level signal, and the signal of the first power line VDD is a continuously provided high level signal. The first scanning signal line S1 is a scanning signal line in the pixel driving circuit of the current display row, and the second scanning signal line S2 is a scanning signal line in the pixel driving circuit of the previous display row, that is, for the nth display row, the first scanning signal line S1 is S(n), and the second scanning signal line S2 is S(n-1), and the second scanning signal line S2 of the current display row is the same as the first scanning signal line S1 in the pixel driving circuit of the previous display row, which can reduce the signal lines of the display panel and realize the narrow frame of the display panel.

[0096] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be a P-type transistor, or may be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include a P-type transistor and an N-type transistor.

[0097] In an exemplary embodiment, the first scan signal line S1, the second scan signal line S2, the emission signal line E, and the initial signal line INIT extend in a horizontal direction, and the second power line VSS, the first power line VDD, and the data line D extend in a vertical direction.

[0098] In an exemplary embodiment, the light emitting device may be an organic light emitting diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.

[0099] Figure 6 This is a working timing diagram of a pixel driving circuit. Figure 5 The operation process of the pixel driving circuit of the example is described in detail. Figure 5 The pixel driving circuit includes 7 transistors (first transistor T1 to sixth transistor T7), 1 storage capacitor C and 7 signal lines (data line D, first scanning signal line S1, second scanning signal line S2, light emitting signal line E, initial signal line INIT, first power line VDD and second power line VSS), and all 7 transistors are P-type transistors.

[0100] In an exemplary embodiment, the operation process of the pixel driving circuit may include:

[0101] The first stage A1 is called the reset stage. The signal of the second scanning signal line S2 is a low-level signal, and the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals. The signal of the second scanning signal line S2 is a low-level signal, which turns on the first transistor T1. The signal of the initial signal line INIT is provided to the second node N2 to initialize the storage capacitor C and clear the original data voltage in the storage capacitor. The signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals, which turns off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7. In this stage, the OLED does not emit light.

[0102] The second stage A2 is called the data writing stage or the threshold compensation stage. The signal of the first scanning signal line S1 is a low level signal, the signals of the second scanning signal line S2 and the light emitting signal line E are high level signals, and the data line D outputs the data voltage. In this stage, since the second end of the storage capacitor C is at a low level, the third transistor T3 is turned on. The signal of the first scanning signal line S1 is a low level signal, which turns on the second transistor T2, the fourth transistor T4 and the seventh transistor T7. The second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output by the data line D is provided to the second node N2 through the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and the difference between the data voltage output by the data line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C. The voltage of the second end (the second node N2) of the storage capacitor C is Vd-|Vth|, Vd is the data voltage output by the data line D, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on so that the initial voltage of the initial signal line INIT is provided to the first electrode of the OLED, the first electrode of the OLED is initialized (reset), the pre-stored voltage inside it is cleared, the initialization is completed, and the OLED is ensured not to emit light. The signal of the second scanning signal line S2 is a high-level signal, which turns off the first transistor T1. The signal of the light-emitting signal line E is a high-level signal, which turns off the fifth transistor T5 and the sixth transistor T6.

[0103] The third stage A3 is called the light-emitting stage, the signal of the light-emitting signal line E is a low-level signal, and the signals of the first scanning signal line S1 and the second scanning signal line S2 are high-level signals. The signal of the light-emitting signal line E is a low-level signal, which turns on the fifth transistor T5 and the sixth transistor T6, and the power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, driving the OLED to emit light.

[0104] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-|Vth|, the driving current of the third transistor T3 is:

[0105] I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd] 2

[0106] Among them, I is the driving current flowing through the third transistor T3, that is, the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data line D, and Vdd is the power supply voltage output by the first power supply line VDD.

[0107] Figure 7 A schematic diagram showing a planar structure of a binding area in a substrate. Figure 8 Figure 1 is a schematic diagram of a data fan-out line in a binding area. Figure 7 As shown, in a plane parallel to the display substrate, the binding area 200 is located on one side of the display area 100, and the binding area 200 may include a first fan-out area 201, a bending area 202, a second fan-out area 203, an anti-static area 204, a driver chip area 205 and a binding pin area 206 which are sequentially arranged in a direction away from the display area 100. The first fan-out area 201 includes at least a data fan-out line, and a plurality of data fan-out lines are configured to connect the data lines (Data Line) of the display area in a fan-out routing manner, as shown in FIG. Figure 8 As shown. The bending area 202 includes a composite insulating layer provided with grooves, which is configured to bend the binding area 200 to the back of the display area 100. The second fan-out area 203 includes a plurality of data fan-out lines led out in a fan-out routing manner. The anti-static area 204 includes an anti-static circuit, which is configured to prevent electrostatic damage to the display substrate by eliminating static electricity. The driving chip area 205 includes an integrated circuit (IC), which is configured to be connected to a plurality of data fan-out lines. The binding pin area 206 includes a binding pad (Bonding Pad), which is configured to be bound and connected to an external flexible printed circuit (FPC).

[0108] With the development of OLED display technology, consumers have higher and higher requirements for the display effect of display products, and extremely narrow borders have become a new trend in the development of display products. Therefore, the narrowing of the border or even the borderless design has received more and more attention in the design of OLED display products. At present, the left border, right border and upper border of the display device can be controlled within 1.0mm, but the narrowing design of the lower border (the border on the side of the binding area) is more difficult and has been maintained at about 2.0mm. This is because the data fan-out line is usually set in the fan-out area of ​​the binding area, and the fan-shaped area occupies a large space. Usually, the width of the binding area is smaller than the width of the display area. The signal lines of the integrated circuit and the binding pad in the binding area need to be introduced into the wider display area in a fan-out manner through the fan-out area. The greater the width difference between the display area and the binding area, the more oblique fan-out lines in the fan-shaped area, and the greater the distance between the driver chip area and the display area, the wider the lower border, resulting in the lower border being much larger than the left and right borders.

[0109] The exemplary embodiments of the present disclosure provide a display substrate. The display substrate may include a display area and a binding area located on one side of the display area, the binding area at least including a lead area; the display area includes a plurality of data lines and a plurality of data fan-out lines, the lead area includes a plurality of lead lines; at least one lead line is connected to the data line through the data fan-out line, and the orthographic projections of the plurality of data lines and the plurality of data fan-out lines on the display substrate plane at least partially overlap; in the lead area, the orthographic projection of any lead line on the display substrate plane has no overlapping area with the orthographic projections of other lead lines on the display substrate plane.

[0110] In an exemplary embodiment, at least one lead line is directly connected to the data line.

[0111] In an exemplary embodiment, the number of the data lines is greater than the number of the data fan-out lines.

[0112] In an exemplary embodiment, at least one data fan-out line includes a first line segment, a second line segment and a third line segment; the first end of the first line segment is connected to the lead line, and the second end of the first line segment is connected to the first end of the second line segment after extending in a direction away from the lead area; the second end of the second line segment is connected to the first end of the third line segment after extending along a second direction or a direction opposite to the second direction; the second end of the third line segment is connected to the data line through a via after extending in a direction close to the lead area; the second direction intersects the first direction, and the first direction is parallel to the data line.

[0113] In an exemplary embodiment, the vias connecting the plurality of data fan-out lines to the data lines are at the same distance from the edge of the display area; the edge of the display area is the edge of the display area close to the lead area.

[0114] In an exemplary embodiment, at least one data fan-out line includes a first line segment and a second line segment; the first end of the first line segment is connected to the lead-out line, and the second end of the first line segment is connected to the first end of the second line segment after extending in a direction away from the lead area; the second end of the second line segment is connected to the data line through a via after extending along the second direction or the opposite direction of the second direction.

[0115] In an exemplary embodiment, a plurality of via holes through which the data fan-out lines are connected to the data lines have different distances from the edge of the display area.

[0116] In an exemplary embodiment, the at least one data fan-out line includes a first line segment and a second line segment; the first end of the first line segment is connected to the lead-out line, and the second end of the first line segment is connected to the second line segment after extending in a direction away from the lead-out area; the second line segment includes a plurality of sub-line segments, the plurality of sub-line segments are interwoven to form a plurality of grid patterns, the plurality of grid patterns are repeated and continuously arranged in a first direction and / or a second direction, and at least one sub-line segment is connected to the data line through a via.

[0117] In an exemplary embodiment, the plurality of lead lines in the lead area have the same width, and the intervals between adjacent lead lines are the same; the width and the interval are dimensions in the second direction.

[0118] In an exemplary embodiment, in a plane parallel to the display substrate, the display substrate has a center line, the center line extends along the first direction and bisects the display area; on one side of the center line, the plurality of data lines include a first data line group and a second data line group, and the plurality of lead lines include a first lead line group and a second lead line group;

[0119] The first data line group includes a first data line, a second data line, ..., an Mth data line arranged in sequence along the second direction, the second data line group is arranged at one side of the first data line group in the second direction, and the second data line group includes an (M+1)th data line, a (M+2)th data line, ..., an Nth data line arranged in sequence along the second direction; the first lead line group includes a first lead line, a second lead line, ..., an Mth lead line arranged in sequence in a direction opposite to the second direction, the second lead line group includes a (M+1)th lead line, a (M+2)th lead line, ..., an Nth lead line arranged in sequence along the second direction, and the lead lines of the first lead line group and the lead lines of the second lead line group are alternately arranged; M and N are positive integers greater than 2, and M is less than N;

[0120] The lead-out lines in the first lead line group are connected to the data lines in the first data line group through the data fan-out lines, and the lead-out lines in the second lead line group are directly connected to the data lines in the second data line group.

[0121] In an exemplary embodiment, in a plane perpendicular to the display substrate, the display substrate includes a first conductive layer, a second conductive layer and a third conductive layer, and an insulating layer is provided between the first conductive layer and the second conductive layer and between the second conductive layer and the third conductive layer; the data line and the data fan-out line are provided in different conductive layers.

[0122] In an exemplary embodiment, the data fan-out lines include odd data fan-out lines and even data fan-out lines, the odd data fan-out lines are connected to the data lines of odd columns in the first data line group, and the even data fan-out lines are connected to the data lines of even columns in the first data line group; the odd data fan-out lines and the even data fan-out lines are arranged in different conductive layers.

[0123] In an exemplary embodiment, the lead-out lines include odd lead-out lines and even lead-out lines; the odd lead-out lines are connected to the data lines of odd columns in the first data line group through the odd data fan-out lines, or are directly connected to the data lines of odd columns in the second data line group; the even lead-out lines are connected to the data lines of even columns in the first data line group through the even data fan-out lines, or are directly connected to the data lines of even columns in the second data line group; the odd lead-out lines and the odd data fan-out lines are arranged on the same layer and are an integrated structure connected to each other, and the even lead-out lines and the even data fan-out lines are arranged on the same layer and are an integrated structure connected to each other.

[0124] In an exemplary embodiment, the odd data fan-out lines are arranged in the first conductive layer, the even data fan-out lines are arranged in the second conductive layer, and the data lines are arranged in the third conductive layer; or, the even data fan-out lines are arranged in the first conductive layer, the odd data fan-out lines are arranged in the second conductive layer, and the data lines are arranged in the third conductive layer.

[0125] In an exemplary embodiment, a material of the first conductive layer and a material of the second conductive layer are the same.

[0126] Fig. 9 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure. Fig.10 for Fig. 9 A side view of the substrate is shown in FIG. Fig. 9 and Fig.10As shown, the display substrate 10 may include a display area 100, a binding area 500 located on one side of the display area 100 in the opposite direction of the first direction D1, and a frame area 300 located on the other side of the display area 100. In an exemplary embodiment, the display area 100 may be a planarized area, including a plurality of sub-pixels Pxij constituting a pixel array, a plurality of data lines, and a plurality of data fan-out lines, the plurality of sub-pixels Pxij are configured to display dynamic pictures or still images, the plurality of data lines are configured to provide data signals to the plurality of sub-pixels Pxij, the plurality of data fan-out lines are correspondingly connected to the plurality of data lines, and are configured to make the plurality of data lines correspondingly connected to the plurality of lead-out lines in the binding area 500. In an exemplary embodiment, the display substrate may be a flexible substrate, so the display substrate may be deformable, such as curling, bending, folding, or rolling.

[0127] In an exemplary embodiment, the binding area 500 may include a lead area 501, a bending area 502 and a composite circuit area 503 arranged in sequence along the opposite direction of the first direction D1 (the direction away from the display area), the lead area 501 is connected to the display area 100, the bending area 502 is connected to the lead area 501, and the composite circuit area 503 is connected to the bending area 502.

[0128] In an exemplary embodiment, the lead area 501 may be provided with a plurality of lead lines, one end of a portion of the plurality of lead lines being connected to a plurality of data fan-out lines in the display area 100, one end of another portion of the plurality of lead lines being connected to a plurality of data lines in the display area 100, and the other ends of the plurality of lead lines crossing the bending area 502 to connect to the integrated circuit of the composite circuit area 503, so that the integrated circuit applies data signals to the data lines through the lead lines and the data fan-out lines.

[0129] In an exemplary embodiment, the bending region 502 may be bent with a curvature in the third direction D3, and the surface of the composite circuit region 503 may be reversed, that is, the surface of the composite circuit region 503 facing upward may be converted to face downward by the bending of the bending region 502, and the third direction D3 intersects with the first direction D1. In an exemplary embodiment, when the bending region 502 is bent, the composite circuit region 503 may overlap with the display region 100 in the third direction D3 (thickness direction).

[0130] In an exemplary embodiment, the composite circuit area 503 may include an antistatic area, a driving chip area, and a binding pin area, the integrated circuit (IC) 20 may be bound and connected to the driving chip area, and the flexible printed circuit (FPC) 30 may be bound and connected to the binding pin area. In an exemplary embodiment, the integrated circuit 20 may generate a driving signal required for driving a sub-pixel, and may provide the driving signal to the sub-pixel in the display area 100. For example, the driving signal may be a data signal for driving the luminous brightness of the sub-pixel. In an exemplary embodiment, the integrated circuit 20 may be bound and connected to the driving chip area through an anisotropic conductive film or other means, and the width of the integrated circuit 20 in the second direction D2 may be less than the width of the composite circuit area 503 in the second direction D2, and the second direction D2 intersects with the first direction D1. In an exemplary embodiment, the binding pin area may be provided with a pad including a plurality of pins (PINs), and the flexible printed circuit 30 may be bound and connected to the pad.

[0131] In an exemplary embodiment, the first direction D1 may be an extension direction (column direction) of a data line in the display area, the second direction D2 may be an extension direction (row direction) of a scanning signal line in the display area, and the third direction D3 may be a direction perpendicular to the plane of the display substrate. The first direction D1 and the second direction D2 may be perpendicular to each other, and the first direction D1 and the third direction D3 may be perpendicular to each other.

[0132] Fig.11 FIG. 1 is a schematic diagram of a structure of a lead-out line and a data fan-out line according to an exemplary embodiment of the present disclosure. Fig.11 As shown, the display area 100 may include a plurality of sub-pixels, a plurality of data lines DA, and a plurality of data fan-out lines 700 arranged in a matrix manner, and the lead area 501 of the binding area may include a plurality of lead lines 600. In an exemplary embodiment, the plurality of sub-pixels in the display area 100 form a plurality of pixel rows and a plurality of pixel columns, the plurality of data lines DA extend in the opposite direction of the first direction D1, and are sequentially arranged at set intervals along the second direction D2, each data line DA is connected to all sub-pixels of a pixel column in the display area 100, and the end of each data line DA extends to the lead area 501 of the binding area. The first end of each data fan-out line 700 is connected to a portion of the lead lines 600 in the lead area 501, and the second end of each data fan-out line 700 is connected to a portion of the data lines DA extending to the lead area 501. A portion of the lead lines 600 in the lead area 501 is connected to the data fan-out line 700, and another portion of the lead lines 600 is connected to another portion of the data lines DA extending to the lead area 501.

[0133] In an exemplary embodiment, the display substrate has a center line O, which extends along the first direction D1 and bisects a plurality of pixel columns of the display region 100. The plurality of data lines DA in the display region 100, the plurality of data fan-out lines 700, and the plurality of lead lines 600 in the lead area 501 of the bonding region may be symmetrically arranged relative to the center line O. The following description is made by taking the example that the left side of the display substrate includes N data lines, M data fan-out lines, and N lead lines, where N is a positive integer greater than 2, and M is a positive integer greater than 2 and less than N.

[0134] In an exemplary embodiment, the N data lines on the left side of the display area may include a first data line group and a second data line group divided according to the number size. The first data line group may include a first data line DA1, a second data line DA2, ..., an Mth data line, and the second data line group may include an (M+1)th data line, an (M+2)th data line, ..., an Nth data line.

[0135] In an exemplary embodiment, M may be the number of data lines that need to be led out in a fan-out manner. For example, when N is an even number, M may be N / 2, and when N is an odd number, M may be (N+1) / 2, or M may be (N-1) / 2. M may be set according to actual conditions, and the present disclosure does not limit this.

[0136] In an exemplary embodiment, a plurality of data lines of the first data line group are sequentially arranged along the second direction D2 in an ascending manner, a plurality of data lines of the second data line group are sequentially arranged along the second direction D2 in an ascending manner, and the second data line group is arranged on one side of the first data line group in the second direction D2. That is, the N data lines include a first data line DA1, a second data line DA2, ..., an Nth data line DAN sequentially arranged along the second direction D2, that is, the numbers of the N data lines are sequentially increased along the second direction D2. In an exemplary embodiment, the i-th data line may be a data line located in the i-th pixel column, and the i-th data line is connected to a sub-pixel in the i-th pixel column.

[0137] In an exemplary embodiment, the N lead wires on the left side of the lead wire area 501 may include a first lead wire group and a second lead wire group divided according to the number size. The first lead wire group may include a first lead wire 601, a second lead wire 602, ..., an Mth lead wire, and the second lead wire group may include an (M+1)th lead wire, an (M+2)th lead wire, ..., an Nth lead wire.

[0138] In an exemplary embodiment, the plurality of lead wires of the first lead wire group are sequentially arranged along the reverse direction of the second direction D2 in an ascending manner, the plurality of lead wires of the second lead wire group are sequentially arranged along the second direction D2 in an ascending manner, and the lead wires of the first lead wire group are alternately arranged with the lead wires of the second lead wire group. For example, the first lead wire is adjacent to the Nth lead wire, the second lead wire is adjacent to the N-1th lead wire, ..., the Mth lead wire is adjacent to the (M+1)th lead wire.

[0139] In an exemplary embodiment, multiple lead lines in the first lead group can be correspondingly connected to multiple data lines in the first data line group through multiple data fan-out lines, and multiple lead lines in the second lead group can be directly connected to multiple data lines in the second data line group, and the lead lines can provide data signals to the data lines directly or through the data fan-out lines.

[0140] In an exemplary embodiment, the first end of the i-th data fan-out line is connected to the i-th lead line in the first lead line group near the display area edge B, and the second end of the i-th data fan-out line first extends in a direction away from the lead area 501, then returns to the lead area 501, and is connected to the i-th data line in the first data line group extending to the lead area 501, i=1, 2, ..., M. In an exemplary embodiment, the display area edge B is the edge of the display area 100 on the side close to the lead area 501.

[0141] In an exemplary embodiment, the i-th data fan-out line may include a first line segment, a second line segment, and a third line segment connected in sequence. The first end of the first line segment is located near the edge B of the display area and is connected to the i-th lead line. The second end of the first line segment is connected to the first end of the second line segment after extending in a direction away from the lead area. The second end of the second line segment is connected to the first end of the third line segment after extending to the vicinity of the i-th data line along the second direction D2 or the opposite direction of the second direction D2. The second end of the third line segment is connected to the i-th data line extending to the lead area 501 from the display area 100 in the direction of the lead area.

[0142] In an exemplary embodiment, the third line segment may include an extension segment and a connection segment. The first end of the extension segment is located in the display area 100 and is connected to the second end of the second line segment. The second end of the extension segment extends toward the direction close to the lead area to the edge B of the display area and is connected to the first end of the connection segment. The second end of the connection segment extends toward the direction away from the display area and is connected to the i-th data line extending to the lead area through a via hole.

[0143] In an exemplary embodiment, the connection segment may be a broken line segment including a vertical line segment parallel to the first direction D1 and a horizontal line segment parallel to the second direction D2.

[0144] In an exemplary embodiment, a plurality of lead lines in the first lead line group and the second lead line group may be disposed to be parallel to the first direction D1 , that is, the lead lines are parallel to the data lines.

[0145] In an exemplary embodiment, extension lines of the plurality of data lines in the second data line group in the first direction D1 may overlap with corresponding lead lines in the second lead line group.

[0146] In an exemplary embodiment, the first line segments of the plurality of data fan-out lines may be arranged to be parallel to the first direction D1, the plurality of second line segments may be arranged to be parallel to the second direction D2, and the extended segments of the plurality of third line segments may be arranged to be parallel to the first direction D1. At least one first line segment is arranged between adjacent data lines, and at least one third line segment is arranged between adjacent data lines.

[0147] In an exemplary embodiment, the spacing between adjacent first line segments and the spacing between adjacent data lines may be the same, and the spacing between the extended segments of adjacent third line segments and the adjacent data lines may be the same, so that the distribution density of the data fan-out lines is substantially the same as the distribution density of the data lines.

[0148] In an exemplary embodiment, multiple line segments of the kth data fan-out line can form a rectangular routing line, and the rectangular routing line formed by the kth data fan-out line is nested in the rectangular routing line formed by the k-1th data fan-out line to form a rectangular nested structure, and the distance between the second line segment of the k-1th data fan-out line and the edge B of the display area is greater than the distance between the second line segment of the kth data fan-out line and the edge B of the display area, and the distance between the first line segment and the third line segment in the k-1th data fan-out line is greater than the distance between the first line segment and the third line segment in the kth data fan-out line, k=2,...,M.

[0149] Fig.12 for Fig.11 The enlarged view of the C1 area in the figure shows the structure of the lead-out line and the data fan-out line when N=8. Fig.12 As shown, the multiple data lines may include a first data line DA1, a second data line DA2, a third data line DA3, a fourth data line DA4, a fifth data line DA5, a sixth data line DA6, a seventh data line DA7 and an eighth data line DA8 arranged in sequence along the second direction D2, and the multiple lead lines of the lead area 501 of the binding area may include a first lead line 601, an eighth lead line 608, a second lead line 602, a seventh lead line 607, a third lead line 603, a sixth lead line 606, a fourth lead line 604 and a fifth lead line 605 arranged in sequence along the opposite direction of the second direction D2.

[0150] In an exemplary embodiment, a first end of the first data fan-out line 701 is connected to the first lead line 601 through a via near the edge B of the display area, and a second end extends to the vicinity of the first data line DA1 of the display area 100, and then extends from the display area 100 to the lead area 501 to be connected to the first data line DA1 through a via. A first end of the second data fan-out line 702 is connected to the second lead line 602 through a via near the edge B of the display area, and a second end extends to the vicinity of the second data line DA2 of the display area 100, and then extends from the display area 100 to the lead area 501 to be connected to the second data line DA2 through a via. A first end of the third data fan-out line 703 is connected to the third lead line 603 through a via near the edge B of the display area, and a second end extends to the vicinity of the third data line DA3 of the display area 100, and then extends from the display area 100 to the lead area 501 to be connected to the third data line DA3 through a via. The first end of the fourth data fan-out line 704 is connected to the fourth lead line 604 through a via near the edge B of the display area, and the second end extends to the vicinity of the fourth data line DA4 of the display area 100, and then extends from the display area 100 to the lead area 501 and is connected to the fourth data line DA4 through a via.

[0151] In an exemplary embodiment, the distances between the plurality of via holes correspondingly connected to the data fan-out lines and the edge B of the display area are substantially the same, that is, the plurality of via holes are located on the same straight line extending along the second direction D2.

[0152] In an exemplary embodiment, the distances between the plurality of vias correspondingly connected to the data fan-out lines and the lead-out lines and the edge B of the display area are substantially the same, that is, the plurality of vias are located on the same straight line extending along the second direction D2.

[0153] In an exemplary embodiment, the fifth data line DA5 extending to the lead area 501 is directly connected to the fifth lead line 605 through a via, the sixth data line DA6 extending to the lead area 501 is directly connected to the sixth lead line 606 through a via, the seventh data line DA7 extending to the lead area 501 is directly connected to the seventh lead line 607 through a via, and the eighth data line DA8 extending to the lead area 501 is directly connected to the eighth lead line 608 through a via.

[0154] In an exemplary embodiment, the distances between the plurality of via holes correspondingly connecting the data lines and the lead-out lines and the edge B of the display area are substantially the same, that is, the plurality of via holes are located on the same straight line extending along the second direction D2.

[0155] Although Fig.12The exemplary embodiment shown is described by taking the example that the third line segment of the data fan-out line is located on the right side of the corresponding data line, but in the present disclosure, the third line segment of the data fan-out line may be located on the left side of the corresponding data line, or a portion of the third line segment is located on the right side of the data line and another portion of the third line segment is located on the left side of the data line, and the present disclosure does not make any limitation thereto.

[0156] Fig.13 for Fig.12 Magnified view of the C2 region. Fig.13 As shown, the third data line DA3, the fourth data line DA4, the fifth data line DA5 and the sixth data line DA6 are respectively extended to the lead area 501 of the binding area along the first direction D1. In the lead area 501, the third data fan-out line 703 first extends to the vicinity of the third data line DA3 of the display area 100, and then extends from the display area 100 to the lead area 501, and is connected to the end of the third data line DA3 through the first via K1. The fourth data fan-out line 704 first extends to the vicinity of the fourth data line DA4 of the display area 100, and then extends from the display area 100 to the lead area 501, and is connected to the end of the fourth data line DA4 through the second via K2. The fifth lead line 605 is connected to the end of the fifth data line DA5 through the third via K3, and the sixth connection signal line 606 is connected to the end of the sixth data line DA6 through the fourth via K4.

[0157] In an exemplary embodiment, the data line and the data fan-out line may be disposed in different film layers with an insulating layer disposed therebetween.

[0158] In an exemplary embodiment, the lead-out line and the data fan-out line may be disposed in the same film layer and formed simultaneously through the same patterning process, and the lead-out line and the data fan-out line may be an integrated structure connected to each other.

[0159] In an exemplary embodiment, the lead-out line and the data fan-out line may be disposed in different film layers, with an insulating layer disposed therebetween, and the two are connected through vias.

[0160] In an exemplary embodiment, the data line may include a data line of an odd column and a data line of an even column, the data line of the odd column is arranged in an odd sub-pixel column, and the data line of the even column is arranged in an even sub-pixel column. Accordingly, the data fan-out line may include an odd data fan-out line and an even data fan-out line, the data fan-out line connected to the data line of the odd column is called an odd data fan-out line, and the data fan-out line connected to the data line of the even column is called an even data fan-out line. Accordingly, the lead-out line may include an odd lead-out line and an even lead-out line, the lead-out line connected to the data line of the odd column directly or through the odd data fan-out line is called an odd lead-out line, and the lead-out line connected to the data line of the even column directly or through the even data fan-out line is called an even lead-out line.

[0161] In an exemplary embodiment, the odd-numbered data fan-out lines and the even-numbered data fan-out lines may be disposed in the same film layer.

[0162] In an exemplary embodiment, the odd data fan-out lines and the even data fan-out lines can be arranged in different film layers, and an insulating layer is arranged between the odd data fan-out lines and the even data fan-out lines, that is, an insulating layer is arranged between the data lines and the odd data fan-out lines, an insulating layer is arranged between the data lines and the even data fan-out lines, and an insulating layer is arranged between the odd data fan-out lines and the even data fan-out lines.

[0163] In an exemplary embodiment, the odd lead lines and the odd data fan-out lines may be arranged in the same layer and formed simultaneously by the same patterning process, and the odd lead lines and the odd data fan-out lines may be an integrated structure connected to each other. The even lead lines and the even data fan-out lines may be arranged in the same layer and formed simultaneously by the same patterning process, and the even lead lines and the even data fan-out lines may be an integrated structure connected to each other.

[0164] Fig.14 for Fig.13 Sectional view along AA direction. Fig.14 As shown, in a plane perpendicular to the display substrate, the display substrate may include a plurality of conductive layers arranged on a base, the plurality of conductive layers may include a first conductive layer, a second conductive layer, and a third conductive layer arranged in sequence along a direction away from the base, the first conductive layer may include odd lead lines and odd data fan-out lines, such as the third lead line 603, the fifth lead line 605, and the third data fan-out line 703, the second conductive layer may include even lead lines and even data fan-out lines, such as the fourth lead line 604, the sixth lead line 606, and the fourth data fan-out line 704, and the third conductive layer may include data lines, such as the third data line DA3, the fourth data line DA4, the fifth data line DA5, and the sixth data line DA6.

[0165] In an exemplary embodiment, in a plane perpendicular to the display substrate, the display substrate may include a semiconductor layer and a plurality of insulating layers, and the plurality of insulating layers may include a first insulating layer 11, a second insulating layer 12, a third insulating layer 13, and a fourth insulating layer 14 sequentially disposed in a direction away from the substrate. In an exemplary embodiment, the first insulating layer 11 is disposed on the substrate 10, the semiconductor layer is disposed on a side of the first insulating layer 11 away from the substrate, the second insulating layer 12 covers the semiconductor layer, the first conductive layer is disposed on a side of the second insulating layer 12 away from the substrate, the third insulating layer 13 covers the first conductive layer, the second conductive layer is disposed on a side of the third insulating layer 13 away from the substrate, the fourth insulating layer 14 covers the second conductive layer, and the third conductive layer is disposed on a side of the fourth insulating layer 14 away from the substrate.

[0166] In an exemplary embodiment, the orthographic projection of any lead line on the substrate has no overlapping area with the orthographic projection of other lead lines on the substrate, and the orthographic projection of any data fan-out line on the substrate has no overlapping area with the orthographic projection of other data fan-out lines on the substrate.

[0167] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer. The first insulating layer may be referred to as a buffer layer, configured to prevent ionic impurity diffusion, prevent moisture penetration, and perform a surface flattening function, the second insulating layer disposed between the semiconductor layer and the first conductive layer, the third insulating layer disposed between the first conductive layer and the second conductive layer may be referred to as a gate insulating (GI) layer, and the fourth insulating layer disposed between the second conductive layer and the third conductive layer may be referred to as an interlayer insulating (ILD) layer. The first conductive layer, the second conductive layer and the third conductive layer may be metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure, or a multilayer composite structure, such as Ti / Al / Ti, etc. The semiconductor layer can be made of amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene or polythiophene and the like, that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology or organic technology. The active layer based on oxide technology can be made of oxides containing indium and tin, oxides containing tungsten and indium, oxides containing tungsten, indium and zinc, oxides containing titanium and indium, oxides containing titanium, indium and tin, oxides containing indium and zinc, oxides containing silicon, indium and tin, oxides containing indium, gallium and zinc, and the like.

[0168] In an exemplary embodiment, in the display area, the semiconductor layer may include an active layer of multiple transistors, the first conductive layer may include a scan signal line, gate electrodes of multiple transistors, a first capacitor plate, odd lead lines, and odd data fan-out lines, the second conductive layer may include a second capacitor plate, even lead lines, and even data fan-out lines, and the third conductive layer may include a data line, a source electrode, and a drain electrode of multiple transistors.

[0169] In the binding area, the first conductive layer may include odd-numbered lead lines, the second conductive layer may include even-numbered lead lines, and the third conductive layer may include data lines.

[0170] In an exemplary embodiment, a plurality of first via holes K1 may be formed on the third insulating layer 13 and the fourth insulating layer 14. The plurality of first via holes K1 are located at the ends of the odd-numbered data fan-out lines. The third insulating layer 13 and the fourth insulating layer 14 in the first via holes K1 are etched away to expose the surfaces of the odd-numbered data fan-out lines. The first via holes K1 are configured to allow the subsequently formed odd-numbered columns of data lines to be connected to the odd-numbered data fan-out lines through the via holes.

[0171] In an exemplary embodiment, a plurality of second via holes K2 may be formed on the fourth insulating layer 14, and the plurality of second via holes K2 are located at the ends of the even-numbered data fan-out lines, and the fourth insulating layer 14 in the second via holes K2 is etched away to expose the surface of the even-numbered data fan-out lines. The second via holes K2 are configured to allow the data lines of the even-numbered columns formed subsequently to be connected to the even-numbered data fan-out lines through the via holes.

[0172] In an exemplary embodiment, a plurality of third via holes K3 may be formed on the third insulating layer 13 and the fourth insulating layer 14. The plurality of third via holes K3 are located at the ends of the odd-numbered lead wires in the lead area 501. The third insulating layer 13 and the fourth insulating layer 14 in the third via holes K3 are etched away to expose the surfaces of the odd-numbered lead wires. The third via holes K3 are configured to allow the data lines of the odd-numbered columns formed subsequently to be connected to the odd-numbered lead wires through the via holes.

[0173] In an exemplary embodiment, a plurality of fourth via holes K4 may be formed on the fourth insulating layer 14, and the plurality of fourth via holes K4 are located at the ends of the even-numbered lead wires in the lead area 501. The fourth insulating layer 14 in the fourth via holes K4 is etched away to expose the surfaces of the even-numbered lead wires. The fourth via holes K4 are configured to allow the data lines of the even-numbered columns formed subsequently to be connected to the even-numbered lead wires through the via holes.

[0174] The following is an exemplary description of a preparation process of a display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be any one or more of spraying, spin coating, and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a layer of thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of A includes the orthographic projection of B" or "the orthographic projection of B is located within the "orthographic projection range of A" means that the edge of the display area of ​​the orthographic projection of B falls within the display area edge range of the orthographic projection of A, or the display area edge of the orthographic projection of A overlaps with the display area edge of the orthographic projection of B.

[0175] In an exemplary embodiment, the preparation process of the display substrate may include the following operations.

[0176] (1) Forming a semiconductor layer pattern on a substrate. In an exemplary embodiment, forming a semiconductor layer pattern on a substrate may include: sequentially depositing a first insulating film and a semiconductor film on the substrate, patterning the semiconductor film through a patterning process to form a first insulating layer covering the entire substrate, and a semiconductor layer pattern disposed on the first insulating layer, wherein the semiconductor layer pattern includes at least active layers of a plurality of transistors. In an exemplary embodiment, the substrate may be a flexible substrate.

[0177] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first metal film on the substrate on which the aforementioned pattern is formed, patterning the first metal film through a patterning process to form a second insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, wherein the first conductive layer pattern includes at least a plurality of odd data fan-out lines, a plurality of scan signal lines, a plurality of gate electrodes of transistors, and a plurality of first capacitor electrodes located in the display area, and a plurality of odd lead lines located in the lead area of ​​the binding area, and the odd data fan-out lines and the odd lead lines may be an integrated structure connected to each other.

[0178] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second metal film on the substrate on which the aforementioned pattern is formed, patterning the second metal film through a patterning process to form a third insulating layer covering the first conductive layer pattern, and a second conductive layer pattern disposed on the third insulating layer, wherein the second conductive layer pattern includes at least a plurality of even-numbered data fan-out lines and a plurality of second capacitor electrodes located in the display area, and a plurality of even-numbered lead lines located in the lead area of ​​the binding area, and the even-numbered data fan-out lines and the even-numbered lead lines may be an integrated structure connected to each other.

[0179] (4) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film through a patterning process to form a fourth insulating layer covering the second conductive layer pattern, and a plurality of vias are provided on the fourth insulating layer. The plurality of vias may include: active vias located at the positions of the plurality of active layers in the display area, and a plurality of first vias, second vias, third vias, and fourth vias located in the lead area. The active vias expose the active layer, the first vias expose the odd data fan-out lines, the second vias expose the even data fan-out lines, the third vias expose the odd lead lines, and the fourth vias expose the even lead lines.

[0180] (5) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: depositing a third metal film on the substrate on which the aforementioned pattern is formed, patterning the third metal film through a patterning process, and forming a third conductive layer pattern on the fourth insulating layer, wherein the third conductive layer pattern includes at least: a plurality of data lines, source electrodes and drain electrodes of a plurality of transistors, the source electrodes and the drain electrodes are respectively connected to the corresponding active layers through active vias, a plurality of data lines extend to the lead area of ​​the binding region, the data lines of odd columns in the first data line group are connected to the odd data fan-out lines through the first vias, the data lines of even columns in the first data line group are connected to the even data fan-out lines through the second vias, the data lines of odd columns in the second data line group are connected to the odd lead-out lines through the third vias, and the data lines of even columns in the second data line group are connected to the even lead-out lines through the fourth vias.

[0181] In an exemplary embodiment, the preparation of the display substrate may further include forming a light emitting structure layer, an encapsulation layer, etc., which will not be described in detail here.

[0182] In an exemplary embodiment, the first conductive layer and the second conductive layer may be made of the same metal material, such as molybdenum (Mo), the width M of each lead line is the same, the spacing L between adjacent lead lines is the same, and the width M and the spacing L are both dimensions in the second direction D2. In an exemplary embodiment, the width of each data fan-out line may be the same.

[0183] Although Fig.14 The exemplary embodiment shown is described by taking the example that the odd data fan-out lines are set in the first conductive layer, the even data fan-out lines are set in the second conductive layer, and the data lines are set in the third conductive layer. However, in the present disclosure, the odd data fan-out lines, the even data fan-out lines and the data lines can be set in any layer, as long as the data signal lines and the data fan-out lines are located in different conductive layers. The present disclosure does not make any limitation here.

[0184] The structure of the display substrate and its preparation process shown in the present disclosure are merely exemplary. In an exemplary embodiment, the corresponding structure can be changed and the composition process can be increased or decreased according to actual needs, and the present disclosure does not limit this.

[0185] In a display substrate, a fan-out area is provided in a binding area, and data lines in a display area are led out through data fan-out lines in the fan-out area. Since there are many oblique lines in the fan-shaped area, the lower frame is wide, which is not conducive to realizing a narrow frame. In an exemplary embodiment of the present disclosure, a lead-out line is provided in the lead area of ​​the binding area, and a data fan-out line is provided in the display area. The lead-out line is connected to the corresponding data signal line through the data fan-out line, which not only realizes the corresponding connection between multiple lead-out lines and multiple data signal lines, but also makes it unnecessary to provide fan-shaped oblique lines in the lead area. Multiple lead-out lines are mutually parallel vertical lines, which can be directly introduced into the composite circuit area of ​​the binding area, effectively reducing the length of the lead area in the vertical direction, greatly reducing the width of the lower frame, so that the widths of the upper frame, lower frame, left frame and right frame of the display device are similar, all less than 1.0 mm, thereby improving the screen-to-body ratio and facilitating the realization of full-screen display.

[0186] In the exemplary embodiment of the present disclosure, by respectively setting the adjacent data fan-out lines and lead-out lines in two film layers, and the data fan-out lines and lead-out lines are alternately set in the two film layers, the spacing between the adjacent data fan-out lines and lead-out lines is effectively reduced, the connection reliability is effectively improved, and the width of the lower frame can be further reduced. The present disclosure sets the data fan-out lines and lead-out lines in the two film layers to use the same material, the width of each data fan-out line and lead-out line is the same, and the spacing between adjacent lead-out lines is the same, which effectively avoids the size deviation of the two film layers. The data line can connect the data fan-out lines and lead-out lines in any film layer, so that the lead-out lines in the lead area do not need to be bent or crossed, and the data fan-out lines and lead-out lines alternately set in the two film layers have substantially the same electrical characteristics, which effectively improves the display uniformity and display quality.

[0187] Fig.15 FIG. 1 is a schematic diagram of another structure of a lead-out line and a data fan-out line according to an exemplary embodiment of the present disclosure. Fig.16 for Fig.15 A magnified view of the C3 region. Fig.15 and Fig.16 As shown, the multiple data lines DA and the multiple data fan-out lines 700 in the display area 100 and the multiple lead lines 600 in the lead area 501 can be symmetrically arranged relative to the center line O. The following is an example in which the left side of the display substrate includes 12 (i.e., N=12) data lines, 6 data fan-out lines and 12 lead lines.

[0188] In an exemplary embodiment, the first data line group may include first to sixth data lines DA1 to DA6, the second data line group may include seventh to twelfth data lines DA7 to DA12. The first lead line group may include first to sixth lead lines 601 to 606, the second lead line group may include seventh to twelfth lead lines 607 to 6012, and the six data fan-out lines may include first to sixth data fan-out lines 701 to 706.

[0189] In an exemplary embodiment, the plurality of data lines of the first data line group are sequentially arranged along the second direction D2 in an ascending manner, and the plurality of lead lines of the first lead line group are sequentially arranged along the opposite direction of the second direction D2 in an ascending manner. The plurality of data lines of the second data line group are sequentially arranged along the second direction D2 in an ascending manner, and the second data line group is arranged on one side of the first data line group in the second direction D2. The plurality of lead lines of the second lead line group are sequentially arranged along the second direction D2 in an ascending manner, and the lead lines of the first lead line group are alternately arranged with the lead lines of the second lead line group.

[0190] In an exemplary embodiment, the first ends of the six data fan-out lines are connected to the six lead lines in the first lead line group in the vicinity of the display area edge B, and the second ends of the six data fan-out lines first extend in a direction away from the lead line area 501, then return to the lead line area 501, and are correspondingly connected to the six data lines in the first data line group extending to the lead line area 501. After the six data lines in the second data line group extend to the lead line area 501, they are directly correspondingly connected to the six lead lines in the second lead line group.

[0191] In an exemplary embodiment, the i-th data fan-out line may include a first line segment, a second line segment, and a third line segment connected in sequence. The first end of the first line segment is located near the edge B of the display area and is connected to the i-th lead line. The second end of the first line segment is connected to the first end of the second line segment after extending in a direction away from the lead area. The first line segment has a first angle θ1 with the first direction D1, and the first angle θ1 may be greater than 0° and less than 90°. The second end of the second line segment is connected to the first end of the third line segment after extending along the second direction D2 or the opposite direction of the second direction D2. The second end of the third line segment is connected to the i-th data line extending to the lead area 501 after extending from the display area 100 to the lead area 501 in the direction of the lead area.

[0192] In an exemplary embodiment, the third line segment may include an extension segment and a connection segment. The first end of the extension segment is located in the display area 100 and is connected to the second end of the second line segment. The second end of the extension segment extends toward the direction close to the lead area to the edge B of the display area and is connected to the first end of the connection segment. The second end of the connection segment extends toward the direction away from the display area and is connected to the i-th data line extending to the lead area through a via. The extension segment of the third line segment has a second angle θ2 with the first direction D1, and the second angle θ2 may be approximately greater than 0° and less than 90°. Wherein, i=1, 2, 3, 4, 5, 6.

[0193] In an exemplary embodiment, the connection segment may be a broken line segment including a vertical line segment parallel to the first direction D1 and a horizontal line segment parallel to the second direction D2.

[0194] In an exemplary embodiment, the first angle θ1 and the second angle θ2 may be approximately 20° to 70°, and the first angle θ1 and the second angle θ2 may be the same or may be different.

[0195] In an exemplary embodiment, multiple line segments of the kth data fan-out line can form a trapezoidal routing, and the trapezoidal routing formed by the kth data fan-out line is nested in the trapezoidal routing formed by the k-1th data fan-out line to form a trapezoidal nested structure, and the distance between the second line segment of the k-1th data fan-out line and the edge B of the display area is greater than the distance between the second line segment of the kth data fan-out line and the edge B of the display area, k=2, 3, 4, 5, 6.

[0196] In an exemplary embodiment, the seventh to twelfth lead lines 607 to 6012 are directly connected to the seventh to twelfth data lines DA7 to DA12 extending to the lead area 501 , respectively.

[0197] In an exemplary embodiment, the plurality of lead lines in the first and second lead lines may be arranged parallel to the first direction D1. Extension lines of the plurality of data lines in the second data line group in the first direction D1 may overlap with the plurality of lead lines in the second lead line group.

[0198] In an exemplary embodiment, the orthographic projection of any lead line on the substrate has no overlapping area with the orthographic projection of other lead lines on the substrate, and the orthographic projection of any data fan-out line on the substrate has no overlapping area with the orthographic projection of other data fan-out lines on the substrate.

[0199] In this exemplary embodiment, the film layer structures of the data lines, data fan-out lines and lead-out lines may be similar to those of the aforementioned exemplary embodiments, and will not be described in detail here.

[0200] The exemplary embodiments of the present disclosure can achieve the technical effects of the aforementioned embodiments, including effectively reducing the width of the lower frame, effectively avoiding the size deviation of the two film layers, and effectively improving the display uniformity and display quality. In addition, the present disclosure fully utilizes the space of the display area by forming a data fan-out line with a trapezoidal routing in the display area, which can avoid interference with the data line and effectively improve the display performance.

[0201] Fig.17 Schematic diagram of another structure of a lead-out line and a data fan-out line according to an exemplary embodiment of the present disclosure. Fig.15 The structure of the lead-out line and the data fan-out line of this exemplary embodiment is similar to Fig.16 The structures of the embodiments shown are similar, except that the extended segments of the first line segment and the third line segment can be broken lines, and the data fan-out lines form polygonal routing lines.

[0202] In an exemplary embodiment, the first line segment may include a first straight line segment and a first oblique line segment, the first end of the first straight line segment is located near the edge B of the display area and is connected to the lead line, the second end of the first straight line segment is connected to the first end of the first oblique line segment after extending a distance along the first direction D1, and the first oblique line segment is connected to the first end of the second line segment after extending in a direction away from the lead area. The first oblique line segment has a first angle θ1 with the first direction D1, the first angle θ1 may be greater than 0° and less than 90°, and the distance B1 between the second end of the first straight line segment and the edge B of the display area may be set as needed.

[0203] In an exemplary embodiment, the third line segment may include an extension segment and a connection segment. The first end of the extension segment is located in the display area 100 and is connected to the second end of the second line segment. The second end of the extension segment extends toward the direction close to the lead area to the edge B of the display area and is connected to the first end of the connection segment. The second end of the connection segment extends toward the direction away from the display area and is connected to the data line extending to the lead area through a via. In an exemplary embodiment, the connection segment may be a broken line segment, including a vertical line segment parallel to the first direction D1 and a horizontal line segment parallel to the second direction D2.

[0204] In an exemplary embodiment, the extended section of the third line segment may include a third oblique line segment and a third straight line segment, the first end of the third oblique line segment is located in the display area 100 and is connected to the second end of the second line segment, the second end of the third oblique line segment is connected to the first end of the third straight line segment after extending in the direction of the lead area, and the second end of the third straight line segment is connected to the first end of the connecting segment after extending in the opposite direction of the first direction D1 to the edge B of the display area. The third oblique line segment has a second angle θ2 with the first direction D1, the second angle θ2 may be greater than 0° and less than 90°, and the distance B2 between the first end of the third straight line segment and the edge B of the display area can be set as needed.

[0205] In an exemplary embodiment, multiple line segments of the kth data fan-out line can form a polygonal routing, and the polygonal routing formed by the kth data fan-out line is nested within the polygonal routing formed by the k-1th data fan-out line to form a polygonal nested structure, and the distance between the second line segment of the k-1th data fan-out line and the edge B of the display area is greater than the distance between the second line segment of the kth data fan-out line and the edge B of the display area, k=2, 3, 4, 5, 6.

[0206] The exemplary embodiments of the present disclosure can achieve the technical effects of the aforementioned embodiments, including effectively reducing the width of the lower frame, effectively avoiding the size deviation of the two film layers, and effectively improving the display uniformity and display quality. In addition, the present disclosure fully utilizes the space of the display area by forming a polygonal wiring in the display area, which can avoid interference with the data line, and by setting the data fan-out line as a vertical line in the area of ​​the display area close to the lead area, it is helpful to reduce the difficulty of wiring design.

[0207] Fig.18 2 is a schematic diagram of the structure of another lead-out line and a data fan-out line according to an exemplary embodiment of the present disclosure. Fig.19 for Fig.18 A magnified view of the C4 region. Fig.18 and Fig.19As shown, the multiple data lines, data fan-out lines in the display area 100 and the multiple lead lines in the lead area 501 can be symmetrically arranged relative to the center line O. The following is an example in which the left side of the display substrate includes 8 (N=8) data lines, 4 data fan-out lines and 8 lead lines.

[0208] In an exemplary embodiment, the arrangement of the 8 data lines on the left side of the display area and the 8 lead lines on the left side of the lead area 501 can be similar to the aforementioned embodiment, and the multiple lead lines in the first lead group can be connected to the multiple data lines in the first data line group through the multiple data fan-out lines, and the multiple lead lines in the second lead group can be directly connected to the multiple data lines in the second data line group.

[0209] In an exemplary embodiment, the i-th data fan-out line may include a first line segment, a second line segment, and a third line segment connected in sequence, wherein the first end of the first line segment is located near the edge B of the display area and is connected to the i-th lead line, and the second end of the first line segment is connected to the first end of the second line segment after extending in a direction away from the lead area. The second end of the second line segment is connected to the first end of the third line segment after extending along the second direction D2 or the opposite direction of the second direction D2. The second end of the third line segment is connected to the i-th data line extending to the lead area 501 after extending from the display area 100 to the lead area 501 in the direction of the lead area.

[0210] In an exemplary embodiment, at least one of the first line segment, the second line segment, and the third line segment may include a plurality of sub-line segments, the plurality of sub-line segments are interwoven to form a grid pattern, and the grid pattern is a polygon surrounded by the plurality of sub-line segments. In an exemplary embodiment, the shape of the grid pattern may include any one or more of a triangle, a square, a rectangle, a rhombus, a trapezoid, a pentagon, and a hexagon.

[0211] In an exemplary embodiment, the area surrounded by multiple sub-line segments in a grid pattern includes the light-emitting area of ​​the sub-pixel, and each sub-line segment is located in the non-light-emitting area between adjacent light-emitting areas. For example, when the display substrate is an OLED display substrate, the light-emitting area is the area of ​​the pixel opening in the pixel definition layer, the non-light-emitting area is the area outside the pixel opening, the orthographic projection of the light-emitting area on the display substrate is located within the range of the orthographic projection of the area surrounded by the sub-line segments on the display substrate, and the orthographic projection of the sub-line segments on the display substrate is located within the range of the orthographic projection of the non-light-emitting area on the display substrate.

[0212] In an exemplary embodiment, along the first direction D1, the display area 100 can be divided into four (N / 2=4) sub-areas, namely, a first sub-area 600-1, a second sub-area 600-2, a third sub-area 600-3 and a fourth sub-area 600-4 arranged in sequence in the opposite direction of the first direction D1. In an exemplary embodiment, the lengths of the four sub-areas in the first direction D1 can be the same or different, which is not limited in the present disclosure.

[0213] In an exemplary embodiment, the second line segment in the first data fan-out line 701 may include a plurality of sub-line segments, and a first block grid pattern formed by the plurality of sub-line segments may be set in the area where the first sub-region 600-1 is located. The second line segment in the second data fan-out line 702 may include a plurality of sub-line segments, and a second block grid pattern formed by the plurality of sub-line segments may be set in the area where the second sub-region 600-2 is located. The second line segment in the third data fan-out line 703 may include a plurality of sub-line segments, and a third block grid pattern formed by the plurality of sub-line segments may be set in the area where the third sub-region 600-3 is located. The second line segment in the fourth data fan-out line 704 may include a plurality of sub-line segments, and a fourth block grid pattern formed by the plurality of sub-line segments may be set in the area where the fourth sub-region 600-4 is located.

[0214] In an exemplary embodiment, the block grid pattern is formed by repeatedly and continuously arranging and splicing a plurality of grid patterns in the first direction D1 and / or the second direction D2. At least one of the first block grid pattern, the second block grid pattern, the third block grid pattern, and the fourth block grid pattern may occupy an area of ​​about 50% to 90% of the area of ​​the sub-region.

[0215] In an exemplary embodiment, at least one of the first line segment and the third line segment in the first data fan-out line 701 may include a plurality of sub-line segments, and a first strip grid pattern formed by the plurality of sub-line segments may be set in the area where the first sub-region 600-1 and the second sub-region 600-2 are located, and the first strip grid pattern is connected to the first block grid pattern. At least one of the first line segment and the third line segment in the second data fan-out line 702 may include a plurality of sub-line segments, and a second strip grid pattern formed by the plurality of sub-line segments may be set in the area where the second sub-region 600-2 and the third sub-region 600-3 are located, and the second strip grid pattern is connected to the second block grid pattern. At least one of the first line segment and the third line segment in the third data fan-out line 703 may include a plurality of sub-line segments, and a third strip grid pattern formed by the plurality of sub-line segments may be set in the area where the third sub-region 600-3 and the fourth sub-region 600-4 are located, and the third strip grid pattern is connected to the third block grid pattern.

[0216] In an exemplary embodiment, the strip grid pattern is formed by repeatedly and continuously arranging multiple grid patterns in the first direction D1 or the second direction D2. In an exemplary embodiment, the strip grid pattern may include multiple sub-strip grid patterns, which are sequentially connected in the first direction D1 or the second direction D2.

[0217] In an exemplary embodiment, multiple line segments of the kth data fan-out line can form a grid routing with a block grid pattern, and the grid routing formed by the kth data fan-out line is nested within the grid routing formed by the k-1th data fan-out line to form a grid nested structure, k=2, 3, 4.

[0218] In this exemplary embodiment, the film layer structures of the data lines, data fan-out lines and lead-out lines may be similar to those of the aforementioned exemplary embodiments, and will not be described in detail here.

[0219] The exemplary embodiments of the present disclosure can achieve the technical effects of the aforementioned embodiments, including effectively reducing the width of the lower frame, effectively avoiding the size deviation of the two film layers, and effectively improving the display uniformity and display quality. In addition, the present disclosure can not only reduce the resistance difference of the data fan-out line, but also reduce the reflective optical difference of the data fan-out line by setting a data fan-out line with a grid pattern. Since the lead-out line in the first lead group is connected to the data line through the data fan-out line, and the lead-out line in the second lead group is directly connected to the data line, the resistance of the lead-out line in the first lead group is much greater than the resistance of the lead-out line in the second lead group. This resistance difference can cause display problems, such as the difference between the color on both sides and the middle color, the flashing screen is powdery, etc. The present disclosure effectively reduces the resistance of the lead-out line by setting a data fan-out line with a grid pattern, and the grid pattern basically covers the entire display area, effectively reducing the resistance difference, avoiding the display problem caused by the resistance difference, and improving the display quality. However, when the data fan-out line is set in a part of the display area, when viewed in sunlight or strong light, there will be a reflective display difference with or without the data fan-out line, which will cause display problems. The present disclosure provides data fan-out lines with a grid pattern, and the grid pattern substantially covers the entire display area, thereby effectively avoiding the reflective optical difference caused by the presence or absence of the data fan-out lines, and improving the display quality.

[0220] Fig. 20 2 is a schematic diagram of the structure of another lead-out line and a data fan-out line according to an exemplary embodiment of the present disclosure. Fig.21 for Fig. 20 A magnified view of the C5 region in Figure 2. Fig. 20 and Fig.21 As shown, the multiple data lines, data fan-out lines in the display area 100 and the multiple lead lines in the lead area 501 can be symmetrically arranged relative to the center line O. The following is an example in which the left side of the display substrate includes 8 (N=8) data lines, 4 data fan-out lines and 8 lead lines.

[0221] In an exemplary embodiment, the arrangement of the 8 data lines on the left side of the display area and the 8 lead lines on the left side of the lead area 501 can be similar to the aforementioned embodiment, and the multiple lead lines in the first lead group can be connected to the multiple data lines in the first data line group through the multiple data fan-out lines, and the multiple lead lines in the second lead group can be directly connected to the multiple data lines in the second data line group.

[0222] In an exemplary embodiment, a plurality of data fan-out lines may be connected correspondingly to a plurality of data lines in the first data line group within the display area 100 .

[0223] In an exemplary embodiment, the i-th data fan-out line may include a first line segment and a second line segment connected to each other, the first end of the first line segment is located near the edge B of the display area and connected to the i-th lead line, the second end of the first line segment is connected to the first end of the second line segment after extending in a direction away from the lead area, and the second end of the second line segment is connected to the i-th data line after extending along the second direction D2 or the reverse direction of the second direction D2.

[0224] In an exemplary embodiment, at least one of the first line segment and the second line segment may include a plurality of sub-line segments, and the plurality of sub-line segments are interwoven to form a plurality of grid patterns, and the structure of the grid patterns is similar to that of the aforementioned embodiment.

[0225] In an exemplary embodiment, the second line segment in the first data fan-out line 701 may include a plurality of sub-line segments, and the first block-shaped grid pattern formed by the plurality of sub-line segments may be set in the area where the first sub-region 600-1 is located. The second line segment in the second data fan-out line 702 may include a plurality of sub-line segments, and the second block-shaped grid pattern formed by the plurality of sub-line segments may be set in the area where the second sub-region 600-2 is located. The second line segment in the third data fan-out line 703 may include a plurality of sub-line segments, and the third block-shaped grid pattern formed by the plurality of sub-line segments may be set in the area where the third sub-region 600-3 is located. The second line segment in the fourth data fan-out line 704 may include a plurality of sub-line segments, and the fourth block-shaped grid pattern formed by the plurality of sub-line segments may be set in the area where the fourth sub-region 600-4 is located. In an exemplary embodiment, the first line segment of at least one data fan-out line may include a plurality of sub-line segments, and the plurality of sub-line segments form a strip-shaped grid pattern.

[0226] In an exemplary embodiment, in an overlapping region of the i-th block grid pattern and the i-th data line, a sub-line segment in the i-th block grid pattern is connected to the i-th data line through at least one via K. In an exemplary embodiment, a sub-line segment in the i-th block grid pattern may be connected to the i-th data line through a plurality of vias to improve connection reliability.

[0227] In this exemplary embodiment, the film layer structures of the data lines, data fan-out lines and lead-out lines may be similar to those of the aforementioned exemplary embodiments, and will not be described in detail here.

[0228] The exemplary embodiments of the present disclosure can achieve the technical effects of the aforementioned embodiments, including effectively reducing the width of the lower frame, effectively avoiding the dimensional deviation of the two film layers, effectively improving the display uniformity and display quality, reducing the resistance difference, and reducing the reflective optical difference of the data fan-out line. In addition, the present disclosure improves the connection reliability by setting a plurality of vias in the display area so that the data fan-out line is connected to the data line through a plurality of vias. When a via is set in the lead area, display problems may occur due to the possibility of failure of the hole connection due to corrosion or static electricity. The present disclosure enhances the stability and reliability of the via connection and improves the display quality by setting a data fan-out line with a grid pattern, and the grid pattern is connected to the data line through a plurality of vias in the display area.

[0229] Fig. 22 2 is a schematic diagram of the structure of another lead-out line and a data fan-out line according to an exemplary embodiment of the present disclosure. Fig.23 for Fig. 22 A magnified view of the C6 region in the middle. Fig. 22 and Fig.23 As shown, the structure of the data fan-out line in this exemplary embodiment is similar to Fig.21 and Fig. 20 The structures of the data fan-out lines in the illustrated embodiments are basically similar, except that the fourth block grid pattern in the fourth data fan-out line 704 is connected to the first data line DA1 through a plurality of vias, the third block grid pattern in the third data fan-out line 703 is connected to the second data line DA2 through a plurality of vias, the second block grid pattern in the second data fan-out line 702 is connected to the third data line DA3 through a plurality of vias, and the first block grid pattern in the first data fan-out line 701 is connected to the fourth data line DA4 through a plurality of vias.

[0230] The exemplary embodiments of the present disclosure can achieve the technical effects of the aforementioned embodiments, including effectively reducing the width of the lower frame, effectively avoiding the size deviation of the two film layers, effectively improving the display uniformity and display quality, reducing the resistance difference, reducing the reflective optical difference of the data fan-out line, enhancing the stability and reliability of the via connection, and improving the display quality.

[0231] Fig.24 2 is a schematic diagram of the structure of another lead-out line and a data fan-out line according to an exemplary embodiment of the present disclosure. Fig.25 for Fig.24 A magnified view of the C7 region in the middle. Fig.24 and Fig.25As shown, the multiple data lines, data fan-out lines in the display area 100 and the multiple lead lines in the lead area 501 can be symmetrically arranged relative to the center line O. The following is an example in which the left side of the display substrate includes 8 (N=8) data lines, 4 data fan-out lines and 8 lead lines.

[0232] In an exemplary embodiment, the arrangement of the 8 data lines on the left side of the display area and the 8 lead lines on the left side of the lead area can be similar to the aforementioned embodiment, and the multiple lead lines in the first lead group can be connected to the multiple data lines in the first data line group through multiple data fan-out lines, and the multiple lead lines in the second lead group can be directly connected to the multiple data lines in the second data line group.

[0233] In an exemplary embodiment, a plurality of data fan-out lines may be connected correspondingly to a plurality of data lines in the first data line group within the display area.

[0234] In an exemplary embodiment, the i-th data fan-out line may include a first line segment and a second line segment connected to each other, the first end of the first line segment is located near the edge B of the display area and connected to the i-th lead line, the second end of the first line segment is connected to the first end of the second line segment after extending in a direction away from the lead area, and the second end of the second line segment is connected to the i-th data line through a via after extending along the second direction D2 or the reverse direction of the second direction D2.

[0235] In an exemplary embodiment, the distances between the plurality of vias connecting the data fan-out lines and the edge B of the display area are different, that is, the plurality of vias are not in the same pixel row.

[0236] In this exemplary embodiment, the film layer structures of the data lines, data fan-out lines and lead-out lines may be similar to those of the aforementioned exemplary embodiments, and will not be described in detail here.

[0237] The exemplary embodiments of the present disclosure can achieve the technical effects of the aforementioned embodiments, including effectively reducing the width of the lower frame, effectively avoiding the size deviation of the two film layers, and effectively improving the display uniformity and display quality. In addition, the present disclosure provides vias in the display area so that the data fan-out line is connected to the data line through the vias in the display area, thereby reducing the length of the data fan-out line, which is beneficial to reducing the space occupied by the data fan-out line and reducing the difficulty of wiring design.

[0238] Fig.26 Schematic diagram of another structure of a lead-out line and a data fan-out line according to an exemplary embodiment of the present disclosure. Fig.24 A magnified view of the C7 region in the middle. Fig.26 As shown, the structure of the lead-out line and the data fan-out line of this exemplary embodiment is similar to Fig.25The structures of the embodiments shown are similar, except that the fourth data fan-out line 704 is connected to the first data line DA1 through a via, the third data fan-out line 703 is connected to the second data line DA2 through a via, the second data fan-out line 702 is connected to the third data line DA3 through a via, and the first data fan-out line 701 is connected to the fourth data line DA4 through a via.

[0239] In an exemplary embodiment, the distances between the plurality of vias connecting the data fan-out lines and the edge B of the display area are different, that is, the plurality of vias are not in the same pixel row.

[0240] In an exemplary embodiment, the extension lengths of the plurality of data fan-out lines may be substantially the same.

[0241] The exemplary embodiments of the present disclosure can achieve the technical effects of the aforementioned embodiments, including effectively reducing the width of the lower frame, effectively avoiding the size deviation of the two film layers, effectively improving the display uniformity and display quality, reducing the length of the data fan-out line, and helping to reduce the difficulty of wiring design. In addition, the present disclosure sets the extension lengths of the data fan-out lines to be basically similar, so that the resistances of the multiple data fan-out lines are basically similar, and the resistance voltage drop difference of the multiple data fan-out lines is very small, which can achieve a more uniform screen display and improve the display quality.

[0242] The exemplary embodiment of the present disclosure also provides a method for preparing a display substrate. In an exemplary embodiment, the display substrate includes a display area and a binding area located on one side of the display area, and the binding area includes at least a lead area; the preparation method may include:

[0243] A plurality of data lines and a plurality of data fan-out lines are formed in the display area, and a plurality of lead-out lines are formed in the lead area, wherein the orthographic projections of the plurality of data lines and the plurality of data fan-out lines on the display substrate plane at least partially overlap; at least one lead-out line is connected to the data line through the data fan-out line; and in the lead area, the orthographic projection of any lead-out line on the display substrate plane has no overlapping area with the orthographic projections of other lead-out lines on the display substrate plane.

[0244] The exemplary embodiments of the present disclosure further provide a display device, including the display substrate of the aforementioned embodiment. The display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, an advertising panel, a watch phone, an e-book portable multimedia player, or a display screen of various Internet of Things products. In an exemplary embodiment, the display device may be a wearable display device that can be worn on a human body in some way, such as a smart watch, a smart bracelet, etc.

[0245] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures can refer to the general design. In the absence of conflict, the embodiments of this disclosure, that is, the features in the embodiments, can be combined with each other to obtain new embodiments.

[0246] Those skilled in the art should understand that the technical solutions of the present disclosure may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present disclosure, and all should be included in the scope of the claims of the present disclosure.

Claims

1. A display substrate, comprising a display area and a binding area located on one side of the display area, wherein the binding area at least comprises a lead area; the display area comprises a plurality of data lines and a plurality of data fan-out lines, the lead area comprises a plurality of lead lines, and the orthographic projections of the plurality of data lines and the plurality of data fan-out lines on the plane of the display substrate at least partially overlap; at least one lead line is connected to the data line through the data fan-out line; in the lead area, the orthographic projection of any lead line on the plane of the display substrate has no overlapping area with the orthographic projections of other lead lines on the plane of the display substrate; in, At least one data fan-out line includes a first line segment, a second line segment and a third line segment; the first end of the first line segment is connected to the lead line, and the second end of the first line segment is connected to the first end of the second line segment after extending in a direction away from the lead area; the second end of the second line segment is connected to the first end of the third line segment after extending along a second direction or a direction opposite to the second direction; the second end of the third line segment is connected to the data line through a via after extending in a direction close to the lead area; the second direction intersects with the first direction, and the first direction is parallel to the data line; wherein the second line segment includes a plurality of sub-line segments, the plurality of sub-line segments are interwoven to form a plurality of grid patterns, and the plurality of grid patterns are repeated and continuously arranged in the first direction and / or the second direction.

2. The display substrate according to claim 1, wherein: At least one lead-out line is directly connected to the data line.

3. The display substrate according to claim 1, wherein: The number of the data lines is greater than the number of the data fan-out lines.

4. The display substrate according to claim 3, wherein: The third line segment includes an extension segment and a connection segment; the first end of the extension segment is located in the display area and is connected to the second end of the second line segment; the second end of the extension segment extends to the edge of the display area in the direction close to the lead area and is connected to the first end of the connection segment; the second end of the connection segment extends in the direction away from the display area and is connected to the data line extending to the lead area through a via; the edge of the display area is the edge of the display area close to the lead area.

5. The display substrate according to claim 4, wherein: A plurality of vias connecting the data fan-out lines to the data lines are at the same distance from the edge of the display area.

6. The display substrate according to claim 4, wherein: The first line segment is parallel to the first direction, and an extended segment of the third line segment is parallel to the first direction.

7. The display substrate according to claim 6, wherein: The spacing between adjacent first line segments is the same as the spacing between adjacent data lines, and the spacing between extended segments of adjacent third line segments is the same as the spacing between adjacent data lines.

8. The display substrate according to claim 4, wherein: There is a first angle between the first line segment and the first direction, and / or there is a second angle between the extended segment of the third line segment and the first direction, the first angle is 20︒ to 70︒, and the second angle is 20︒ to 70︒.

9. The display substrate according to claim 4, wherein: The first line segment includes a first straight line segment and a first oblique line segment; the first end of the first straight line segment is connected to the lead line, and the second end of the first straight line segment is connected to the first end of the first oblique line segment after extending in a direction away from the lead area; the first oblique line segment is connected to the first end of the second line segment after extending in a direction away from the lead area; the first oblique line segment has a first angle with the first direction, the first angle is 20︒ to 70︒, and the second end of the first straight line segment is at a first distance from the edge of the display area; and / or the extended section of the third line segment includes a third oblique line segment and a third straight line segment; the first end of the third oblique line segment is connected to the second end of the second line segment, the second end of the third oblique line segment is connected to the first end of the third straight line segment after extending in a direction close to the lead area, and the second end of the third straight line segment is connected to the first end of the connecting section after extending in a direction close to the lead area to the edge of the display area; the third oblique line segment has a second angle with the first direction, the second angle is 20︒ to 70︒, and the first end of the third straight line segment is at a second distance from the edge of the display area.

10. The display substrate according to claim 1, wherein: The widths of the plurality of lead lines in the lead area are the same, and the spacings between adjacent lead lines are the same; the width and spacing are dimensions in a second direction, the second direction intersects with the first direction, and the first direction is parallel to the data line.

11. The display substrate according to claim 1, wherein: In a plane parallel to the display substrate, the display substrate has a center line, the center line extends along a first direction and bisects the pixel columns of the display area, the first direction is parallel to the data lines; on one side of the center line, the plurality of data lines include a first data line group and a second data line group, the plurality of lead lines include a first lead line group and a second lead line group; the first data line group includes a first data line, a second data line, ..., an Mth data line sequentially arranged along the second direction, the second data line group is arranged on one side of the first data line group in the second direction, the second data line group includes an (M+1)th data line, an (M+2)th data line, an (M+3)th data line, an (M+4)th data line, and an (M+5)th data line. +2)th data line, ..., Nth data line, the second direction intersects with the first direction; the first lead group includes a first lead line, a second lead line, ..., an Mth lead line arranged in sequence along the opposite direction of the second direction, the second lead group includes a (M+1)th lead line, a (M+2)th lead line, ..., an Nth lead line arranged in sequence along the second direction, the lead lines of the first lead group and the lead lines of the second lead group are arranged alternately; M, N are positive integers greater than 2, and M is less than N; the lead lines in the first lead group are connected to the data lines in the first data line group through the data fan-out lines, and the lead lines in the second lead group are directly connected to the data lines in the second data line group.

12. The display substrate according to any one of claims 1 to 11, wherein: In a plane perpendicular to the display substrate, the display substrate includes a first conductive layer, a second conductive layer and a third conductive layer, an insulating layer is arranged between the first conductive layer and the second conductive layer, and between the second conductive layer and the third conductive layer; the data line and the data fan-out line are arranged in different conductive layers.

13. The display substrate according to claim 12, wherein: The data fan-out lines include odd data fan-out lines and even data fan-out lines, the odd data fan-out lines are connected to the data lines of odd columns in the first data line group, and the even data fan-out lines are connected to the data lines of even columns in the first data line group; the odd data fan-out lines and the even data fan-out lines are arranged in different conductive layers.

14. The display substrate according to claim 13, wherein: The lead-out lines include odd lead-out lines and even lead-out lines; the odd lead-out lines are connected to the data lines of the odd columns in the first data line group through the odd data fan-out lines, or are directly connected to the data lines of the odd columns in the second data line group; the even lead-out lines are connected to the data lines of the even columns in the first data line group through the even data fan-out lines, or are directly connected to the data lines of the even columns in the second data line group; the odd lead-out lines and the odd data fan-out lines are arranged on the same layer and are an integrated structure connected to each other, and the even lead-out lines and the even data fan-out lines are arranged on the same layer and are an integrated structure connected to each other.

15. The display substrate according to claim 13, wherein: The odd data fan-out lines are arranged in the first conductive layer, the even data fan-out lines are arranged in the second conductive layer, and the data lines are arranged in the third conductive layer; or, the even data fan-out lines are arranged in the first conductive layer, the odd data fan-out lines are arranged in the second conductive layer, and the data lines are arranged in the third conductive layer.

16. The display substrate according to claim 15, wherein: The material of the first conductive layer is the same as that of the second conductive layer.

17. A display substrate, comprising a display area and a binding area located on one side of the display area, the binding area at least comprising a lead area; the display area comprises a plurality of data lines and a plurality of data fan-out lines, the lead area comprises a plurality of lead lines, and the orthographic projections of the plurality of data lines and the plurality of data fan-out lines on the plane of the display substrate at least partially overlap; at least one lead line is connected to the data line through the data fan-out line; in the lead area, the orthographic projection of any lead line on the plane of the display substrate has no overlapping area with the orthographic projections of other lead lines on the plane of the display substrate; in, At least one data fan-out line includes a first line segment and a second line segment; the first end of the first line segment is connected to the lead-out line, and the second end of the first line segment is connected to the second line segment after extending in a direction away from the lead-out area; the second line segment includes a plurality of sub-line segments, and the plurality of sub-line segments are interwoven to form a plurality of grid patterns, and the plurality of grid patterns are repeated and continuously arranged in a first direction and / or a second direction, and at least one sub-line segment is connected to the data line through a via; the second direction intersects with the first direction, and the first direction is parallel to the data line.

18. The display substrate according to claim 17, wherein: At least one lead-out line is directly connected to the data line.

19. The display substrate according to claim 17, wherein: The number of the data lines is greater than the number of the data fan-out lines.

20. The display substrate according to claim 17, wherein: The widths of the plurality of lead lines in the lead area are the same, and the spacings between adjacent lead lines are the same; the width and spacing are dimensions in a second direction, the second direction intersects with the first direction, and the first direction is parallel to the data line.

21. The display substrate according to claim 17, wherein: In a plane parallel to the display substrate, the display substrate has a center line, the center line extends along a first direction and bisects the pixel columns of the display area, the first direction is parallel to the data lines; on one side of the center line, the plurality of data lines include a first data line group and a second data line group, the plurality of lead lines include a first lead line group and a second lead line group; the first data line group includes a first data line, a second data line, ..., an Mth data line sequentially arranged along the second direction, the second data line group is arranged on one side of the first data line group in the second direction, the second data line group includes an (M+1)th data line, an (M+2)th data line, an (M+3)th data line, an (M+4)th data line, and an (M+5)th data line. +2)th data line, ..., Nth data line, the second direction intersects with the first direction; the first lead group includes a first lead line, a second lead line, ..., an Mth lead line arranged in sequence along the opposite direction of the second direction, the second lead group includes a (M+1)th lead line, a (M+2)th lead line, ..., an Nth lead line arranged in sequence along the second direction, the lead lines of the first lead group and the lead lines of the second lead group are arranged alternately; M, N are positive integers greater than 2, and M is less than N; the lead lines in the first lead group are connected to the data lines in the first data line group through the data fan-out lines, and the lead lines in the second lead group are directly connected to the data lines in the second data line group.

22. The display substrate according to any one of claims 17 to 21, wherein: In a plane perpendicular to the display substrate, the display substrate includes a first conductive layer, a second conductive layer and a third conductive layer, an insulating layer is arranged between the first conductive layer and the second conductive layer, and between the second conductive layer and the third conductive layer; the data line and the data fan-out line are arranged in different conductive layers.

23. The display substrate according to claim 22, wherein: The data fan-out lines include odd data fan-out lines and even data fan-out lines, the odd data fan-out lines are connected to the data lines of odd columns in the first data line group, and the even data fan-out lines are connected to the data lines of even columns in the first data line group; the odd data fan-out lines and the even data fan-out lines are arranged in different conductive layers.

24. The display substrate according to claim 23, wherein: The lead-out lines include odd lead-out lines and even lead-out lines; the odd lead-out lines are connected to the data lines of the odd columns in the first data line group through the odd data fan-out lines, or are directly connected to the data lines of the odd columns in the second data line group; the even lead-out lines are connected to the data lines of the even columns in the first data line group through the even data fan-out lines, or are directly connected to the data lines of the even columns in the second data line group; the odd lead-out lines and the odd data fan-out lines are arranged on the same layer and are an integrated structure connected to each other, and the even lead-out lines and the even data fan-out lines are arranged on the same layer and are an integrated structure connected to each other.

25. The display substrate according to claim 23, wherein: The odd data fan-out lines are arranged in the first conductive layer, the even data fan-out lines are arranged in the second conductive layer, and the data lines are arranged in the third conductive layer; or, the even data fan-out lines are arranged in the first conductive layer, the odd data fan-out lines are arranged in the second conductive layer, and the data lines are arranged in the third conductive layer.

26. The display substrate according to claim 25, wherein: The material of the first conductive layer is the same as that of the second conductive layer.

27. A display device comprising the display substrate according to any one of claims 1 to 26.

28. A method for preparing a display substrate, the display substrate comprising a display area and a binding area located on one side of the display area, the binding area at least comprising a lead area; the method comprising: A plurality of data lines and a plurality of data fan-out lines are formed in the display area, and a plurality of lead-out lines are formed in the lead-out area, wherein the orthographic projections of the plurality of data lines and the plurality of data fan-out lines on the display substrate plane at least partially overlap; at least one lead-out line is connected to the data line through the data fan-out line; in the lead-out area, the orthographic projection of any lead-out line on the display substrate plane has no overlapping area with the orthographic projections of other lead-out lines on the display substrate plane; in, At least one data fan-out line includes a first line segment, a second line segment and a third line segment; the first end of the first line segment is connected to the lead-out line, and the second end of the first line segment is connected to the first end of the second line segment after extending in a direction away from the lead-out area; the second end of the second line segment is connected to the first end of the third line segment after extending along a second direction or in a direction opposite to the second direction; the second end of the third line segment is connected to the data line through a via after extending in a direction close to the lead-out area; the second direction intersects with the first direction, and the first direction is parallel to the data line; wherein the second line segment includes a plurality of sub-line segments, the plurality of sub-line segments are interwoven to form a plurality of grid patterns, and the plurality of grid patterns are repeatedly and continuously arranged in the first direction and / or the second direction; or, At least one data fan-out line includes a first line segment and a second line segment; the first end of the first line segment is connected to the lead-out line, and the second end of the first line segment is connected to the second line segment after extending in a direction away from the lead-out area; the second line segment includes a plurality of sub-line segments, and the plurality of sub-line segments are interwoven to form a plurality of grid patterns, and the plurality of grid patterns are repeated and continuously arranged in a first direction and / or a second direction, and at least one sub-line segment is connected to the data line through a via; the second direction intersects with the first direction, and the first direction is parallel to the data line.

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