Fan speed signal processing method, device, electronic equipment and storage medium

Abstract

The present disclosure provides a method, apparatus, electronic device and storage medium for processing a fan rotation speed signal. The method includes obtaining an initial rotation speed signal of the fan; performing cyclic value-taking processing on the initial rotation speed signal to obtain a target rotation speed signal; and determining the fan rotation speed based on the target rotation speed signal. Through the present disclosure, the processing effect of the rotation speed signal can be effectively improved, and the accuracy and objectivity of determining the fan rotation speed can be effectively improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of nuclear power instrumentation and control, and particularly to a method, device, electronic device, and storage medium for processing fan speed signals. Background Art

[0002] As an important rotating equipment of a high-temperature gas-cooled reactor, the monitoring of the operating state of the main helium fan is related to the safe and stable operation of the entire unit.

[0003] In the related art, a distributed control system (DCS) is used to directly obtain the speed signal from the electromagnetic bearing control cabinet and determine the fan speed.

[0004] In this way, since the speed signal obtained by the electromagnetic bearing control cabinet is prone to jitter, the processing effect of the speed signal is prone to be poor, and the accuracy of the obtained fan speed is low. Summary of the Invention

[0005] The present disclosure aims to at least solve one of the technical problems in the related art to some extent.

[0006] To this end, the purpose of the present disclosure is to propose a method, device, electronic device, and storage medium for processing fan speed signals, which can effectively improve the processing effect of the speed signal and effectively improve the accuracy and objectivity of the determination of the fan speed.

[0007] The method for processing fan speed signals proposed in the first aspect embodiment of the present disclosure includes: obtaining an initial speed signal of the fan; performing cyclic value-taking processing on the initial speed signal to obtain a target speed signal; and determining the fan speed based on the target speed signal.

[0008] The method for processing fan speed signals proposed in the first aspect embodiment of the present disclosure obtains the initial speed signal of the fan, then performs cyclic value-taking processing on the initial speed signal to obtain a target speed signal, and then determines the fan speed based on the target speed signal. Since the initial speed signal is processed in a cyclic value-taking manner to obtain the target speed signal, the processing effect of the speed signal can be effectively improved. Since the fan speed is determined based on the target speed signal, the accuracy and objectivity of the determination of the fan speed can be effectively improved.

[0009] The device for processing fan speed signals proposed in the second aspect embodiment of the present disclosure includes: an obtaining module, configured to obtain an initial speed signal of the fan; a first processing module, configured to perform cyclic value-taking processing on the initial speed signal to obtain a target speed signal; and a first determining module, configured to determine the fan speed based on the target speed signal.

[0010] The fan speed signal processing device proposed in the second aspect of the present disclosure obtains the initial fan speed signal, then performs cyclic value-taking processing on the initial fan speed signal to obtain the target speed signal, and then determines the fan speed based on the target speed signal. Since the cyclic value-taking method is used to process the initial fan speed signal to obtain the target speed signal, the processing effect of the speed signal can be effectively improved. Since the fan speed is determined based on the target speed signal, the accuracy and objectivity of the fan speed determination can be effectively improved.

[0011] In the third aspect of the present disclosure, an electronic device is provided, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the fan speed signal processing method of the first aspect embodiment of the present disclosure.

[0012] In the fourth aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is proposed, and the computer instructions are used to cause the computer to execute the fan speed signal processing method of the first aspect embodiment of the present disclosure.

[0013] In the fifth aspect of the present disclosure, a computer program product is provided, including a computer program, and the computer program realizes the fan speed signal processing method of the first aspect embodiment of the present disclosure when executed by a processor.

[0014] The additional aspects and advantages of the present disclosure will be partly given in the following description, partly will become obvious from the following description, or will be understood through the practice of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above and / or additional aspects and advantages of the present disclosure will become obvious and easy to understand from the following description of the embodiments in conjunction with the drawings, where:

[0016] Figure 1 is a flowchart of the fan speed signal processing method proposed in an embodiment of the present disclosure;

[0017] Figure 2 is a flowchart of the fan speed signal processing method proposed in another embodiment of the present disclosure;

[0018] Figure 3 is a flowchart of the fan speed signal processing method proposed in another embodiment of the present disclosure;

[0019] Figure 4 is a schematic diagram of an arithmetic operation algorithm block proposed in another embodiment of the present disclosure;

[0020] Figure 5It is a schematic flowchart of a method for processing a fan speed signal proposed in another embodiment of the present disclosure;

[0021] Figure 6 It is a schematic diagram of a selection algorithm block proposed in another embodiment of the present disclosure;

[0022] Figure 7 It is a schematic diagram of a processing framework for a fan speed signal proposed in another embodiment of the present disclosure;

[0023] Figure 8 It is a schematic structural diagram of a device for processing a fan speed signal proposed in an embodiment of the present disclosure;

[0024] Figure 9 It is a schematic structural diagram of a device for processing a fan speed signal proposed in another embodiment of the present disclosure;

[0025] Figure 10 It shows a block diagram of an exemplary electronic device suitable for implementing the embodiments of the present disclosure. Detailed Embodiments

[0026] The embodiments of the present disclosure will be described in detail below. The examples of the embodiments are shown in the drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary only for explaining the present disclosure and should not be construed as a limitation of the present disclosure. On the contrary, the embodiments of the present disclosure include all variations, modifications, and equivalents falling within the spirit and scope of the appended claims.

[0027] Figure 1 It is a schematic flowchart of a method for processing a fan speed signal proposed in an embodiment of the present disclosure.

[0028] The execution subject of the method for processing a fan speed signal in this embodiment is a device for processing a fan speed signal, and this device can be implemented in software and / or hardware.

[0029] The method for processing a fan speed signal in this embodiment can be applied to a Distributed Control System (DCS). The distributed control system is a new generation of instrument control system based on microprocessors, adopting the design principle of decentralized control functions, centralized display and operation, and taking into account both decentralized autonomy and comprehensive coordination. This distributed control system can control the relevant states of the main helium fan through decentralized control functions such as signal input, transformation, operation, and output, and there is no limitation on this.

[0030] As Figure 1 shown, the method for processing a fan speed signal includes:

[0031] S101: Obtain the initial speed signal of the fan.

[0032] Among them, the initial rotational speed signal is the signal information used to record the rotational speed of the main helium blower. The initial rotational speed signal can be, for example, an electromagnetic signal, a frequency signal, a voltage signal, etc., or any other possible signal, and there is no limitation on this.

[0033] In the embodiments of the present disclosure, the rotational speed-related signal can be directly obtained from the main helium blower, or a certain tool can also be used to obtain the rotational speed-related signal. For example, for the electromagnetic bearing control cabinet, the initial rotational speed signal sent by the electromagnetic bearing control cabinet is received. Or, any other possible implementation manner can also be used to obtain the initial rotational speed signal of the blower, and there is no limitation on this.

[0034] That is to say, a specific application scenario of the embodiments of the present disclosure can be, for example, using a distributed control system to receive the initial rotational speed signal sent by the electromagnetic bearing control cabinet of the main helium blower. The following description in the embodiments of the present disclosure will take this application scenario as an example for specific explanation. Of course, the method for processing the rotational speed signal of the blower described in the embodiments of the present disclosure can also be applied to any other possible scenarios for processing the rotational speed signal of the blower, and there is no limitation on this.

[0035] After obtaining the initial rotational speed signal of the blower in the embodiments of the present disclosure, subsequent methods for processing the rotational speed signal of the blower can be executed based on the initial rotational speed signal. For specific details, please refer to the subsequent embodiments.

[0036] S102: Perform cyclic value-taking processing on the initial rotational speed signal to obtain a target rotational speed signal.

[0037] Among them, the target rotational speed signal is the rotational speed signal obtained by processing the initial rotational speed signal. The target rotational speed signal can be used to determine the rotational speed of the main helium blower, and there is no limitation on this.

[0038] Among them, the cyclic value-taking processing is a processing method for the initial rotational speed signal. A certain cyclic period can be set, and based on this cyclic period, cyclic value-taking and related processing are performed on the initial rotational speed signal to obtain the target rotational speed signal.

[0039] Since the main helium blower is prone to rotational speed jumps during operation, for example, jumping between 6 revolutions per second and 7 revolutions per second. When determining the rotational speed of the blower, the rotational speed jump is likely to result in insufficient accuracy in determining the final rotational speed of the blower, thereby affecting the misjudgment of the rotational speed of the blower by relevant staff. Therefore, performing cyclic value-taking processing on the initial rotational speed signal can effectively avoid the influence of rotational speed jumps and improve the accuracy and objectivity of determining the rotational speed of the blower.

[0040] In some embodiments of the present disclosure, the initial rotational speed signal can be cyclically value-taken multiple times, and based on the multiple value-taking results obtained from the multiple value-takings, the target rotational speed signal is determined.

[0041] In some other embodiments, the initial rotational speed signal may also be sampled, and the sampling results with relatively large changes between adjacent samplings may be discarded. Then, the target rotational speed signal is determined based on the sampling results and the time taken for sampling.

[0042] Of course, the present disclosure may also use any other possible implementation to perform cyclic sampling on the initial rotational speed signal. For example, an initial rotational speed signal processing model may be built, and deep learning methods may be used to process the initial rotational speed signal, etc. There is no limitation in this regard.

[0043] S103: Determine the fan rotational speed based on the target rotational speed signal.

[0044] In the embodiments of the present disclosure, the target rotational speed signal can be used to determine the fan rotational speed. The target rotational speed signal can be directly used as the fan rotational speed, or alternatively, the target rotational speed signal can be processed accordingly to obtain the fan rotational speed, or still alternatively, any other possible implementation can be used to determine the fan rotational speed based on the target rotational speed signal. There is no limitation in this regard.

[0045] For example, if the target rotational speed signal is a signal representing "the rotational speed of the fan per second", it can be processed to represent "the rotational speed of the fan per minute", and this "rotational speed of the fan per minute" can be used as the fan rotational speed.

[0046] Of course, a signal processing system can also be built, the target rotational speed signal is input, and the signal processing system processes it to output the fan rotational speed data. There is no limitation in this regard.

[0047] In this embodiment, by obtaining the initial rotational speed signal of the fan, then performing cyclic sampling on the initial rotational speed signal to obtain the target rotational speed signal, and then determining the fan rotational speed based on the target rotational speed signal. Since the initial rotational speed signal is processed in a cyclic sampling manner to obtain the target rotational speed signal, the processing effect of the rotational speed signal can be effectively improved. Since the fan rotational speed is determined based on the target rotational speed signal, the accuracy and objectivity of determining the fan rotational speed can be effectively improved.

[0048] Figure 2 It is a schematic flowchart of a method for processing a fan rotational speed signal proposed in another embodiment of the present disclosure.

[0049] As Figure 2 shown, the method for processing a fan rotational speed signal includes:

[0050] S201: Obtain the initial rotational speed signal of the fan.

[0051] For the description of S201, reference can be specifically made to the above embodiments, and details will not be repeated here.

[0052] S202: Determine the sampling period, where the sampling period includes: the first sampling period and the second sampling period.

[0053] Among them, the sampling period is the period information used to obtain the initial rotational speed signal of the fan. This sampling period includes the first sampling period and the second sampling period.

[0054] Among them, the first sampling period is the period information used to process the initial rotational speed signal, and the second sampling period is the period information used to cyclically sample the initial rotational speed signal.

[0055] For example, the first sampling period can be 8 seconds, and the second sampling period can be 1 second. It can be expressed as sampling once every 1 second within an 8 - second period, and a total of 7 initial rotational speed signals can be sampled, obtaining 7 sampling results of the initial rotational speed signal.

[0056] Optionally, in some embodiments, a pulse signal generator algorithm block and a delay algorithm block can be set in the distributed control system (DCS). Then, according to the pulse signal generator algorithm block, the first sampling period is determined, and according to the delay algorithm block, the second sampling period is determined. Also, the first sampling period and the second sampling period are jointly used as the sampling period. Since the first sampling period is determined according to the pulse signal generator algorithm block and the second sampling period is determined according to the delay algorithm block, the first sampling period and the second sampling period can be accurately determined, facilitating the setting of the sampling period, effectively improving the accuracy of determining the sampling period, and thus being able to accurately and stably sample the initial rotational speed signal.

[0057] Among them, the pulse signal generator algorithm block is the algorithm module corresponding to a generator that can emit a pulse signal with a certain period frequency. The pulse signal generator algorithm block can output a high level for a specified time and output a low level for a specified time to form a periodic square - wave signal, etc., without limitation in this regard.

[0058] For example, the first sampling period can be set to 8 seconds, then the pulse signal generator algorithm block triggers a periodic square - wave signal with a high level for 8 seconds and a low level for 1 second.

[0059] Among them, the delay algorithm block is an algorithm module used to periodically output a high level.

[0060] In the embodiments of the present disclosure, multiple delay algorithm blocks are supported to be set to form a delay algorithm block group for facilitating the acquisition of the initial rotational speed signal of the fan according to the second sampling period.

[0061] For example, delay algorithm blocks 1, 2, 3, 4, 5, 6, and 7 can be set. When the pulse signal generator algorithm block starts to output a high level, it is recorded as the 0th second of delay. After a 1-second delay, the output of delay algorithm block 1 is 1 and remains so for 7 seconds, while the outputs of delay algorithm blocks 2 to 7 are 0. After a 2-second delay, the outputs of delay algorithm blocks 1 and 2 are 1 and the outputs of the other delay algorithm blocks are 0, and so on. Then, the first value-taking period can be determined to be 8 seconds and the second value-taking period to be 1 second.

[0062] Certainly, in the embodiments of the present disclosure, multiple methods are also supported for determining the first value-taking period and the second value-taking period. For example, a first value-taking period control program and a second value-taking period control program can be designed through a single-chip microcomputer chip, or a clock program can be built to determine the first value-taking period and the second value-taking period, and there is no limitation in this regard.

[0063] S203: Perform cyclic value-taking processing on the initial rotational speed signal to obtain a target rotational speed signal.

[0064] S204: Determine the fan rotational speed based on the target rotational speed signal.

[0065] For the descriptions of S203 - S204, specific reference can be made to the above embodiments and will not be elaborated here.

[0066] In this embodiment, since the initial rotational speed signal is processed by means of cyclic value-taking to obtain the target rotational speed signal, the processing effect of the rotational speed signal can be effectively improved. Since the fan rotational speed is determined based on the target rotational speed signal, the accuracy and objectivity of determining the fan rotational speed can be effectively improved. Since the value-taking period is divided into a first value-taking period and a second value-taking period, the usage effect of the value-taking period can be effectively improved. By setting multiple value-taking periods, the initial rotational speed signal can be processed by means of cyclic value-taking according to the value-taking period, improving the accuracy of value-taking. Since the first value-taking period is determined according to the pulse signal generator algorithm block and the second value-taking period is determined according to the delay algorithm block, the first value-taking period and the second value-taking period can be accurately determined, facilitating the setting of the value-taking period and effectively improving the accuracy of determining the value-taking period, and thus the initial rotational speed signal can be accurately and stably value-taken.

[0067] Figure 3 It is a flowchart of a method for processing a fan rotational speed signal proposed in another embodiment of the present disclosure.

[0068] As Figure 3 shown, the method for processing a fan rotational speed signal includes:

[0069] S301: Obtain the initial rotational speed signal of the fan.

[0070] S302: Determine the value-taking period, where the value-taking period includes: a first value-taking period and a second value-taking period.

[0071] For the descriptions of S301 - S302, please refer to the above embodiments for details and will not be elaborated here.

[0072] S303: Take values from the initial rotational speed signal according to the selection algorithm block to obtain a first rotational speed signal.

[0073] Among them, the selection algorithm block is an algorithm module that takes values from the initial rotational speed signal according to the second value-taking period. The selection algorithm block can be used to output the initial rotational speed signal with values taken, and use the output initial rotational speed signal with values taken as the first rotational speed signal.

[0074] In the embodiments of the present disclosure, the output of the delay algorithm block can be determined to take values from the initial rotational speed signal to obtain a first rotational speed signal.

[0075] In the embodiments of the present disclosure, the number of selection algorithm blocks can be set to multiple. The selection algorithm block can receive the initial rotational speed signal and take values from the initial rotational speed signal when specific conditions are met to obtain a first rotational speed signal.

[0076] In some embodiments, multiple selection algorithm blocks can be used to form an initial rotational speed signal value-taking model to facilitate taking values from the initial rotational speed signal. Or, an intelligent value-taking big data model can be built to facilitate taking values from the initial rotational speed signal. Or, any other possible implementation manner can also be used to take values from the initial rotational speed signal to obtain a first rotational speed signal, and this is not limited.

[0077] S304: Process the first rotational speed signal according to the arithmetic operation algorithm block to obtain a target rotational speed signal.

[0078] Among them, the arithmetic operation algorithm block is an algorithm module that performs arithmetic operations on the first rotational speed signal. The arithmetic operation algorithm block can include various types such as an addition algorithm block, a division algorithm block, and a multiplication algorithm block, and this is not limited.

[0079] In some embodiments, the arithmetic operation algorithm block can be used to form an arithmetic operation model to process the first rotational speed signal based on this arithmetic operation model to obtain a target rotational speed signal.

[0080] Optionally, the arithmetic operation algorithm block includes: an addition algorithm block, a multiplication algorithm block, and a division algorithm block. The arithmetic operation processing is to perform arithmetic operations on the first rotational speed signal according to the addition algorithm block, the division algorithm block, and the multiplication algorithm block, and use the rotational speed signal obtained after the arithmetic operation processing as the target rotational speed signal. Since the arithmetic operation processing is performed on the first rotational speed signal according to the addition algorithm block, the division algorithm block, and the multiplication algorithm block, the accuracy and objectivity of the obtained target rotational speed signal can be effectively improved, and the signal processing effect can be effectively enhanced.

[0081] Among them, the arithmetic operation algorithm block includes: an addition algorithm block, a multiplication algorithm block, and a division algorithm block. The arithmetic operation processing is a combination of arithmetic operation processing methods such as addition, multiplication, and division. That is to say, in the embodiments of the present disclosure, the obtained first rotational speed signal can be added using the addition algorithm block, multiplied using the multiplication algorithm block, and divided using the division algorithm block. Alternatively, the first rotational speed signal can also be processed using a combination of arithmetic operations such as addition, multiplication, and division, and there is no limitation in this regard.

[0082] In the embodiments of the present disclosure, within the first value-taking period, since the number of first rotational speed signals obtained through the selection algorithm block can be multiple, the corresponding addition algorithm block can be used to process the multiple obtained first rotational speed signals, and the target rotational speed signal can be obtained according to the processing of the multiplication algorithm block and the division algorithm block.

[0083] For example, as Figure 4 shown, Figure 4 is a schematic diagram of the arithmetic operation algorithm block proposed in another embodiment of the present disclosure. Among them, if 7 first rotational speed signals (first rotational speed signal 1 - first rotational speed signal 7) are obtained, the addition algorithm block can be used to perform arithmetic addition processing on the 7 first rotational speed signals, and then the division algorithm block can be used to perform arithmetic division processing to obtain the average value of the first rotational speed signal 1 - first rotational speed signal 7. Since the unit of the first rotational speed signal can be "revolutions per second", the multiplication algorithm block can be used to perform arithmetic multiplication processing, and multiply the result obtained after the division processing by 60 to change the unit to "rotational speed per minute" for easy display. After this series of processing, the target rotational speed signal is output.

[0084] Of course, in other embodiments of the present disclosure, other arbitrary possible arithmetic operation processing methods can also be used to perform arithmetic operation processing on the first rotational speed signal to obtain the target rotational speed signal, and there is no limitation in this regard.

[0085] In this embodiment, since the initial rotation speed signal is processed by means of cyclic value taking to obtain the target rotation speed signal, the processing effect of the rotation speed signal can be effectively improved. Since the fan rotation speed is determined based on the target rotation speed signal, the accuracy and objectivity of the fan rotation speed determination can be effectively improved. Since the value taking period is divided into a first value taking period and a second value taking period, the use effect of the value taking period can be effectively improved. By setting multiple value taking periods, the initial rotation speed signal can be processed by means of cyclic value taking according to the value taking period, and the accuracy of value taking can be improved. Since the initial rotation speed signal is taken according to the selection algorithm block to obtain the first rotation speed signal, and the first rotation speed signal is arithmetically processed according to the arithmetic operation algorithm block to obtain the target rotation speed signal, the selection algorithm block and the arithmetic operation algorithm block are used to process the initial rotation speed signal to obtain the target rotation speed signal, and more accurate target rotation speed information can be obtained, which is convenient for smoothing the initial rotation speed signal and enhancing the processing effect of the initial rotation speed signal. Since the first rotation speed signal is arithmetically processed according to the addition algorithm block, the division algorithm block and the multiplication algorithm block, the accuracy and objectivity of the obtained target rotation speed signal can be effectively improved, and the signal processing effect can be effectively enhanced.

[0086] Figure 5 It is a schematic flow chart of a method for processing a fan rotation speed signal proposed in another embodiment of the present disclosure.

[0087] As Figure 5 shown, the method for processing a fan rotation speed signal includes:

[0088] S501: Obtain the initial rotation speed signal of the fan.

[0089] S502: Determine the value taking period, where the value taking period includes: a first value taking period and a second value taking period.

[0090] For the descriptions of S501 - S502, reference can be specifically made to the above - mentioned embodiment, and details will not be repeated here.

[0091] S503: Perform value taking processing on the initial rotation speed signal according to the second value taking period.

[0092] In the embodiment of the present disclosure, value taking processing can be performed on the initial rotation speed signal according to the second value taking period, that is to say, within the first value taking period, the initial rotation speed signal can be taken once every other second value taking period, or any other possible implementation manner can be used to perform value taking processing on the initial rotation speed signal according to the second value taking period, and no limitation is imposed thereon.

[0093] For example, if the first value taking period is 8 seconds and the second value taking period is 1 second, then within the 8 - second period, the initial rotation speed signal is taken once every 1 second.

[0094] S504: Determine the selection condition of the selection algorithm block.

[0095] Among them, the selection condition is the condition information corresponding to the selection algorithm block when making a selection.

[0096] In the embodiments of the present disclosure, the selection condition can be a pre-set condition information for selecting the initial rotational speed signal. The state of the delay algorithm block can be set as the selection condition, so as to more conveniently process the initial rotational speed signal according to the first value-taking period and the second value-taking period in subsequent steps.

[0097] S505: Perform selection processing on the value-taking rotational speed signal according to the selection condition to obtain the first rotational speed signal.

[0098] In the embodiments of the present disclosure, it is supported to set multiple selection conditions in the selection algorithm block to face multiple value-taking situations.

[0099] Optionally, in the embodiments of the present disclosure, if the selection condition is satisfied, the value-taking rotational speed signal is used as the first rotational speed signal; if the selection condition is not satisfied, the current value-taking is maintained and waiting continues until the selection condition is satisfied to obtain the first rotational speed signal.

[0100] In the embodiments of the present disclosure, when the output of the delay algorithm block is set as the selection condition, the output of the delay algorithm block can be set to 0 and 1. By combining multiple delay algorithm blocks, the selection logic of the selection algorithm block can be obtained.

[0101] For example, as Figure 6 shown, Figure 6It is a schematic diagram of a selection algorithm block proposed in another embodiment of the present disclosure. When the number of delay algorithm blocks is 7 (delay algorithm block 1 - delay algorithm block 7) and the number of selection algorithm blocks is also 7 (selection algorithm block 1 - selection algorithm block 7), the first rotational speed signal can be determined according to the outputs of different delay algorithm blocks by activating different selection algorithm blocks according to the selection conditions. Among them, the outputs of the delay algorithm blocks are set to two types: "0" and "1". The output of delay algorithm block 1 and the output of delay algorithm block 2 are input into arithmetic AND algorithm block 1 for logical AND operation. When the operation result is 1, it is determined that selection algorithm block 1 meets the selection conditions, and selection algorithm block 1 is started to take values from the initial rotational speed signal to obtain the first rotational speed signal 1. The output of delay algorithm block 2 and the output of delay algorithm block 3 are input into arithmetic AND algorithm block 2 for logical AND operation. When the operation result is 1, it is determined that selection algorithm block 2 meets the selection conditions, and selection algorithm block 2 is started to take values from the initial rotational speed signal to obtain the first rotational speed signal 2. The value-taking is cycled in turn until the output of delay algorithm block 7 is input into arithmetic AND algorithm block 7 for logical AND operation. When the operation result is 1, it is determined that selection algorithm block 7 meets the selection conditions, and selection algorithm block 7 is started to take values from the initial rotational speed signal to obtain the first rotational speed signal 7. Thus, the first rotational speed signals 1 - 7 are obtained periodically.

[0102] S506: Process the first rotational speed signal according to the arithmetic operation algorithm block to obtain the target rotational speed signal.

[0103] For the description of S506, specific reference can be made to the above embodiments, which will not be elaborated here.

[0104] In this embodiment, since the initial rotational speed signal is processed by means of cyclic value-taking to obtain the target rotational speed signal, the processing effect of the rotational speed signal can be effectively improved. Since the fan rotational speed is determined based on the target rotational speed signal, the accuracy and objectivity of the fan rotational speed determination can be effectively improved. Since the value-taking period is divided into the first value-taking period and the second value-taking period, the use effect of the value-taking period can be effectively improved. By setting multiple value-taking periods, the initial rotational speed signal can be processed in a cyclic value-taking manner according to the value-taking period, improving the accuracy of value-taking. Since the rotational speed signal after value-taking is selected and processed according to the selection conditions of the selection algorithm block to obtain the first rotational speed signal, the stability of the selection and processing of the rotational speed signal after value-taking can be effectively improved. Since when the selection conditions are met, the rotational speed signal after value-taking is used as the first rotational speed signal, and when the selection conditions are not met, the current value-taking is maintained and waiting continues until the selection conditions are met to obtain the first rotational speed signal, the first rotational speed signal can be periodically determined according to the selection conditions, improving the accuracy of the first rotational speed signal.

[0105] In summary, as Figure 7 shown, Figure 7It is a schematic diagram of a fan speed signal processing framework proposed in another embodiment of the present disclosure. A periodic square wave signal with a high level of 8 seconds and a low level of 1 second is triggered by a pulse signal generator algorithm block. Among them, 8 seconds is used as the first value-taking period, and then the periodic square wave signal is input into delay algorithm blocks 1 - 7 simultaneously. The delay algorithm blocks contain preset delay times, and the corresponding delay times in different delay algorithm blocks are different. For example, the delay time of delay algorithm block 1 is 1 second, which means that at the time point 1 second after receiving the periodic square wave signal, the output of delay algorithm block 1 is triggered to be 1 and lasts for 7 seconds. At this time, the outputs of delay algorithm blocks 2 - 7 are 0; the delay time of delay algorithm block 2 is 2 seconds, then at the time point 2 seconds after receiving the periodic square wave signal, the output of delay algorithm block 2 is triggered to be 1. The selection condition of the selection algorithm block is set to that the output of the corresponding connected arithmetic AND algorithm block is 1. At the time point 1 second after receiving the periodic square wave signal, the output of delay algorithm block 1 and the non-value of the output of delay algorithm block 2 are input into arithmetic AND algorithm block 1. Because at this time, the output of delay algorithm block 1 is 1, the output of delay algorithm block 2 is 0, and the non-value of the output of delay algorithm block 2 is 1, after arithmetic AND processing, the output of arithmetic AND algorithm block 1 is 1, which meets the selection condition, and the selection algorithm block is triggered to select the first speed signal 1 from the initial speed signal. After 8 seconds of the first value-taking period, a total of 7 first speed signals, namely the first speed signal 1 - the first speed signal 7, can be cyclically obtained by value-taking. Also, because the unit of the first speed signal cyclically obtained from the initial speed signal is "revolutions per second", the 7 first speed signals can be added by an arithmetic addition algorithm block, and then divided by the number 7 by an arithmetic division algorithm block to obtain an average value. After that, it is multiplied by 60 by an arithmetic multiplication algorithm block to convert the unit into "revolutions per minute", and the target speed signal is output, and the target speed signal is directly used as the fan speed. Since the initial speed signal is processed by the method of cyclically taking values to obtain the target speed signal, the processing effect of the speed signal can be effectively improved. Since the fan speed is determined based on the target speed signal, the accuracy and objectivity of the fan speed determination can be effectively improved.

[0106] Figure 8 It is a schematic structural diagram of a fan speed signal processing device proposed in an embodiment of the present disclosure.

[0107] As Figure 8 shown, the fan speed signal processing device 80 includes:

[0108] An acquisition module 801, configured to acquire an initial speed signal;

[0109] A first processing module 802, configured to perform cyclic value-taking processing on the initial speed signal to obtain a target speed signal;

[0110] The first determination module 803 is configured to determine the fan speed based on the target speed signal.

[0111] In some embodiments of the present disclosure, as Figure 9 shown, Figure 9 FIG. is a schematic structural diagram of a fan speed signal processing device proposed in another embodiment of the present disclosure, which further includes:

[0112] The second determination module 804 is configured to determine the value-taking period after obtaining the initial speed signal, where the value-taking period includes: a first value-taking period and a second value-taking period.

[0113] In some embodiments of the present disclosure, as Figure 9 shown, the distributed control system DCS includes: a pulse signal generator algorithm block and a delay algorithm block, where the second determination module 804 is specifically configured to:

[0114] Determine the first value-taking period according to the pulse signal generator algorithm block;

[0115] Determine the second value-taking period according to the delay algorithm block;

[0116] Regard the first value-taking period and the second value-taking period together as the value-taking period.

[0117] In some embodiments of the present disclosure, as Figure 9 shown, the distributed control system DCS includes: a selection algorithm block and an arithmetic operation algorithm block, where the first processing module 802 is specifically configured to:

[0118] Take values from the initial speed signal according to the selection algorithm block to obtain a first speed signal.

[0119] Perform arithmetic operation processing on the first speed signal according to the arithmetic operation algorithm block to obtain the target speed signal.

[0120] In some embodiments of the present disclosure, as Figure 9 shown, the first processing module 802 is specifically configured to:

[0121] Perform value-taking processing on the initial speed signal according to the second value-taking period;

[0122] Perform selection processing on the speed signal after value-taking to obtain the first speed signal.

[0123] In some embodiments of the present disclosure, as Figure 9 shown, the first processing module 802 is specifically configured to:

[0124] Determine the selection condition of the selection algorithm block;

[0125] Selectively process the sampled rotational speed signal according to the selection conditions to obtain a first rotational speed signal.

[0126] In some embodiments of the present disclosure, as Figure 9 shown, the first processing module 802 is specifically configured to:

[0127] When the selection conditions are met, use the sampled rotational speed signal as the first rotational speed signal;

[0128] When the selection conditions are not met, maintain the current sample value and continuously wait until the selection conditions are met to obtain the first rotational speed signal.

[0129] In some embodiments of the present disclosure, as Figure 9 shown, the arithmetic operation algorithm block includes: an addition algorithm block, a division algorithm block, and a multiplication algorithm block. The first processing module 802 is specifically configured to:

[0130] Perform arithmetic operation processing on the first rotational speed signal according to the addition algorithm block, the division algorithm block, and the multiplication algorithm block;

[0131] Use the rotational speed signal obtained after the arithmetic operation processing as the target rotational speed signal.

[0132] Corresponding to the method for processing the fan rotational speed signal provided in the above Figures 1 to 7 embodiment, the present disclosure also provides a device for processing the fan rotational speed signal. Since the device for processing the fan rotational speed signal provided in the embodiments of the present disclosure corresponds to the method for processing the fan rotational speed signal provided in the above Figures 1 to 7 embodiment, the implementation manners of the method for processing the fan rotational speed signal are also applicable to the device for processing the fan rotational speed signal provided in the embodiments of the present disclosure, and will not be described in detail in the embodiments of the present disclosure.

[0133] In this embodiment, by obtaining the initial rotational speed signal of the fan, then performing cyclic sampling processing on the initial rotational speed signal to obtain the target rotational speed signal, and then determining the fan rotational speed based on the target rotational speed signal. Since the initial rotational speed signal is processed in a cyclic sampling manner to obtain the target rotational speed signal, the processing effect of the rotational speed signal can be effectively improved. Since the fan rotational speed is determined based on the target rotational speed signal, the accuracy and objectivity of determining the fan rotational speed can be effectively improved.

[0134] To implement the above embodiment, the present disclosure also proposes an electronic device, including: a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, it implements the method for processing the fan rotational speed signal as proposed in the foregoing embodiments of the present disclosure.

[0135] To implement the above embodiments, the present disclosure also provides a non - transitory computer - readable storage medium having stored thereon a computer program, which when executed by a processor, implements the method for processing a fan speed signal as proposed in the foregoing embodiments of the present disclosure.

[0136] To implement the above embodiments, the present disclosure also provides a computer program product, which when the instructions in the computer program product are executed by a processor, executes the method for processing a fan speed signal as proposed in the foregoing embodiments of the present disclosure.

[0137] Figure 10 The block diagram of an exemplary electronic device suitable for implementing the embodiments of the present disclosure is shown. Figure 10 The shown electronic device 12 is merely an example and should not impose any limitation on the functions and usage scope of the embodiments of the present disclosure.

[0138] As Figure 10 shown, the electronic device 12 is presented in the form of a general - purpose computing device. The components of the electronic device 12 may include, but are not limited to: one or more processors or processing units 16, a system memory 28, and a bus 18 connecting different system components (including the system memory 28 and the processing unit 16).

[0139] The bus 18 represents one or more of several types of bus structures, including a memory bus or a memory controller, a peripheral bus, a graphics acceleration port, a processor, or a local bus using any of the multiple bus structures. For example, these architectures include, but are not limited to, Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MAC) bus, Enhanced ISA bus, Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnection (PCI) bus.

[0140] The electronic device 12 typically includes a variety of computer - system - readable media. These media can be any available media accessible by the electronic device 12, including volatile and non - volatile media, removable and non - removable media.

[0141] The memory 28 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 30 and / or cache memory 32. The electronic device 12 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, the storage system 34 may be used for reading and writing on non-removable, non-volatile magnetic media ( Figure 10 not shown, commonly referred to as a "hard disk drive").

[0142] Although Figure 10 not shown in the figure, a disk drive for reading and writing on a removable non-volatile disk (such as a "floppy disk") and an optical disk drive for reading and writing on a removable non-volatile optical disk (such as a compact disc read only memory (CD-ROM), digital versatile disc read only memory (DVD-ROM) or other optical media) may be provided. In these cases, each drive may be connected to the bus 18 through one or more data media interfaces. The memory 28 may include at least one program product having a set (such as at least one) of program modules that are configured to perform the functions of the various embodiments of the present disclosure.

[0143] A program / utility 40 having a set (at least one) of program modules 42 may be stored, for example, in the memory 28. Such program modules 42 include, but are not limited to, an operating system, one or more application programs, other program modules, and program data. An implementation of a network environment may be included in each or some combination of these examples. The program modules 42 generally execute the functions and / or methods in the embodiments described in the present disclosure.

[0144] The electronic device 12 can also communicate with one or more external devices 14 (such as a keyboard, a pointing device, a display 24, etc.), and can also communicate with one or more devices that enable a user to interact with the electronic device 12, and / or communicate with any device that enables the electronic device 12 to communicate with one or more other computing devices (such as a network card, a modem, etc.). Such communication can be carried out through the input / output (I / O) interface 22. Moreover, the electronic device 12 can also communicate with one or more networks (such as a Local Area Network (LAN), a Wide Area Network (WAN), and / or a public network, such as the Internet) through the network adapter 20. As shown in the figure, the network adapter 20 communicates with other modules of the electronic device 12 through the bus 18. It should be understood that although not shown in the figure, other hardware and / or software modules can be used in combination with the electronic device 12, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, etc.

[0145] The processing unit 16 executes various functional applications and data processing by running programs stored in the system memory 28, such as implementing the fan speed signal processing method mentioned in the foregoing embodiments.

[0146] Those skilled in the art will readily think of other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses, or adaptations of the present disclosure, which follow the general principles of the present disclosure and include well-known common general knowledge or conventional technical means in the technical field not disclosed in the present disclosure. The specification and embodiments are only regarded as exemplary, and the true scope and spirit of the present disclosure are pointed out by the following claims.

[0147] It should be understood that the present disclosure is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present disclosure is only limited by the appended claims.

[0148] It should be noted that in the description of the present disclosure, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present disclosure, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0149] Any process or method description depicted in a flowchart or otherwise described herein can be understood to represent a module, segment, or portion of code including one or more executable instructions for implementing a specific logical function or process. The scope of the preferred embodiments of the present disclosure includes additional implementations where functions may be performed in a substantially simultaneous manner or in a reverse order according to the involved functions, rather than in the order shown or discussed, which should be understood by those skilled in the art to which the embodiments of the present disclosure pertain.

[0150] It should be understood that various parts of the present disclosure can be implemented by hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or a combination of the following techniques well known in the art can be used: discrete logic circuits having logic gate circuits for implementing logical functions on data signals, application specific integrated circuits having appropriate combinational logic gate circuits, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.

[0151] Those of ordinary skill in the art of this technology can understand that all or part of the steps carried by the methods of the above embodiments can be completed by instructing relevant hardware through a program. The said program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiments.

[0152] In addition, in each of the embodiments of the present disclosure, the functional units can be integrated into one processing module, or each unit can exist physically alone, or two or more units can be integrated into one module. The above integrated module can be implemented in the form of hardware or in the form of a software functional module. When the above integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0153] The above-mentioned storage medium can be a read-only memory, a magnetic disk, an optical disc, etc.

[0154] In the description of this specification, the descriptions referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0155] Although the embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present disclosure.

Claims

1. A method for processing the fan speed signal, which is applied to the distributed control system DCS, is characterized in that, Including: Obtain the initial rotational speed signal of the fan; Perform cyclic value-taking processing on the initial rotational speed signal to obtain a target rotational speed signal; Determine the fan rotational speed based on the target rotational speed signal; After obtaining the initial rotational speed signal of the fan, it further includes: Determine the value-taking period, where the value-taking period includes: a first value-taking period and a second value-taking period; The distributed control system DCS includes: a pulse signal generator algorithm block, a delay algorithm block, and determining the value-taking period includes: Determine the first value-taking period according to the pulse signal generator algorithm block; Determine the second value-taking period according to the delay algorithm block; Use the first value-taking period and the second value-taking period together as the value-taking period; The distributed control system DCS includes: a selection algorithm block, an arithmetic operation algorithm block, and performing cyclic value-taking processing on the initial rotational speed signal to obtain a target rotational speed signal includes: Take a value from the initial rotational speed signal according to the selection algorithm block to obtain a first rotational speed signal; Perform arithmetic operation processing on the first rotational speed signal according to the arithmetic operation algorithm block to obtain a target rotational speed signal; Taking a value from the initial rotational speed signal according to the selection algorithm block to obtain a first rotational speed signal includes: During the first value-taking period, take a value from the initial rotational speed signal according to the second value-taking period; Perform selection processing on the value-taking rotational speed signal to obtain a first rotational speed signal.

2. The method according to claim 1, wherein Performing selection processing on the value-taking rotational speed signal to obtain a first rotational speed signal includes: Determine the selection condition of the selection algorithm block; Perform selection processing on the value-taking rotational speed signal according to the selection condition to obtain a first rotational speed signal.

3. The method according to claim 2, wherein Performing selection processing on the value-taking rotational speed signal according to the selection condition to obtain a first rotational speed signal includes: If the selection condition is satisfied, use the value-taking rotational speed signal as the first rotational speed signal; If the selection condition is not satisfied, maintain the current value-taking and continue to wait until the selection condition is satisfied to obtain the first rotational speed signal.

4. The method according to claim 3, wherein The arithmetic operation algorithm block includes: an addition algorithm block, a division algorithm block, a multiplication algorithm block, and performing arithmetic operation processing on the first rotational speed signal according to the arithmetic operation algorithm block to obtain a target rotational speed signal includes: Perform arithmetic operation processing on the first rotational speed signal according to the addition algorithm block, the division algorithm block, and the multiplication algorithm block; Use the rotational speed signal obtained after the arithmetic operation processing as the target rotational speed signal.

5. A fan speed signal processing device is applied to a distributed control system (DCS), and is characterized in that, Including: An acquisition module for acquiring the initial rotational speed signal of the fan; A first processing module for performing cyclic value-taking processing on the initial rotational speed signal to obtain a target rotational speed signal; A first determination module for determining the fan rotational speed based on the target rotational speed signal; It further includes: A second determination module for determining the value-taking period after obtaining the initial rotational speed signal of the fan, where the value-taking period includes: a first value-taking period and a second value-taking period; The distributed control system DCS includes: a pulse signal generator algorithm block and a delay algorithm block. Among them, determining the value-taking period includes: Determining the first value-taking period according to the pulse signal generator algorithm block; Determining the second value-taking period according to the delay algorithm block; Regarding the first value-taking period and the second value-taking period together as the value-taking period; The distributed control system DCS includes: a selection algorithm block and an arithmetic operation algorithm block. Among them, performing cyclic value-taking processing on the initial rotational speed signal to obtain a target rotational speed signal includes: Taking values of the initial rotational speed signal according to the selection algorithm block to obtain a first rotational speed signal; Performing arithmetic operation processing on the first rotational speed signal according to the arithmetic operation algorithm block to obtain a target rotational speed signal; The step of taking values of the initial rotational speed signal according to the selection algorithm block to obtain a first rotational speed signal includes: Taking values of the initial rotational speed signal according to the second value-taking period within the first value-taking period; Performing selection processing on the value-taken rotational speed signal to obtain a first rotational speed signal.

6. An electronic device, characterized in that, It includes: At least one processor; And A memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method for processing a fan rotational speed signal according to any one of claims 1-4.

7. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, Wherein, The computer instructions are used to cause the computer to execute the method for processing a fan rotational speed signal according to any one of claims 1-4.

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