Semiconductor Memory and Data Writing Method

Abstract

An embodiment of the present application relates to a semiconductor memory and a data writing method. The semiconductor memory includes: at least one memory array, the memory array including a plurality of data storage units and a plurality of check bit storage units; a check module for receiving write data and generating check data according to the write data; a data transmission module respectively connected to the check module and the memory array for transmitting the write data to the data storage units and transmitting the check data to the check bit storage units; wherein, a first transmission time of the check data is shorter than a second transmission time of the write data, the first transmission time being the time required for the check data to be transmitted from the data transmission module to the check bit storage units, and the second transmission time being the time required for the write data to be transmitted from the data transmission module to the data storage units.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of memories, and in particular, to a semiconductor memory and a data writing method. Background Art

[0002] A semiconductor memory is a memory that uses semiconductor circuits for access. Among them, a Dynamic Random Access Memory (DRAM) is widely used in various fields due to its fast storage speed and high integration. In order to obtain higher data reading and writing reliability, a check module needs to be set in the semiconductor memory to check whether the read data is accurate. However, introducing the check module may cause the reading and writing speed of the memory to slow down, affecting the performance of the semiconductor memory. Summary of the Invention

[0003] The embodiments of the present application provide a semiconductor memory and a data writing method, which can optimize the writing speed of the semiconductor memory and improve the performance of the semiconductor memory.

[0004] A semiconductor memory includes:

[0005] At least one memory array, where the memory array includes a plurality of data storage units and a plurality of check bit storage units;

[0006] A check module, configured to receive the write data and generate check data according to the write data;

[0007] A data transmission module, respectively connected to the check module and the memory array, configured to transmit the write data to the data storage units and transmit the check data to the check bit storage units;

[0008] Wherein, a first transmission duration of the check data is shorter than a second transmission duration of the write data, the first transmission duration is the duration required for the check data to be transmitted by the data transmission module to the check bit storage units, and the second transmission duration is the duration required for the write data to be transmitted by the data transmission module to the data storage units.

[0009] In one embodiment, a first transmission path of the check data is shorter than a second transmission path of the write data, the first transmission path is the path between the data transmission module and the check bit storage units, and the second transmission path is the path between the data transmission module and the data storage units;

[0010] Wherein, the first transmission path corresponds to the first transmission duration, and the second transmission path corresponds to the second transmission duration.

[0011] In one embodiment, the verification data includes error correction verification data. Both the written data and the error correction verification data include a plurality of data bits, and the number of data bits of the written data is more than that of the error correction verification data. The verification module includes:

[0012] An error correction verification unit, connected to the data transmission module, for generating the error correction verification data according to the written data;

[0013] Wherein, the data of one data bit is correspondingly stored in one data storage unit or one parity bit storage unit. The transmission duration required for the data transmission module to transmit the written data of each data bit to the corresponding data storage unit is defined as the data transmission duration, and the transmission duration required for the data transmission module to transmit the error correction verification data of each data bit to the corresponding parity bit storage unit is defined as the verification transmission duration.

[0014] In one embodiment, the first transmission duration is the maximum value among a plurality of the verification transmission durations, and the second transmission duration is the minimum value among a plurality of the data transmission durations.

[0015] In one embodiment, the first transmission duration is the average value among a plurality of the verification transmission durations, and the second transmission duration is the average value among a plurality of the data transmission durations.

[0016] In one embodiment, the first transmission duration is the maximum value among a plurality of the verification transmission durations, and the second transmission duration is the maximum value among a plurality of the data transmission durations.

[0017] In one embodiment, the verification data includes parity verification data. The written data includes a plurality of data bits, the parity verification data includes one data bit, and the verification module includes:

[0018] A parity verification unit, connected to the data transmission module, for generating the parity verification data according to the written data;

[0019] Wherein, the data of one data bit is correspondingly stored in one data storage unit or one parity bit storage unit. The transmission duration required for the data transmission module to transmit the written data of each data bit to the corresponding data storage unit is defined as the data transmission duration, and the transmission duration required for the data transmission module to transmit the parity verification data to the corresponding parity bit storage unit is defined as the verification transmission duration.

[0020] In one embodiment, the first transmission duration is the verification transmission duration, and the second transmission duration is the minimum value among a plurality of the data transmission durations.

[0021] In one embodiment, the difference between the first transmission duration and the second transmission duration is greater than a preset duration, and the preset duration is the duration required for the verification module to generate verification data based on the written data.

[0022] In one embodiment, the preset duration is from 0.5 ns to 1 ns.

[0023] In one embodiment, the verification module includes a first verification unit and a second verification unit, and the data transmission module includes a first transmission unit and a second transmission unit. One of the two storage units located in adjacent columns is connected to the first verification unit via the first transmission unit, and the other is connected to the second verification unit via the second transmission unit.

[0024] In one embodiment, it further includes:

[0025] A plurality of bit line pairs, each bit line pair includes a first bit line and a second bit line, and the signals transmitted by the first bit line and the second bit line are opposite. A plurality of the storage units located in the same column are connected to the same bit line pair;

[0026] A plurality of local data line pairs, each local data line pair includes a first local data line and a second local data line, and the signals transmitted by the first local data line and the second local data line are opposite;

[0027] A plurality of sense amplifiers, each sense amplifier is respectively connected to one bit line pair and one local data line pair;

[0028] Wherein, two storage units located in adjacent columns are respectively connected to different local data line pairs via corresponding bit line pairs and sense amplifiers.

[0029] In one embodiment, it further includes:

[0030] A plurality of global data line pairs, each global data line pair includes a first global data line and a second global data line, and each global data line pair corresponds to a plurality of local data line pairs respectively;

[0031] A plurality of read / write conversion circuits, each read / write conversion circuit is respectively connected to the global data line pair and one local data line pair, and is used to convert the data transmission direction between the global data line pair and the local data line pair.

[0032] In one embodiment, the semiconductor memory includes two of the storage arrays.

[0033] In one embodiment, it further includes:

[0034] At least one column decoding circuit, the column decoding circuit being correspondingly connected to the memory array;

[0035] A row decoding circuit, being respectively connected to the two memory arrays;

[0036] Wherein, the column decoding circuit and the row decoding circuit are jointly used for decoding an address signal to select the memory cell to be written.

[0037] In one embodiment, the data transmission module synchronously transmits write data to the two memory arrays; or

[0038] The data transmission module transmits write data to the two memory arrays in a time-division manner.

[0039] In one embodiment, the memory array close to the data transmission module is used to store 128 bits of write data and 16 bits of check data, and the memory array far from the data transmission module is used to store 128 bits of write data.

[0040] A data writing method, the data writing method comprising:

[0041] Obtain write data and transmit the write data to a check module;

[0042] Transmit the write data to a data storage unit via a data transmission module, the data transmission module being respectively connected to the check module and the data storage unit;

[0043] Generate check data according to the write data and transmit the check data to a check bit storage unit, the data transmission module being respectively connected to the check bit storage unit;

[0044] Wherein, a first transmission duration of the check data is shorter than a second transmission duration of the write data, the first transmission duration being the duration required for the data transmission module to transmit the check data to the check bit storage unit, and the second transmission duration being the duration required for the data transmission module to transmit the write data to the data storage unit.

[0045] The above semiconductor memory and data writing method, the semiconductor memory includes: at least one memory array, the memory array includes a plurality of data storage units and a plurality of parity bit storage units; a parity module, configured to receive write data and generate parity data according to the write data; a data transmission module, respectively connected to the parity module and the memory array, configured to transmit the write data to the data storage units and transmit the parity data to the parity bit storage units; wherein, a first transmission duration of the parity data is shorter than a second transmission duration of the write data, the first transmission duration is the duration required for the parity data to be transmitted from the data transmission module to the parity bit storage units, and the second transmission duration is the duration required for the write data to be transmitted from the data transmission module to the data storage units. In an embodiment of the present application, by adjusting the first transmission duration and / or the second transmission duration to make the first transmission duration shorter, the duration consumed by the parity module to generate the parity data can be effectively compensated, so that the sum of the generation duration of the parity data and the first transmission duration matches the second transmission duration, thereby improving the write synchronization of different data, increasing the data write speed, and further improving the performance of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained according to these drawings.

[0047] Figure 1 FIG. 1 is a schematic structural diagram of a semiconductor memory according to an embodiment;

[0048] Figure 2 FIG. 2 is a schematic structural diagram of a semiconductor memory according to another embodiment;

[0049] Figure 3 FIG. 3 is a timing diagram of a write operation of a semiconductor memory according to an embodiment;

[0050] Figure 4 FIG. 4 is Figure 2 a partial enlarged view of a semiconductor memory according to an embodiment;

[0051] Figure 5 FIG. 5 is a schematic structural diagram of a semiconductor memory according to a further embodiment;

[0052] Figure 6 FIG. 6 is a schematic structural diagram of a semiconductor memory according to yet another embodiment;

[0053] Figure 7 FIG. 7 is a flowchart of a data writing method according to an embodiment.

[0054] Description of Component Labels:

[0055] Storage array: 100; Data storage unit: 110; Parity bit storage unit: 120; Parity module: 200; First parity unit: 210; Second parity unit: 220; Data transmission module: 300; First transmission unit: 310; Second transmission unit: 320; Bit line pair: 410; Sense amplifier: 420; Local data line pair: 430; Read / write conversion circuit: 440; Global data line pair: 450; Column decoding circuit: 510; Row decoding circuit: 520. Detailed Implementation Manner

[0056] To facilitate the understanding of the embodiments of the present application, the embodiments of the present application will be described more comprehensively below with reference to the relevant drawings. The preferred embodiments of the embodiments of the present application are given in the drawings. However, the embodiments of the present application can be implemented in many different forms and are not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the embodiments of the present application more thorough and comprehensive.

[0057] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the embodiments of the present application belong. The terms used in the specification of the embodiments of the present application herein are only for the purpose of describing specific embodiments and are not intended to limit the embodiments of the present application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0058] In the description of the embodiments of the present application, it should be understood that the orientation or positional relationships indicated by the terms "upper", "lower", "vertical", "horizontal", "inner", "outer", etc. are based on the methods or positional relationships shown in the drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the embodiments of the present application.

[0059] It can be understood that the terms "first", "second", etc. used in the present application can be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present application, the first bit line can be called the second bit line, and similarly, the second bit line can be called the first bit line. Both the first bit line and the second bit line are bit lines, but they are not the same bit line.

[0060] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In the description of this application, "a plurality of" means at least two, such as two, three, etc., unless otherwise specifically defined. In the description of this application, "several" means at least one, such as one, two, etc., unless otherwise specifically defined.

[0061] Figure 1 is one of the schematic structural diagrams of a semiconductor memory of an embodiment. Refer to Figure 1 , in this embodiment, the semiconductor memory includes a check module, a data transmission module 300, and at least one memory array 100.

[0062] The check module is used to receive the write data and generate check data according to the write data. The check data is generated and saved during the data write stage for determining whether an error occurs during the data read stage, that is, whether the data read from the data storage unit 110 is the same as the write data, so as to determine whether an error occurs during the data read and write process. Among them, the check module can be used to check the data information of multiple memory arrays 100, so as to optimize the number of check modules, and further provide a semiconductor memory with a small volume. It can be understood that the check module can be any circuit structure with a check data generation function. The specific type of the check module is not limited in this embodiment, and it can have at least one of parity check function, error correction check function, etc.

[0063] The memory array 100 includes a plurality of data storage units 110 and a plurality of check bit storage units 120. The storage units are used to store data, so as to realize the storage function of the semiconductor memory. Among them, the data storage unit 110 is used to store the write data input from the outside to the memory, and the check bit storage unit 120 is used to store the check data generated according to the write data. Specifically, the storage unit also includes a storage capacitor and a transistor. The control end of the transistor is connected to the word line, the first end of the transistor is connected to the storage capacitor, and the second end of the transistor is connected to the bit line. When the word line controls the transistor to conduct, the storage capacitor is conducted with the bit line, so as to realize the read and write of data information, that is, when reading data information, the storage capacitor transmits the stored data information to the bit line; when writing data information, the bit line sends the data information to be written to the storage capacitor.

[0064] The data transmission module 300 is respectively connected to the verification module and the storage array 100, and is configured to transmit the written data to the data storage unit 110 and transmit the verification data to the parity bit storage unit 120. Among them, the first transmission duration of the verification data is shorter than the second transmission duration of the written data. The first transmission duration is the duration required for the verification data to be transmitted from the data transmission module 300 to the parity bit storage unit 120, and the second transmission duration is the duration required for the written data to be transmitted from the data transmission module 300 to the data storage unit 110. The written data can be directly written into the data storage unit 110 through the data transmission module 300, while the verification data needs to be generated by the verification module according to the written data. Therefore, the time when the verification data arrives at the data transmission module 300 must be later than the time when the written data arrives at the data transmission module 300. Correspondingly, the moment when the verification data is written into the parity bit storage unit 120 will also be slightly later than the writing moment of the corresponding written data, resulting in poor data writing synchronization and further increasing the problem of writing speed. In this embodiment, by shortening the first transmission duration and / or increasing the second transmission duration, the above synchronization problem can be effectively compensated. It can be understood that the data transmission module 300 can implement the above transmission duration by controlling at least one of characteristics such as the path length of data transmission, the trigger moment of data transmission, and the speed of data transmission. This embodiment does not limit the specific manner of making the first transmission duration shorter than the second transmission duration.

[0065] In this embodiment, the semiconductor memory includes: at least one storage array 100, where the storage array 100 includes a plurality of data storage units 110 and a plurality of parity bit storage units 120; a verification module, configured to receive the written data and generate verification data according to the written data; a data transmission module 300, respectively connected to the verification module and the storage array 100, and configured to transmit the written data to the data storage unit 110 and transmit the verification data to the parity bit storage unit 120; among them, the first transmission duration of the verification data is shorter than the second transmission duration of the written data. The first transmission duration is the duration required for the verification data to be transmitted from the data transmission module 300 to the parity bit storage unit 120, and the second transmission duration is the duration required for the written data to be transmitted from the data transmission module 300 to the data storage unit 110. By adjusting the first transmission duration and / or the second transmission duration to make the first transmission duration shorter, the duration consumed by the verification module to generate the verification data can be effectively compensated, so that the sum of the generation duration of the verification data and the first transmission duration matches the second transmission duration, thereby improving the writing synchronization of different data and further enhancing the reliability of data writing.

[0066] In one embodiment, the first transmission path of the check data is shorter than the second transmission path of the write data. The first transmission path is the path between the data transmission module 300 and the check bit storage unit 120, and the second transmission path is the path between the data transmission module 300 and the data storage unit 110. Among them, the first transmission path corresponds to the first transmission duration, and the second transmission path corresponds to the second transmission duration. Among them, the same transmission speed of the write data and the check data can be used as a reference, and the corresponding path lengths can be obtained according to the transmission durations respectively. The above method can effectively reduce the difficulty of obtaining the path lengths and obtain relatively accurate path length information at the same time. It can be understood that the method of adjusting the transmission duration by using the path length has relatively low requirements for design requirements, process requirements, device performance requirements, etc. For example, if the transmission duration is adjusted by controlling the trigger time of data transmission, the reliability and window of the clock signal are required to be relatively high, that is, the performance requirements for the device are relatively high. That is, this embodiment provides a semiconductor memory with better accuracy and easy implementation.

[0067] In one embodiment, the difference between the first transmission duration and the second transmission duration is greater than a preset duration, and the preset duration is the duration required for the check module to generate check data according to the write data. In this embodiment, the corresponding duration difference can be determined according to the way the check module generates the check data. Specifically, if the way to generate the check data is relatively simple, the operation duration of the check module is shorter, and a smaller duration difference can be set to improve the operation efficiency of the memory. Moreover, if the transmission duration is set by adjusting the path length, selecting a smaller duration difference further has the function of shortening the signal trace to improve the signal stability and reliability on the signal transmission path. If the way to generate the check data is relatively complex, the operation duration of the check module is longer, and a larger duration difference can be set to ensure the synchronization between the write data and the check data. Exemplarily, taking the check module as an error correction check module as an example, the data generation duration required by it is longer, usually 0.5 ns to 1 ns, and correspondingly, the preset duration can be set to 0.5 ns to 1 ns to ensure the synchronization of the memory.

[0068] Figure 2 FIG. 2 is a second schematic structural diagram of a semiconductor memory according to an embodiment, refer to Figure 2, in this embodiment, the memory further includes a row decoding circuit 520 and at least one column decoding circuit 510. The column decoding circuit 510 is correspondingly connected to the storage array 100, and the row decoding circuit 520 is connected to the storage array 100. Among them, the column decoding circuit 510 and the row decoding circuit 520 are jointly used to decode the address signal to select the storage unit to be written. Further, the semiconductor memory may include two column decoding circuits 510, and the two column decoding circuits 510 are correspondingly connected to the same storage array 100, and the two column decoding circuits 510 are oppositely arranged on both sides of the storage array 100 along the extending direction of the bit line.

[0069] In this embodiment, the storage units in the dotted line area on the right side in the storage array 100 may be used as check bit storage units 120, and the remaining storage units in the storage array 100 may be used as data storage units 110. Among them, the quantitative relationship between the check bit storage units 120 and the data storage units 110 may be determined according to the checking method of the checking module. For example, if the checking module generates 1-bit check data based on 8-bit written data, the number of check bit storage units 120 may be 1 / 8 of the number of data storage units 110. In this embodiment, by setting the check bit storage units 120 at a position close to the data transmission module 300, the transmission path of the check data in the storage array 100 can be made the shortest and the load can be the lightest, thereby effectively compensating for the delay of the pre-stage of the check data in the checking operation. Moreover, combined with Figure 2 it can be found that the process of data reaching the storage unit from the data transmission module 300 is a T-shaped data transmission structure, and the T-shaped structure is relatively flexible and fast, which can effectively optimize the area and performance of the memory.

[0070] Figure 3 is a timing diagram of the write operation of a semiconductor memory in an embodiment. Figure 3 The timing diagram in Figure 2 can be implemented based on the semiconductor memory provided in the embodiment. Refer to Figure 3 , in this embodiment, the enable signals of the written data and the check data can be further controlled separately. Specifically, it means separating the CSL decoding enable signal and the write enable signal, so as to achieve the purpose of balancing the speeds of the two paths and improving the flexibility of the timing signal control. From Figure 3 it can be found that although the starting times of writing the two data are different, by adjusting the transmission duration, the response duration tdp of the global data line of the check data can be made less than the response duration td of the global data line of the written data, and the two data can be written at similar times, thereby effectively improving the synchronization of data writing and further improving the writing performance of the semiconductor memory.

[0071] Figure 4 is Figure 2 a partial enlarged view of the semiconductor memory of the embodiment. Refer to Figure 4 , in this embodiment, the memory further includes a plurality of bit line pairs 410, a plurality of local data line pairs 430, and a plurality of sense amplifiers 420, and the above structure can be used to transmit write data signals and check data signals. Therefore, the above structure can also be understood as a part of the data transmission module 300.

[0072] The bit line pair 410 includes a first bit line and a second bit line, and the signals transmitted by the first bit line and the second bit line are opposite. A plurality of the memory cells located in the same column are connected to the same bit line pair 410. In this embodiment, the signal transmitted by the first bit line can be made the same as the actual data, and the signal transmitted by the second bit line can be made opposite to the actual data. By setting two signal lines with opposite transmitted signals to transmit the same data, the reliability of the data transmission process can be effectively improved. The line pairs for differential transmission in other embodiments also have the above function. It should be noted that, for the sake of simplicity of the drawings, Figure 4 only the single-line structure is shown for the bit line pair 410. The local data line pair 430 includes a first local data line Ldat and a second local data line Ldat#, and the signals transmitted by the first local data line Ldat and the second local data line Ldat# are opposite. Each sense amplifier 420 is respectively connected to a bit line pair 410 and a local data line pair 430; wherein, two memory cells located in adjacent columns are respectively connected to different local data line pairs 430 via the corresponding bit line pairs 410 and sense amplifiers 420.

[0073] Further, continue to refer to Figure 4 , the memory further includes a plurality of global data line pairs 450 and a plurality of read / write conversion circuits 440. Similarly to the foregoing content, the above structure can also be understood as a part of the data transmission module 300.

[0074] The global data line pair 450 includes a first global data line YIO and a second global data line YIO#, and each global data line pair 450 corresponds to a plurality of local data line pairs 430 respectively. Each check module is connected to a group of global data line pairs 450, and the check module realizes the sending and receiving of data information through the global data line pairs 450. Each read / write conversion circuit 440 is respectively connected to the global data line pair 450 and a local data line pair 430, and is used to convert the data transmission direction between the global data line pair 450 and the local data line pair 430.

[0075] Specifically, when the data in the storage unit needs to be changed or rewritten, the column decoding circuit 510 selects the corresponding sense amplifier 420. The data is transmitted from the global data line pair 450, through the local read / write conversion circuit 440 (lrwap), to the local data line pair 430, and then written into the corresponding sense amplifier 420, and transmitted to the connected storage unit through the bit line pair 410. When data is read out, the data transmission direction is opposite. The column decoding circuit 510 selects the position of the corresponding sense amplifier 420. The data is transmitted to the local data line pair 430 through the bit line pair 410 and the sense amplifier 420, and then transmitted to the global data line pair 450 by the local read / write conversion circuit 440 (lrwap), and finally amplified and output by the SSA (second sense amplifier).

[0076] In one embodiment, the verification data includes error correction verification data. Both the written data and the error correction verification data include a plurality of data bits, and the number of data bits of the written data is more than that of the error correction verification data. The verification module includes an error correction verification unit, which is connected to the data transmission module 300 and is used to generate the error correction verification data according to the written data. Among them, the data corresponding to one data bit is stored in one data storage unit 110 or one parity bit storage unit 120. The transmission duration required for the data transmission module 300 to transmit the written data corresponding to each data bit to the corresponding data storage unit 110 is defined as the data transmission duration, and the transmission duration required for the data transmission module 300 to transmit the error correction verification data corresponding to each data bit to the corresponding parity bit storage unit 120 is defined as the verification transmission duration. In this embodiment, the error correction verification module can detect and / or correct errors in the data during storage or transmission to improve the reliability of the memory.

[0077] Exemplarily, the first transmission duration is the maximum value among multiple verification transmission durations, and the second transmission duration is the minimum value among multiple data transmission durations. By adopting the above method, it can most effectively ensure that all verification data can be accurately written, that is, a memory with relatively high accuracy is provided. Another exemplarily, the first transmission duration is the maximum value among multiple verification transmission durations, and the second transmission duration is the maximum value among multiple data transmission durations. By adopting the above method, the influence on the data storage speed can be largely avoided. Yet another exemplarily, the first transmission duration is the average value among multiple verification transmission durations, and the second transmission duration is the average value among multiple data transmission durations. By adopting the above method, the above multiple performance parameters can be more effectively balanced, that is, a memory with relatively balanced performance is provided.

[0078] Figure 5The third structural schematic diagram of a semiconductor memory according to an embodiment. Refer to Figure 5 In this embodiment, the verification module includes a first verification unit 210 and a second verification unit 220. The data transmission module 300 includes a first transmission unit 310 and a second transmission unit 320. One of the two storage units located in adjacent columns is connected to the first verification unit 210 via the first transmission unit 310, and the other is connected to the second verification unit 220 via the second transmission unit 320. Exemplarily, for a verification module including an error correction verification unit, the first verification unit 210 can be understood as the first error correction verification unit, and the second verification unit 220 can be understood as the second error correction verification unit. That is, the type of the verification module does not conflict with the number of verification units.

[0079] It can be understood that for a memory, due to the manufacturing process, when a storage unit has an abnormality, the probability of an adjacent storage unit having an abnormality is higher than that of other storage units. Therefore, in this embodiment, ensuring that the data corresponding to adjacent bit line pairs 410 respectively corresponds to different verification units can effectively improve the detection efficiency. Especially for error correction verification units, the data stored in abnormal storage units located in adjacent columns can be respectively and one-to-one corrected by the first verification unit 210 and the second verification unit 220, so as to achieve the ability to repair two errors simultaneously (assuming that each verification unit can only repair 1 error).

[0080] In one embodiment, the verification data includes parity verification data, the written data includes multiple data bits, the parity verification data includes one data bit, the verification module includes a parity verification unit, and the parity verification unit is connected to the data transmission module 300 and is used to generate the parity verification data according to the written data. Among them, the data of one data bit is correspondingly stored in a data storage unit 110 or a parity bit storage unit 120. The transmission duration required for the data transmission module 300 to transmit the written data of each data bit to the corresponding data storage unit 110 is defined as the data transmission duration, and the transmission duration required for the data transmission module 300 to transmit the parity verification data to the corresponding parity bit storage unit 120 is defined as the verification transmission duration. In this embodiment, the operation logic of the parity verification unit is simple and can quickly generate verification data. Therefore, the user can select to set at least one of an error correction verification unit and a parity verification unit in the verification module according to needs.

[0081] Exemplarily, the first transmission duration is the verification transmission duration, and the second transmission duration is the minimum value among multiple data transmission durations. By adopting the above method, it is possible to most effectively ensure that all verification data can be accurately written, that is, a memory with relatively high accuracy is provided. Another exemplarily, the second transmission duration is the maximum value among multiple data transmission durations. By adopting the above method, the influence on the data storage speed can be largely avoided. Still another exemplarily, the second transmission duration is the average value among multiple data transmission durations. By adopting the above method, the above-mentioned multiple performance parameters can be more effectively balanced, that is, a memory with relatively balanced performance is provided.

[0082] Figure 6 FIG. 4 is a schematic structural diagram of a semiconductor memory according to an embodiment. Refer to Figure 6 , in this embodiment, the semiconductor memory includes two storage arrays 100. Specifically, when the semiconductor memory includes two storage arrays 100, the check bit storage unit can be provided only in one storage array 100, that is, as Figure 6 shown, the storage array 100 on the left (i.e., the storage array 100 far from the transmission unit) only includes data storage units 110, and the storage array 100 on the right (i.e., the storage array 100 far from the transmission unit) includes data storage units 110 and check bit storage units 120. Exemplarily, the storage array 100 close to the data transmission module 300 can be used to store 128 bits of write data and 16 bits of check data, and the storage array 100 far from the data transmission module 300 can be used to store 128 bits of write data. The memory with the above parameter settings has relatively balanced requirements for driving ability and write speed, so the performance is relatively stable.

[0083] Further, the two storage arrays 100 can be connected to the same row decoding circuit 520 to reduce the number of row decoding circuits 520 that need to be provided, thereby providing a memory with a small volume. Optionally, the data transmission module 300 can synchronously transmit write data to the two storage arrays 100 to improve the write speed of the data. The data transmission module 300 can also transmit write data to the two storage arrays 100 in a time-sharing manner to improve the stability and reliability of the data transmission.

[0084] Figure 7 FIG. is a flowchart of a data writing method according to an embodiment. Refer to Figure 7 , in this embodiment, the data writing method includes steps S100 to S300.

[0085] S100: Obtain write data and transmit the write data to the verification module;

[0086] S200: Transmit the written data to the data storage unit 110 via the data transmission module 300. The data transmission module 300 is respectively connected to the verification module and the data storage unit 110;

[0087] S300: Generate verification data according to the written data, and transmit the verification data to the verification bit storage unit 120. The data transmission module 300 is respectively connected to the verification bit storage unit 120.

[0088] Wherein, the first transmission duration of the verification data is shorter than the second transmission duration of the written data. The first transmission duration is the duration required for the verification data to be transmitted from the data transmission module 300 to the verification bit storage unit 120, and the second transmission duration is the duration required for the written data to be transmitted from the data transmission module 300 to the data storage unit 110. In this embodiment, by setting the above steps, the writing synchronization of the written data and the verification data can be improved, and the writing speed can be increased. That is, a data writing method with better data writing performance is provided. It can be understood that for the further limitations of this embodiment, reference can be made to the specific implementation manners of the foregoing semiconductor memory, which will not be elaborated here.

[0089] It should be understood that although Figure 7 the steps in the flowchart are shown in sequence according to the indication of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise clearly stated in this article, the execution of these steps has no strict order limitation, and these steps can be executed in other orders. Moreover, Figure 7 at least a part of the steps in

[0090] may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same moment, but can be executed at different moments. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or sub-steps or stages of other steps.

[0090] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope described in this specification.

[0091] The above-described embodiments merely represent several implementation manners of the embodiments of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the embodiments of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the embodiments of the present application. Therefore, the protection scope of the patent of the embodiments of the present application shall be subject to the appended claims.

Claims

1. A semiconductor memory, characterized in that, Comprising: At least one storage array, the storage array including a plurality of data storage units and a plurality of parity bit storage units; A parity check module, configured to receive write data and generate parity check data according to the write data; A data transmission module, respectively connected to the parity check module and the storage array, configured to transmit the write data to the data storage units and transmit the parity check data to the parity bit storage units; Wherein, a first transmission duration of the parity check data is shorter than a second transmission duration of the write data, the first transmission duration being the duration required for the parity check data to be transmitted by the data transmission module to the parity bit storage units, and the second transmission duration being the duration required for the write data to be transmitted by the data transmission module to the data storage units; The parity check module includes a first parity check unit and a second parity check unit, and the data transmission module includes a first transmission unit and a second transmission unit. One of two storage units located in adjacent columns is connected to the first parity check unit via the first transmission unit, and the other is connected to the second parity check unit via the second transmission unit.

2. The semiconductor memory according to claim 1, wherein A first transmission path of the parity check data is shorter than a second transmission path of the write data, the first transmission path being the path between the data transmission module and the parity bit storage units, and the second transmission path being the path between the data transmission module and the data storage units; Wherein, the first transmission path corresponds to the first transmission duration, and the second transmission path corresponds to the second transmission duration.

3. The semiconductor memory according to claim 2, wherein The parity check data includes error correction parity check data, both the write data and the error correction parity check data include a plurality of data bits, and the number of data bits of the write data is more than the number of data bits of the error correction parity check data. The parity check module includes: An error correction parity check unit, connected to the data transmission module, configured to generate the error correction parity check data according to the write data; Wherein, one data bit of data is correspondingly stored in one data storage unit or one parity bit storage unit. The transmission duration required for the write data defining each data bit to be transmitted by the data transmission module to the corresponding data storage unit is defined as the data transmission duration, and the transmission duration required for the error correction parity check data defining each data bit to be transmitted by the data transmission module to the corresponding parity bit storage unit is defined as the parity check transmission duration.

4. The semiconductor memory according to claim 3, wherein the first transmission duration is the maximum value among a plurality of the parity check transmission durations, and the second transmission duration is the minimum value among a plurality of the data transmission durations.

5. The semiconductor memory according to claim 3, wherein, The first transmission duration is the average value among a plurality of the parity check transmission durations, and the second transmission duration is the average value among a plurality of the data transmission durations.

6. The semiconductor memory according to claim 3, wherein, The first transmission duration is the maximum value among a plurality of the parity check transmission durations, and the second transmission duration is the maximum value among a plurality of the data transmission durations.

7. The semiconductor memory according to claim 2, wherein The parity check data includes parity check data, the write data includes a plurality of data bits, the parity check data includes one data bit, and the parity check module includes: A parity check unit, connected to the data transmission module, for generating the parity check data according to the write data; Wherein, the data of one data bit is correspondingly stored in one data storage unit or one parity bit storage unit. The transmission duration required for the data transmission module to transmit the write data of each data bit to the corresponding data storage unit is defined as the data transmission duration, and the transmission duration required for the data transmission module to transmit the parity check data to the corresponding parity bit storage unit is defined as the parity check transmission duration.

8. The semiconductor memory according to claim 7, wherein the first transmission duration is the parity check transmission duration, and the second transmission duration is the minimum value of multiple data transmission durations.

9. The semiconductor memory according to any one of claims 2 to 7, characterized in that, The difference between the first transmission duration and the second transmission duration is greater than a preset duration, and the preset duration is the duration required for the check module to generate check data according to the write data.

10. The semiconductor memory according to claim 9, wherein, The preset duration is from 0.5 ns to 1 ns.

11. The semiconductor memory according to claim 1, characterized in that, Further comprising: Multiple bit line pairs, each bit line pair includes a first bit line and a second bit line, and the signals transmitted by the first bit line and the second bit line are opposite. Multiple storage units in the same column are connected to the same bit line pair; Multiple local data line pairs, each local data line pair includes a first local data line and a second local data line, and the signals transmitted by the first local data line and the second local data line are opposite; Multiple sense amplifiers, each sense amplifier is respectively connected to one bit line pair and one local data line pair; Wherein, two storage units in adjacent columns are respectively connected to different local data line pairs via corresponding bit line pairs and sense amplifiers.

12. The semiconductor memory according to claim 11, wherein, Further comprising: Multiple global data line pairs, each global data line pair includes a first global data line and a second global data line, and each global data line pair corresponds to multiple local data line pairs respectively; Multiple read / write conversion circuits, each read / write conversion circuit is respectively connected to the global data line pair and one local data line pair, for converting the data transmission direction between the global data line pair and the local data line pair.

13. The semiconductor memory according to claim 1, characterized in that, The semiconductor memory includes two of the storage arrays.

14. The semiconductor memory according to claim 13, wherein Further comprising: At least one column decoding circuit, the column decoding circuit is correspondingly connected to the storage array; A row decoding circuit, connected to two of the storage arrays respectively; Wherein, the column decoding circuit and the row decoding circuit are jointly used for decoding the address signal to select the storage unit to be written.

15. The semiconductor memory according to claim 13, wherein, The data transmission module synchronously transmits write data to two of the storage arrays; or The data transmission module transmits write data to two of the storage arrays in a time-sharing manner.

16. The semiconductor memory according to claim 13, wherein, The storage array close to the data transmission module is used to store 128 bits of write data and 16 bits of parity check data, and the storage array far from the data transmission module is used to store 128 bits of write data.

17. A data writing method, characterized in that, The data writing method includes: Obtaining write data and transmitting the write data to the check module; The written data is transmitted to the data storage unit via the data transmission module, and the data transmission module is respectively connected to the verification module and the data storage unit; Verification data is generated according to the written data, and the verification data is transmitted to the verification bit storage unit. The data transmission module is respectively connected to the verification bit storage unit; Wherein, the first transmission duration of the verification data is shorter than the second transmission duration of the written data. The first transmission duration is the duration required for the verification data to be transmitted from the data transmission module to the verification bit storage unit, and the second transmission duration is the duration required for the written data to be transmitted from the data transmission module to the data storage unit; The verification module includes a first verification unit and a second verification unit. The data transmission module includes a first transmission unit and a second transmission unit. One of the two storage units located in adjacent columns is connected to the first verification unit via the first transmission unit, and the other is connected to the second verification unit via the second transmission unit.

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