A method for implementing a sorting circuit based on pipeline processing

Abstract

The present invention discloses a method for implementing a sorting circuit based on pipeline processing, comprising the following steps: inputting a sequence to be sorted into the sorting circuit in sequence according to a clock; the first data to be sorted will be directly stored into the first-stage register of the shift register from the input port of the shift register, and the sorting sequence number corresponding to the input data is set to 0; starting from the second data to be sorted being placed at the input port of the shift register, the data to be sorted stored in each stage register of the shift register will be compared with the input port or the last-stage data of the shift register, and judging whether to increase the sorting sequence number stored in the self-stored register by one according to the comparison result, and updating the updated sorting sequence number together with the sorted data stored in the current stage register to the next stage register at the next clock; starting from the second stage, the shift register performs comparison and judgment operations at each stage, and outputs the data to be sorted at the output port of the shift register.

Description

Technical Field

[0001] The present invention relates to the field of HDL circuit data sorting, and in particular to a method for realizing a sorting circuit based on pipeline processing. Background Art

[0002] Sorting is a common operation performed within computers, aiming to restructure a "disordered" sequence of records into an "ordered" one. Sorting plays a significant role in both work and life. From a human perspective, sorting makes data easier to read and more user-friendly. Search algorithms based on sorting are also easier to implement, enabling faster retrieval of results from entire datasets. From a computer science perspective, since computers, programs, or applications often search vast datasets, efficient sorting greatly improves work efficiency.

[0003] Most current solutions for sorting requirements rely on processors like CPUs and MCUs to execute sorting algorithms. While this approach offers design flexibility, it has been proven that sorting algorithms have a lower bound of O(nlog(n)) time complexity. This means that for a sequence of length n, the time required to sort on a CPU or MCU is bounded by nlog(n) sorting operations. Furthermore, data access operations on the CPU / MCU further extend the execution time. Furthermore, considering the complexity of CPU and MCU interface circuitry, integrating a CPU or MCU solely for sorting significantly increases design complexity and adds significant area to ASIC designs. Summary of the Invention

[0004] The present invention provides a method for implementing a sorting circuit based on pipeline processing, which solves the problems that current solutions for sorting requirements require the introduction of complex CPUs / MCUs, resulting in a sharp increase in design complexity, insufficient speed, and consumption of additional ASIC area.

[0005] The present invention is achieved through the following technical solutions:

[0006] A method for implementing a sorting circuit based on pipeline processing, comprising:

[0007] When performing a sorting operation, the sequence to be sorted is input into the sorting circuit in sequence according to the clock;

[0008] The first data to be sorted will be directly stored into the first-order register of the shift register from the input port of the shift register, and the sorting number corresponding to the input data will be set to 0;

[0009] Starting from the second data to be sorted being placed at the input port of the shift register, the data to be sorted stored in each stage register of the shift register will be compared with the input port or the last stage data of the shift register, and according to the comparison result, it is determined whether to increase the sorting sequence number stored in itself by one, and the updated sorting sequence number together with the sorted data stored in the current stage register will be updated to the next stage register at the next clock;

[0010] The shift register starts from the second stage, and performs comparison and judgment operations at each stage, outputting the data to be sorted and its position number in the sorted sequence at the output port of the shift register;

[0011] The position number is used as the write address of the storage unit, and the data to be sorted is used as the write data of the storage unit to write the data into the sorting storage unit; after all the data in the current sequence to be sorted has been written into the sorting storage unit, the read address is accumulated starting from the low address of the storage unit, and the sorted sequence is output from the read data output port of the storage unit.

[0012] Furthermore, the length of the selected shift register is equal to the sum of the length of the sequence to be sorted and the operation delay of the sorting circuit.

[0013] Furthermore, the sorting circuit is provided with an input comparison array, which is used to compare the storage items of each stage in the shift register with the input data items. When the data items of the sequence to be sorted are input to the shift register, the comparison method is as follows:

[0014] For ascending sorting, when the stored item is greater than or equal to the input data item, the sort position number corresponding to the stored item is counted up by one, otherwise it remains unchanged;

[0015] For descending sorting, when the stored item is less than or equal to the input data item, the sort position sequence number count corresponding to the stored item is increased by one, otherwise it remains unchanged.

[0016] Furthermore, when the last item of the sequence to be sorted has been input into the shift register, the data item to be output is compared with the unoutput storage item of the current sequence to be sorted stored in the shift register, and the sorting position sequence number count is updated according to the comparison result.

[0017] Furthermore, the sorting circuit is provided with an output comparison array, which is used to compare each item of the sequence to be sorted stored in each stage of the shift register, and the comparison method is:

[0018] For ascending sorting, when the stored item is larger than the data item to be output, the sort position number corresponding to the stored item is incremented by one, otherwise it remains unchanged.

[0019] For descending sorting, when the stored item is smaller than the data item to be output, the sorting position number count corresponding to the stored item is increased by one, otherwise it remains unchanged.

[0020] Furthermore, after the output comparison array is executed, the sorting sequence output by the shift register and the corresponding sorting position number are sequentially stored and output in order;

[0021] The execution method of the sorted storage is as follows: writing each data of the sorted sequence into a random storage unit using its corresponding sort position number as the write address;

[0022] The execution method of the sorted output is as follows: after the sorted sequence performs the complete sorting, the read address is accumulated sequentially starting from 0, and the sorted sequence is output from the random storage unit read port.

[0023] Furthermore, when any sequence to be sorted is input, an end mark is added to the last data item of the sequence; the end mark is used to distinguish the sequence to be sorted newly input into the shift register from other sequences to be sorted waiting to be output.

[0024] Furthermore, the time delay of the sorting circuit is the delay beat number of the sorting circuit output comparison result, and the update order of each order position number in the shift register is greater than the output delay beat number of the sorting circuit.

[0025] Furthermore, it is characterized in that the random access memory unit includes a first random access memory unit and a second random access memory unit, and the first random access memory unit and the second random access memory unit alternately perform sorted storage and sorted output in a ping-pong cache manner.

[0026] On the other hand, this embodiment provides a sorting circuit for executing the above-mentioned method for implementing a sorting circuit based on pipeline processing, including:

[0027] Sorting position number calculation unit and sorting unit;

[0028] The sorting position number calculation unit includes:

[0029] shift register;

[0030] An input comparator, the input comparator is used to perform an input comparison array;

[0031] An output comparator, the output comparator is used to implement an output comparison array;

[0032] The reordering unit includes a first random access memory, a second random access memory and an address accumulator.

[0033] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0034] 1. Low computational delay. The lower limit of the time complexity of existing CPU / MCU-based sorting solutions is O(nlog(n)). Assuming that the program manager wants to optimize, data reading and data writing can be executed in parallel with comparison operations in a pipeline form. Sorting a sequence of length n also requires at least n×log(n) instruction cycles. Adding the communication interface delay between the CPU / MCU and the ASIC, the total processing delay will be even larger. The sorting circuit implementation method provided by the present invention realizes the pipeline processing of comparison, sorting position number calculation, and reordering operations. The comparison operation between data items and the sorting position number calculation are executed in parallel, which greatly reduces the computational delay of the sorting operation.

[0035] 2. Simple interface. CPU / MCU-based sorting solutions require the design of complex bus data interaction interfaces and related bus data interaction protocols for the CPU / MCU, greatly increasing the design complexity. The sorting circuit described in the present invention does not require a complex bus data interaction interface or bus data interaction protocol. It only requires a flag indicating whether the sequence is complete or not along with the sorted data input, greatly simplifying the interaction interface.

[0036] 3. High reusability and low implementation difficulty. The sorting circuit designed in this invention is based on HDL description, and the sorting sequence length and the type of data to be sorted can be easily changed according to needs. In addition to processing standard unsigned integers and signed integers, it can also process highly mature IEEE754 standard floating-point numbers. Even the comparator module of the sorted data can be customized according to needs, which has great flexibility and ease of use. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the following briefly introduces the drawings required for use in the examples. It should be understood that the following drawings only illustrate certain embodiments of the present invention and should not be considered as limiting the scope. A person of ordinary skill in the art can also derive other relevant drawings based on these drawings without inventive effort. In the drawings:

[0038] Figure 1 A flowchart of the steps for implementing the sorting circuit provided in an embodiment of the present invention;

[0039] Figure 2 A schematic diagram of the top-level principle structure of a sorting circuit provided in an embodiment of the present invention;

[0040] Figure 3 A schematic diagram illustrating the principle of a sorting position number calculation unit provided in an embodiment of the present invention;

[0041] Figure 4 A schematic diagram of the principle of an input comparator provided in an embodiment of the present invention;

[0042] Figure 5 A schematic diagram of the principle of an output comparator provided by an embodiment of the present invention;

[0043] Figure 6 A schematic diagram of the structural principle of the sequencing unit provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0044] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with examples and drawings. The exemplary embodiments of the present invention and their descriptions are only used to explain the present invention and are not intended to limit the present invention.

[0045] Example 1

[0046] See also Figures 1-6 This embodiment provides a method for implementing a pipeline-based sorting circuit. A sequence to be sorted is sequentially input into the circuit. The circuit calculates the sorting position of each input data item in the sorted sequence based on a given sorting sequence length n, and outputs a sequence rearranged according to the sorting position number. This embodiment is implemented as follows:

[0047] When performing a sorting operation, the sequence to be sorted is input into the sorting circuit in sequence according to the clock. The first data to be sorted is directly stored into the first-stage register of the shift register from the input port of the shift register, and the sorting sequence number corresponding to the input data is set to 0. Starting from the second data to be sorted is placed at the input port of the shift register, the data to be sorted stored in each stage register of the shift register is compared with the input port or the last-stage data of the shift register. Based on the comparison result, it is determined whether to increase the sorting sequence number stored in the shift register by one. The updated sorting sequence number is updated together with the sorted data stored in the current stage register to the next stage register at the next clock. Starting from the second stage, the shift register executes the above-mentioned comparison steps at each stage, outputting the data to be sorted and its position number in the sorted sequence at the output port of the shift register. The data is written into the sorting storage unit using the position number as the write address of the storage unit and the data to be sorted as the write data of the storage unit. After all the data of the current sequence to be sorted has been written into the sorting storage unit, the read address is accumulated starting from the lower address of the storage unit, and the sorted sequence is output from the read data output port of the storage unit.

[0048] It can also be understood as inputting a sequence to be sorted of length n, and storing the sequence to be sorted into the shift register in the order of input; comparing each data item with the previous data item of the first n-1 stages in the shift register according to the input order of the data items in the sequence to be sorted, and performing operations based on the comparison results; shifting the above operation results together with the current data item into the next stage register, and generating the sorting position number of the current data item. The operation delay of the sorting circuit is c, then when the last data item of the sequence to be sorted has been shifted into the cth stage of the shift register, and the sorting position number of the item has been updated to the cth stage storage unit of the shift register, the sorted sequence is output at the output end of the shift register. Among them, when any sequence to be sorted is input, an end flag is added to the last data item of its sequence; the end flag is used to distinguish the newly input sequence to be sorted in the shift register from other sequences to be sorted waiting to be output.

[0049] Please refer again Figure 2 and Figure 3 Let SE be the sequence to be sorted, SIDX be the sorting position sequence number, and SEF be the end of the input sequence. The register contents of the input stage (i.e., stage 0) are updated by the input SE, the initial SIDX set to 0, and the input SEF. The SE and SEF values ​​of the registers in the remaining stages are updated by the SE and SEF values ​​of the registers in the previous stage. The SIDX values ​​of the sorting positions in the remaining stages are updated based on the output of the comparators in each stage.

[0050] Please refer again Figure 3 and Figure 4 When inputting, the input sequence data is sequentially input into the shift register together with its initial sorting position and sorting position number 0. At the same time, the input data and the sorted data in the registers of each stage before the stage where SEF is set in the first n-1 stages of the shift register (excluding the stage where SEF is set) are input into n-1 sorting circuits in parallel. When comparing the input, the sorting circuit is provided with an input comparison array, which is used to compare the storage items and data items of each stage in the shift register. When the data items of the sequence to be sorted are input into the shift register, the comparison method is as follows: for ascending sorting, when the storage item is greater than or equal to the input data item, the sorting position number count corresponding to the storage item is increased by one, otherwise it remains unchanged; for descending sorting, when the storage item is less than or equal to the input data item, the sorting position number count corresponding to the storage item is increased by one, otherwise it remains unchanged. Therefore, according to the output result of the input comparator, the SIDX in each stage register is updated by adding 1 or remains unchanged (for ascending sorting, if the SE in the register is greater than the input SE, the SIDX in the register is added by 1, otherwise it remains unchanged; for descending sorting, if the SE in the register is less than the input SE, the SIDX in the register is added by 1, otherwise it remains unchanged), and the updated result is stored in the shift register from stage c to stage c+n-1.

[0051] Afterwards, when the last item of the sequence to be sorted has been input into the shift register, in order to ensure that the sorting position number counts of all data items output by the shift register are correct and valid, the data item to be output is compared with the unoutput storage items of the current sequence to be sorted stored in the shift register, and the sorting position number count of the sort is updated according to the comparison result.

[0052] Please refer again Figure 3 and Figure 5 When preparing for output, when the data at the output end of the shift register (i.e., the c+n-1th register) is valid, the sorted data SE at the output end needs to be compared with the sorted items SE stored in the stage starting from the stage where SEF is set in the previous n-1th stage register to the stage before the output end. The result needs to be used to update the SIDX in the registers of these stages. In this embodiment, the sorting circuit is provided with an output comparison array, which is used to compare each item of the sequence to be sorted stored in each stage of the shift register. The comparison method is: for ascending sorting, when the stored item is larger than the data item to be output, the sorting position number count corresponding to the stored item is increased by one, otherwise it remains unchanged; for descending sorting, when the stored item is smaller than the data item to be output, the sorting position number count corresponding to the stored item is increased by one, otherwise it remains unchanged (for ascending sorting, in the first n-1 stage registers, when the SE stored in each stage register is greater than the SE at the output end, the SIDX in each stage register is increased by 1, otherwise the SIDX remains unchanged; for descending sorting, in the first n-1 stage registers, when the SE stored in each stage register is smaller than the SE at the output end, the SIDX in each stage register is increased by 1, otherwise the SIDX remains unchanged.). Since there is a delay c in the comparator operation, in order to obtain the comparison result before the data item is shifted out of the shift register, it is necessary to extract the output item and the preceding n-1 data items c beats in advance and send them to the comparator array. That is, the storage item in the n-1th order register is taken as the output item to be output, and the SE in the 0th to n-2th order registers and the SE in the n-1th order are input and output into the comparator array together.

[0053] Please refer again Figure 6After completing the above comparison steps, the sorted sequence output by the shift register and its corresponding sort position number are sequentially stored and output. The method for performing the sorted storage is to write each data item in the sorted sequence into a random access memory unit using its corresponding sort position number as the write address. The method for performing the sorted output is to accumulate read addresses sequentially starting from 0 after the sorted sequence is completely stored, and output the sorted sequence from the random access memory unit read port. The sorting unit is composed of a random access memory unit (RAM) and an address accumulator. The random access memory unit includes a first random access memory unit and a second random access memory unit, which alternately perform sorted storage and sorted output in a ping-pong buffering manner. When the sequence end flag SEF output by the shift register is 1, the ping-pong selection signal is triggered. For the RAM performing storage, the data item output by the position sort position number calculation unit is written to the RAM using its accompanying output position sort position number as the address. For the RAM performing output, the read address is accumulated sequentially starting from 0, and the sorted sequence item is output from the RAM read port, completing the sorting process.

[0054] The sorting circuit described in this embodiment implements pipeline processing of comparison, sort position number calculation, and reordering operations. The comparison operation between data items and the sort position number calculation are performed in parallel, which greatly reduces the computational delay of the sorting operation. The total delay includes the shift register delay n+c, the reordering storage delay n, the reordering read delay n, and the 2-beat delay during the dual RAM input and output ping-pong selection, which is only about 2*n+2+c beats. It is significantly lower than the latency of the CPU / MCU-based solution, and the longer the length n of the sequence to be sorted, the greater the low latency advantage.

[0055] Example 2

[0056] This embodiment discloses a method for implementing an unsigned integer sorting circuit based on pipeline processing. An example is given based on the operation steps in Example 1.

[0057] The comparison operation of unsigned integers consumes one clock cycle, so c in Example 1 is 1; assuming the length of the sequence to be sorted is 10, n in the above technical solution is 10. Because the length of the selected shift register is equal to the sum of the length of the sequence to be sorted and the operation delay of the sorting circuit, and the delay of the sorting circuit is the number of delay cycles of the sorting circuit outputting the comparison result, please refer to Figure 3 , the shift register length is set to 11 steps, the input comparator array length is 9, and the output comparator array length is 9. Therefore, the data to be sorted is and end-of-sequence marker Input from the 0th order of the shift register in sequence, specifically:

[0058] Data to be sorted at beat 0 Compare with the sequence data to be sorted in the register between the 0th order and the i-1th order (including the 0th order and the i-1th order) in the shift register;

[0059] Data to be sorted at the first beat End of sequence marker The initial value of the sorting position sequence number 0 is stored in the 0th order register, and the sequence data to be sorted and the sequence end flag of the original 0th order to i-1th register are stored in the 1st order to i-1th order registers in sequence; the sorting position sequence number SIDX of the original 0th order to i-1th register is determined by the output results of the 0th to i-1th comparators in the input comparator array to determine whether SIDX is increased by 1, and the updated results are stored in the sorting position sequence numbers in the 1st order to i-1th order registers in sequence.

[0060] The data of the calculated sorting position and sorting position number, the data corresponding sequence end flag and the corresponding sorting position and sorting position number are output from the 10th stage of the shift register, specifically:

[0061] Data to be output at beat 0 and the first i The data to be sorted in the register between the beginning of the ith stage and the end of the 9th stage (including the ith and 9th stages) are compared, and at the same time, the output data receiver, the reordering unit, samples the data to be output from the 10th stage register. End of sequence marker Sorting position Sorting position serial number

[0062] At the first beat, the sequence data to be sorted and the sequence end flag of the original i-th to 9-th order registers are stored in sequence in the i+1-th to 10-th order registers; the sorting position sequence number SIDX of the original i-th to 9-th order registers is determined by whether SIDX is increased by 1 according to the output results of the i-th to 9-th comparators in the output comparator array, and the updated results are stored in sequence in the sorting position sequence number stored in the i+1-th to 10-th order registers.

[0063] Please refer again Figure 6The address lengths of the first and second random access memories are set to 10. SIDX, output by the sort position number calculation unit, is connected to the write address ports (waddr) of the first and second random access memories. SE, output by the sort position number calculation unit, is connected to the write data ports (wdata) of the first and second random access memories. After power-on reset, the write enable signal 1 defaults to enabling the write enable port (we) of the first random access memory. A high level of the SEF signal, output by the sort position number calculation unit, triggers the write enable signal to alternately switch between the write enable ports (we) of the first and second random access memories. The address accumulator defaults to 0 after power-on reset and resets to 0 after accumulating to 9. In other states, it increments by 1 per clock cycle. The output of the address accumulator is connected to the read address ports (raddr) of the first and second random access memories. The output sequence defaults to enabling the read data port (rdata) of the second random access memory after power-on reset and alternates between the read data ports (rdata) of the first and second random access memories after the address accumulator accumulates to 9.

[0064] In this embodiment, considering that the comparator calculation delay is 1 beat, and the random access memory storage and retrieval operation delays are 1 beat each, the delay from data input to output can be controlled to be fixed: the number of shift register orders (11) + random access memory storage delay (1) + sorting sequence length (10) + random access memory retrieval delay (1) = 23 beats. For the same length of the sequence to be sorted, the time complexity of the MCU / CPU-based solution is 10×log(10)=23.026. Considering that the read, compare, store, and instruction jump operations each have a delay of 1 beat, and the MCU / CPU has an ideal pipeline instruction processing capability, sorting a sequence of length 10 requires at least 23.026+4≈28 beats of delay. It can be seen that the present invention has obvious advantages over the MCU / CPU-based sorting solution in terms of processing delay, and this advantage will continue to expand as the length of the sequence to be sorted increases.

[0065] In terms of resource consumption, this embodiment uses an 11-step shift register, 18 unsigned integer comparators, 2 random access memories with an address length of 10, and a multiplexer for Figure 6The sorted data output selection in the CPU / MCU-based sorting scheme, as well as the register and logic resources consumed by some other functional maintenance circuits. In contrast, the sorting scheme based on MCU / CPU requires a MCU / CPU with complex functions, a data bus and an address bus for data interaction, and related functional maintenance circuits. Some random access memories may also be added as data caches according to the needs of the CPU / MCU. It can be seen that for the sorting work of sequences that are not too long, the hardware resources consumed by this embodiment have obvious advantages, and the shorter the sequence length, the more obvious the advantage. However, since the CPU / MCU in the CPU / MCU-based sorting scheme does not change its design as the sequence length increases, the increase in sequence length will only cause its internal cache and address bus to increase some resources. Therefore, as the sequence length increases, the resource-saving advantage of this embodiment relative to the MCU / CPU-based sorting scheme will continue to shrink until it exceeds a critical value, and this advantage will turn into a disadvantage.

[0066] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for implementing a sorting circuit based on pipeline processing, characterized in that: include: When performing a sorting operation, the sequence to be sorted is input into the sorting circuit in sequence according to the clock; The first data to be sorted will be directly stored into the first-order register of the shift register from the input port of the shift register, and the sorting sequence number corresponding to the input data will be set to 0; Starting from the second data to be sorted being placed at the input port of the shift register, the data to be sorted stored in each stage register of the shift register will be compared with the input port or the last stage data of the shift register, and according to the comparison result, it is determined whether to increase the sorting sequence number stored in itself by one, and the updated sorting sequence number together with the sorted data stored in the current stage register will be updated to the next stage register at the next clock; The shift register starts from the second stage, and performs comparison and judgment operations at each stage, outputting the data to be sorted and its position number in the sorted sequence at the output port of the shift register; Use the position number as the write address of the storage unit and the data to be sorted as the write data of the storage unit to write the data into the sorting storage unit; After all the data of the current sequence to be sorted has been written into the sorting storage unit, the read addresses are accumulated in sequence starting from the low address of the storage unit, and the sorted sequence is output from the read data output port of the storage unit.

2. The method for implementing a sorting circuit based on pipeline processing according to claim 1, wherein: The length of the selected shift register is equal to the sum of the length of the sequence to be sorted and the operation delay of the sorting circuit.

3. The method for implementing a sorting circuit based on pipeline processing according to claim 2, wherein: The sorting circuit is provided with an input comparison array, which is used to compare the storage items of each stage in the shift register with the input data items. When the data items of the sequence to be sorted are input to the shift register, the comparison method is as follows: For ascending sorting, when the stored item is greater than or equal to the input data item, the sort position number count corresponding to the stored item is increased by one, otherwise it remains unchanged; For descending sorting, when the stored item is less than or equal to the input data item, the sort position sequence number count corresponding to the stored item is increased by one, otherwise it remains unchanged.

4. The method for implementing a sorting circuit based on pipeline processing according to claim 3, wherein: When the last item of the sequence to be sorted has been input into the shift register, the data item to be output is compared with the unoutput storage item of the current sequence to be sorted stored in the shift register, and the sorting position sequence number count is updated according to the comparison result.

5. The method for implementing a sorting circuit based on pipeline processing according to claim 4, characterized in that: The sorting circuit is provided with an output comparison array, which is used to compare each item of the sequence to be sorted stored in each stage of the shift register. The comparison method is: For ascending sorting, when the stored item is larger than the data item to be output, the sort position number corresponding to the stored item is incremented by one, otherwise it remains unchanged. For descending sorting, when the stored item is smaller than the data item to be output, the sorting position number count corresponding to the stored item is increased by one, otherwise it remains unchanged.

6. A method for implementing a sorting circuit based on pipeline processing according to claim 5, characterized in that: After the output comparison array is executed, the sorting sequence output by the shift register and its corresponding sorting position number are sequentially stored and output in order; The execution method of the sorted storage is as follows: writing each data of the sorted sequence into a random storage unit using its corresponding sort position number as the write address; The execution method of the sorted output is as follows: after the sorted sequence performs the complete sorting, the read address is accumulated sequentially starting from 0, and the sorted sequence is output from the random storage unit read port.

7. A method for implementing a sorting circuit based on pipeline processing according to claim 6, characterized in that: When any sequence to be sorted is input, an end flag is added to the last data item of the sequence; the end flag is used to distinguish the sequence to be sorted newly input into the shift register from other sequences to be sorted waiting to be output.

8. The method for implementing a sorting circuit based on pipeline processing according to claim 2, wherein: The time delay of the sorting circuit is the delay beat number of the sorting circuit output comparison result, and the update order of each order position number in the shift register is greater than the output delay beat number of the sorting circuit.

9. A method for implementing a sorting circuit based on pipeline processing according to claim 6, characterized in that The random access memory unit includes a first random access memory unit and a second random access memory unit. The first random access memory unit and the second random access memory unit perform sequential storage and sequential output alternately in a ping-pong buffer manner.

10. A sorting circuit, used to execute the pipeline processing-based sorting circuit implementation method according to any one of claims 1 to 9, characterized in that: include: Sorting position number calculation unit and sorting unit; The sorting position number calculation unit includes: a shift register, an input comparator and an output comparator; wherein the input comparator is used to execute an input comparison array, and the output comparator is used to execute an output comparison array; The reordering unit includes a first random access memory, a second random access memory and an address accumulator.

Images