Architecture design and implementation method of multi-MCU system

Abstract

The present invention provides a system architecture design and implementation method for a multi-MCU system, comprising a master MCU and multiple slave MCUs, wherein the master MCU and the multiple slave MCUs are communicatively connected via a parallel backplane bus; wherein the backplane bus comprises a data bus, a control bus, and an address bus; wherein: the control vertical line comprises a read-write control line, a clock control line, and an interrupt control line, wherein the clock control line is time-division multiplexed and the control direction of the clock control line is consistent with the data transmission direction of the data bus; the system architecture can effectively ensure stable communication between the master MCU and the slave MCUs in an industrial system, and the entire system architecture is simple, effectively preventing the failure of a device from affecting the operation of the entire system, and the system has high data transmission efficiency and real-time performance, good system flexibility, and strong adaptability.

Description

Technical Field

[0001] The present invention relates to a bus control system, and in particular to a system architecture design and implementation method of a multi-MCU system. Background Art

[0002] In the industrial automation industry, a large number of devices are interconnected, with the master MCU writing data to the slave MCU and the master MCU reading data from the slave MCU;

[0003] In the existing transmission control system architecture, when a field device fails, it is easy for the failure to spread, thereby causing communication failure of the entire system. In addition, the existing technology has a complex structure, poor real-time data transmission and system flexibility.

[0004] Therefore, in order to solve the above technical problems, it is urgent to propose a new technical means. Summary of the Invention

[0005] In view of this, the system architecture design and implementation method of the multi-MCU system provided by the present invention can effectively ensure stable communication between the master MCU and the slave MCU in the industrial system. The entire system architecture is simple, effectively preventing the failure of a certain device from affecting the operation of the entire system. In addition, the data transmission efficiency and real-time performance are high, the system is flexible and adaptable.

[0006] The present invention provides a system architecture design and implementation method of a multi-MCU system, which includes a master MCU and multiple slave MCUs, wherein the master MCU and the multiple slave MCUs are communicatively connected via a parallel backplane bus;

[0007] The backplane bus includes a data bus, a control bus, and an address bus;

[0008] The control vertical line includes a read / write control line, a clock control line, and an interrupt control line, wherein the clock control line is time-division multiplexed and the control direction of the clock control line is consistent with the data transmission direction of the data bus.

[0009] Furthermore, when the master MCU writes data to the slave MCU:

[0010] The master MCU sends a clock control signal to the slave MCU, and the master MCU sends the write data from the storage unit of the master MCU to the I / O pin of the master MCU through DMA, and sends the write data to the slave MCU through the data bus;

[0011] The I / O pin of the slave MCU receives the clock instruction and write data sent by the master MCU, and the slave MCU starts DMA according to the clock signal, and then the slave MCU sends the write data received by the I / O pin to the storage unit of the slave MCU through DMA;

[0012] When the master MCU reads data from the slave MCU:

[0013] The slave MCU sends a clock control signal to the master MCU, and the slave MCU sends the read data from the storage unit of the slave MCU to the I / O pin of the slave MCU through DMA, and sends the read data to the master MCU through the data bus;

[0014] The I / O pin of the main MCU receives the clock signal and read data sent by the slave MCU, and the main MCU starts DMA according to the clock signal, and then the main MCU sends the read data received by the I / O pin to the storage unit of the main MCU through DMA.

[0015] Furthermore, the main MCU adopts a Cortex-M4 chip.

[0016] Furthermore, the slave MCU adopts a Cortex-M0 chip.

[0017] The beneficial effects of the present invention are as follows: Through the present invention, stable communication between the master MCU and the slave MCU in the industrial system can be effectively ensured, and the entire system architecture is simple, effectively preventing the failure of a certain device from affecting the operation of the entire system, and the data transmission efficiency and real-time performance are high, the system is flexible and adaptable. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The present invention will be further described below in conjunction with the accompanying drawings and embodiments:

[0019] Figure 1 Schematic diagram of the system architecture of the present invention.

[0020] Figure 2 A control timing diagram is written for the architecture of the present invention.

[0021] Figure 3 This is a read control timing diagram of the system architecture of the present invention.

[0022] Figure 4 Write a schematic diagram for the system architecture of the present invention.

[0023] Figure 5 A schematic diagram of the system architecture of the present invention is read. DETAILED DESCRIPTION

[0024] The present invention is further described in detail below with reference to the accompanying drawings:

[0025] The present invention provides a system architecture design and implementation method of a multi-MCU system, which includes a master MCU and multiple slave MCUs, wherein the master MCU and the multiple slave MCUs are communicatively connected via a parallel backplane bus;

[0026] The backplane bus includes a data bus, a control bus, and an address bus;

[0027] The control lines include read / write control lines, clock control lines, and interrupt control lines. The clock control lines are time-division multiplexed, and their control direction aligns with the data transmission direction of the data bus. This means that the clock control line is a single line, and its clock signal is sent in different directions during different operating periods, while remaining consistent with the data transmission direction.

[0028] The master MCU uses a Cortex-M4 chip, such as the STM32F407ZGT6, and the slave MCU uses a Cortex-M0 chip, such as the STM32L152RBT6. The entire system uses the Modbus TCP communication protocol for communication. This architecture effectively ensures stable communication between the master and slave MCUs in industrial systems. The architecture is simple, effectively preventing device failures from affecting the entire system. It also boasts high data transmission efficiency and real-time performance, along with excellent system flexibility and adaptability.

[0029] In this embodiment, further, when the master MCU writes data to the slave MCU:

[0030] The master MCU sends a clock control signal to the slave MCU, and the master MCU sends the write data from the storage unit of the master MCU to the I / O pin of the master MCU through DMA, and sends the write data to the slave MCU through the data bus;

[0031] The I / O pin of the slave MCU receives the clock instruction and write data sent by the master MCU, and the slave MCU starts DMA according to the clock signal, and then the slave MCU sends the write data received by the I / O pin to the storage unit of the slave MCU through DMA;

[0032] When the master MCU reads data from the slave MCU:

[0033] The slave MCU sends a clock control signal to the master MCU, and the slave MCU sends the read data from the storage unit of the slave MCU to the I / O pin of the slave MCU through DMA, and sends the read data to the master MCU through the data bus;

[0034] The I / O pin of the main MCU receives the clock signal and read data sent by the slave MCU, and the main MCU starts DMA according to the clock signal, and then the main MCU sends the read data received by the I / O pin to the storage unit of the main MCU through DMA.

[0035] like Figure 2 As shown: The main MCU performs write operation control timing as follows:

[0036] 1) The master MCU pulls up the R / W read / write control bus, indicating that the master MCU is performing a write operation. 2) The master MCU selects the slave MCU to communicate with through the six-bit address bus of Addr. 3) The master MCU pulls up the INT interrupt control bus, indicating that the master MCU has initiated communication. 4) When the master MCU is performing a write operation, the CLK clock control bus is output relative to the master MCU and input relative to the slave MCU. CLK uses PWM output, and PWM is generated by TIM1. 5) The master MCU generates a DMA request at each falling edge of PWM, causing the DMA2 controller to move data from the SRAM to the lower eight bits of the ODR register of the GPIOF port of the Data-8-bit data bus. 6) When the slave MCU receives an external interrupt request from the INT interrupt control line, it first enters the external interrupt service function, reads the level signal on the Addr six-bit address bus, that is, the address, and compares it with the hardware address of its own module slot. If they are different, the external interrupt flag is cleared and the interrupt service function is exited; if they are the same, the level signal of the R / W read-write control bus is read; if the level signal of the R / W read-write control bus is low, it indicates a read operation of the main MCU, and the module enters the corresponding read operation function for processing, and finally clears the flag and exits the external interrupt service function. If the level signal of the R / W read-write control bus is high, it indicates a write operation of the main MCU, and the module enters the corresponding write operation function for processing, and finally clears the external interrupt flag and exits the external interrupt service function.

[0037] like Figure 3 As shown: The main MCU performs read operation control timing as follows:

[0038] 1) The master MCU pulls down the R / W read / write control bus, indicating that the master MCU is performing a read operation. 2) The master MCU selects the slave MCU to communicate with via the six-bit address bus of Addr. 3) The master MCU pulls up the INT interrupt control bus, indicating that the master MCU has initiated communication. 4) During a read operation, the CLK clock control bus is an input to the master MCU and an output to the slave MCU. CLK uses PWM output, and the PWM wave is generated by TIM1. 5) The master MCU generates a DMA request on each rising edge of the PWM wave, causing DMA2 (the master MCU's DMA controller) to transfer data from the IDR register of the Data-8-bit data bus GPIO to the SRAM. 6) The slave MCU receives data from IN The external interrupt request of the T interrupt control line first enters the external interrupt service function, reads the level signal on the Addr six-bit address bus, that is, the address, and compares it with the hardware address of its own module slot. If they are different, clear the external interrupt flag and jump out of the interrupt service function; if they are the same, read the level signal of the R / W read-write control bus; if the level signal of the R / W read-write control bus is low, it indicates that the main MCU is reading operation, and the module enters the corresponding read operation function for processing, and finally clears the flag and jumps out of the external interrupt service function. If the level signal of the R / W read-write control bus is high, it indicates that the main MCU is writing operation, and the module enters the corresponding write operation function for processing, and finally clears the external interrupt flag and jumps out of the external interrupt service function.

[0039] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not limiting. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the purpose and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. A multi-MCU system architecture design and implementation method, characterized by: The system comprises a master MCU and a plurality of slave MCUs, wherein the master MCU and the plurality of slave MCUs are communicatively connected via a parallel backplane bus; The backplane bus includes a data bus, a control bus, and an address bus; The control vertical direction includes a read / write control line, a clock control line, and an interrupt control line, wherein the clock control line is time-division multiplexed and the control direction of the clock control line is consistent with the data transmission direction of the data bus; When the master MCU writes data to the slave MCU: The master MCU sends a clock control signal to the slave MCU, and the master MCU sends the write data from the storage unit of the master MCU to the I / O pin of the master MCU through DMA, and sends the write data to the slave MCU through the data bus; The I / O pin of the slave MCU receives the clock instruction and write data sent by the master MCU, and the slave MCU starts DMA according to the clock signal, and then the slave MCU sends the write data received by the I / O pin to the storage unit of the slave MCU through DMA; When the master MCU reads data from the slave MCU: The slave MCU sends a clock control signal to the master MCU, and the slave MCU sends the read data from the storage unit of the slave MCU to the I / O pin of the slave MCU through DMA, and sends the read data to the master MCU through the data bus; The I / O pin of the main MCU receives the clock signal and read data sent by the slave MCU, and the main MCU starts DMA according to the clock signal, and then the main MCU sends the read data received by the I / O pin to the storage unit of the main MCU through DMA.

2. The system architecture design and implementation method of the multi-MCU system according to claim 1 is characterized in that: The main MCU adopts a Cortex-M4 chip.

3. The system architecture design and implementation method of the multi-MCU system according to claim 1 is characterized in that: The slave MCU adopts a Cortex-M0 chip.

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