A high-efficiency circuit layout method and system

Abstract

The present application provides an efficient circuit layout method and system, which is specifically applied to the field of circuit design, including: roughly dividing the integrated circuit to obtain the initial layout of the integrated circuit; constructing a simplified directed weighted graph according to the initial layout and the edge length threshold; placing the rectangular units in the integrated circuit at the initial nodes of the simplified directed weighted graph; using a simulated annealing algorithm to move the rectangular units, calculating the degree of association, line length and aggregation between the moved rectangular units, and determining the objective function: outputting the optimal circuit layout solution according to the objective function. In this way, efficient and accurate circuit layout is achieved.

Description

Technical Field

[0001] The present application relates to the field of circuit design, and more specifically, to an efficient circuit layout method and system. Background Art

[0002] In today's rapidly developing social economy, the integrated circuit industry, the pillar of the information industry, is developing rapidly and its scale is increasing day by day. As integrated circuit process technology gradually approaches its physical limits, how to improve circuit efficiency and reduce circuit scale has become an urgent problem to be solved.

[0003] In the prior art, a search algorithm is usually used to implement circuit layout design. However, this method lacks flexibility, resulting in low chip operating efficiency. Summary of the invention

[0004] The purpose of the embodiments of the present invention is to provide an efficient circuit layout method and system, by moving rectangular units in a directed weighted graph, designing an objective function according to the degree of association, line length and aggregation between rectangular units, thereby improving work efficiency while controlling line length.

[0005] The specific technical solutions are as follows:

[0006] In a first aspect of an embodiment of the present invention, there is provided an efficient circuit layout method, comprising:

[0007] Step S1: roughly divide the integrated circuit to obtain an initial layout of the integrated circuit;

[0008] Step S2: constructing a directed weighted graph according to the initial layout; wherein the directed weighted graph includes an initial node and a plurality of directed edges with weights, and the nodes in the directed weighted graph correspond one-to-one to the rectangular units in the integrated circuit;

[0009] Step S3: Preset an edge length threshold, split the directed edges in the directed weighted graph whose weights are greater than the edge length threshold, and construct a simplified directed weighted graph;

[0010] Step S4: placing all rectangular cells in the integrated circuit at the initial nodes of the simplified directed weighted graph;

[0011] Step S5: Move the rectangular units according to the simulated annealing algorithm, calculate the association degree, line length and aggregation degree between the moved rectangular units, and determine the objective function:

[0012]

[0013] in, Represents a rectangular unit With rectangular unit The degree of correlation between Represents a rectangular unit With rectangular unit The length of the line between Represents a rectangular unit The degree of aggregation, Represents a rectangular unit Repeat this step until the objective function value is minimum, and then execute step S6;

[0014] Step S6: The layout result outputted according to the objective function is the optimal circuit layout solution.

[0015] Optionally, step S1: roughly dividing the integrated circuit to obtain an initial layout of the integrated circuit includes:

[0016] Initializing an integrated circuit; the integrated circuit includes a plurality of initial rectangular units;

[0017] Clustering the initial rectangular units, classifying all the initial rectangular units in the same cluster, and obtaining a plurality of classified, directionally connected rectangular units;

[0018] An initial layout of the integrated circuit is obtained according to the classified multiple directionally connected rectangular units.

[0019] Optionally, the step S2: constructing a directed weighted graph according to the initial layout includes:

[0020] The rectangular units in the initial layout are used as nodes of a graph, and the connection relationships between the rectangular units are used as directed edges of the graph;

[0021] Using a hierarchical clustering algorithm to calculate the weights of the directed edges;

[0022] A directed weighted graph is constructed according to the nodes, directed edges and weights of the directed edges.

[0023] Optionally, the step S3: presetting an edge length threshold, splitting the directed edges in the directed weighted graph whose weights are greater than the edge length threshold, and constructing a simplified directed weighted graph includes:

[0024] Preset a first edge length threshold and a second edge length threshold; wherein the first edge length threshold is smaller than the second edge length threshold;

[0025] If any weight in the directed weighted graph is greater than the second edge length threshold, cutting off the directed edge corresponding to the weight;

[0026] If any weight in the directed weighted graph is less than or equal to the second edge length threshold and greater than the first edge length threshold, split the directed edge corresponding to the weight;

[0027] If any weight in the directed weighted graph is less than or equal to the first edge length threshold, the directed edge corresponding to the weight is not processed;

[0028] Repeat the above steps to construct a simplified directed weighted graph.

[0029] Further, the splitting of the directed edge corresponding to the weight includes:

[0030] Preset segmentation parameters; the segmentation parameters ∈ [0, 1];

[0031] The directed edge corresponding to the weight is split according to the splitting parameter.

[0032] Optionally, the degree of association between the moved rectangular units is calculated using the following formula:

[0033]

[0034] in, Represents a rectangular unit To rectangular element The probability that there is a directed edge.

[0035] Optionally, the line length between the moved rectangular units is calculated using the following formula:

[0036]

[0037] in, Represents the matrix unit corresponding to the initial node The coordinate value of Represents a rectangular unit Relative to The coordinate value of It is a rectangular unit and matrix unit The maximum weight of the edges between them.

[0038] Optionally, the degree of aggregation between the moved rectangular units is calculated using the following formula:

[0039]

[0040]

[0041] Where N represents the total number of nodes in the simplified directed weighted graph, Represents a rectangular unit The number of out-degree nodes, Represents a rectangular unit The total length between the out-degree nodes, Represents a rectangular unit The number of in-degree nodes, Represents a rectangular unit The total length between the in-degree nodes; Represents a rectangular unit The number of out-degree nodes, Represents a rectangular unit The total length between the out-degree nodes, Represents a rectangular unit The number of in-degree nodes, Represents a rectangular unit The total length between the in-degree nodes and F represents the total length of the rectangular unit.

[0042] In another aspect of an embodiment of the present invention, there is provided an efficient circuit layout system, comprising:

[0043] An initial layout module, used to roughly divide the integrated circuit to obtain an initial layout of the integrated circuit;

[0044] A graph construction module, configured to construct a directed weighted graph according to the initial layout; wherein the directed weighted graph includes an initial node and a plurality of directed edges with weights, and the nodes in the directed weighted graph correspond one-to-one to the rectangular units in the integrated circuit;

[0045] A graph simplification module, configured to preset an edge length threshold, split the directed edges in the directed weighted graph whose weights are greater than the edge length threshold, and construct a simplified directed weighted graph;

[0046] The circuit layout module is used to place all rectangular cells in the integrated circuit at the initial node of the simplified directed weighted graph; move the rectangular cells according to the simulated annealing algorithm, calculate the degree of association, line length and aggregation between the moved rectangular cells, and determine the objective function:

[0047]

[0048] in, Represents a rectangular unit With rectangular unit The degree of correlation between Represents a rectangular unit With rectangular unit The length of the line between Represents a rectangular unit The degree of aggregation, Represents a rectangular unit Repeat this step until the objective function value is minimized and the layout result is output, which is the optimal circuit layout solution.

[0049] Optionally, the initial layout module is specifically used to:

[0050] Initializing an integrated circuit; the integrated circuit includes a plurality of initial rectangular units;

[0051] Clustering the initial rectangular units, classifying all the initial rectangular units in the same cluster, and obtaining a plurality of classified, directionally connected rectangular units;

[0052] An initial layout of the integrated circuit is obtained according to the classified multiple directionally connected rectangular units.

[0053] Optionally, the graph construction module is specifically used to:

[0054] The rectangular units in the initial layout are used as nodes of a graph, and the connection relationships between the rectangular units are used as directed edges of the graph;

[0055] Using a hierarchical clustering algorithm to calculate the weights of the directed edges;

[0056] A directed weighted graph is constructed according to the nodes, directed edges and weights of the directed edges.

[0057] Optionally, the graph simplification module is specifically used for:

[0058] Preset a first edge length threshold and a second edge length threshold; wherein the first edge length threshold is smaller than the second edge length threshold;

[0059] If any weight in the directed weighted graph is greater than the second edge length threshold, cutting off the directed edge corresponding to the weight;

[0060] If any weight in the directed weighted graph is less than or equal to the second edge length threshold and greater than the first edge length threshold, split the directed edge corresponding to the weight;

[0061] If any weight in the directed weighted graph is less than or equal to the first edge length threshold, the directed edge corresponding to the weight is not processed;

[0062] Repeat the above steps to construct a simplified directed weighted graph.

[0063] Further, the splitting of the directed edge corresponding to the weight includes:

[0064] Preset segmentation parameters; the segmentation parameters ∈ [0, 1];

[0065] The directed edge corresponding to the weight is split according to the splitting parameter.

[0066] Optionally, the degree of association between the moved rectangular units is calculated using the following formula:

[0067]

[0068] in, Represents a rectangular unit To rectangular element The probability that there is a directed edge.

[0069] Optionally, the line length between the moved rectangular units is calculated using the following formula:

[0070]

[0071] in, Represents the matrix unit corresponding to the initial node The coordinate value of Represents a rectangular unit Relative to The coordinate value of It is a rectangular unit and matrix unit The maximum weight of the edges between them.

[0072] Optionally, the degree of aggregation between the moved rectangular units is calculated using the following formula:

[0073]

[0074]

[0075] Where N represents the total number of nodes in the simplified directed weighted graph, Represents a rectangular unit The number of out-degree nodes, Represents a rectangular unit The total length between the out-degree nodes, Represents a rectangular unit The number of in-degree nodes, Represents a rectangular unit The total length between the in-degree nodes; Represents a rectangular unit The number of out-degree nodes, Represents a rectangular unit The total length between the out-degree nodes, Represents a rectangular unit The number of in-degree nodes, Represents a rectangular unit The total length between the in-degree nodes and F represents the total length of the rectangular unit.

[0076] Beneficial effects:

[0077] (1) A directed weighted graph is introduced to realize circuit layout. Specifically, the integrated circuit is roughly divided by clustering to obtain an initial layout. A directed weighted graph is constructed based on the initial layout, and it is simplified by segmentation. The circuit layout result obtained in this way is efficient and accurate, which can improve the working efficiency of the chip.

[0078] (2) By using the first edge length threshold and the second edge length threshold, the cutting operation and the splitting operation of the directed edge are selected, and the splitting parameters are preset to realize the splitting of the directed edge, thereby controlling the line length and improving the layout efficiency.

[0079] (3) All rectangular cells in the integrated circuit are placed at the initial nodes of the simplified directed weighted graph, and the rectangular cells are moved according to the simulated annealing algorithm. The degree of association, line length and aggregation degree between the moved rectangular cells are calculated, and a new objective function is designed. The layout result is output according to the iteration of the objective function. In this way, the optimal layout can be found while ensuring circuit connectivity, reducing congestion and controlling line length. BRIEF DESCRIPTION OF THE DRAWINGS

[0080] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0081] Figure 1 It is a flowchart of an efficient circuit layout method provided by an embodiment of the present application;

[0082] Figure 2 is a flow chart of a layout result output method provided in an embodiment of the present application;

[0083] Figure 3 It is a structural schematic diagram of an efficient circuit layout system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0084] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0085] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0086] The embodiment of the present application provides an efficient circuit layout method and system, including: roughly dividing the integrated circuit to obtain the initial layout of the integrated circuit; constructing a simplified directed weighted graph according to the initial layout and the edge length threshold; placing the rectangular units in the integrated circuit at the initial nodes of the simplified directed weighted graph; using a simulated annealing algorithm to move the rectangular units, calculating the degree of association, line length and aggregation between the moved rectangular units, and determining the objective function: outputting the optimal circuit layout solution according to the objective function. In this way, efficient and accurate circuit layout is achieved.

[0087] The efficient circuit layout method and system can be integrated into electronic devices, which can be terminals, servers and other devices. The terminal can be a light field camera, a car camera, a mobile phone, a tablet computer, a smart Bluetooth device, a laptop computer, or a personal computer (PC). The server can be a single server or a server cluster composed of multiple servers.

[0088] It is understandable that the efficient circuit layout method and system of this embodiment can be executed on a terminal, on a server, or jointly by a terminal and a server. The above examples should not be construed as limiting the present application.

[0089] Embodiment 1

[0090] Figure 1 FIG. 1 is a flow chart showing an efficient circuit layout method provided by an embodiment of the present application. Please refer to FIG. Figure 1 , specifically including the following steps:

[0091] Step S110: roughly divide the integrated circuit to obtain an initial layout of the integrated circuit.

[0092] Specifically, an integrated circuit is initialized; the integrated circuit includes a plurality of initial rectangular units; the initial rectangular units are clustered, and all initial rectangular units in the same cluster are classified to obtain a plurality of classified rectangular units with direction connections; and an initial layout of the integrated circuit is obtained based on the plurality of classified rectangular units with direction connections.

[0093] Step S120: constructing a directed weighted graph according to the initial layout.

[0094] The directed weighted graph includes an initial node and a plurality of directed edges with weights, and the nodes in the directed weighted graph correspond one-to-one to the rectangular units in the integrated circuit.

[0095] Specifically, the rectangular units in the initial layout are used as nodes of the graph, and the connection relationships between the rectangular units are used as directed edges of the graph; a hierarchical clustering algorithm is used to calculate the weights of the directed edges; and a directed weighted graph is constructed based on the nodes, directed edges and the weights of the directed edges.

[0096] Step S130: preset an edge length threshold, split the directed edges in the directed weighted graph whose weights are greater than the edge length threshold, and construct a simplified directed weighted graph.

[0097] In one implementation, step S130 may specifically include the following steps:

[0098] Step S131: preset a first side length threshold and a second side length threshold; wherein the first side length threshold is smaller than the second side length threshold.

[0099] Step S132: If any weight in the directed weighted graph is greater than the second edge length threshold, the directed edge corresponding to the weight is cut off. If any weight in the directed weighted graph is less than or equal to the second edge length threshold and greater than the first edge length threshold, the directed edge corresponding to the weight is split. If any weight in the directed weighted graph is less than or equal to the first edge length threshold, the directed edge corresponding to the weight is not processed. Repeat the above steps to construct a simplified directed weighted graph.

[0100] Furthermore, a segmentation parameter is preset; the segmentation parameter∈[0,1]; and the directed edge corresponding to the weight is segmented according to the segmentation parameter.

[0101] This cutting and segmenting method controls line length and improves layout efficiency.

[0102] Step S140: placing all rectangular cells in the integrated circuit at initial nodes of the simplified directed weighted graph.

[0103] Step S150: moving the rectangular units according to the simulated annealing algorithm, calculating the association degree, line length and aggregation degree between the moved rectangular units, and determining the objective function.

[0104] Step S160: Layout results output according to the objective function.

[0105] Among them, the layout result is the optimal circuit layout solution.

[0106] This results in an efficient and accurate circuit layout, which can improve chip operating efficiency.

[0107] Embodiment 2

[0108] Figure 2 A schematic diagram showing the flow of the layout result output method provided in the embodiment of the present application is shown. Figure 2 , specifically including the following steps:

[0109] S210, calculating the degree of association between the moved rectangular units, the formula is as follows:

[0110]

[0111] in, Represents a rectangular unit To rectangular element The probability that there is a directed edge.

[0112] S220, calculating the line length between the moved rectangular units, the formula is as follows:

[0113]

[0114] in, Represents the matrix unit corresponding to the initial node The coordinate value of Represents a rectangular unit Relative to The coordinate value of It is a rectangular unit and matrix unit S230, calculate the degree of aggregation between the moved rectangular units, the formula is as follows:

[0115]

[0116]

[0117] Where N represents the total number of nodes in the simplified directed weighted graph, Represents a rectangular unit The number of out-degree nodes, Represents a rectangular unit The total length between the out-degree nodes, Represents a rectangular unit The number of in-degree nodes, Represents a rectangular unit The total length between the in-degree nodes; Represents a rectangular unit The number of out-degree nodes, Represents a rectangular unit The total length between the out-degree nodes, Represents a rectangular unit The number of in-degree nodes, Represents a rectangular unit The total length between the in-degree nodes and F represents the total length of the rectangular unit.

[0118] S240, iterative calculation of the objective function:

[0119]

[0120] in, Represents a rectangular unit With rectangular unit The degree of correlation between Represents a rectangular unit With rectangular unit The length of the line between Represents a rectangular unit The degree of aggregation, Represents a rectangular unit degree of aggregation.

[0121] S240. Output the layout result when the objective function value is minimum.

[0122] This method can find the optimal layout while ensuring circuit connectivity, reducing congestion and controlling line length.

[0123] Embodiment 3

[0124] To implement the above method embodiments, this embodiment also provides an efficient circuit layout system, such as Figure 3 As shown, the system includes:

[0125] The initial layout module 310 is used to roughly divide the integrated circuit to obtain an initial layout of the integrated circuit.

[0126] The graph construction module 320 is used to construct a directed weighted graph according to the initial layout.

[0127] The directed weighted graph includes an initial node and a plurality of directed edges with weights, and the nodes in the directed weighted graph correspond one-to-one to the rectangular units in the integrated circuit.

[0128] The graph simplification module 330 is used to preset an edge length threshold, split the directed edges whose weights are greater than the edge length threshold in the directed weighted graph, and construct a simplified directed weighted graph.

[0129] The circuit layout module 340 is used to place all rectangular cells in the integrated circuit at the initial node of the simplified directed weighted graph; move the rectangular cells according to the simulated annealing algorithm, calculate the degree of association, line length and aggregation degree between the moved rectangular cells, and determine the objective function:

[0130]

[0131] in, Represents a rectangular unit With rectangular unit The degree of correlation between Represents a rectangular unit With rectangular unit The length of the line between Represents a rectangular unit The degree of aggregation, Represents a rectangular unit Repeat this step until the objective function value is minimized and the layout result is output, which is the optimal circuit layout solution.

[0132] Optionally, the initial layout module 310 is specifically used to: initialize an integrated circuit; the integrated circuit includes multiple initial rectangular units; cluster the initial rectangular units, classify all initial rectangular units in the same cluster to obtain multiple classified rectangular units with direction connections; obtain the initial layout of the integrated circuit based on the multiple classified rectangular units with direction connections.

[0133] Optionally, the graph construction module 320 is specifically used to: use the rectangular units in the initial layout as nodes of the graph, and the connection relationships between the rectangular units as directed edges of the graph; use a hierarchical clustering algorithm to calculate the weights of the directed edges; and construct a directed weighted graph based on the nodes, directed edges, and the weights of the directed edges.

[0134] Optionally, the graph simplification module 330 is specifically used to: preset a first edge length threshold and a second edge length threshold; wherein the first edge length threshold is less than the second edge length threshold; if any weight in the directed weighted graph is greater than the second edge length threshold, the directed edge corresponding to the weight is cut off; if any weight in the directed weighted graph is less than or equal to the second edge length threshold, and greater than the first edge length threshold, the directed edge corresponding to the weight is split; if any weight in the directed weighted graph is less than or equal to the first edge length threshold, the directed edge corresponding to the weight is not processed; repeat the above steps to construct a simplified directed weighted graph.

[0135] Furthermore, the segmenting of the directed edge corresponding to the weight includes: presetting a segmentation parameter; the segmentation parameter∈[0,1]; and segmenting the directed edge corresponding to the weight according to the segmentation parameter.

[0136] Optionally, the degree of association between the moved rectangular units is calculated using the following formula:

[0137]

[0138] in, Represents a rectangular unit To rectangular element The probability that there is a directed edge.

[0139] Optionally, the line length between the moved rectangular units is calculated using the following formula:

[0140]

[0141] in, Represents the matrix unit corresponding to the initial node The coordinate value of Represents a rectangular unit Relative to The coordinate value of It is a rectangular unit and matrix unit The maximum weight of the edges between them.

[0142] Optionally, the degree of aggregation between the moved rectangular units is calculated using the following formula:

[0143]

[0144]

[0145] Where N represents the total number of nodes in the simplified directed weighted graph, Represents a rectangular unit The number of out-degree nodes, Represents a rectangular unit The total length between the out-degree nodes, Represents a rectangular unit The number of in-degree nodes, Represents a rectangular unit The total length between the in-degree nodes; Represents a rectangular unit The number of out-degree nodes, Represents a rectangular unit The total length between the out-degree nodes, Represents a rectangular unit The number of in-degree nodes, Represents a rectangular unit The total length between the in-degree nodes and F represents the total length of the rectangular unit.

[0146] Therefore, the efficient circuit layout system can find the optimal layout while ensuring circuit connectivity, reducing congestion and controlling line length, thereby improving chip operating efficiency.

[0147] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the modules / units / sub-units / components in the above-described device can refer to the corresponding process in the aforementioned method embodiment and will not be repeated here.

[0148] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0149] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0150] In addition, each functional unit in the embodiments provided in the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0151] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0152] It should be noted that similar numbers and letters represent similar items in the following figures. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description and are not to be understood as indicating or implying relative importance.

[0153] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The protection scope of the present application is not limited thereto. Although the present application is described in detail with reference to the above-mentioned embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-mentioned embodiments within the technical scope disclosed in the present application, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application. They should all be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. An efficient circuit layout method, characterized in that: The method includes: Step S1: roughly divide the integrated circuit to obtain an initial layout of the integrated circuit; Step S2: constructing a directed weighted graph according to the initial layout; wherein the directed weighted graph includes an initial node and a plurality of directed edges with weights, and the nodes in the directed weighted graph correspond one-to-one to the rectangular units in the integrated circuit; Step S3: Preset an edge length threshold, split the directed edges in the directed weighted graph whose weights are greater than the edge length threshold, and construct a simplified directed weighted graph; Step S4: placing all rectangular cells in the integrated circuit at the initial nodes of the simplified directed weighted graph; Step S5: Move the rectangular units according to the simulated annealing algorithm, calculate the association degree, line length and aggregation degree between the moved rectangular units, and determine the objective function: ； in, Represents a rectangular unit With rectangular unit The degree of correlation between Represents a rectangular unit With rectangular unit The line length between Represents a rectangular unit The degree of aggregation, Represents a rectangular unit Repeat this step until the objective function value is minimum, and then execute step S6; Step S6: The layout result outputted according to the objective function is the optimal circuit layout solution.

2. The efficient circuit layout method according to claim 1, characterized in that: The step S1: roughly dividing the integrated circuit to obtain the initial layout of the integrated circuit includes: Initializing an integrated circuit; the integrated circuit includes a plurality of initial rectangular units; Clustering the initial rectangular units, classifying all the initial rectangular units in the same cluster, and obtaining a plurality of classified, directionally connected rectangular units; An initial layout of the integrated circuit is obtained according to the classified multiple directionally connected rectangular units.

3. The efficient circuit layout method according to claim 1, characterized in that: The step S2: constructing a directed weighted graph according to the initial layout, including: The rectangular units in the initial layout are used as nodes of a graph, and the connection relationships between the rectangular units are used as directed edges of the graph; Using a hierarchical clustering algorithm to calculate the weights of the directed edges; A directed weighted graph is constructed according to the nodes, directed edges and weights of the directed edges.

4. The efficient circuit layout method according to claim 1, characterized in that: The step S3: presetting an edge length threshold, splitting the directed edges in the directed weighted graph whose weights are greater than the edge length threshold, and constructing a simplified directed weighted graph, comprises: Preset a first edge length threshold and a second edge length threshold; wherein the first edge length threshold is smaller than the second edge length threshold; If any weight in the directed weighted graph is greater than the second edge length threshold, cutting off the directed edge corresponding to the weight; If any weight in the directed weighted graph is less than or equal to the second edge length threshold and greater than the first edge length threshold, split the directed edge corresponding to the weight; If any weight in the directed weighted graph is less than or equal to the first edge length threshold, the directed edge corresponding to the weight is not processed; Repeat the above steps to construct a simplified directed weighted graph.

5. The efficient circuit layout method according to claim 4, characterized in that: The step of splitting the directed edge corresponding to the weight includes: Preset segmentation parameters; the segmentation parameters ∈ [0, 1]; The directed edge corresponding to the weight is split according to the splitting parameter.

6. The efficient circuit layout method according to claim 1, characterized in that: Calculate the degree of association between the moved rectangular units. The formula is as follows: ； in, Represents a rectangular unit To rectangular element The probability that there is a directed edge.

7. The efficient circuit layout method according to claim 1, characterized in that: Calculate the line length between the moved rectangular units using the following formula: ； in, Represents the matrix unit corresponding to the initial node The coordinate value of Represents a rectangular unit Relative to The coordinate value of It is a rectangular unit and matrix unit The maximum weight of the edges between them.

8. The efficient circuit layout method according to claim 1, characterized in that: Calculate the degree of aggregation between the moved rectangular units. The formula is as follows: ； ； Where N represents the total number of nodes in the simplified directed weighted graph, Represents a rectangular unit The number of out-degree nodes, Represents a rectangular unit The total length between the out-degree nodes, Represents a rectangular unit The number of in-degree nodes, Represents a rectangular unit The total length between the in-degree nodes; Represents a rectangular unit The number of out-degree nodes, Represents a rectangular unit The total length between the out-degree nodes, Represents a rectangular unit The number of in-degree nodes, Represents a rectangular unit The total length between the in-degree nodes and F represents the total length of the rectangular unit.

9. An efficient circuit layout system, characterized in that: The system includes: An initial layout module, used to roughly divide the integrated circuit to obtain an initial layout of the integrated circuit; A graph construction module, configured to construct a directed weighted graph according to the initial layout; wherein the directed weighted graph includes an initial node and a plurality of directed edges with weights, and the nodes in the directed weighted graph correspond one-to-one to the rectangular units in the integrated circuit; A graph simplification module, configured to preset an edge length threshold, split the directed edges in the directed weighted graph whose weights are greater than the edge length threshold, and construct a simplified directed weighted graph; The circuit layout module is used to place all rectangular cells in the integrated circuit at the initial node of the simplified directed weighted graph; move the rectangular cells according to the simulated annealing algorithm, calculate the degree of association, line length and aggregation between the moved rectangular cells, and determine the objective function: ； in, Represents a rectangular unit With rectangular unit The degree of correlation between Represents a rectangular unit With rectangular unit The line length between Represents a rectangular unit The degree of aggregation, Represents a rectangular unit The degree of aggregation; repeat the determination process of the objective function until the layout result is output when the objective function value is minimum, which is the optimal circuit layout solution.

10. The efficient circuit layout system according to claim 9, characterized in that: The initial layout module is specifically used for: Initializing an integrated circuit; the integrated circuit includes a plurality of initial rectangular units; Clustering the initial rectangular units, classifying all the initial rectangular units in the same cluster, and obtaining a plurality of classified, directionally connected rectangular units; An initial layout of the integrated circuit is obtained according to the classified multiple directionally connected rectangular units.

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