Display panels and electronic terminals

Abstract

The present invention discloses a display panel and an electronic terminal, comprising an insulating substrate, and a plurality of data lines arranged on the insulating substrate and electrically connected to a source driving circuit, wherein the source driving circuit in the present invention comprises a first module and a second module arranged on the insulating substrate, so as to reduce the size of the supporting module or device including but not limited to a chip, thereby reducing the cost, and the gating part in the present invention is connected between the first module and the second module, and is used to control the output pins of the first module to be electrically connected to different input pins of the second module at different times, so that the number of output pins of the first module is different from the number of input pins of the second module, so as to reduce the size of at least one of the first module and the second module, thereby reducing the cost.

Description

Technical Field

[0001] The present invention relates to the field of display technology, in particular to the field of display panel manufacturing technology, and specifically to a display panel and an electronic terminal. Background Art

[0002] Display panels can process electrical signals to display images and transmit information, and have become an indispensable part of life and work.

[0003] At present, the driving circuit in the display panel includes multiple functional parts. Due to the limitation of the process capability of the driving circuit, the size of the devices in the functional parts cannot be made small enough, and the number of devices in some functional parts is large, resulting in a large occupied area of ​​the corresponding functional parts and the occupied area of ​​the driving circuit as a whole, thereby increasing the cost of the substrate used to carry the driving circuit.

[0004] Therefore, the existing problem of the driving circuit in the display panel occupying a large area and causing an increase in the cost of the substrate used for carrying the circuit needs to be improved urgently. Summary of the invention

[0005] Embodiments of the present invention provide a display panel and an electronic terminal to solve the technical problem that a driving circuit in an existing display panel occupies a large area, which results in an increased cost of a substrate for carrying the circuit.

[0006] An embodiment of the present invention provides a display panel, including:

[0007] Insulating substrate;

[0008] A plurality of data lines are arranged on the insulating substrate;

[0009] A source driving circuit, electrically connected to the plurality of data lines, comprises a first module and a second module disposed on the insulating substrate;

[0010] In which, the source driving circuit also includes a gating module arranged on the insulating substrate and connected between multiple output pins of the first module and multiple input pins of the second module, the number of output pins of the first module is different from the number of input pins of the second module, and the gating module is used to control the output pins of the first module to be electrically connected to different input pins of the second module at different times.

[0011] In one embodiment, it comprises a signal generating module, a signal storage module and a signal output module, wherein the signal storage module is connected between a plurality of the signal generating modules and a plurality of the signal output modules;

[0012] The first module includes one of the signal generating module, the signal storing module and the signal output module, and the second module includes one of the signal generating module, the signal storing module and the signal output module which is different from the second module.

[0013] In one embodiment, the signal generating module, the signal storing module and the signal output module all include thin film transistors, and the thin film transistors are disposed on the insulating substrate.

[0014] In one embodiment, one of the first module and the second module includes the signal storage module, and the other of the first module and the second module includes the signal output module;

[0015] Wherein, the display panel further includes a semiconductor device electrically connected to the display panel, and the semiconductor device includes the signal generating module.

[0016] In one embodiment, the selection module includes multiple input terminals, multiple output terminals and multiple control terminals, the input terminals are connected to the corresponding output pins of the first module, the output terminals are connected to the corresponding input pins of the second module, the number of the input terminals is different from the number of the output terminals, and the control terminals are used to load control signals so that the input terminals are electrically connected to different output terminals at different times.

[0017] In one embodiment, the first module includes a signal generating module, and the second module includes a signal storing module;

[0018] Wherein, the input end is connected to the output pin of the signal generating module, the multiple output ends of the gating module include a first output end and a second output end, the first output end is connected to the first input pin of the corresponding signal storage module, and the second output end is connected to the second input pin of the corresponding signal storage module;

[0019] The signal storage module is used to store the first data generated by the signal generation module in the first time period and the second data generated by the signal generation module in the second time period.

[0020] In one embodiment, the source driving circuit further includes a signal output module electrically connected between the signal storage module and the plurality of data lines;

[0021] Wherein, at the same time, the signal storage module is used to transmit the first data and the second data to the signal output module.

[0022] In one embodiment, the gating module includes a plurality of first transistors and second transistors;

[0023] Among them, the source of the first transistor and the source of the second transistor are configured as the corresponding input terminals, the gate of the first transistor and the gate of the second transistor are configured as the corresponding control terminals, the drain of the first transistor is configured as the corresponding first output terminal, and the drain of the second transistor is configured as the corresponding second output terminal.

[0024] In one embodiment, the first module includes a signal storage module, the second module includes a signal output module, and the signal output module is connected between the signal storage module and the plurality of data lines;

[0025] Among them, the multiple input ends of the gating module include a first input end and a second input end, and the multiple output ends of the gating module include a first output end and a second output end, the first input end is connected to the first output pin of the signal storage module, the second input end is connected to the second output pin of the signal storage module, the first output end is connected to the first input pin of the corresponding signal output module, and the second output end is connected to the second input pin of the corresponding signal output module.

[0026] In one embodiment, the source driving circuit further includes a signal generating module electrically connected to the signal storage;

[0027] Among them, at the same time, multiple signal generating modules are used to generate first data and second data, and the first input pin of the signal output module is used to receive the corresponding first data while the second input pin of the signal output module is used to receive the corresponding second data.

[0028] In one embodiment, the gating module includes a first transistor, a second transistor, a third transistor and a fourth transistor;

[0029] Among them, the source of the first transistor and the source of the second transistor are configured as the first input terminal, the source of the third transistor and the source of the fourth transistor are configured as the corresponding second input terminal, the gate of the first transistor, the gate of the second transistor, the gate of the third transistor and the gate of the fourth transistor are configured as the corresponding control terminals, the drain of the first transistor and the drain of the third transistor are configured as the corresponding first output terminal, and the drain of the second transistor and the drain of the fourth transistor are configured as the corresponding second output terminal.

[0030] In one embodiment, the first module includes a signal output module, the second module includes a signal storage module, and the plurality of data lines include a plurality of first data lines, a plurality of second data lines, and a plurality of third data lines;

[0031] Wherein, the gating module comprises a first gating module connected between the first module and the second module, and a second gating module connected between the first module and the plurality of data lines;

[0032] Wherein, the plurality of input terminals of the first gating module include a first input terminal, a second input terminal and a third input terminal, the plurality of output terminals of the first gating module include a first output terminal, the first input terminal is connected to a first output pin of the signal storage module, the second input terminal is connected to a second output pin of the signal storage module, the third input terminal is connected to a third output pin of the signal storage module, and the first output terminal is connected to an input pin of the corresponding signal output module;

[0033] Among them, the multiple input terminals of the second selection module include a fourth input terminal, the multiple output terminals of the second selection module include a second output terminal, a third output terminal and a fourth output terminal, the fourth input terminal is connected to the corresponding output pin of the signal output module, the second output terminal is connected to the corresponding first data line, the third output terminal is connected to the corresponding second data line, and the fourth output terminal is connected to the corresponding third data line.

[0034] In one embodiment, the source driving circuit further comprises a signal generating module electrically connected to the signal storage module;

[0035] Among them, the signal output module is used to transmit the first data output by the first output pin of the signal generating module to the corresponding first data line, and to transmit the second data output by the second output pin of the signal generating module to the corresponding second data line, and to transmit the third data output by the third output pin of the signal generating module to the corresponding third data line.

[0036] In one embodiment, the first gating module includes a first transistor, a second transistor, and a third transistor;

[0037] Among them, the source of the first transistor is configured as the first input terminal, the drain of the second transistor is configured as the second input terminal, the drain of the third transistor is configured as the corresponding third input terminal, the gate of the first transistor, the gate of the second transistor and the gate of the third transistor are configured as the corresponding control terminals, and the drain of the first transistor, the drain of the second transistor and the drain of the third transistor are configured as the corresponding first output terminal.

[0038] In one embodiment, the second gating module includes a fourth transistor, a fifth transistor, and a sixth transistor;

[0039] Among them, the source of the fourth transistor, the source of the fifth transistor and the source of the sixth transistor are configured as the fourth input terminal, the gate of the fourth transistor, the gate of the fifth transistor and the gate of the sixth transistor are configured as the corresponding control terminal, the drain of the fourth transistor is configured as the second output terminal, the drain of the fifth transistor is configured as the corresponding third output terminal, and the drain of the sixth transistor is configured as the corresponding fourth output terminal.

[0040] An embodiment of the present invention provides an electronic terminal, which includes any display panel as described above.

[0041] The display panel and electronic terminal provided by the embodiment of the present invention include: an insulating substrate; a plurality of data lines, arranged on the insulating substrate; a source driving circuit, electrically connected to the plurality of data lines, including a first module and a second module arranged on the insulating substrate; wherein the source driving circuit also includes a gating module arranged on the insulating substrate and connected between a plurality of output pins of the first module and a plurality of input pins of the second module, the number of output pins of the first module is different from the number of input pins of the second module, and the gating module is used to control the output pins of the first module to be electrically connected to different input pins of the second module at different times. On the one hand, at least the first module and the second module in the source driving circuit of the present invention are arranged on the insulating substrate to reduce the size of the chip including but not limited to the chip used to carry the module or device, on the other hand, the gating part of the present invention is connected between the first module and the second module, and is used to control the output pins of the first module to be electrically connected to different input pins of different second modules at different times, so that the number of output pins of the first module is different from the number of input pins of the second module, so as to reduce the size of at least one of the first module and the second module, and both of the above aspects can reduce the cost of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The technical solutions and other beneficial effects of the present invention will be made apparent by describing in detail the specific embodiments of the present invention in conjunction with the accompanying drawings.

[0043] Figure 1 A schematic top view of a display panel provided by an embodiment of the present invention.

[0044] Figure 2 A schematic top view of another display panel provided by an embodiment of the present invention.

[0045] Figure 3 A schematic top view of another display panel provided by an embodiment of the present invention.

[0046] Figure 4A schematic diagram of the structure of a gating unit provided in an embodiment of the present invention.

[0047] Figure 5 A schematic structural diagram of a source driving circuit provided by an embodiment of the present invention.

[0048] Figure 6 A circuit diagram of a gating unit provided in an embodiment of the present invention.

[0049] Figure 7 A schematic structural diagram of another source driving circuit provided by an embodiment of the present invention.

[0050] Figure 8 A circuit diagram of another gating unit provided in an embodiment of the present invention.

[0051] Fig. 9 A schematic diagram of the structure of yet another source driving circuit provided by an embodiment of the present invention.

[0052] Fig.10 A circuit diagram of a first gating unit provided in an embodiment of the present invention.

[0053] Fig.11 A circuit diagram of a second gating unit provided in an embodiment of the present invention.

[0054] Fig.12 A schematic diagram of the structure of another source driving circuit provided by an embodiment of the present invention.

[0055] Fig.13 A schematic structural diagram of the minimum unit in the shift register and latch provided in an embodiment of the present invention.

[0056] Fig.14 The specific circuit structure of the level converter provided by the embodiment of the present invention.

[0057] Fig.15 A specific circuit structure of a decoder provided by an embodiment of the present invention.

[0058] Fig.16 Another specific circuit structure of a decoder provided by an embodiment of the present invention.

[0059] Fig.17 The specific circuit structure of the digital-to-analog converter provided by the embodiment of the present invention. DETAILED DESCRIPTION

[0060] The following will be combined with the drawings in the embodiments of the present invention to clearly and continuously describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0061] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "between", "connected", "side", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first", "second", etc. are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0062] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0063] An embodiment of the present invention provides a display panel, which includes but is not limited to the following embodiments and combinations of the following embodiments.

[0064] In one embodiment, if Figure 1 and Figure 2 As shown, the display panel 100 includes: an insulating substrate 110; a plurality of data lines 101, which are arranged on the insulating substrate 110; a source driving circuit 20, which is electrically connected to the plurality of data lines 101, and includes a first module 111 and a second module 112, which are arranged on the insulating substrate 110; wherein, the source driving circuit 20, which is arranged on the insulating substrate 110, also includes a gating module 113 connected between a plurality of output pins of the first module 111 and a plurality of input pins of the second module 112, the number of output pins of the first module 111 is different from the number of input pins of the second module 112, and the gating module 113 is used to control the output pins of the first module 111 to be electrically connected to different input pins of the second module 112 at different times.

[0065] Specifically, the first module 111 may include multiple first parts 201, the second module 112 may include multiple second parts 202, the gating module 113 may include multiple gating parts 200, the multiple gating parts 200 are connected between the multiple first parts 201 and the multiple second parts 202, the number of the first parts 201 is different from the number of the second parts 202, and the gating parts 200 are used to control the first parts 201 to be electrically connected to different second parts 202 at different times. Among them, each first part 201 includes an input pin and an output pin, and each second part 202 includes an input pin and an output pin; combined with the above discussion, it can be seen that when the first module 111 transmits a signal to the second module 112, it can be considered that the number of output pins of the first module 111 is equal to the number of the first part 201, and the number of input pins of the second module 112 is equal to the number of the second part 202. Similarly, when the second module 112 transmits a signal to the first module 111, it can be considered that the number of output pins of the second module 112 is equal to the number of the second part 202, and the number of input pins of the first module 111 is equal to the number of the first part 201.

[0066] Specifically, Figure 1 and Figure 2 As shown, the insulating substrate 110 may include a display area A1 and a non-display area A2 surrounding the display area A1, and a plurality of data lines 101 may be provided in the display area A1 to transmit data signals generated by the source driving circuit 20 to a plurality of sub-pixels located in the display area A1 to control the luminous brightness of the plurality of sub-pixels and realize picture display. The source driving circuit 20 may be provided close to at least one side of the insulating substrate 110 to facilitate electrical connection to the plurality of data lines 101.

[0067] It can be understood that, on the one hand, in this embodiment, at least the first module 111, the second module 112 and the gating module 113 in the source driving circuit 20 are arranged on the insulating substrate 110 including the display area A1 and the non-display area A2, which can reduce the number of modules or devices integrated in the source driving circuit 20, such as in a chip, so as to reduce the size requirements of the high-cost chip and reduce the manufacturing cost of the source driving circuit 20. Among them, the specific modules, types and numbers of devices arranged on the insulating substrate 110 in the source driving circuit 20 are not limited here, and can be allocated according to performance requirements, etc., and further, as Figure 3 As shown, all modules in the source driving circuit 20 (including but not limited to a signal generating module 210 including a plurality of signal generating units 21, a signal storing module 220 including a plurality of signal storing units 22, a signal output module 230 including a plurality of signal output units 23, and a gating module 113 (not shown)) and all devices may be disposed on the insulating substrate 110. Figure 2As shown, some modules 209 in the source driving circuit 20 may also be disposed outside the insulating substrate 110, for example, may be located on a chip 300 connected to the insulating substrate 110. The chip 300 may be fixed to the insulating substrate 110 by, but not limited to, being bound to the side or back of the insulating substrate 110 or being attached to the non-display area A2A1.

[0068] It can be understood that, on the other hand, the present embodiment is provided with a plurality of gating parts 200 connected to a plurality of first parts 201 and a plurality of second parts 202. By setting the gating parts 200 to control the first parts 201 to be electrically connected to different second parts 202 at different times, it is possible to achieve at least one of the two functions of at least one first part 201 transmitting a signal to at least two second parts 202 and at least one second part 202 transmitting a signal to at least two first parts 201. That is, it is possible to achieve that at least two second parts 202 only need to be provided with a corresponding first part 201 instead of two. At least two first parts 201 only need to be provided with a corresponding first part 201 instead of two at least one of the two functions. Compared with the one-to-one correspondence between multiple first parts 201 and multiple second parts 202, this embodiment can reduce the number of at least one of the first parts 201 and the second parts 202, so as to reduce the size of at least one of the first module 111, the second module 112 and the selection module 113, so as to effectively reduce the occupied area of ​​the source driving circuit 20, thereby reducing the size and cost of the carrier that carries the source driving circuit 20, such as but not limited to the chip 300, the insulating substrate 110, etc.

[0069] It should be noted that, in this embodiment, by reasonably defining the structures of the first part 201 and the second part 202, and the selection part 200 in the source driving circuit 20, compared with a scheme in which multiple first parts 201 and multiple second parts 202 correspond one to one, the occupied area of ​​the multiple selection parts 200 added in this embodiment can be smaller than the total occupied area of ​​the first part 201 and the second part 202 saved thereby.

[0070] In one embodiment, in combination Figures 1 to 4 As shown, the gating module 113 includes a plurality of input terminals 01, a plurality of output terminals 02 and a plurality of control terminals 03, wherein the input terminals 01 are connected to the corresponding output pins of the first module 111, and the output terminals 02 are connected to the corresponding input pins of the second module 112, the number of the input terminals 01 is different from the number of the output terminals 02, and the control terminals 03 are used to load control signals so that the input terminals 01 are electrically connected to different output terminals 02 at different times. Figure 4 Only one gating section 200 in the gating module 113 is illustrated. One of the input terminal 01 and the output terminal 02 of the gating section 200 may be equal to 1.

[0071] Specific, combined Figures 1 to 4 As shown, in combination with the above discussion on the plurality of first sections 201, the plurality of second sections 202 and the plurality of gating sections 200, the input terminal 01 is connected to one of the corresponding first section 201 and the corresponding second section 202, the output terminal 02 is connected to the other of the corresponding first section 201 and the corresponding second section 202, the number of the input terminals 01 is different from the number of the output terminals 02, and the control terminal 03 is used to load a control signal to control the input terminal 01 to be electrically connected to different output terminals 02 at different times, or to control the output terminal 02 to be electrically connected to different input terminals 01 at different times. For one of the gating sections 200, the number of the input terminals 01 may be equal to the number of one of the first section 201 and the second section 202 corresponding to the gating section 200, and the number of the output terminals 02 may be equal to the number of the other of the first section 201 and the second section 202 corresponding to the gating section 200.

[0072] Specifically, in this embodiment, the specific numbers of the input terminals 01, the output terminals 02, and the control terminals 03 in the gating section 200 are not limited. It is only necessary to satisfy that the number of the input terminals 01 is different from the number of the output terminals 02. Based on this, according to the corresponding relationship between the at least one first section 201 and the at least one second section 202, a gating section 200 having a suitable number of input terminals 01, a suitable number of output terminals 02, and a suitable number of control terminals 03 can be arranged between the two. By setting the control signal on each control terminal 03, In order to realize that the input terminal 01 is electrically connected to different output terminals 02 at different times, or that the output terminal 02 is electrically connected to different input terminals 01 at different times, time-sharing multiplexing of at least one of the first part 201 and the second part 202 is realized, so as to achieve a one-to-one correspondence between multiple first parts 201 and multiple second parts 202, and the number of at least one of the first parts 201 and the second parts 202 can be reduced, thereby reducing the size and cost of the carrier that carries the source driver circuit 20, such as but not limited to the chip and the insulating substrate 110.

[0073] In one embodiment, in combination Figures 1 to 6As shown, the first module 111 includes a signal generating module 210, and the second module 112 includes a signal storage module 220; wherein the input terminal 01 is connected to the output pin of the signal generating module 210, and the multiple output terminals 02 of the selection module 113 include a first output terminal 021 and a second output terminal 022, the first output terminal 021 is connected to the corresponding first input pin of the signal storage module 220, and the second output terminal 022 is connected to the corresponding second input pin of the signal storage module 220; wherein the signal storage module 220 is used to store the first data generated by the signal generating module 210 in a first time period and the second data generated by the signal generating module 210 in a second time period.

[0074] Specific, combined Figures 1 to 6 As shown, in combination with the above discussion on multiple first parts 201, multiple second parts 202 and multiple selection parts 200, the multiple first parts 201 in the first module 111 include multiple signal generating parts 21, and the multiple second parts 202 in the second module 112 include multiple first signal storage parts 221 and multiple second signal storage parts 222; wherein, at least one of the output terminals 02 of the selection part 200 in the selection module 113 includes a first output terminal 021 and a second output terminal 022, the input terminal 01 is connected to the signal generating part 21, the first output terminal is connected to the corresponding first signal storage part 221, and the second output terminal is connected to the corresponding second signal storage part 222; wherein, the first signal storage part 221 is used to store the first data generated by the signal generating part 21 in the first time period, and the second signal storage part 222 is used to store the second data generated by the signal generating part 21 in the second time period.

[0075] It can be understood that, in combination with the above discussion, in this embodiment, by setting a selection unit 200 including an input terminal 01 and two output terminals 02 (a first output terminal 021 and a second output terminal 022), it can be achieved that a signal generating unit 21 can transmit the first data to the corresponding first signal storage unit 221 and the second data to the corresponding second signal storage unit 222 in a time-sharing manner, so that the two signal storage units can only be provided with a corresponding signal generating unit 21. Compared with multiple signal storage units and multiple signal generating units 21 corresponding one to one, this embodiment effectively reduces the number of signal generating units 21, thereby reducing the size and cost of carriers that carry the source driver circuit 20, such as chips, insulating substrates 110, etc.

[0076] Specifically, in combination with the above discussion, the signal generating unit 21 can generate first data within a first time period, and generate second data within a second time period that is located after the first time period. Furthermore, due to the independence of the operation of the first signal storage unit 221 and the second signal storage unit 222, the time when the first signal storage unit 221 stores the first data can be earlier than the time when the second signal storage unit 222 stores the second data, so as to avoid signal interference caused by the simultaneous transmission of the first data and the second data.

[0077] In one embodiment, in combination Figures 2 to 6 As shown, the source driving circuit 20 also includes a signal output module 230 electrically connected between the signal storage module 220 and the plurality of data lines 101; wherein, at the same time, the signal storage module 220 is used to transmit the first data and the second data to the signal output module 230.

[0078] Specific, combined Figures 1 to 6 As shown, in combination with the above discussion on multiple first parts 201, multiple second parts 202 and multiple selection parts 200, the source driving circuit 20 also includes a first signal output part 231 electrically connected between the corresponding first signal storage part 221 and the corresponding data line 101, and a second signal output part 232 electrically connected between the corresponding second signal storage part 222 and the corresponding data line 101; wherein, at the same time, the first signal storage part 221 transmits the corresponding first data to the corresponding first signal output part 231, and the second signal storage part 222 transmits the corresponding second data to the corresponding second signal output part 232.

[0079] Specifically, in combination with the above discussion, the moment when the first signal storage unit 221 stores the first data can be earlier than the moment when the second signal storage unit 222 stores the second data. Furthermore, in this embodiment, at the same moment, the first signal storage unit 221 transmits the corresponding first data to the corresponding first signal output unit 231, and the second signal storage unit 222 transmits the corresponding second data to the corresponding second signal output unit 232, that is, the corresponding first signal output unit 231 receives the first data and the corresponding second signal output unit 232 receives the second data. It can also be achieved at the same time, which can improve the consistency of the transmission of the first data and the second data in the subsequent period; further, multiple first signal output units 231 and multiple second signal output units 232 can also simultaneously transmit multiple first data and multiple second data to multiple data lines 101, so as to further improve the consistency of the light-emitting moments of multiple sub-pixels in the same row.

[0080] In one embodiment, in combination Figures 2 to 6As shown, the gating module 113 includes a plurality of first transistors T1 and second transistors T2; wherein the source of the first transistor T1 and the source of the second transistor T2 are configured as the corresponding input terminal 01, the gate of the first transistor T1 and the gate of the second transistor T2 are configured as the corresponding control terminal 03, the drain of the first transistor T1 is configured as the corresponding first output terminal 021, and the drain of the second transistor T2 is configured as the corresponding second output terminal 022.

[0081] Specific, combined Figures 1 to 6 As shown, in combination with the above discussion on multiple first parts 201, multiple second parts 202 and multiple gating parts 200, the gating part 200 includes a first transistor T1 and a second transistor T2; wherein, the source of the first transistor T1 and the source of the second transistor T2 are configured as the input terminal 01 of the gating part 200, the gate of the first transistor T1 and the gate of the second transistor T2 are configured as at least one control terminal 03 of the gating part 200, the drain of the first transistor T1 is configured as the first output terminal 021 of the gating part 200, and the drain of the second transistor T2 is configured as the second output terminal 022 of the gating part 200.

[0082] Among them, in combination with the above discussion, the control signal loaded on at least one control terminal 03 can be controlled to control the closing status of the first transistor T1 and the second transistor T2 at the same time, specifically, at the same time, one of the first transistor T1 and the second transistor T2 is closed and the other is disconnected, so that the signal generating unit 21 can transmit the first data to the corresponding first signal storage unit 221, or transmit the second data to the corresponding second signal storage unit 222, and the transmission of the first data and the second data is respectively realized at two different times, so as to avoid signal interference caused by the simultaneous transmission of the first data and the second data.

[0083] Specifically, in this embodiment, there is no limit on the number of corresponding control terminals 03. Figure 6As shown, the gating section 200 may include two control terminals 03 (i.e., a first control terminal 031 and a second control terminal 032), the gate of the first transistor T1 may be configured as the first control terminal 031 of the gating section 200, and the gate of the second transistor T2 may be configured as the second control terminal 032 of the gating section 200. Based on this, a first control signal may be loaded on the first control terminal 031, and a second control signal may be loaded on the second control terminal 032, so as to control the closing conditions of the first transistor T1 and the second transistor T2 separately, and the first control signal and the second signal may be inverse signals of each other; for another example, the gating section 200 may include a control terminal 03, one of the gate of the first transistor T1 and the gate of the second transistor T2 may be configured as the control terminal 03 of the gating section 200, and the other of the gate of the first transistor T1 and the gate of the second transistor T2 may be electrically connected to the control terminal 03 through an inverter or a NOT gate circuit, so as to achieve opposite closing conditions of the first transistor T1 and the second transistor T2.

[0084] In one embodiment, in combination Figures 2 to 4 , Figures 7 and 8 As shown, the first module 111 includes a signal storage module 220, and the second module 112 includes a signal output module 230, and the signal output module 230 is connected between the signal storage module 220 and the plurality of data lines 101; wherein the plurality of input terminals 01 of the selection module 113 include a first input terminal 011 and a second input terminal 012, and the plurality of output terminals 02 of the selection module 113 include a first output terminal 021 and a second output terminal 022, the first input terminal 011 is connected to the first output pin of the signal storage module 220, the second input terminal 012 is connected to the second output pin of the signal storage module 220, the first output terminal 021 is connected to the corresponding first input pin of the signal output module 230, and the second output terminal 022 is connected to the corresponding second input pin of the signal output module 230.

[0085] Specific, combined Figures 2 to 4 , Figures 7 and 8As shown, in combination with the above discussion on multiple first parts 201, multiple second parts 202 and multiple selection parts 200, the multiple first parts 201 include multiple signal storage parts 22, the multiple second parts 202 include multiple first signal output parts 231 and multiple second signal output parts 232, and the multiple first signal output parts 231 and multiple second signal output parts 232 are connected to the multiple data lines 101; wherein, at least one input terminal 01 of the selection part 200 includes a first input terminal 011 and a second input terminal 012, and at least two output terminals 02 of the selection part 200 include a first output terminal 021 and a second output terminal 022, the input terminal is connected to the signal storage part 22, the first output terminal 021 is connected to the corresponding first signal output part 231, and the second output terminal 022 is connected to the corresponding second signal output part 232.

[0086] It can be understood that, in combination with the above discussion, in this embodiment, by providing a selection unit 200 including two input terminals 01 (a first input terminal 011 and a second input terminal 012) and two output terminals 02 (a first output terminal 021 and a second output terminal 022), it can be achieved that one signal storage unit 22 can simultaneously transmit the first data to the corresponding first signal output unit 231 and the second data to the corresponding second signal output unit 232, or vice versa, so that the two signal output units can only be provided with a corresponding signal storage unit 22. Compared with a plurality of signal storage units 22 and a plurality of signal output units corresponding one to one, this embodiment effectively reduces the number of signal storage units 22, thereby reducing the size and cost of carriers that carry the source driver circuit 20, such as chips, insulating substrates 110, etc.

[0087] Specifically, in combination with the above discussion, due to the differences between the first signal output unit 231 and the second signal output unit 232, the selection unit 200 can control the transmission of the first data stored in the signal storage unit 22 to the first signal output unit 231, and control the transmission of the second data to the second signal output unit 232, or vice versa, to avoid the inability to identify the transmission path when the first data and the second data are transmitted simultaneously.

[0088] Alternatively, similarly, a connection may be provided between the signal output portion (the first signal output portion 231 or the second signal output portion 232) and the corresponding two adjacent data lines 101 (the first data line and the second data line). Figure 8 The gating unit 200 shown in the figure, wherein the two input terminals 01 of the gating unit 200 can be electrically connected to the signal output unit, and the two output terminals 02 of the gating unit 200 can be electrically connected to the corresponding first data line and the corresponding second data line, for details, please refer to the relevant description above. Similarly, based on the same number of the plurality of data lines 101, the number of the signal output unit can be further controlled here.

[0089] In one embodiment, in combination Figures 2 to 4 , Figures 7 and 8 As shown, the source driving circuit 20 also includes a signal generating module 210 electrically connected to the signal storage module 220; wherein, at the same time, multiple signal generating modules 210 are used to generate first data and second data, and the first input pin of the signal output module 230 is used to receive the corresponding first data while the second input pin of the signal output module 230 is used to receive the corresponding second data.

[0090] Specific, combined Figures 2 to 4 , Figures 7 and 8 As shown, in combination with the above discussion on the multiple first parts 201, the multiple second parts 202 and the multiple strobe parts 200, the source driving circuit 20 also includes multiple signal generating parts 21 electrically connected to the multiple signal storage parts 22, and the multiple data lines 101 are electrically connected to the multiple first signal output parts 231 and the multiple second signal output parts 232; wherein, at the same time, the multiple signal generating parts 21 are used to generate the first data and the second data, and the first signal output part 231 is used to receive the corresponding first data while the second signal output part 232 is used to receive the corresponding second data. It can be understood that the signal generating part 21 can simultaneously generate and transmit the first data and the second data to the corresponding signal storage part 22, and further, the strobe part 200 can transmit the received first data to one of the first signal output part 231 and the second signal output part 232, and also transmit the received second data to the other of the first signal output part 231 and the second signal output part 232. Therefore, this embodiment can also reduce the number of signal generating parts 21.

[0091] In one embodiment, in combination Figures 2 to 4 , Figures 7 and 8 As shown, the gating module 113 includes a first transistor T1, a second transistor T2, a third transistor T3 and a fourth transistor T4; wherein the source of the first transistor T1 and the source of the second transistor T2 are configured as the first input terminal 011, the source of the third transistor T3 and the source of the fourth transistor T4 are configured as the corresponding second input terminal 012, the gate of the first transistor T1, the gate of the second transistor T2, the gate of the third transistor T3 and the gate of the fourth transistor T4 are configured as the corresponding control terminal 03, the drain of the first transistor T1 and the drain of the third transistor T3 are configured as the corresponding first output terminal 021, and the drain of the second transistor T2 and the drain of the fourth transistor T4 are configured as the corresponding second output terminal 022.

[0092] Specific, combined Figures 2 to 4 , Figures 7 and 8As shown, in combination with the above discussion on multiple first parts 201, multiple second parts 202 and multiple gating parts 200, the gating part 200 includes a first transistor T1, a second transistor T2, a third transistor T3 and a fourth transistor T4; wherein, the source of the first transistor T1 and the source of the second transistor T2 are configured as the first input terminal 011 of the gating part 200, the source of the third transistor T3 and the source of the fourth transistor T4 are configured as the second input terminal 012 of the gating part 200, the gate of the first transistor T1, the gate of the second transistor T2, the gate of the third transistor T3 and the gate of the fourth transistor T4 are configured as at least one of the control terminals 03 of the gating part 200, the drain of the first transistor T1 and the drain of the third transistor T3 are configured as the first output terminal 021 of the gating part 200, and the drain of the second transistor T2 and the drain of the fourth transistor T4 are configured as the second output terminal 022 of the gating part 200.

[0093] In combination with the above discussion, the control signal loaded on at least one control terminal 03 can be controlled to control the closing conditions of the first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 at the same time, specifically, the first transistor T1 and the fourth transistor T4 are closed at the same time, and the second transistor T2 and the third transistor T3 are disconnected, or the first transistor T1 and the fourth transistor T4 are disconnected at the same time, and the second transistor T2 and the third transistor T3 are closed, so as to simultaneously realize the first data in the signal storage unit 22 is transmitted to the first signal output unit 231, and the second data is transmitted to the second signal output unit 232, or vice versa. Specifically, this embodiment can be applied to column inversion, for example, the first data can be a positive signal, and the second data can be a negative signal. Further, the first transistor T1 and the fourth transistor T4, and the second transistor T2 and the third transistor T3 can be alternately closed or disconnected, so as to realize that the corresponding two data lines 101 can be mutually reversed and alternately loaded with positive signals and negative signals.

[0094] Specifically, in this embodiment, there is no limit on the number of corresponding control terminals 03. Figure 8 As shown, the gating unit 200 may include two control terminals 03 (i.e., a first control terminal 031 and a second control terminal 032), the gate of the first transistor T1 and the fourth transistor T4 may be configured as the first control terminal 031 of the gating unit 200, the gate of the second transistor T2 and the gate of the third transistor T3 may be configured as the second control terminal 032 of the gating unit 200, combined with the above discussion, similarly, based on this, a first control signal may be loaded on the first control terminal 031, and a second control signal may be loaded on the second control terminal 032, and the first control signal and the second signal may be inverse signals of each other; for another example, the gating unit 200 may include one, three or four control terminals 03, and specific reference may be made to the above description of Figure 6 Related description of control terminal 03 in.

[0095] In one embodiment, in combination Figures 2 to 4 , Figures 9 to 11 As shown, the first module 111 includes a signal output module 230, the second module 112 includes a signal storage module 220, and the plurality of data lines 101 include a plurality of first data lines 1011, a plurality of second data lines 1012, and a plurality of third data lines 1013; wherein the gating module 113 includes a first gating module 1131 connected between the first module 111 and the second module 112, and a second gating module 1132 connected between the first module 111 and the plurality of data lines 101; wherein the plurality of input terminals 01 of the first gating module 1131 include a first input terminal 011, a second input terminal 012, and a third input terminal 013, wherein the plurality of output terminals 02 of the first gating module 1131 include a first output terminal 021, and the first input terminal 011 is connected to a first output pin of the signal storage module 220, wherein the plurality of data lines 101 are connected to the first output pin of the signal storage module 220, and the plurality of data lines 101 are connected to the first output pin of the signal storage module 220, and the plurality of data lines 101 are connected to the first output pin of the signal storage module 220, and the plurality of data lines 101 are connected to the first output pin of the signal storage module 220, and the plurality of data lines 101 are connected to the first output pin of the signal storage module 220, and the plurality of data lines 101 are connected to the second ... The second input terminal 012 is connected to the second output pin of the signal storage module 220, the third input terminal 013 is connected to the third output pin of the signal storage module 220, and the first output terminal 021 is connected to the corresponding input pin of the signal output module 230; wherein, the multiple input terminals 01 of the second selection module 1132 include a fourth input terminal 014, the multiple output terminals 02 of the second selection module 1132 include a second output terminal 022, a third output terminal 023 and a fourth output terminal 024, the fourth input terminal 014 is connected to the corresponding output pin of the signal output module 230, the second output terminal 022 is connected to the corresponding first data line 1011, the third output terminal 023 is connected to the corresponding second data line 1012, and the fourth output terminal 024 is connected to the corresponding third data line 1013.

[0096] Specific, combined Figures 2 to 4 , Figures 9 to 11 As shown, in combination with the above discussion on the plurality of first parts 201, the plurality of second parts 202 and the plurality of gating parts 200, the plurality of first parts 201 include a plurality of signal output parts 23, the plurality of second parts 202 include a plurality of first signal storage parts 221, a plurality of second signal storage parts 222 and a plurality of third signal storage parts 223, the plurality of data lines 101 include a plurality of first data lines 1011, a plurality of second data lines 1012 and a plurality of third data lines 1013; wherein the plurality of gating parts 200 include a plurality of first gating parts 2001 connected between the plurality of first parts 201 and the plurality of second parts 202, and a plurality of second gating parts 2002 connected between the plurality of first parts 201 and the plurality of data lines 101; wherein, in combination with Figure 2 , Figure 4 , Fig. 9 and Fig.10 As shown, at least one input terminal 01 of the first selection unit 2001 includes a first input terminal 011, a second input terminal 012 and a third input terminal 013, at least one output terminal 02 of the first selection unit 2001 includes a first output terminal 021, the first input terminal 011 is connected to the corresponding first signal storage unit 221, the second input terminal 012 is connected to the corresponding second signal storage unit 222, the third input terminal 013 is connected to the corresponding third signal storage unit 223, and the first output terminal 021 is connected to the corresponding signal output Part 23; wherein, at least one input terminal 01 of the second selection part 2002 includes a fourth input terminal 014, and at least one output terminal 02 of the second selection part 2002 includes a second output terminal 022, a third output terminal 023 and a fourth output terminal 024, the fourth input terminal 014 is connected to the corresponding signal output part 23, the second output terminal 022 is connected to the corresponding first data line 1011, the third output terminal 023 is connected to the corresponding second data line 1012, and the fourth output terminal 024 is connected to the corresponding third data line 1013.

[0097] On the one hand, it can be understood that, in combination with the above discussion, by setting a first selection unit 2001 including three input terminals 01 and one output terminal 02, the first signal storage unit 221, the second signal storage unit 222 and the third signal storage unit 223 can transmit their respective data to the signal output unit 23 in a time-sharing manner, that is, one signal output unit 23 can receive the first data transmitted by the corresponding first signal storage unit 221, the second data transmitted by the corresponding second signal storage unit 222, and the third data transmitted by the corresponding third signal storage unit 223 in a time-sharing manner, so that the three signal storage units can only be provided with a corresponding signal output unit 23. Compared with multiple signal storage units and multiple signal output units 23 corresponding to each other, the present embodiment effectively reduces the number of signal output units 23, thereby reducing the size and cost of carriers that carry the source driver circuit 20, such as chips, insulating substrates 110, etc.

[0098] On the other hand, in combination with the above discussion, it can be seen that in this embodiment, by setting a first selection unit 2001 including three input terminals 01 and one output terminal 02, the signal output unit 23 can transmit data to the first data line 1011, the second data line 1012 and the third data line 1013 in a time-sharing manner, that is, the first data line 1011, the second data line 1012 and the third data line 1013 can receive the first data (corresponding to the first data line 1011), the second data (corresponding to the second data line 1012), and the third data (corresponding to the third data line 1013) transmitted by the corresponding signal output unit 23 in a time-sharing manner. Compared with a plurality of data lines 101 and a plurality of signal output units 23 that correspond one to one, this embodiment effectively reduces the number of signal output units 23, thereby reducing the size and cost of carriers that carry the source drive circuit 20, such as chips and insulating substrates 110.

[0099] It can be understood that, in combination with the above two aspects, the present embodiment can effectively reduce the number of signal output units 23 by setting the first selection unit 2001 and the second selection unit 2002, and considering that the operating frequency requirement of the signal output unit 23 is relatively low, one signal output unit 23 can process the signals of the corresponding three signal storage units in a time-sharing manner within a unit time. Furthermore, a latch can be set between the second selection unit 2002 and the corresponding three data lines to enable the first data line 1011, the second data line 1012 and the third data line 1013 to load their respective data at the same time, thereby improving the consistency of the light-emitting moments of multiple sub-pixels in the same row.

[0100] In one embodiment, in combination Figures 2 to 4 , Figures 9 to 11 As shown, the source driving circuit 20 also includes a signal generating module 210 electrically connected to the signal storage module 220; wherein the signal output module 230 is used to transmit the first data output by the first output pin of the signal generating module 210 to the corresponding first data line 1011, and to transmit the second data output by the second output pin of the signal generating module 210 to the corresponding second data line 1012, and to transmit the third data output by the third output pin of the signal generating module 210 to the corresponding third data line 1013.

[0101] Specific, combined Figures 2 to 4 , Figures 9 to 11As shown, in combination with the above discussion on multiple first parts 201, multiple second parts 202 and multiple selection parts 200, the source driving circuit 20 also includes multiple first signal generating parts 211, multiple second signal generating parts 212 and multiple third signal generating parts 213 electrically connected to multiple first signal storage parts 221, multiple second signal storage parts 222 and multiple third signal storage parts 223; wherein the signal output part 23 is used to transmit the first data generated by the first signal generating part 211 to the corresponding first data line 1011, and to transmit the second data generated by the second signal generating part 212 to the corresponding second data line 1012, and to transmit the third data generated by the third signal generating part 213 to the corresponding third data line 1013.

[0102] It can be understood that since the operating frequency requirement of the signal generating unit 21 is relatively high, in this embodiment, the number of signal generating units 21 is set to be consistent with the number of corresponding data lines 101. For example, in a group of pixels, three sub-pixels of different colors are electrically connected to the corresponding three data lines 101 respectively. Therefore, the corresponding three signal generating units 21 can work simultaneously to generate the corresponding three data almost simultaneously, and then the same signal output unit with a shorter data processing time can output the corresponding three data almost simultaneously, thereby improving the consistency of the light-emitting moments of multiple sub-pixels in the same row.

[0103] In one embodiment, in combination Figures 2 to 4 , Fig. 9 , Fig.10 As shown, the first selection module 1131 includes a first transistor T1, a second transistor T2, and a third transistor T3; wherein the source of the first transistor T1 is configured as the first input terminal 011, the drain of the second transistor T2 is configured as the second input terminal 012, the drain of the third transistor T3 is configured as the corresponding third input terminal 013, the gate of the first transistor T1, the gate of the second transistor T2 and the gate of the third transistor T3 are configured as the corresponding control terminal 03, and the drain of the first transistor T1, the drain of the second transistor T2 and the drain of the third transistor T3 are configured as the corresponding first output terminal 021.

[0104] Specific, combined Figures 2 to 4 , Figures 9 to 11As shown, in combination with the above discussion on multiple first parts 201, multiple second parts 202 and multiple selection parts 200, the first selection part 2001 includes a first transistor T1, a second transistor T2, and a third transistor T3; wherein, the source of the first transistor T1 is configured as a first input terminal 011, the drain of the second transistor T2 is configured as a second input terminal 012, the drain of the third transistor T3 is configured as a third input terminal 013, the gate of the first transistor T1, the gate of the second transistor T2 and the gate of the third transistor T3 are configured as a control terminal 03, and the drain of the first transistor T1, the drain of the second transistor T2 and the drain of the third transistor T3 are configured as a first output terminal 021.

[0105] Among them, combined with the above discussion, the control signal loaded on at least one control terminal 03 can be controlled to control the closing status of the first transistor T1, the second transistor T2 and the third transistor T3 at the same time, specifically, one of the three is closed and the other two are disconnected at the same time, so that the first signal storage unit 221, the second signal storage unit 222 and the third signal storage unit 223 can transmit their respective data to the signal output unit 23 in a time-sharing manner to avoid signal interference caused by the simultaneous transmission of multiple data.

[0106] Specifically, in this embodiment, there is no limit on the number of corresponding control terminals 03. Fig.10 As shown, the selection unit 200 may include three control terminals 03 (i.e., a first control terminal 031, a second control terminal 032, and a third control terminal 033), the gate of the first transistor T1 may be configured as the first control terminal 031, the gate of the second transistor T2 may be configured as the second control terminal 032, and the gate of the third transistor T3 may be configured as the third control terminal 033. Similarly, based on this, the closing conditions of the first transistor T1, the second transistor T2, and the third transistor T3 may be controlled individually to control the closing of the three in time-sharing.

[0107] In one embodiment, in combination Figures 2 to 4 , Fig. 9 , Fig.11 As shown, the second gating module includes a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6; wherein the source of the fourth transistor T4, the source of the fifth transistor T5, and the source of the sixth transistor T6 are configured as the fourth input terminal 014, the gate of the fourth transistor T4, the gate of the fifth transistor T5, and the gate of the sixth transistor T6 are configured as the corresponding control terminal 03, the drain of the fourth transistor T4 is configured as the second output terminal 022, the drain of the fifth transistor T5 is configured as the corresponding third output terminal 023, and the drain of the sixth transistor T6 is configured as the corresponding fourth output terminal 024.

[0108] Specific, combined Figures 2 to 4 , Figures 9 to 11 As shown, in combination with the above discussion on multiple first parts 201, multiple second parts 202 and multiple selection parts 200, the second selection part 2002 includes a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6; wherein, the source of the fourth transistor T4, the source of the fourth transistor T4 and the source of the sixth transistor T6 are configured as the fourth input terminal 014 of the second selection part 2002, the gate of the fourth transistor T4, the gate of the fifth transistor T5 and the gate of the sixth transistor T6 are configured as at least one control terminal of the second selection part 2002, the drain of the fourth transistor T4 is configured as the second output terminal 022 of the second selection part 2002, the drain of the fifth transistor T5 is configured as the third output terminal 023 of the second selection part 2002, and the drain of the sixth transistor T6 is configured as the fourth output terminal 024 of the second selection part 2002.

[0109] Among them, combined with the above discussion, the control signal loaded on at least one control terminal 03 can be controlled to control the closing status of the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 at the same time, specifically, one of the three is closed and the other two are disconnected at the same time, so that the signal output unit 23 can transmit respective data to the first data line 1011, the second data line 1012 and the third data line 1013 in a time-sharing manner to avoid signal interference caused by the simultaneous transmission of multiple data.

[0110] Specifically, in this embodiment, there is no limit on the number of corresponding control terminals 03. Fig.11 As shown, the selection unit 200 may include three control terminals 03 (i.e., a first control terminal 031, a second control terminal 032, and a third control terminal 033), the gate of the fourth transistor T4 may be configured as the first control terminal 031, the gate of the fifth transistor T5 may be configured as the second control terminal 032, and the gate of the sixth transistor T6 may be configured as the third control terminal 033. Similarly, based on this, the closing conditions of the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be controlled separately to control the closing of the three in time-sharing manner.

[0111] In one embodiment, in combination Figure 2 , Figure 3 , Figure 5 , Figure 7 , Fig. 9As shown, the display panel 100 includes a signal generating module 210, a signal storage module 220 and a signal output module 230, and the signal storage module 220 is connected between the signal generating module 210 and the signal output module 230; wherein, the first module 111 includes one of the signal generating module 210, the signal storage module 220 and the signal output module 230, and the second module 112 includes one of the signal generating module 210, the signal storage module 220 and the signal output module 230 that is different from the second module 112.

[0112] Among them, Fig.12 As shown, the signal generating unit 21 may include a shift register 91, and the signal storage unit 22 may include a latch 92. The shift register 91 may be a serial input and parallel output register. The number of bits of the latch 92 may be equal to the number of bits of the shift register 91. The shift register 91 and the latch 92 may include cascaded multi-stage D flip-flops, and the number of stages of the D flip-flops in the two is the same. Specifically, in the shift register 91, the D end of the first stage D flip-flop is loaded with the initial data signal, the CK end of the multi-stage D flip-flop is loaded with the first clock signal, the Q end of the D flip-flop of this stage is connected to the D end of the next stage D flip-flop and the D end of the corresponding stage of the D flip-flop in the latch 92, and the CK end of the multi-stage D flip-flop in the latch 92 is loaded with the second clock signal to simultaneously release multiple parallel data in the initial data signal to the digital-to-analog converter 93 in the signal output unit 23. Specifically, the specific circuit structure of the D flip-flops in the shift register 91 and the latch 92 can be referred to. Fig.13 , can be composed of multiple NAND gate circuits, where the data output from the Q' end is opposite to the data output from the Q end.

[0113] Furthermore, the signal output unit 23 may also include a level converter and a decoder. The level converter may be electrically connected to the latch, and the decoder may be electrically connected between the level converter and the digital-to-analog converter. Further, the signal output unit 23 may also include a buffer amplifier electrically connected between the digital-to-analog converter and the plurality of data lines 101.

[0114] For details, please refer to the specific circuit structure of the level converter. Fig.14 , wherein the transistor T01 may be a P-type transistor, the transistor T02 may be an N-type transistor, the voltage value corresponding to the first high-voltage signal VGH may be greater than the voltage value corresponding to the first low-voltage signal VGL, the voltage value corresponding to the second high-voltage signal VGHH may be greater than the voltage value corresponding to the second low-voltage signal VGLL, the IN terminal of the level converter may be connected to the output terminal of the latch 92, and the level converter converts the corresponding low voltage (high voltage) into a high voltage (low voltage) and outputs it to the decoder through the OUT terminal.

[0115] Specifically, the specific circuit structure of the decoder can refer to Fig.15 or Fig.16 .in, Fig.15 and Fig.16 It can be a 3-8 decoder, each of the three input terminals (IN1 to IN3) of the 3-8 decoder can be connected to the OUT terminal of a corresponding level converter, and the eight output terminals (OUT1 to OUT8) of the 3-8 decoder can be connected to the digital analog converter 93. The 3-8 decoder can translate the three data corresponding to the three voltages output by the three level converters into eight data. Specifically, Fig.15 The specific circuit structure of the NTFT-diode decoder may include a plurality of NOT gates G, a plurality of NTFTs, and a plurality of first resistors R1, wherein the gate and source or drain of the NTFT are short-circuited to form a diode structure, and the NOT gate G may also include an NTFT, which is an N-type transistor; Fig.16 The specific circuit structure of the TFT-decoder may include a NOT gate G and a NAND gate NG, wherein the NOT gate G and the NAND gate NG may also include an N-type transistor and a P-type transistor.

[0116] Specifically, the digital-to-analog converter 93 can refer to Fig.17 The digital-to-analog converter 93 may include a plurality of second resistors R2, a plurality of transistors TFT, the transistor TFT may be a P-type transistor, the third high voltage VDD is greater than the third low voltage VSS, wherein a plurality of input terminals (H0 to H7, P0 to P7) may be respectively connected to a plurality of output terminals of the decoder, and the VOUT terminal may be connected to the corresponding data line 101 through a buffer amplifier.

[0117] In one embodiment, in combination Figure 2 , Figure 5 , Figure 7 , Fig. 9 As shown, one of the first module 111 and the second module 112 includes the signal storage module 220, and the other of the first module 111 and the second module 112 includes the signal output module 230; wherein the display panel 100 further includes a semiconductor device electrically connected to the display panel, and the semiconductor device includes the signal generating module 210. Specifically, Figure 2 The chip 300 in the embodiment may be a semiconductor device independent of the insulating substrate 110 discussed in this embodiment. Figure 2 The “partial module 209 ” may include a signal generating module 210 .

[0118] It can be understood that the signal generating unit 21 including the shift register is a higher frequency module than the signal storage unit 22 including the latch. In this embodiment, the signal generating unit 21 is arranged in a separate chip 300. For example, the substrate of the chip 300 can be but not limited to silicon-based or glass-based, which can meet the high frequency requirements of the signal generating unit 21.

[0119] Further, such as Figure 1 As shown, the signal storage unit 22 includes a first transistor device, the signal output unit 23 includes a second transistor device, and a third transistor device is provided in the display area A1 of the insulating substrate 110; wherein the first transistor device, the second transistor device and the third transistor device are arranged in the same layer and the materials of the three are the same. Specifically, in combination with the above discussion, in this embodiment, the signal output unit 23, the signal storage unit 22 and other modules with lower frequency requirements are arranged on the insulating substrate 110, and materials including but not limited to glass are used as substrates, which can reduce the overall cost and facilitate the layout of the source drive circuit. Further, in this embodiment, the first transistor device, the second transistor device and the third transistor device can be made of the same material and in the same layer. For example, the active layers of the three can be made in the same layer and the materials are the same, the gate layers of the three can be made in the same layer and the materials are the same, and the source and drain layers of the three can be made in the same layer and the materials are the same, so as to save the process and improve the efficiency.

[0120] Further, combined with Figure 2 , Figure 5 , Figure 7 , Fig. 9 As shown, the signal output unit 23 includes a resistor, and the resistor is arranged in the same layer as part of the third transistor device and the materials of the two are the same. Specifically, in combination with the above discussion, the third transistor device may include a third active layer, a third gate layer and a third source-drain layer, and the resistor element may be arranged in the same layer as at least one of the third active layer, the third gate layer and the third source-drain layer and the materials are the same. Further, the resistor element here may be arranged in the same layer as the third active layer and the materials are the same. Among them, the constituent material of the third active layer is not limited here, and it can be but not limited to metal oxide or polysilicon.

[0121] In one embodiment, in combination Figure 3 , Figure 5 , Figure 7 , Fig. 9As shown, the signal generating module 210, the signal storage module 220 and the signal output module 230 all include thin film transistor devices, and the thin film transistor devices are arranged on the insulating substrate. Specifically, in combination with the above discussion, the thin film transistor devices in the signal generating module 210, the signal storage module 220 and the signal output module 230 can be arranged in the same layer and with the same material as the third transistor device arranged in the display area A1, and the specific details can refer to the above description of the processes and materials of the first transistor device, the second transistor device and the third transistor device.

[0122] An embodiment of the present invention provides an electronic terminal, which includes any display panel as described above.

[0123] The display panel and electronic terminal provided by the embodiment of the present invention include: an insulating substrate; a plurality of data lines, arranged on the insulating substrate; a source driving circuit, electrically connected to the plurality of data lines, including a first module and a second module arranged on the insulating substrate; wherein the source driving circuit also includes a gating module arranged on the insulating substrate and connected between a plurality of output pins of the first module and a plurality of input pins of the second module, the number of output pins of the first module is different from the number of input pins of the second module, and the gating module is used to control the output pins of the first module to be electrically connected to different input pins of the second module at different times. On the one hand, at least the first module and the second module in the source driving circuit of the present invention are arranged on the insulating substrate to reduce the size of the chip including but not limited to the chip used to carry the module or device, on the other hand, the gating part of the present invention is connected between the first module and the second module, and is used to control the output pins of the first module to be electrically connected to different input pins of different second modules at different times, so that the number of output pins of the first module is different from the number of input pins of the second module, so as to reduce the size of at least one of the first module and the second module, and both of the above aspects can reduce the cost of the display panel.

[0124] The display panel and the electronic terminal provided in the embodiments of the present invention are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present invention. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that: include: Insulating substrate; A plurality of data lines are arranged on the insulating substrate; A source driving circuit, electrically connected to the plurality of data lines, comprises a first module and a second module disposed on the insulating substrate; The source driving circuit further includes a gating module disposed on the insulating substrate and connected between a plurality of output pins of the first module and a plurality of input pins of the second module, the number of output pins of the first module is different from the number of input pins of the second module, and the gating module is used to control the output pins of the first module to be electrically connected to different input pins of the second module at different times; Wherein, the gating module comprises a plurality of input terminals, a plurality of output terminals and a plurality of control terminals, the input terminals are connected to the corresponding output pins of the first module, and the output terminals are connected to the corresponding input pins of the second module; Wherein, the source driving circuit includes a signal generating module, a signal storage module and a signal output module, the signal storage module is connected between the signal generating module and the signal output module, the first module includes one of the signal generating module, the signal storage module and the signal output module, and the second module includes one of the signal generating module, the signal storage module and the signal output module which is different from the first module; Wherein, the multiple output terminals of the gating module include multiple first output terminals and multiple second output terminals, the first output terminal is connected to the corresponding first input pin of the second module, the second output terminal is connected to the corresponding second input pin of the second module, the gating module includes multiple first transistors and multiple second transistors, the source of the first transistor and the source of the corresponding second transistor are configured as the corresponding input terminal, the gate of the first transistor and the gate of the corresponding second transistor are configured as the corresponding control terminal, the drain of the first transistor is configured as the corresponding first output terminal, and the drain of the corresponding second transistor is configured as the corresponding second output terminal; Alternatively, the plurality of input terminals of the gating module include a plurality of first input terminals and a plurality of second input terminals, the plurality of output terminals of the gating module include a plurality of first output terminals and a plurality of second output terminals, the first input terminal is connected to a first output pin of the first module, the second input terminal is connected to a second output pin of the first module, the first output terminal is connected to a corresponding first input pin of the second module, the second output terminal is connected to a corresponding second input pin of the second module, the gating module includes a plurality of first transistors, a plurality of second transistors, a plurality of third transistors and a plurality of fourth transistors, the source of the first transistor and the source of the corresponding second transistor are configured as the first input terminal, the source of the third transistor and the source of the corresponding fourth transistor are configured as the corresponding second input terminal, the gate of the first transistor, the gate of the corresponding second transistor, the gate of the corresponding third transistor and the gate of the corresponding fourth transistor are configured as the corresponding control terminals, the drain of the first transistor and the drain of the corresponding third transistor are configured as the corresponding first output terminal, the drain of the second transistor and the drain of the corresponding fourth transistor are configured as the corresponding second output terminal; Alternatively, the first module includes a signal output module, the second module includes a signal storage module, the plurality of data lines include a plurality of first data lines, a plurality of second data lines and a plurality of third data lines, and the source driving circuit further includes a second gating module connected between the first module and the plurality of data lines, wherein: The multiple input terminals of the gating module include multiple first input terminals, multiple second input terminals and multiple third input terminals, and the multiple output terminals of the gating module include multiple first output terminals, the first input terminals are connected to the first output pins of the signal storage module, the corresponding second input terminals are connected to the second output pins of the signal storage module, the corresponding third input terminals are connected to the third output pins of the signal storage module, and the corresponding first output terminals are connected to the corresponding input pins of the signal output module; Furthermore, the multiple input terminals of the second selection module include multiple fourth input terminals, the multiple output terminals of the second selection module include multiple second output terminals, multiple third output terminals and multiple fourth output terminals, the fourth input terminal is connected to the corresponding output pin of the signal output module, the corresponding second output terminal is connected to the corresponding first data line, the corresponding third output terminal is connected to the corresponding second data line, and the corresponding fourth output terminal is connected to the corresponding third data line.

2. The display panel according to claim 1, characterized in that: The signal generating module, the signal storing module and the signal output module all include thin film transistors, and the thin film transistors are arranged on the insulating substrate.

3. The display panel according to claim 1, characterized in that: One of the first module and the second module includes the signal storage module, and the other of the first module and the second module includes the signal output module; Wherein, the display panel further includes a semiconductor device electrically connected to the display panel, and the semiconductor device includes the signal generating module.

4. The display panel according to claim 1, characterized in that: The control end is used to load a control signal so that the input end is electrically connected to different output ends at different times.

5. The display panel according to claim 4, characterized in that: When the input end of the gating module corresponds to the first output end and the second output end, the first module includes the signal generating module, and the second module includes the signal storing module; Wherein, the input end is connected to the output pin of the signal generating module, the first output end is connected to the corresponding first input pin of the signal storage module, and the second output end is connected to the corresponding second input pin of the signal storage module; The signal storage module is used to store the first data generated by the signal generation module in the first time period and the second data generated by the signal generation module in the second time period.

6. The display panel according to claim 5, characterized in that: The source driving circuit further comprises a signal output module electrically connected between the signal storage module and the plurality of data lines; Wherein, at the same time, the signal storage module is used to transmit the first data and the second data to the signal output module.

7. The display panel according to claim 4, characterized in that: When the first input terminal and the second input terminal of the gating module correspond to the first output terminal and the second output terminal, the first module includes the signal storage module, the second module includes the signal output module, and the signal output module is connected between the signal storage module and the plurality of data lines; Among them, the first input end is connected to the first output pin of the signal storage module, the second input end is connected to the second output pin of the signal storage module, the first output end is connected to the corresponding first input pin of the signal output module, and the second output end is connected to the corresponding second input pin of the signal output module.

8. The display panel according to claim 7, characterized in that: The source driving circuit further comprises a signal generating module electrically connected to the signal storage module; Among them, at the same time, multiple signal generating modules are used to generate first data and second data, and the first input pin of the signal output module is used to receive the corresponding first data while the second input pin of the signal output module is used to receive the corresponding second data.

9. The display panel according to claim 4, characterized in that: When the first module includes the signal output module, the second module includes the signal storage module, the plurality of data lines include a plurality of the first data lines, a plurality of the second data lines and a plurality of the third data lines, and the source driving circuit further includes the second gating module connected between the first module and the plurality of the data lines, the source driving circuit further includes a signal generating module electrically connected to the signal storage module; Among them, the signal output module is used to transmit the first data output by the first output pin of the signal generating module to the corresponding first data line, and to transmit the second data output by the second output pin of the signal generating module to the corresponding second data line, and to transmit the third data output by the third output pin of the signal generating module to the corresponding third data line.

10. The display panel according to claim 4, characterized in that: When the first module includes the signal output module, the second module includes the signal storage module, the plurality of data lines include a plurality of the first data lines, a plurality of the second data lines and a plurality of the third data lines, and the source driving circuit further includes the second gating module connected between the first module and the plurality of the data lines, the gating module includes a plurality of first transistors, a plurality of second transistors and a plurality of third transistors; Among them, the source of the first transistor is configured as the first input terminal, the corresponding drain of the second transistor is configured as the second input terminal, the corresponding drain of the third transistor is configured as the corresponding third input terminal, the gate of the first transistor, the corresponding gate of the second transistor and the corresponding gate of the third transistor are configured as the corresponding control terminals, and the drain of the first transistor, the corresponding drain of the second transistor and the corresponding drain of the third transistor are configured as the corresponding first output terminal.

11. The display panel according to claim 4, characterized in that: When the first module includes the signal output module, the second module includes the signal storage module, the plurality of data lines include a plurality of the first data lines, a plurality of the second data lines and a plurality of the third data lines, and the source driving circuit further includes the second gating module connected between the first module and the plurality of the data lines, the second gating module includes a plurality of fourth transistors, a plurality of fifth transistors and a plurality of sixth transistors; Among them, the source of the fourth transistor, the corresponding source of the fifth transistor and the corresponding source of the sixth transistor are configured as the fourth input terminal, the gate of the fourth transistor, the corresponding gate of the fifth transistor and the corresponding gate of the sixth transistor are configured as the corresponding control terminal, the drain of the fourth transistor is configured as the second output terminal, the corresponding drain of the fifth transistor is configured as the corresponding third output terminal, and the corresponding drain of the sixth transistor is configured as the corresponding fourth output terminal.

12. An electronic terminal, characterized in that: The electronic terminal comprises the display panel as claimed in any one of claims 1 to 11.

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