RHBD-12T radiation-resistant SRAM memory cells, chips, and modules

Abstract

The present invention relates to an RHBD-12T radiation-resistant SRAM memory cell, chip, and module. The RHBD-12T radiation-resistant SRAM memory cell, based on source isolation and polarity reinforcement technology, includes NMOS transistors N1 to N8 and PMOS transistors P1 to P4. Transistors P1 to P4 and N3 and N4 serve as pull-up transistors, while transistors N1, N2, N5, and N6 serve as pull-down transistors. Transistors N1 and P3 form an inverter, while transistors N2 and P4 form another inverter, and the two inverters are cross-coupled. Two main storage nodes, Q and QB, are connected to bit lines BL and BLB, respectively, via N7 and N8. Transistors N7 and N8 are controlled by word lines WL. By providing only two sensitive storage nodes, the present invention greatly reduces the number of sensitive nodes and the area of the sensitive region of the circuit, thereby improving the circuit's radiation resistance.

Description

Technical Field

[0001] The present invention relates to the technical field of static random access memory unit circuits, in particular to an RHBD-12T radiation-resistant SRAM memory unit, a chip and a module. Background Art

[0002] In an environment without atmospheric protection, various radiation from space can penetrate spacecraft and the electronic equipment within them, and static random access memory (SRAM) can also be affected. As SRAM becomes increasingly integrated, the probability of single event upsets (SEUs) (Single Event Effects) (SETs) affecting SRAM is increasing. SEUs are a major reliability failure mechanism that can cause electronic system failures by temporarily changing stored values. When a charged particle strikes a sensitive node on an integrated circuit, the induced charge along its path can be effectively collected and accumulated through a drift process. Once the transient voltage pulse generated by the accumulated charge exceeds the switching threshold of the circuit, the stored value in the sensitive node may change, causing the stored data of the entire circuit to flip.

[0003] Several methods have been adopted in the prior art to improve the unit's ability to resist SEU, such as Figure 1 The single-event upset-resistant DICE-12T circuit shown in the figure uses four storage nodes and four transmission transistors. When an SEU occurs on a single storage node, that node will eventually recover from the other nodes. However, if an SEU occurs on any two storage nodes, the stored information in that circuit node will be flipped and unable to recover, resulting in data errors. Figure 2 The QUATRO-10T circuit shown has better SEU immunity than the traditional six-tube cell structure, but the write capability of this cell is poor, and its hold noise margin HSNM and read static noise margin RSNM are poor; Figure 3 The RHPD-12T circuit shown in the figure can resist some double-node flips in addition to single-node flips, but at the expense of lower HSNM and RSNM. Figure 4 The QUCCE-12T circuit shown is resistant to all single-node upsets and has a high read static noise margin RSNM, but its critical charge is small; Figure 5 The SEA-14T circuit shown, although it reduces the number of sensitive nodes, results in a larger read latency and lower HSNM and RSNM values. Summary of the Invention

[0004] Based on this, it is necessary to provide RHBD-12T radiation-resistant SRAM storage cells, chips, and modules to address the problems of larger read delays and lower HSNM values caused by improving the cell's ability to resist SEU.

[0005] To achieve the above object, the present invention adopts the following technical solutions:

[0006] The RHBD-12T radiation-hardened SRAM memory cell, based on source isolation and polarity hardening technology, includes:

[0007] PMOS transistor P1;

[0008] A PMOS transistor P2, wherein the source of P2 is electrically connected to the source of P1;

[0009] A PMOS transistor P3, wherein the source of P3 is electrically connected to the drain of P1;

[0010] a PMOS transistor P4, wherein the source of P4 is electrically connected to the drain of P2, the drain of P4 is electrically connected to the gate of P3, and the gate of P4 is electrically connected to the drain of P3;

[0011] NMOS transistor N1, the drain of N1 is electrically connected to the drain of P3 and the gate of P4, and the gate of N1 is electrically connected to the gate of P3 and the drain of P4;

[0012] NMOS transistor N2, the source of N2 is electrically connected to the source of N1, the drain of N2 is electrically connected to the drain of P4, the gate of P3, and the gate of N1, and the gate of N2 is electrically connected to the gate of P4, the drain of P3, and the drain of N1;

[0013] an NMOS transistor N3, wherein the source of N3 is electrically connected to the gate of P2, the drain of N3 is electrically connected to the drain of P1, and the gate of N3 is electrically connected to the source of P2 and the source of P1;

[0014] an NMOS transistor N4, wherein the source of N4 is electrically connected to the gate of P1, the drain of N4 is electrically connected to the drain of P2, and the gate of N4 is electrically connected to the gate of N3, the source of P2, and the source of P1;

[0015] NMOS transistor N5, the source of N5 is electrically connected to the source of N2 and the source of N1, the drain of N5 is electrically connected to the source of N3 and the gate of P2, and the gate of N5 is electrically connected to the drain of P4, the drain of N2, the gate of P3, and the gate of N1;

[0016] NMOS transistor N6, the source of N6 is electrically connected to the source of N5, the source of N2, and the source of N1, the drain of N6 is electrically connected to the source of N4 and the gate of P1, and the gate of N6 is electrically connected to the drain of P3, the gate of N2, the gate of P4, the drain of P3, and the drain of N1;

[0017] NMOS transistor N7, wherein the drain of N7 is electrically connected to the drain of N1 and the drain of P3, the source of N7 is electrically connected to the bit line BL, and the gate of N7 is electrically connected to the word line WL;

[0018] NMOS transistor N8, wherein the drain of N8 is electrically connected to the drain of N2 and the drain of P4, the source of N8 is electrically connected to the bit line BLB, and the gate of N8 is electrically connected to the word line WL;

[0019] The sources of transistors P1 and P2 are connected to VDD, the sources of transistors N1, N2, N5, and N6 are connected to ground, transistors P1 to P4 and N3, N4 serve as pull-up transistors, and transistors N1, N2, N5, and N6 serve as pull-down transistors; transistors N1 and P3 form an inverter, transistors N2 and P4 form another inverter, and the two inverters are cross-coupled; the two main storage nodes Q and QB are connected to the bit line BL and the bit line BLB respectively through N7 and N8, and transistors N7 and N8 are controlled by the word line WL.

[0020] Furthermore, the gate length of all transistors is 65nm, wherein the gate width of transistors P1 to P4 is 80nm, the gate width of transistors N3 and N4 is 80nm, the gate width of transistors N1, N2, N5, and N6 is 280nm, and the gate width of transistors N7 and N8 is 140nm.

[0021] In one embodiment, when the memory cell is in the holding stage, the bit lines BL and BLB are precharged to a high level, the word line WL is at a low level, and the memory cell maintains its initial state and does not operate.

[0022] In one embodiment, when the memory cell is in the data reading phase, the bit lines BL and BLB are precharged to a high level, the word line WL is at a high level, and the transistors N7 and N8 are turned on.

[0023] Furthermore, if the data stored in the memory cell is '0', then "Q=S0=0, QB=S1=1"; the bit line BL is discharged to the ground through transistors N7 and N1, so that a voltage difference is generated between the bit line BL and the bit line BLB, and the data is read out through the sense amplifier.

[0024] Furthermore, if the data stored in the memory cell is '1', then "Q=S0=1, QB=S1=0"; the bit line BLB is discharged to the ground through transistors N8 and N2, so that a voltage difference is generated between the bit lines BL and BLB, and the data is read out through the sense amplifier.

[0025] In one embodiment, the memory cell is in the data writing phase, the word line WL is high, if the bit line BL is high and the bit line BLB is low, then '1' is written to the storage nodes Q and S0 through the transistor N7.

[0026] In one embodiment, the memory cell is in the data writing phase, the word line WL is high, if the bit line BL is low and the bit line BLB is high, '0' is written to the storage nodes QB and S1 through the transistor N8.

[0027] The present invention also includes an RHBD-12T radiation-resistant SRAM memory chip based on source isolation and polarity reinforcement technology, which is packaged using the circuit of the aforementioned RHBD-12T radiation-resistant SRAM memory unit based on source isolation and polarity reinforcement technology. The pins of the memory chip include:

[0028] A first pin electrically connected to the gates of transistors N7 and N8 through a word line WL;

[0029] a second pin electrically connected to the source of the transistor N7 through the bit line BL;

[0030] The third pin is electrically connected to the source of the transistor N8 through the bit line BLB.

[0031] The present invention also includes an RHBD-12T radiation-resistant SRAM memory module based on source isolation and polarity reinforcement technology, which adopts the circuit of the aforementioned RHBD-12T radiation-resistant SRAM memory cell based on source isolation and polarity reinforcement technology. The memory module includes:

[0032] The gates of transistors N7 and N8 are electrically connected to a word line WL, thereby leading to a first connection terminal;

[0033] The source of the transistor N7 is electrically connected to the bit line BL, thereby leading to a second connection terminal;

[0034] The source of the transistor N8 is electrically connected to the bit line BLB, thereby leading to a third connection terminal.

[0035] The technical solution provided by the present invention has the following beneficial effects:

[0036] By setting only two sensitive storage nodes, the present invention greatly reduces the number of sensitive nodes and the area of the sensitive region of the circuit, thereby improving the radiation resistance of the circuit, being able to tolerate the flipping of all single-node data, significantly improving the SEU resistance of the unit circuit, and having a faster reading speed and a higher maintenance noise margin HSNM. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A schematic diagram of the structure of DICE-12T in the prior art provided as background technology for the present invention;

[0038] Figure 2 A schematic diagram of the structure of a QUATRO-10T circuit in the prior art provided as background technology for the present invention;

[0039] Figure 3 A schematic diagram of the structure of the RHPD-12T circuit in the prior art provided as background technology of the present invention;

[0040] Figure 4 A schematic diagram of the structure of a QUCCE-12T circuit in the prior art provided as background technology for the present invention;

[0041] Figure 5 A schematic diagram of the structure of a SEA-14T circuit in the prior art provided as background technology for the present invention;

[0042] Figure 6 This is a schematic structural diagram of the RHBD-12T radiation-resistant SRAM memory cell based on source isolation and polarity reinforcement technology of the present invention;

[0043] Figure 7 Based on Figure 1 Timing waveform simulation diagram;

[0044] Figure 8 Based on Figure 1 Transient waveform simulation diagram of the storage node of the memory cell injected with double exponential current source pulses at different times;

[0045] Figure 9 Based on Figure 1 Comparison diagram of HSNM, RSNM, and WSNM of the memory cell and other typical SRAM cell circuits;

[0046] Figure 10 Based on Figure 1 The simulation result diagram of the sensitive node of the storage unit using three-dimensional simulation software;

[0047] Figure 11 For Figure 1 Schematic diagram of the structure of the RHBD-12T radiation-resistant SRAM memory chip based on basic source isolation and polarity reinforcement technology. DETAILED DESCRIPTION

[0048] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0049] like Figure 6 As shown, this embodiment provides an RHBD-12T radiation-resistant SRAM memory cell based on source isolation and polarity reinforcement technology, which mainly includes NMOS transistors N1 to N8 and PMOS transistors P1 to P4. PMOS transistors P1, P2, P3, P4 and NMOS transistors N3 and N4 serve as pull-up transistors, and NMOS transistors N1, N2, N5, and N6 serve as pull-down transistors; N1 and P3 form an inverter, N2 and P4 form another inverter, and the two inverters are cross-coupled; two main storage nodes Q and QB are respectively connected to bit lines BL and BLB through two NMOS transistors N7 and N8, and the two NMOS transistors N7 and N8 are controlled by word line WL.

[0050] The specific connection method is as follows: the bit line BL is electrically connected to the source of the transfer transistor N7; the bit line BLB is electrically connected to the source of the transistor N8; the word line WL is electrically connected to the gates of the transfer transistors N7 and N8; the drain of the transfer transistor N7 is electrically connected to the drains of the NMOS transistor N1 and the PMOS transistor P3; the drain of the transfer transistor N8 is electrically connected to the drains of the NMOS transistor N2 and the PMOS transistor P4; VDD is electrically connected to the sources of the PMOS transistors P1 and P2; the sources of the NMOS transistors N1, N2, N5, and N6 are grounded.

[0051] The drain of the PMOS transistor P1 is electrically connected to the source of the PMOS transistor P3 and the drain of the NMOS transistor N3, and the gate of the PMOS transistor P1 is electrically connected to the source of the NMOS transistor N4 and the drain of the NMOS transistor N6; the drain of the PMOS transistor P2 is electrically connected to the source of the PMOS transistor P4 and the drain of the NMOS transistor N4, and the gate of the PMOS transistor P2 is electrically connected to the source of the NMOS transistor N3 and the drain of the NMOS transistor N5; the drain of the PMOS transistor P3 is electrically connected to the drain of the NMOS transistor N1, the gate of the NMOS transistor N2, the gate of the PMOS transistor P4, The gate of the NMOS transistor N6 is electrically connected, and the gate of the PMOS transistor P3 is electrically connected to the drain of the NMOS transistor N2, the drain of the PMOS transistor P4, the gate of the NMOS transistor N5, and the gate of the NMOS transistor N1; the drain of the PMOS transistor P4 is electrically connected to the drain of the NMOS transistor N2, the gate of the NMOS transistor N1, the gate of the PMOS transistor P3, and the gate of the NMOS transistor N5, and the gate of the PMOS transistor P4 is electrically connected to the drain of the NMOS transistor N1, the drain of the PMOS transistor P3, the gate of the NMOS transistor N6, and the gate of the NMOS transistor N2.

[0052] The drain of the NMOS transistor N1 is electrically connected to the drain of the PMOS transistor P3, the gate of the PMOS transistor P4, the gate of the NMOS transistor N2, and the gate of the NMOS transistor N6, and the gate of the NMOS transistor N1 is electrically connected to the gate of the PMOS transistor P3, the drain of the PMOS transistor P4, the gate of the NMOS transistor N5, and the drain of the NMOS transistor N2; the drain of the NMOS transistor N2 is electrically connected to the drain of the PMOS transistor P4, the gate of the PMOS transistor P3, the gate of the NMOS transistor N1, and the gate of the NMOS transistor N5, and the gate of the NMOS transistor N2 is electrically connected to the gate of the PMOS transistor P4, the drain of the PMOS transistor P3, the gate of the NMOS transistor N6, and the drain of the NMOS transistor N1; the drain of the NMOS transistor N3 is electrically connected to the drain of the PMOS transistor P1, and the source of the NMOS transistor N3 is electrically connected to the drain of the PMOS transistor P1. The gate of the NMOS transistor N3 is electrically connected to the drain of the PMOS transistor P2 and the drain of the NMOS transistor N5, and the gate of the NMOS transistor N3 is electrically connected to VDD; the drain of the NMOS transistor N4 is electrically connected to the drain of the PMOS transistor P2, the source of the NMOS transistor N4 is electrically connected to the gate of the PMOS transistor P1 and the drain of the NMOS transistor N6, and the gate of the NMOS transistor N4 is electrically connected to VDD; the drain of the NMOS transistor N5 is electrically connected to the source of the NMOS transistor N3 and the gate of the PMOS transistor P2, and the gate of the NMOS transistor N5 is electrically connected to the drain of the PMOS transistor P4 and the drain of the NMOS transistor N2; the drain of the NMOS transistor N6 is electrically connected to the source of the NMOS transistor N4 and the gate of the PMOS transistor P1, and the gate of the NMOS transistor N6 is electrically connected to the drain of the PMOS transistor P3 and the drain of the NMOS transistor N1.

[0053] The gate length of all MOS transistors is 65nm, among which the gate width of PMOS transistors is 80nm, the gate width of NMOS transistors N3 and N4 is 80nm, the gate width of N1, N2, N5, and N6 is 280nm, and the gate width of transmission transistors N7 and N8 is 140nm.

[0054] The principle of the RHBD-12T radiation-resistant SRAM memory cell based on source isolation and polarity hardening technology is as follows: During the hold phase, both bit lines BL and BLB are precharged to a high level, while word line WL is low. The circuit maintains its initial state and does not operate. During the read phase, both bit lines BL and BLB are precharged to a high level, word line WL is high, and pass transistors N7 and N8 are turned on. If the cell circuit stores a '0' value, then "Q = S0 = 0, QB = S1 = 1." BL then discharges to ground through transistors N7 and N1, creating a voltage difference between bit lines BL and BLB. The data is then read out through a sense amplifier. If the cell circuit stores a '1' value, then "Q = S0 = 1, QB = S1 = 0." BLB then discharges to ground through transistors N8 and N2, creating a voltage difference between bit lines BL and BLB. The data is then read out through a sense amplifier. In the data writing phase, word line WL is at a high level. If BL is at a high level and BLB is at a low level, then '1' is written to storage nodes Q and S0 through transfer transistor N7; if BL is at a low level and BLB is at a high level, then '0' is written to storage nodes QB and S1 through transfer transistor N8.

[0055] For the analysis of the circuit structure's radiation resistance performance, assuming that the circuit stores data "Q=S0=0, QB=S1=1", if the circuit's storage node is bombarded by particles, since the circuit nodes S0 and S1 are surrounded by NMOS transistors, according to the polarity reinforcement principle, the space particles bombard the sensitive node (the drain end of the closed NMOS transistor), and can only generate a "1-0" voltage pulse at the node. The voltage pulse cannot change the S0 data, so it does not affect the switching state of other transistors, which prevents the data of other storage nodes from flipping.

[0056] For node Q, its pull-up transistors are P1 and P3, which are connected in series and use source isolation reinforcement technology, making it difficult for the data stored at point Q to flip to '1'. The switching states of transistors P4, N2, and N6 remain unchanged, so the data at other storage nodes will not flip.

[0057] When node QB flips to '0', P3 turns on. At this point, the data in S1 remains unchanged, and P1 remains off, so the data stored in node Q remains unchanged. Simultaneously, nodes S0 and Q turn P2 and P4 on, restoring the data in node QB to '1'. Similarly, node S1 can also be restored to its original state after a data flip. If particles strike other non-critical nodes, the storage cell is less susceptible to impact.

[0058] It can be seen that the RHBD-12T radiation-resistant SRAM memory cell provided by the embodiment of the present invention has only two sensitive storage nodes and can tolerate data flipping in all single nodes, thereby significantly improving the SEU resistance of the unit circuit.

[0059] The simulation conditions are set as Corner: TT; Temperature: 27°C; VDD: 1.2V. The timing waveform of the RHBD-12T radiation-resistant SRAM memory cell of this embodiment is shown in FIG. Figure 7 As shown; the transient waveform simulation diagram of the double exponential current source pulse injection of the sensitive node of the RHBD-12T radiation-resistant SRAM memory cell of this embodiment at different times is shown as follows Figure 8 As shown; the RHBD-12T radiation-resistant SRAM memory cell of this embodiment and other typical SRAM cell circuits HSNM, RSNM, WSNM comparison diagram as shown Figure 9 As shown in the figure, the charge injection simulation of the sensitive nodes of the RHBD-12T radiation-resistant SRAM storage unit is performed using three-dimensional simulation software. Assuming that the circuit storage data is "Q=S0=0, QB=S1=1", the floating node "A=0, B=1", the bombardment angle is θ=0° (vertical bombardment), and the bombardment position is the drain end of the closed transistor (N6 drain: S1, N2 drain: QB, P0 drain: A, P3 drain: Q), the simulation results are shown in the figure. Figure 10 shown.

[0060] Setting the same simulation conditions as above, a comparison table of read and write time and power consumption simulations of the RHBD-12T radiation-resistant SRAM memory cell provided in this embodiment and the SRAM cell circuit of the prior art is shown in the following table:

[0061] Simulation comparison table

[0062] unit Read latency (ps) Write latency (ps) Power consumption (μW) DICE 60.8 27.3 21.79 Quatro 119.2 388.02 15.19 SEA-14T 100.4 39.7 15.09 RHPD-12T 57.5 20.4 15.27 QUCCE-12T 44.61 34.7 15.28 RHBD-12T 44.2 34.8 15.44

[0063] Setting the same simulation conditions as above, the critical charge comparison table of the RHBD-12T radiation-resistant SRAM memory cell provided in this embodiment is shown in the following table:

[0064] Critical Charge Comparison Table

[0065] Circuit Name Critical charge (fC) Quatro 9.96 QUCCE-12T 18.95 RHPD-12T 32.61 DICE >50 SEA-14T >50 RHBD12T >50

[0066] The critical charge is the maximum amount of charge that can be collected before the data of the circuit node is flipped. The larger the value, the stronger the circuit's ability to resist SEU.

[0067] The memory cell of this embodiment uses two large pull-down transistors, N1 and N2. During data reading, the bit line is discharged through transfer transistors N1 and N7 or N2 and N8. Due to the strong drive capability of transistors N1 and N2, a faster read speed is achieved. Simulation results show that compared to the five existing SRAM cells, the present invention maintains the most outstanding noise margin (HSNM) and exhibits significant advantages in SEU resistance.

[0068] like Figure 11 As shown, based on the aforementioned RHBD-12T radiation-resistant SRAM memory cell based on source isolation and polarity reinforcement technology, an RHBD-12T radiation-resistant SRAM memory chip based on source isolation and polarity reinforcement technology is provided. The memory chip is packaged by the circuit of the RHBD-12T radiation-resistant SRAM memory cell. The pins of the memory chip include: a first pin, which is electrically connected to the gates of transistors N7 and N8 through a word line WL; a second pin, which is electrically connected to the source of transistor N7 through a bit line BL; and a third pin, which is electrically connected to the source of transistor N8 through a bit line BLB.

[0069] The chip packaging model makes it easier to promote and apply the RHBD-12T radiation-resistant SRAM memory unit.

[0070] Based on the aforementioned RHBD-12T radiation-resistant SRAM memory cell based on source isolation and polarity reinforcement technology, an RHBD-12T radiation-resistant SRAM memory module based on source isolation and polarity reinforcement technology is provided, the memory module including: a circuit of a D-12T radiation-resistant SRAM memory cell, the memory module including: the gates of transistors N7 and N8 are electrically connected to the word line WL, thereby leading to a first connection terminal; the source of transistor N7 is electrically connected to the bit line BL, thereby leading to a second connection terminal; the source of transistor N8 is electrically connected to the bit line BLB, thereby leading to a third connection terminal.

[0071] Setting it into module mode makes it easy for technicians in this field to use it quickly. They only need to refer to the product manual and make circuit connections on the connection ends of the module.

[0072] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0073] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. The RHBD-12T radiation-resistant SRAM memory cell based on source isolation and polarity reinforcement technology is characterized by: It includes: PMOS transistor P1; A PMOS transistor P2, wherein the source of P2 is electrically connected to the source of P1; A PMOS transistor P3, wherein the source of P3 is electrically connected to the drain of P1; a PMOS transistor P4, wherein the source of P4 is electrically connected to the drain of P2, the drain of P4 is electrically connected to the gate of P3, and the gate of P4 is electrically connected to the drain of P3; NMOS transistor N1, the drain of N1 is electrically connected to the drain of P3 and the gate of P4, and the gate of N1 is electrically connected to the gate of P3 and the drain of P4; NMOS transistor N2, the source of N2 is electrically connected to the source of N1, the drain of N2 is electrically connected to the drain of P4, the gate of P3, and the gate of N1, and the gate of N2 is electrically connected to the gate of P4, the drain of P3, and the drain of N1; an NMOS transistor N3, wherein the source of N3 is electrically connected to the gate of P2, the drain of N3 is electrically connected to the drain of P1, and the gate of N3 is electrically connected to the source of P2 and the source of P1; an NMOS transistor N4, wherein the source of N4 is electrically connected to the gate of P1, the drain of N4 is electrically connected to the drain of P2, and the gate of N4 is electrically connected to the gate of N3, the source of P2, and the source of P1; NMOS transistor N5, the source of N5 is electrically connected to the source of N2 and the source of N1, the drain of N5 is electrically connected to the source of N3 and the gate of P2, and the gate of N5 is electrically connected to the drain of P4, the drain of N2, the gate of P3, and the gate of N1; NMOS transistor N6, the source of N6 is electrically connected to the source of N5, the source of N2, and the source of N1, the drain of N6 is electrically connected to the source of N4 and the gate of P1, and the gate of N6 is electrically connected to the drain of P3, the gate of N2, the gate of P4, the drain of P3, and the drain of N1; NMOS transistor N7, wherein the drain of N7 is electrically connected to the drain of N1 and the drain of P3, the source of N7 is electrically connected to the bit line BL, and the gate of N7 is electrically connected to the word line WL; NMOS transistor N8, wherein the drain of N8 is electrically connected to the drain of N2 and the drain of P4, the source of N8 is electrically connected to the bit line BLB, and the gate of N8 is electrically connected to the word line WL; The sources of transistors P1 and P2 are connected to VDD, the sources of transistors N1, N2, N5, and N6 are connected to ground, transistors P1 to P4 and N3, N4 serve as pull-up transistors, and transistors N1, N2, N5, and N6 serve as pull-down transistors; transistors N1 and P3 form an inverter, transistors N2 and P4 form another inverter, and the two inverters are cross-coupled; the two main storage nodes Q and QB are connected to the bit line BL and the bit line BLB respectively through N7 and N8, and transistors N7 and N8 are controlled by the word line WL.

2. The RHBD-12T radiation-resistant SRAM memory cell based on source isolation and polarity reinforcement technology according to claim 1, characterized in that: The gate length of all transistors is 65nm, among which the gate width of transistors P1 to P4 is 80nm, the gate width of transistors N3 and N4 is 80nm, the gate width of transistors N1, N2, N5 and N6 is 280nm, and the gate width of transistors N7 and N8 is 140nm.

3. The RHBD-12T radiation-resistant SRAM memory cell based on source isolation and polarity reinforcement technology according to claim 1, characterized in that: When the memory cell is in the holding stage, the bit lines BL and BLB are precharged to a high level, the word line WL is at a low level, and the memory cell maintains an initial state and does not operate.

4. The RHBD-12T radiation-resistant SRAM memory cell based on source isolation and polarity reinforcement technology according to claim 1, characterized in that: When the memory cell is in the data reading phase, the bit lines BL and BLB are precharged to a high level, the word line WL is at a high level, and the transistors N7 and N8 are turned on.

5. The RHBD-12T radiation-resistant SRAM memory cell based on source isolation and polarity reinforcement technology according to claim 4, characterized in that: If the data stored in the memory cell is '0', then "Q=S0=0, QB=S1=1"; the bit line BL is discharged to the ground through transistors N7 and N1, so that a voltage difference is generated between the bit line BL and the bit line BLB, and the data is read out through the sense amplifier.

6. The RHBD-12T radiation-resistant SRAM memory cell based on source isolation and polarity reinforcement technology according to claim 4, characterized in that: If the data stored in the memory cell is '1', then "Q=S0=1, QB=S1=0"; the bit line BLB is discharged to the ground through transistors N8 and N2, so that a voltage difference is generated between the bit lines BL and BLB, and the data is read out through the sense amplifier.

7. The RHBD-12T radiation-resistant SRAM memory cell based on source isolation and polarity reinforcement technology according to claim 1, characterized in that: The memory cell is in the data writing phase, the word line WL is at a high level, if the bit line BL is at a high level and the bit line BLB is at a low level, then '1' is written to the storage nodes Q and S0 through the transistor N7.

8. The RHBD-12T radiation-resistant SRAM memory cell based on source isolation and polarity reinforcement technology according to claim 1, characterized in that: The memory cell is in the data writing phase, the word line WL is at a high level, if the bit line BL is at a low level and the bit line BLB is at a high level, '0' is written to the storage nodes QB and S1 through the transistor N8.

9. The RHBD-12T radiation-resistant SRAM memory chip based on source isolation and polarity reinforcement technology is characterized by: It is formed by encapsulating the circuit of the RHBD-12T radiation-resistant SRAM memory cell based on the source isolation and polarity reinforcement technology according to any one of claims 1 to 8, and the pins of the memory chip include: A first pin electrically connected to the gates of transistors N7 and N8 through a word line WL; a second pin electrically connected to the source of the transistor N7 through the bit line BL; The third pin is electrically connected to the source of the transistor N8 through the bit line BLB.

10. An RHBD-12T radiation-hardened SRAM memory module based on source isolation and polarity hardening technology, comprising: The gates of transistors N7 and N8 are electrically connected to a word line WL, thereby leading to a first connection terminal; The source of the transistor N7 is electrically connected to the bit line BL, thereby leading to a second connection terminal; The source of the transistor N8 is electrically connected to the bit line BLB, thereby leading to a third connection terminal.

Images