Chip testing method, apparatus, device, and medium

Abstract

The application provides a chip test method, device, equipment and medium, comprising: providing a first test stimulus, determining the corresponding public state information and the stimulus time point of the first test stimulus according to the first test stimulus and the public state table; wherein the public state table stores each public state information of the chip after simulation at different times under different stimuli; determining the starting time point of the first test stimulus according to the stimulus time point; loading the corresponding public state information of the first test stimulus to the chip; and simulating the chip with the first test stimulus after the starting time point. The scheme can improve the chip test efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to memory technology, and in particular, to a chip testing method, device, apparatus and medium. BACKGROUND

[0002] With the development of memory technology, memory is widely used, such as Dynamic Random Access Memory (DRAM). In practical applications, in order to ensure the reliability of the product, the design circuit of the chip needs to be tested, that is, chip testing.

[0003] Therefore, how to improve the efficiency of chip testing becomes a problem to be considered. SUMMARY

[0004] Embodiments of the present application provide a chip testing method, device, apparatus and medium.

[0005] According to some embodiments, the first aspect of the present application provides a chip testing method, comprising: providing a first test stimulus, determining the corresponding public state information and the stimulus time point of the first test stimulus according to the first test stimulus and the public state table; wherein the public state table stores each public state information of the chip after simulation at different times under different stimuli; determining the starting time point of the first test stimulus according to the stimulus time point; loading the public state information corresponding to the first test stimulus to the chip; simulating the chip with the first test stimulus after the starting time point.

[0006] In some embodiments, the determining the corresponding public state information and the stimulus time point of the first test stimulus according to the first test stimulus and the public state table comprises: according to the test attribute of the first test stimulus and the public state table, taking the public state information matching the test attribute as the public state information corresponding to the first test stimulus; determining the stimulus time point corresponding to the first test stimulus according to the test attribute of the first test stimulus; wherein the test attribute comprises at least one of the following: stimulus frequency, process angle and test function.

[0007] In some embodiments, the method further comprises: respectively for different stimuli with different test attributes, simulating the chip under the stimulus, and extracting the public state information of the chip after simulation at different times and storing it to the public state table.

[0008] In some embodiments, the common state table stores respective common state information of the chip when completing configuration of a mode register under different excitations and / or respective common state information of the chip after completing configuration of a delay-locked loop parameter under different excitations.

[0009] In some embodiments, the method further comprises: detecting whether a mode register setting function is normal; and determining the common state information and the excitation time point corresponding to the first test excitation according to the first test excitation and the common state table comprises: if the mode register setting function is normal, determining the common state information and the excitation time point corresponding to the first test excitation according to the first test excitation and the common state table.

[0010] In some embodiments, the detection of whether the mode register setting function is normal comprises: testing the chip according to a second test excitation, the second test excitation comprising a mode register setting instruction; and if decoding of the mode register setting instruction is correct, determining that the mode register setting function is normal.

[0011] In some embodiments, the method further comprises: detecting whether a time length required by the delay-locked loop to complete locking of a clock exceeds a predetermined threshold according to a third test excitation; and determining the common state information and the excitation time point corresponding to the first test excitation according to the first test excitation and the common state table comprises: if the time length does not exceed the threshold, determining the common state information and the excitation time point corresponding to the first test excitation according to the first test excitation and the common state table.

[0012] In some embodiments, the chip comprises a double data rate synchronous dynamic random access memory.

[0013] In some embodiments, the test function corresponding to the first test excitation comprises at least one of the following: a read operation function, a write operation function, a read-write operation function, a self-refresh function, a refresh function, an impedance calibration function, and a power-down pre-charge function.

[0014] According to some embodiments, the second aspect of the present application provides a chip testing device, comprising: a determination module configured to provide a first test excitation, and determine common state information and an excitation time point corresponding to the first test excitation according to the first test excitation and a common state table; wherein the common state table stores respective common state information of the chip after simulation at different times under different excitations; the determination module is further configured to determine a starting time point of the first test excitation according to the excitation time point; a loading module configured to load the common state information corresponding to the first test excitation to the chip; and a simulation module configured to simulate the first test excitation after the starting time point on the chip.

[0015] In some embodiments, the determining module is specifically configured to: according to the test attribute of the first test stimulus and the common state table, determine the common state information matching the test attribute as the common state information corresponding to the first test stimulus; and according to the test attribute of the first test stimulus, determine the stimulus time point corresponding to the first test stimulus; wherein the test attribute comprises at least one of the following: stimulus frequency, process angle, and test function.

[0016] In some embodiments, the apparatus further comprises an extracting module configured to simulate the chip under different stimuli with different test attributes, extract common state information of the chip after different simulation times, and store the common state information into the common state table.

[0017] In some embodiments, the common state table stores each common state information of the chip when completing configuration of a mode register under different stimuli and / or each common state information of the chip after completing configuration of a delay-locked loop parameter under different stimuli.

[0018] In some embodiments, the apparatus further comprises a first detecting module configured to detect whether a mode register setting function is normal; and the determining module is specifically configured to, if the mode register setting function is normal, determine the common state information and the stimulus time point corresponding to the first test stimulus according to the first test stimulus and the common state table.

[0019] In some embodiments, the first detecting module is specifically configured to test the chip according to a second test stimulus, wherein the second test stimulus comprises a mode register setting instruction; and the first detecting module is specifically further configured to determine that the mode register setting function is normal if decoding of the mode register setting instruction is correct.

[0020] In some embodiments, the apparatus further comprises a second detecting module configured to detect whether a time length required by a delay-locked loop to complete locking of a clock exceeds a predetermined threshold according to a third test stimulus; and the determining module is specifically configured to, if the time length does not exceed the threshold, determine the common state information and the stimulus time point corresponding to the first test stimulus according to the first test stimulus and the common state table.

[0021] In some embodiments, the chip comprises a double data rate synchronous dynamic random access memory.

[0022] In some embodiments, the test function corresponding to the first test stimulus comprises at least one of the following: read operation function, write operation function, read-write operation function, self-refresh function, refresh function, impedance calibration function, and power-down pre-charge function.

[0023] According to some embodiments, the third aspect of the present application provides an electronic device, comprising: a processor, and a memory connected with the processor in communication; the memory stores computer execution instructions; the processor executes the computer execution instructions stored in the memory to implement the method as described above.

[0024] According to some embodiments, the fourth aspect of the present application provides a computer readable storage medium, wherein the computer readable storage medium stores computer execution instructions, and the computer execution instructions are executed by a processor to implement the method as described above.

[0025] In the chip testing method, device, equipment and medium provided by the embodiments of the present application, the corresponding common state information and the excitation time point are determined for the currently provided first test excitation, wherein the common state information is the state information of the chip after a certain time of simulation under the similar excitation of the first test excitation, and then the common state information is loaded to the chip, and the excitation time point is used as the starting time point of the first test excitation, so that the chip simulation of the entire first test excitation can be realized only by performing the chip simulation based on the first test excitation after the starting time point. In the above scheme, the common state information is directly loaded to the chip, and the chip simulation is performed based on the test excitation after the starting time point, without the need to perform the test excitation before the starting time point, so that the chip simulation under the test excitation can be completed, thereby effectively reducing the time consumption of chip testing and improving the chip testing efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0026] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present application and, together with the specification, serve to explain the principles of the embodiments of the present application.

[0027] Figure 1 The architecture example diagram of the memory shown in an embodiment of the present application is shown in the following figure:

[0028] Figure 2 The structure example diagram of the memory unit shown in an embodiment of the present application is shown in the following figure:

[0029] Figure 3 The state example diagram of DDR is shown in the following figure:

[0030] Figure 4 The test excitation flow example diagram of chip testing is shown in the following figure:

[0031] Figure 5 The flow example diagram of the chip testing method provided by an embodiment is shown in the following figure:

[0032] Figure 6 The conventional timing verification flow is shown in the following figure:

[0033] Figure 7 The simulation process schematic diagram of an example is shown in the following figure:

[0034] Figures 8 to 9 A flowchart example of a chip test method provided for each example;

[0035] Figure 10 A timing verification flowchart for an example;

[0036] Figures 11 to 12 A flowchart example of a chip test method provided for each example;

[0037] Figures 13 to 16 A structural example of a chip test device provided for an embodiment;

[0038] Figure 17 A structural schematic diagram of an electronic device provided in an embodiment.

[0039] The specific embodiments of the present application have been shown through the above-described drawings, and will be described in more detail hereinafter. These drawings and the written description are not intended to restrict the scope of the present application by any means, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0040] The exemplary embodiments will be described in detail herein with reference to the attached drawings. The same reference numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments are not meant to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as detailed in the appended claims.

[0041] The terms "comprise" and "have" in the present application are used to represent an open-ended inclusion, and mean that additional elements / components / etc. can be present in addition to the listed elements / components / etc.; the terms "first" and "second" etc. are used only as labels, and are not meant to limit the number of objects. In addition, the different elements and regions in the drawings are only schematically shown, and thus the present application is not limited to the sizes or distances shown in the drawings.

[0042] The technical solutions of the present application will be described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes can not be described again in some embodiments. The embodiments of the present application will be described below with reference to the drawings.

[0043] Figure 1 A structural example of a memory shown in an embodiment of the present application is as follows: Figure 1As shown, taking DRAM as an example, it includes data input / output buffer, row decoder, column decoder, sense amplifier and storage array. The storage array is mainly composed of word lines, bit lines and storage cells. The word lines in the storage array extend along the row direction, the bit lines in the storage array extend along the column direction, and the intersection of the word lines and the bit lines is the storage cell of the storage array.

[0044] Each storage cell is used to store one bit of data. As shown, Figure 2 Figure 2 As shown in the structural diagram of the storage cell according to an embodiment of the present application, the storage cell is mainly composed of a transistor M and a capacitor C. The capacitor is used to store data, and the transistor is used to turn off or turn on according to the state of the word line.

[0045] A certain storage cell can be activated by controlling the row and column to achieve access to the storage cell. Taking the reading scenario as an example: when the data in the storage cell needs to be read, the word line of the row where the storage cell is located can be selected by the row decoder, and correspondingly, the transistor M in the diagram is turned on, and the state on the capacitor C can be sensed by sensing the bit line signal. For example, if the data stored in the storage cell is 1, then the transistor M will read 1 from the bit line of the storage cell after being turned on, and vice versa. In addition, taking the writing scenario as an example: when data needs to be written to a certain storage cell, such as writing 1. The word line of the row where the storage cell is located can be selected by the row decoder, and correspondingly, the transistor M in the diagram is turned on, and the capacitor C is charged by setting the logic level of the bit line to 1, that is, 1 is written to the storage cell. Conversely, if 0 is to be written, the logic level of the bit line is set to 0, so that the capacitor C is discharged, that is, 0 is written to the storage cell.

[0046] In practical applications, in order to ensure the reliability of the memory product, chip testing needs to be performed in the chip design stage, and the chip testing involves the working principle of the memory. Taking double data rate synchronous dynamic random access memory (DDR) as an example, as shown, Figure 3 Figure 3 ​​For the state diagram of DDR, it first includes Power on, Reset Procedure and Initialization. ZQCL means impedance (ZQ) calibration after power on initialization is completed. ZQCL triggers the calibration engine inside the DRAM, and once the calibration is completed, the calibrated value is transferred to the DRAM input-output (IO) pin, and is reflected as the output drive and on-die termination (ODT) resistance. ZQCS means periodic calibration, which can change with voltage and temperature changes. In addition, the Active Power-Down mode, the memory bank (Bank) is still open after the in-progress command, and the memory enters the Active Power-Down mode; the Precharge Power-Down mode, which refers to the memory bank (Bank) that is closed after the in-progress command, enters the Precharge Power-Down mode; Figure 3 Examples can be understood in conjunction with related technologies, which will not be introduced here.

[0047] Among them, MRS is MODE Register Set, that is, mode register setting. In order to apply flexibility, different functions, features and modes, etc. in the mode register (Mode Register, referred to as MR) on the DDR chip, are realized by programming. The mode register has no default value, so the mode register will be initialized after power on or reset, so that the DDR can work normally. However, it should be noted that the mode register can also be rewritten in the normal working mode. For example, the mode register is divided into MR0, MR1, MR2 and MR4, etc. MR0 is used to store the data of different operation modes of DDR: including but not limited to burst length, read burst type, column address strobe pulse (CAS) delay, test mode, delay-locked loop (Delay-locked Loop, referred to as DLL) reset, etc. MR1 is used to store whether to enable DLL, output drive length, Rtt_Nom, additional length, write level enable, etc. MR2 is used to store the characteristics of controlling updates, Rtt_WR impedance, and CAS write delay, etc. MR3 is used to control multi-purpose register (Multi-purpose register, referred to as MPR), etc. MR4 is used to control the CS to CMD / ADDR delay mode, temperature control refresh mode enable, maximum low power mode enable, etc. MR5 is used to control the parity function enable, etc. MR5 is used to adjust the reference voltage signal (VREFDQ) for the internal data bus, etc.

[0048] Therefore, when testing the chip, the above initialization also needs to be performed first to make the memory chip enter a working state, and the test is performed in the working state. Based on the above example of the working principle of DDR, the flow of the chip test is approximately as shown in Figure 4 Figure 4 The test excitation flowchart of the chip test is shown in the figure. Correspondingly, the test excitation execution chart of the chip test shows the flow, that is, first, the chip is powered on, reset, initialized, ZQ calibrated, mode register configured (or loaded), and the like. Then, the chip is simulated and tested based on the functional test excitation for different test requirements and functions.

[0049] In actual application, in order to ensure the chip test, such as timing verification, as many functions as possible are covered, and many combinations between functions are considered. Therefore, a large number of test excitations need to be executed, and a long time is needed.

[0050] Some aspects of the embodiments of the present application are related to the above considerations. The schemes are exemplarily introduced below in combination with some embodiments of the present application.

[0051] Figure 5 The flowchart of the chip test method provided by an embodiment is shown in Figure 5 The chip test method comprises the following steps.

[0052] Step 101: providing a first test excitation, determining the public state information corresponding to the first test excitation and the excitation time point according to the first test excitation and the public state table;

[0053] Step 102: determining the starting time point of the first test excitation according to the excitation time point;

[0054] Step 103: loading the public state information corresponding to the first test excitation to the chip;

[0055] Step 104: simulating the chip with the first test excitation after the starting time point.

[0056] In actual application, the chip test method provided by the embodiment can be applied to the test of various memory chips. As an example, the chip test method can be applied to DDR chips and the like. As an example, the chip includes but is not limited to double-rate synchronous dynamic random access memory. The chip in the embodiment can be regarded as a design under test (DUT).

[0057] ​The first test stimulus required to verify the function can be determined as required. For example, the test function corresponding to the first test stimulus can include at least one of the following: read operation function, write operation function, read-write operation function, self-refresh function, refresh function, impedance calibration function, and power-down pre-charge function.

[0058] It can be understood that, in order to ensure the reliability of verification, it is necessary to cover various functions and various combinations of various functions as much as possible, and therefore a large number of test stimuli are required. The simulation process of these test stimuli is based on the conventional simulation process described above, and requires a preparation process such as mode register configuration. In this embodiment, the public state table stores the public state information of the chip after simulation for different times under different stimuli. The different stimuli can be determined according to different test requirements and functions, and the stimulus attributes of different stimuli, such as stimulus frequency, process angle, and test function, can be partially the same or different. In this embodiment, the public state information is used to represent the state of the chip at a certain time, such as the state of the chip after a certain time of simulation. Based on the loading of the public state information, the corresponding state can be realized in the chip. The form and content of the public state information can be realized in various ways. As an example, the public state information can include the level state of each node of the chip.

[0059] After the public state table is established, when simulation testing is required, the stimuli in the test stimulus corresponding to the time period of each public state information in the public state information can be directly skipped, that is, based on the public state information, the state of the chip is directly loaded as the state after a certain time of simulation, and only the subsequent test stimulus is used for testing, that is, the test effect of the entire test stimulus can be completed. Specifically, chip testing is performed by inputting the stimulus values of different interface signals at different times into the chip, so the time of the stimulus is actually the same as the time of the finally generated simulation waveform. In this embodiment, the pre-stage of each simulation test process is skipped, such as the pre-preparation process required for each simulation test, and the subsequent simulation test is performed from the starting time point of the simulation test process, such as the stimulus for the function. The chip can be simulated directly from the start, so that the pre-preparation process is not required for each simulation, the time of the entire simulation is effectively shortened, and the simulation test efficiency is greatly improved.

[0060] In order to more intuitively understand the scheme of this embodiment, examples are illustrated in combination with the accompanying drawings:

[0061] Figure 6For a conventional timing verification process, as shown in the figure, the pre-preparation stage of simulation usually includes reset, mode register configuration, delay locked loop parameter configuration, etc. The stage after configuration mainly involves relevant tests for functions, which include, for example, activation command execution test, read-write command execution test, etc. Generally, the timing verification process tests the signals on the interface by inputting them into the chip through excitation. For example, the excitation time is 1.2 microseconds (us). The time consumed by power-on, reset, mode register configuration, and delay locked loop parameter configuration accounts for more than 70% of the total simulation test time. For example, the simulation time T(t) = A + B(t)P; where A refers to the simulation compilation time, which is used to check whether the file exists and read the input file, etc.; B is related to the excitation time, t represents the length of the excitation time, and the longer the length of the excitation time, the longer this time; P is related to the simulation machine. If the simulation machine has many tasks and occupies a lot of memory at that time, this time will be longer. As shown in the figure, taking the configuration of MR0-MR5 of DDR as an example, the time consumed by the reset process is about 250 nanoseconds (ns); the time consumed by the configuration of the six mode registers is about 6xtMRD (minimum load mode register command period), about 60 ns; and the time consumed by the configuration of the delay locked loop parameter is about 700 ns. Therefore, in the simulation process, the preparation stage in the early stage occupies a large amount of time, and these preparation stages actually belong to the process that is repeatedly executed for each test excitation.

[0062] To this end, in the embodiment, the common state information of the chip after simulation for different times under different excitations is pre-established and stored, which is used for subsequent simulation calling, by taking advantage of the feature that the excitation time is consistent with the simulation waveform time. Figure 7 An example is performed, Figure 7 An example of a simulation process is shown in the figure. Different excitation attributes are pre-generated. It should be noted that the excitation at this time is used to extract common state information, so only simple excitation needs to be generated for the acquisition of common state information, so as to further simplify the simulation process. Based on the generated excitation, the chip simulation is performed to obtain the common state information after simulation for a certain time, such as a waveform file. According to the above method, the common state table is established based on the common state information of the chip after simulation for different times under different excitations. The common state table includes common state information and excitation time points. The excitation time point depends on the time length of the simulation, and the common state information is used to represent the state of the chip at a certain time. There are many ways to represent it. In an example, the common state information can be a waveform file obtained after the chip is simulated for a certain time under excitation.

[0063] Correspondingly, when chip simulation needs to be performed subsequently, the first test stimulus can be generated according to the test requirement. Compared with the conventional simulation process, the chip is simulated based on the first test stimulus starting from the beginning. In this embodiment, the common state information corresponding to the first test stimulus and the stimulus time point are obtained from the common state table according to the first test stimulus. Since the stimulus time point represents the time length of simulation, the starting time point of the first test stimulus can be determined based on the stimulus time point. For example, assuming that the stimulus time point is ten minutes after the start of the stimulus, the starting time point of the first test stimulus is correspondingly a time point ten minutes after the start of the first test stimulus. After the common state information corresponding to the first test stimulus and the stimulus time point are determined, the common state information is directly loaded to the chip, so that the chip is directly in the state after a certain time of simulation, and the chip simulation is performed subsequently from the first test stimulus after the starting time point. In combination with the foregoing example, the remaining simulation is directly performed from the first test stimulus after the tenth minute, that is, the entire simulation process of the chip is completed. The dashed line in the figure represents a stage that needs to be performed in the conventional simulation process, but based on the scheme of this embodiment, the stage does not need to be performed. It can be seen that the scheme of this embodiment can effectively shorten the simulation time.

[0064] In actual application, the time length and result required for simulation can be different if the test attributes of simulation test are different. Therefore, in one example, the common state information in the common state table is related to the test attributes of simulation test. The test attributes represent environmental parameters and functions of the test. As an example, the test attributes include at least one of the following: stimulus frequency, process angle, and test function.

[0065] Therefore, in order to accurately determine the common state information corresponding to the first test stimulus and the stimulus time point from the common state table, in one example, as shown in Figure 8 Figure 8 FIG. 1 is a flowchart of an example of a chip test method provided by an embodiment. In step 101, the common state information corresponding to the first test stimulus and the stimulus time point are determined according to the first test stimulus and the common state table, specifically including:

[0066] Step 201: According to the test attributes of the first test stimulus and the common state table, the common state information matching the test attributes is taken as the common state information corresponding to the first test stimulus.

[0067] Step 202: According to the test attributes of the first test stimulus, the stimulus time point corresponding to the first test stimulus is determined. The test attributes include at least one of the following: stimulus frequency, process angle, and test function.

[0068] ​Specifically, in the example, the association between the test stimulus and the common state information is established based on the test attribute. The test attribute represents the simulation environment parameters, functions, etc. of the test stimulus, which can include but is not limited to the stimulus frequency, process angle, and test function, etc. In actual application, the test stimulus file usually contains information such as stimulus frequency, process angle, and test function, etc., and these information will affect the state of the chip after a certain time of simulation.

[0069] Therefore, in the example, the test attribute is used as the mapping association between the test stimulus and the common state information at each stimulus time point. When the simulation of the first test stimulus is needed, the stimulus attribute of the first test stimulus can be determined first, such as the stimulus frequency, process angle, and test function, and then the common state information with the same test attribute, i.e. the common state information corresponding to the first test stimulus, is determined from the common state table. In addition, the common state information is established based on the simulation of the chip under different test attributes of the test stimulus for a certain time, so the corresponding stimulus time point of the first test stimulus can be determined based on the test attribute.

[0070] In the example, the test attribute is used to accurately represent the test stimulus and the common state information of the chip after simulation for different times under different stimuli, so that the association between the two is established based on the test attribute, and the corresponding common state information and stimulus time point of the current test stimulus can be accurately determined from the common state table during subsequent simulation test.

[0071] In order to establish the common state table, in one example, as shown in Figure 9 , the chip test method provided by an embodiment includes the following steps. Figure 9 The flowchart of the chip test method provided by an embodiment is shown in the following figure.

[0072] Step 301: For different stimuli with different test attributes, the chip is simulated under the stimulus, and the common state information of the chip after simulation for different times is extracted and stored in the common state table.

[0073] Specifically, in order to establish the common state table, the chip is simulated for different lengths of time based on different test stimuli. The test stimuli have different test attributes. The test attributes here include, but are not limited to, test attributes such as test frequency, process corner, and test function. In addition, different test attributes include cases where all attributes are different, and cases where some attributes are different. For example, assume that the test attributes of test stimulus 1 include a test frequency of 800 Hz, a process corner of TT (NFET-Typical corner & PFET-Typical corner), and a test function of mode register configuration; the test attributes of test stimulus 2 include a test frequency of 700 Hz, a process corner of FF (NFET-FAST corner & PFET-FAST corner), and a test function of delay locked loop parameter configuration. It can be clearly determined that the test attributes of test stimulus 1 and test stimulus 2 are different. In addition, there is another case, assume that the test attributes of test stimulus 3 include a test frequency of 800 Hz, a process corner of TT, and a test function of delay locked loop parameter configuration, then the test attributes of test stimulus 3 and test stimulus 1 are also different.

[0074] Through the flow of the present example, the chip is simulated for different lengths of time based on test stimuli with different test attributes. The length of time can depend on the process that is expected to be skipped in subsequent simulation. For example, assume that the process of mode register configuration needs to be skipped in subsequent simulation, then when establishing the common state table, the chip can be simulated based on test stimuli with different test attributes until the mode register configuration is completed. The length of time from the start of the simulation to the completion of the mode register configuration is the length of time for which the chip is simulated, and the time point at which the mode register configuration is completed is the stimulus time point corresponding to the test attribute of the test stimulus.

[0075] It should be noted that test stimuli with the same test attribute can also be simulated for different lengths of time to obtain different common state information and stimulus time points. For example, the chip can be simulated under test stimulus 1 until the mode register configuration is completed to obtain common state information 1 and stimulus time point 1 corresponding to the test attributes of test stimulus 1; the chip can also be simulated under test stimulus 1 until the delay locked loop parameter configuration is completed to obtain common state information 2 and stimulus time point 2 corresponding to the test attributes of test stimulus 1.

[0076] Through the above examples, common state information after the chip is simulated for different lengths of time under different test attributes of test stimuli can be established, the coverage of the common state table is improved, the common state information and stimulus time points under various test stimuli are enriched, and it is ensured that corresponding common state information and stimulus time points can be obtained from the common state table during subsequent simulation testing, thereby improving the efficiency and reliability of chip testing.

[0077] Based on the foregoing description, the solution described in the above embodiments can skip repetitive preliminary processes during chip testing, such as initialization, mode register configuration, and delay-locked loop (PLL) parameter configuration. In one example, the common state table stores the common state information of the chip when configuring the mode register under different stimuli and / or the common state information of the chip after configuring the delay-locked loop (PLL) parameters under different stimuli.

[0078] like Figure 10 As shown, Figure 10 This is an example of a timing verification process. When chip testing is required, for the current first test stimulus, the common state information and stimulus time point corresponding to the first test stimulus can be obtained from the common state table. Assuming the stimulus time point is the time point for completing the configuration of the delay-locked loop parameters, based on the scheme of the aforementioned embodiment, the common state information can be directly loaded into the chip. Then, based on the test stimuli after the start time point corresponding to the self-stimulation time point in the first test stimulus, the chip can be simulated. As can be seen in the figure, process 1 enclosed in the dashed box can be omitted, and process 2 can be directly executed to complete the test stimulus.

[0079] Furthermore, to further improve the reliability of chip testing, skipped functions are first tested before simulation tests are performed after the start time point. Only if the skipped function tests are successful are subsequent functional simulation tests conducted, ensuring the accuracy of the entire simulation test results. Therefore, in one example, such as... Figure 11 As shown, Figure 11 The flowchart illustrates a chip testing method according to one embodiment. Based on any embodiment, the method further includes:

[0080] Step 401: Check if the mode register setting function is normal;

[0081] Accordingly, step 101, which involves determining the common state information and the activation time point corresponding to the first test stimulus based on the first test stimulus and the common state table, specifically includes:

[0082] Step 402: If the mode register setting function is normal, then determine the common state information and excitation time point corresponding to the first test stimulus based on the first test stimulus and the common state table.

[0083] In this example, before executing the aforementioned chip testing scheme, it is first checked whether the functions corresponding to the skipped processes are normal. Specifically, in this example, this refers to the functions corresponding to the mode register setting process. If the functions corresponding to the skipped processes are normal, then the aforementioned chip testing scheme is used for chip testing.

[0084] It can be understood that the purpose of the chip test is to obtain accurate results of the overall function test of the chip, so although the common state table is established to skip some early test stages considering the timeliness of the test, the functions involved in the skipped test stages also affect the test results of the whole chip. Therefore, in this example, the functions involved in the skipped test stages are detected first, and if the detection result is normal, the subsequent chip test based on other test excitations can directly skip the functions with normal detection results, thereby reducing the test time while ensuring the accuracy and reliability of the chip test.

[0085] To this end, in order to realize the detection of the mode register setting function, in an implementable manner, the mode register setting function can be detected by simulation test. As an example, step 401 can specifically include: testing the chip according to a second test excitation, the second test excitation including a mode register setting instruction; and if the decoding of the mode register setting instruction is correct, determining that the mode register setting function is normal.

[0086] Specifically, the detection of the mode register setting function mainly involves detecting whether the mode register can respond to the setting instruction to perform normal mode register setting. Therefore, in this embodiment, a second test excitation including a mode register setting instruction is provided, which is input into the chip, and the execution of the mode register setting instruction is detected to realize the test of the mode register setting function. In practical applications, if the decoding of the mode register setting instruction is correct, it can be determined that the mode register setting function is normal.

[0087] The above embodiment realizes the test of the mode register setting function by detecting whether the decoding of the mode register setting instruction is correct through the second test excitation including the mode register setting instruction, thereby ensuring the accuracy and reliability of the subsequent chip test.

[0088] Similarly, in order to ensure the accuracy of the overall simulation test result, in another example, as shown in Figure 12 , the chip test method provided by an embodiment includes: Figure 12 As an example, the method further includes:

[0089] Step 501: detecting whether the time length required by the delay-locked loop to complete the locking of the clock exceeds a predetermined threshold according to a third test excitation;

[0090] Correspondingly, the determination of the common state information and the excitation time point corresponding to the first test excitation according to the first test excitation and the common state table in step 101 specifically includes:

[0091] Step 502: If the time length does not exceed the threshold, determining the public state information and the excitation time point corresponding to the first test excitation according to the first test excitation and the public state table.

[0092] In the example, the skipped process includes the configuration of the DLL parameter, and therefore, the configuration function of the DLL parameter is detected first. If the function is detected to be normal, the chip is tested by using the foregoing chip test scheme. In the example, the functions involved in the skipped test stage are also detected first. If the detection result is normal, when the chip is tested based on other test excitations subsequently, the functions with the normal detection result can be directly skipped, so that the test time is reduced while the accuracy and reliability of the chip test are ensured.

[0093] Specifically, in order to detect the configuration function of the DLL parameter, in the example, a third test excitation is provided and input into the chip. Whether the time length required by the DLL to complete the locking of the clock (i.e., the DLL time length) exceeds a predetermined threshold is detected, so as to test the function of the DLL. In actual application, if the DLL time length does not exceed the predetermined threshold, it can be determined that the configuration function of the DLL parameter is normal. The predetermined threshold can be set based on the JEDEC standard.

[0094] In the foregoing embodiment, the third test excitation is used to detect whether the time length required by the DLL to complete the locking of the clock exceeds a predetermined threshold, so as to test the configuration function of the DLL parameter, and thus the accuracy and reliability of the subsequent chip test are ensured.

[0095] It should be noted that the foregoing two examples can be implemented independently or in combination. For example, the mode register setting stage can be skipped, or the mode register setting stage can be performed, the DLL parameter configuration stage can be skipped, or the DLL parameter configuration stage can also be performed, as shown in the examples. Figure 10 As shown, both the mode register setting stage and the DLL parameter configuration stage are skipped. Correspondingly, the foregoing means for testing the function of the mode register setting and the function of the DLL parameter configuration can also be implemented independently or in combination. Through the foregoing examples, the functions involved in the skipped stage can be detected by using a relatively simple test excitation, so as to support the subsequent test starting from the time point after the start time point, thereby further simplifying the test, improving the test efficiency, and ensuring the accuracy of the test.

[0096] In the chip test method provided in the embodiment, the corresponding common state information and the excitation time point are determined for the provided first test excitation, the common state information is the state information of the chip after simulation for a certain time under similar excitation of the first test excitation, the common state information is then loaded to the chip, and the excitation time point is used as the starting time point of the first test excitation, so that the chip simulation based on the first test excitation after the starting time point can be performed, and the chip simulation of the entire first test excitation can be realized. In the above scheme, the common state information is directly loaded to the chip, and the chip simulation is performed based on the test excitation after the starting time point, and the test excitation before the starting time point does not need to be performed, so that the entire simulation test under the test excitation can be completed, thereby effectively reducing the time consumption of the chip test and improving the chip test efficiency.

[0097] Figure 13 An example of the structure of the chip test device provided in the embodiment is shown in FIG. 1, which includes a determination module 11, a loading module 12, and a simulation module 13. Figure 13

[0098] The determination module 11 is configured to provide a first test excitation, determine the common state information and the excitation time point corresponding to the first test excitation according to the first test excitation and a common state table, and store each common state information of the chip after simulation for different times under different excitations in the common state table.

[0099] The determination module 11 is further configured to determine the starting time point of the first test excitation according to the excitation time point.

[0100] The loading module 12 is configured to load the common state information corresponding to the first test excitation to the chip.

[0101] The simulation module 13 is configured to provide the first test excitation after the starting time point to perform simulation on the chip.

[0102] For example, the chip includes but is not limited to a double data rate synchronous dynamic random access memory. The function to be verified by the first test excitation can be determined as needed, for example, the test function corresponding to the first test excitation can include at least one of the following: read operation function, write operation function, read-write operation function, self-refresh function, refresh function, impedance calibration function, and power-down pre-charge function.

[0103] ​In this embodiment, the public state table stores the public state information of the chip after simulation for different time under different excitations. The different excitations can be determined according to different test requirements and functions, and the excitation attributes of different excitations, such as excitation frequency, process angle and test function, can be partially the same or different. In this embodiment, the public state information is used to represent the state of the chip at a certain time, and as an example, the public state information can include the level state of each node of the chip. In one example, the public state information can be a waveform file obtained after the chip is simulated for a certain time under excitation.

[0104] In order to accurately determine the public state information corresponding to the first test excitation and the excitation time point from the public state table, in one example, the determination module 11 is specifically configured to: according to the test attribute of the first test excitation and the public state table, determine the public state information matching the test attribute as the public state information corresponding to the first test excitation; and according to the test attribute of the first test excitation, determine the excitation time point corresponding to the first test excitation; wherein the test attribute includes at least one of the following: excitation frequency, process angle and test function.

[0105] In this example, the test attribute is used to accurately represent the test excitation and the public state information of the chip after simulation for different time under different excitations, so as to establish the association between the two based on the test attribute, and facilitate accurate determination of the corresponding public state information and excitation time point of the current test excitation from the public state table during subsequent simulation test.

[0106] In order to establish the public state table, in one example, as shown in Figure 14 Figure 14 The structure example diagram of the chip test device provided by one embodiment is shown in the figure, and the device further includes:

[0107] The extraction module 14 is configured to simulate the chip under different excitations with different test attributes, and extract the public state information of the chip after simulation for different time, and store it to the public state table.

[0108] In this example, the extraction module 14 first simulates the chip for different time based on test excitation with different test attributes, and the time can depend on the process that is expected to be skipped during subsequent simulation. Through the above example, the public state information of the chip after simulation for different time under test excitation with different test attributes can be established, the coverage of the public state table is improved, the public state information and excitation time point under various test excitations are enriched, and it is ensured that the corresponding public state information and excitation time point can be obtained from the public state table during subsequent simulation test, thereby improving the efficiency and reliability of chip test.

[0109] ​In one example, the common state table stores each common state information of the chip when completing configuration of the mode register under different excitations and / or each common state information of the chip after completing configuration of the delay-locked loop parameters under different excitations.

[0110] In addition, in order to further improve the reliability of the chip test, the skipped function is tested for function before the simulation test after the starting time point, so as to ensure the accuracy of the whole simulation test result. In one example, as shown in Figure 15 Figure 15 The structure example diagram of the chip test device provided for an embodiment, on the basis of any example, the device further comprises:

[0111] The first detection module 15 is configured to detect whether the mode register setting function is normal.

[0112] The determination module 11 is specifically configured to, if the mode register setting function is normal, determine the common state information corresponding to the first test excitation and the excitation time point according to the first test excitation and the common state table.

[0113] In the example, before the chip test device executes the aforementioned chip test scheme, the first detection module 15 first detects whether the function corresponding to the skipped flow is normal, which is specifically the function corresponding to the mode register setting flow in the example. If the function corresponding to the skipped flow is normal, the aforementioned chip test scheme is used to perform chip test.

[0114] In order to realize the detection of the mode register setting function, in one implementable manner, the first detection module 15 can detect whether the mode register setting function is normal through simulation test. As an example, the first detection module 15 is specifically configured to test the chip according to a second test excitation, and the second test excitation comprises a mode register setting instruction; the first detection module 15 is specifically further configured to, if the decoding of the mode register setting instruction is correct, determine that the mode register setting function is normal.

[0115] In the above embodiment, the first detection module detects whether the decoding of the mode register setting instruction is correct through the second test excitation comprising the mode register setting instruction, so as to realize the test of the mode register setting function, and further ensure the accuracy and reliability of the subsequent chip test.

[0116] Similarly, in order to ensure the accuracy of the whole simulation test result, in another example, as shown in Figure 16 Figure 16 The structure example diagram of the chip test device provided for an embodiment, on the basis of any example, the device further comprises: ​​

[0117] The second detection module 16 is configured to detect whether a time length required for the delay-locked loop to complete locking of a clock exceeds a predetermined threshold according to a third test stimulus.

[0118] The determination module 11 is specifically configured to determine the common state information corresponding to the first test stimulus and the stimulus time point according to the first test stimulus and the common state table if the time length does not exceed the threshold.

[0119] In this example, the second detection module 16 first detects the configuration function of the delay-locked loop parameters, and if the function is detected to be normal, the foregoing chip test scheme is used to test the chip.

[0120] The foregoing embodiment detects whether a time length required for the delay-locked loop to complete locking of a clock exceeds a predetermined threshold according to a third test stimulus, so as to realize the test of the configuration function of the delay-locked loop parameters, and further ensure the accuracy and reliability of subsequent chip test.

[0121] It should be noted that the foregoing two examples can be implemented alone or in combination. Through the foregoing examples, for the functions involved in the skipped stage, a relatively simple test stimulus can be used for function detection, so as to support subsequent direct test after the starting time point, thereby further simplifying the test, improving the test efficiency, and ensuring the accuracy of the test.

[0122] In the chip test device provided in this embodiment, the determination module determines the corresponding common state information and the stimulus time point for the currently provided first test stimulus, wherein the common state information is state information of the chip after simulation for a certain time under a similar stimulus of the first test stimulus, and then the loading module loads the common state information to the chip, and the subsequent simulation module takes the stimulus time point as the starting time point of the first test stimulus, and only needs to perform chip simulation based on the first test stimulus after the starting time point, so as to realize the chip simulation of the entire first test stimulus. In the foregoing scheme, the common state information is directly loaded to the chip, and the chip simulation is performed based on the test stimulus after the starting time point, without the need to perform the test stimulus before the starting time point, so as to complete the entire simulation test under the test stimulus, thereby effectively reducing the time consumption of the chip test and improving the chip test efficiency.

[0123] Figure 17 For an embodiment, a structural schematic diagram of an electronic device is shown in FIG. 1, Figure 17 The electronic device includes:

[0124] The electronic device further includes a processor 291 and a memory 292; and can further include a communication interface 293 and a bus 294. The processor 291, the memory 292, and the communication interface 293 can communicate with each other through the bus 294. The communication interface 293 can be used for information transmission. The processor 291 can invoke the logical instructions in the memory 292 to execute the method of the above-described embodiments.

[0125] In addition, the logical instructions in the memory 292 described above can be implemented in the form of a software functional unit and sold or used as an independent product, which can be stored in a computer readable storage medium.

[0126] The memory 292, as a computer readable storage medium, can be used to store software programs, computer executable programs, such as program instructions / modules corresponding to the method in the embodiments of the present disclosure. The processor 291 executes the functions and data processing by running the software programs, instructions and modules stored in the memory 292, that is, implements the method in the above-described method embodiments.

[0127] The memory 292 can include a program storage area and a data storage area, wherein the program storage area can store an operating system and at least one application required by a function; the data storage area can store data created according to the use of the terminal device, etc. In addition, the memory 292 can include a high-speed random access memory, and can also include a non-volatile memory.

[0128] The embodiments of the present disclosure provide a computer readable storage medium, the computer readable storage medium stores computer execution instructions, and the computer execution instructions are executed by a processor to implement the method described in the foregoing embodiments.

[0129] Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the application being indicated by the following claims.

[0130] It should be understood that the application is not limited to the precise construction that has been described above and shown in the accompanying drawings and that various modifications and changes can be effected therein by those skilled in the art without departing from the scope of the application. The scope of the application should be limited only by the appended claims.

Claims

1. A chip testing method, characterized in that, include: A first test stimulus is provided, and the common state information and stimulus time point corresponding to the first test stimulus are determined based on the first test stimulus and the common state table; wherein, the common state table stores the common state information of the chip after simulation at different times under different stimuli; Based on the excitation time point, determine the start time point of the first test excitation; Load the common state information corresponding to the first test stimulus into the chip; The chip is simulated using the first test stimulus provided after the start time point; The step of determining the common state information and incentive time point corresponding to the first test incentive based on the first test incentive and the common state table specifically includes: When simulation of the first test stimulus is required, the test attributes of the first test stimulus are first determined, and the common state information consistent with the test attributes is determined from the common state table, that is, the common state information corresponding to the first test stimulus; wherein, the test attributes include at least one of the following: stimulus frequency, process angle, and test function; Based on the common state information corresponding to the first test stimulus, the stimulus time point corresponding to the first test stimulus is determined; wherein, the common state information is established by the chip simulating for a certain period of time under test stimuli of different test attributes, and the common state information is used to characterize the state of the chip at a certain moment.

2. The method according to claim 1, characterized in that, The method further includes: The chip is simulated under different stimuli with different test attributes, and the common state information of the chip after different simulation times is extracted and stored in the common state table.

3. The method according to claim 1, characterized in that, The common state table stores the common state information of the chip when configuring the mode register under different stimuli and / or the common state information of the chip after configuring the delay phase-locked loop parameters under different stimuli.

4. The method according to claim 3, characterized in that, The method further includes: Check if the mode register setting function is working properly; The step of determining the common state information and incentive time point corresponding to the first test incentive based on the first test incentive and the common state table includes: If the mode register setting function is normal, the common state information and excitation time point corresponding to the first test stimulus are determined according to the first test stimulus and the common state table.

5. The method according to claim 4, characterized in that, Whether the detection mode register setting function is normal includes: The chip is tested according to a second test stimulus, the second test stimulus including a mode register setting instruction; If the mode register setting instruction is decoded correctly, the mode register setting function is considered to be normal.

6. The method according to claim 3, characterized in that, The method further includes: Based on the third test stimulus, it is detected whether the time required for the delayed phase-locked loop to complete locking the clock exceeds a predetermined threshold. The step of determining the common state information and incentive time point corresponding to the first test incentive based on the first test incentive and the common state table includes: If the duration does not exceed the threshold, then the public state information and the incentive time point corresponding to the first test incentive are determined according to the first test incentive and the public state table.

7. The method according to any one of claims 1-6, characterized in that, The chip includes a double-rate synchronous dynamic random access memory.

8. The method according to any one of claims 1-6, characterized in that, The test functions corresponding to the first test stimulus include at least one of the following: read operation function, write operation function, read and write operation function, self-refresh function, refresh function, impedance calibration function, and power-down pre-charge function.

9. A chip testing device, characterized in that, include: A determination module is used to provide a first test stimulus and determine the common state information and stimulus time point corresponding to the first test stimulus based on the first test stimulus and a common state table; wherein, the common state table stores the common state information of the chip after simulation at different times under different stimuli; The determining module is further configured to determine the start time point of the first test stimulus based on the stimulus time point; A loading module is used to load the common state information corresponding to the first test stimulus into the chip; The simulation module is used to simulate the chip by providing the first test stimulus after the start time point; The step of determining the common state information and incentive time point corresponding to the first test incentive based on the first test incentive and the common state table specifically includes: When simulation of the first test stimulus is required, the test attributes of the first test stimulus are first determined, and the common state information consistent with the test attributes is determined from the common state table, that is, the common state information corresponding to the first test stimulus; wherein, the test attributes include at least one of the following: stimulus frequency, process angle, and test function; Based on the common state information corresponding to the first test stimulus, the stimulus time point corresponding to the first test stimulus is determined; wherein, the common state information is established by the chip simulating for a certain period of time under test stimuli of different test attributes.

10. The apparatus according to claim 9, characterized in that, The device further includes: The extraction module is used to simulate the chip under different stimuli with different test attributes, and extract the common state information of the chip after different simulation times, and store it in the common state table.

11. The apparatus according to claim 9, characterized in that, The common state table stores the common state information of the chip when configuring the mode register under different stimuli and / or the common state information of the chip after configuring the delay phase-locked loop parameters under different stimuli.

12. The apparatus according to claim 11, characterized in that, The device further includes: The first detection module is used to detect whether the mode register setting function is normal. The determining module is specifically used to determine the common state information and excitation time point corresponding to the first test stimulus based on the first test stimulus and the common state table if the mode register setting function is normal.

13. The apparatus according to claim 12, characterized in that, The first detection module is specifically used to test the chip according to the second test stimulus, the second test stimulus including mode register setting instructions; The first detection module is further configured to determine that the mode register setting function is normal if the mode register setting instruction is decoded correctly.

14. The apparatus according to claim 11, characterized in that, The device further includes: The second detection module is used to detect, based on the third test stimulus, whether the time required for the delay phase-locked loop to complete the clock locking exceeds a predetermined threshold. The determining module is specifically used to determine the public state information and the incentive time point corresponding to the first test incentive based on the first test incentive and the public state table if the duration does not exceed the threshold.

15. The apparatus according to any one of claims 9-14, characterized in that, The chip includes a double-rate synchronous dynamic random access memory.

16. The apparatus according to any one of claims 9-14, characterized in that, The test functions corresponding to the first test stimulus include at least one of the following: read operation function, write operation function, read and write operation function, self-refresh function, refresh function, impedance calibration function, and power-down pre-charge function.

17. An electronic device, characterized in that, include: A processor, and a memory communicatively connected to the processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory to implement the method as described in any one of claims 1-8.

18. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method as described in any one of claims 1-8.

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