IGBT Device and Its Manufacturing Method

Abstract

The present invention provides an IGBT device and a method for preparing the same, wherein the method comprises: forming an etching window in an interlayer insulating dielectric layer; removing the remaining interlayer insulating dielectric layer and an isolation oxide layer of a first thickness; removing a portion of the substrate and a portion of the polysilicon layer; wet etching to remove the isolation oxide layer of a second thickness, thereby forming a second peak and a third peak; and dry etching to remove the second peak and the third peak. By etching the substrate and the polysilicon layer and etching the isolation oxide layer, and then dry etching to remove the remaining second peak and third peak, the present application can effectively process the three materials (substrate, isolation oxide layer, and polysilicon layer) present at the top of a trench emitter structure and the two interfaces formed therein, so that the top of the final trench emitter structure is flat, that is, the upper surface of the substrate, the upper surface of the polysilicon layer, and the upper surface of the isolation oxide layer below the etching window are made flush, thereby improving the yield of the IGBT device.

Description

Technical Field

[0001] The present application relates to the technical field of IGBT device manufacturing, and in particular to an IGBT device and a method for manufacturing the same. Background Art

[0002] RET-IGBT devices feature a recessed-emitter-trench (RET) structure. Compared to planar-gate punch-through IGBTs, RET-IGBTs can further reduce IGBT switching losses and improve the trade-off between on-state voltage drop and turn-off losses. By controlling the depth-to-width ratio of the recessed emitter trench (different ratios of H and W), RET-IGBTs can adjust the ratio of electron and hole injection, achieving products with different trade-offs between on-state voltage drop and turn-off losses. This meets the diverse needs of the IGBT market and improves chip short-circuit energy.

[0003] However, when forming an embedded emitter structure, it is currently difficult to achieve a smooth transition on the surface of the embedded emitter structure due to the presence of two interfaces formed by three substances Si-SiO2-Poly at the top of the embedded emitter structure. Summary of the Invention

[0004] The present application provides an IGBT device and a method for manufacturing the same, which can solve the problem of difficulty in achieving a smooth transition on the surface of an embedded emitter structure in the existing RET-IGBT device manufacturing process.

[0005] In one aspect, an embodiment of the present application provides a method for preparing an IGBT device, comprising:

[0006] A substrate is provided, wherein a trench emitter structure and trench gate structures located on both sides of the trench emitter structure are formed in the substrate, and an interlayer insulating dielectric layer is formed on the substrate, wherein the trench emitter structure includes: an isolation oxide layer and a polysilicon layer covering the isolation oxide layer;

[0007] removing a portion of the thickness of the interlayer insulating dielectric layer to form an etching window in the interlayer insulating dielectric layer;

[0008] Removing the remaining thickness of the interlayer insulating dielectric layer according to the etching window, wherein while removing the remaining thickness of the interlayer insulating dielectric layer, the isolation oxide layer of the first thickness is over-etched;

[0009] According to the etching window, an etching process is used to remove a certain thickness of the substrate and a certain thickness of the polysilicon layer, wherein in the etching window, the isolation oxide layer and the substrate and the polysilicon layer remaining on two opposite sides of the isolation oxide layer respectively form two first peaks;

[0010] Removing the isolation oxide layer of the second thickness in the first peak by a wet etching process, wherein a second peak is formed at the interface between the isolation oxide layer and the substrate; and a third peak is formed at the interface between the isolation oxide layer and the polysilicon layer;

[0011] The second peak and the third peak are removed by a dry etching process.

[0012] Optionally, in the method for preparing the IGBT device, a wet etching process is used to remove a portion of the thickness of the interlayer insulating dielectric layer to form the etching window in the interlayer insulating dielectric layer.

[0013] Optionally, in the method for preparing the IGBT device, a dry etching process is used to remove the remaining thickness of the interlayer insulating dielectric layer and to over-etch a certain thickness of the isolation oxide layer according to the etching window.

[0014] Optionally, in the method for preparing the IGBT device, while removing the remaining thickness of the interlayer insulating dielectric layer according to the etching window and over-etching the isolation oxide layer of the first thickness, the first thickness of the over-etched isolation oxide layer is 0 μm to 2 μm.

[0015] Optionally, in the method for preparing the IGBT device, a dry etching process is used to remove a certain thickness of the substrate and a certain thickness of the polysilicon layer according to the etching window.

[0016] Optionally, in the method for preparing the IGBT device, the lateral size of the first peak is

[0017] Optionally, in the method for preparing the IGBT device, the lateral size of the second peak is The transverse dimension of the third peak is

[0018] Optionally, in the method for preparing the IGBT device, before removing a portion of the thickness of the interlayer insulating dielectric layer to form the etching window in the interlayer insulating dielectric layer, the method for preparing the IGBT device further includes:

[0019] A patterned photoresist layer is formed.

[0020] Optionally, in the method for preparing the IGBT device, after removing the substrate and the polysilicon layer of a certain thickness by an etching process according to the etching window and before removing the isolation oxide layer of the second thickness in the first peak by a wet etching process, the method for preparing the IGBT device further includes:

[0021] The patterned photoresist layer is removed.

[0022] On the other hand, an embodiment of the present application further provides an IGBT device, including:

[0023] substrate;

[0024] A trench emitter structure, the trench emitter structure being located in the substrate, wherein the trench emitter structure comprises: an isolation oxide layer and a polysilicon layer covering the isolation oxide layer;

[0025] a trench gate structure, the trench gate structure being located in the substrate on both sides of the trench emitter structure;

[0026] An interlayer insulating dielectric layer is located on the substrate; wherein an etching window is formed in the interlayer insulating layer, and the upper surface of the isolation oxide layer and the upper surface of the polysilicon layer below the etching window are both lower than the upper surface of the trench gate structure at the bottom of the interlayer insulating dielectric layer.

[0027] The technical solution of this application has at least the following advantages:

[0028] In the present application, part of the substrate and part of the polysilicon layer are removed by etching. At this time, the isolation oxide layer and the substrate and the polysilicon layer remaining on two opposite sides of the isolation oxide layer respectively form two first peaks; then a wet etching process is used to remove the second thickness of the isolation oxide layer in the first peak. At this time, a second peak is formed at the junction of the isolation oxide layer and the substrate, and a third peak is formed at the junction of the isolation oxide layer and the polysilicon layer; finally, the second peak and the third peak are removed by dry etching, which can well handle the three materials of substrate-isolation oxide layer-polysilicon layer and the two interfaces formed by them (two second peaks and two third peaks) at the top of each side of the trench emitter structure, so that the top of the final trench emitter structure tends to be flat, without any peaks or burrs, that is, the upper surface of the substrate under the etching window, the upper surface of the polysilicon layer and the upper surface of the isolation oxide layer tend to be flush, thereby improving the yield of the IGBT device. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0030] Figure 1 is a flow chart of a method for preparing an IGBT device according to an embodiment of the present invention;

[0031] Figure 2-Figure 7 Schematic diagram of the semiconductor structure in each process step of manufacturing an IGBT device according to an embodiment of the present invention;

[0032] The description of the accompanying drawings is as follows:

[0033] 10-substrate, 20-trench emitter structure, 30-trench gate structure, 21-isolation oxide layer, 31-polysilicon layer, 22-gate oxide layer, 32-gate polysilicon, 40-interlayer insulating dielectric layer, 50-patterned photoresist layer, 51-etching window, 211-first spike, 212-second spike, 213-third spike. DETAILED DESCRIPTION

[0034] The following is a clear and complete description of the technical solutions in this application in conjunction with the accompanying drawings. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0035] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0036] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal connections between two components; they can refer to wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0037] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0038] The inventors have found that the three substances, substrate - isolation oxide layer - polysilicon layer, and the two interfaces formed by them, present at the top of the trench emitter structure, in the existing process, due to improper selection of the etching process and different selective etching ratios of the materials themselves, resulting in spikes at the top of the trench emitter structure, mainly the second spike formed by the substrate - isolation oxide layer and the third spike formed by the isolation oxide layer - polysilicon layer, resulting in the smooth transition of the three substances, substrate - isolation oxide layer - polysilicon layer, and the two interfaces formed by them (two second spikes and two third spikes) not being processed well at the top of the trench emitter structure.

[0039] Based on this, the present invention provides a method for preparing an IGBT device. Figure 1 , Figure 1 1 is a flow chart of a method for preparing an IGBT device according to an embodiment of the present invention, wherein the method for preparing an IGBT device comprises:

[0040] S10: providing a substrate, wherein a trench emitter structure and trench gate structures located on both sides of the trench emitter structure are formed in the substrate, and an interlayer insulating dielectric layer is formed on the substrate, wherein the trench emitter structure includes: an isolation oxide layer and a polysilicon layer covering the isolation oxide layer;

[0041] S20: removing a portion of the thickness of the interlayer insulating dielectric layer to form an etching window in the interlayer insulating dielectric layer;

[0042] S30: removing the interlayer insulating dielectric layer of a remaining thickness according to the etching window, wherein while removing the interlayer insulating dielectric layer of a remaining thickness, the isolation oxide layer of a first thickness is over-etched;

[0043] S40: removing a certain thickness of the substrate and a certain thickness of the polysilicon layer by an etching process according to the etching window, wherein, in the etching window, the isolation oxide layer and the substrate and the polysilicon layer remaining on two opposite sides of the isolation oxide layer respectively form two first peaks;

[0044] S50: removing the isolation oxide layer of the second thickness in the first peak by a wet etching process, wherein a second peak is formed at a junction between the isolation oxide layer and the substrate; and a third peak is formed at a junction between the isolation oxide layer and the polysilicon layer.

[0045] S60: removing the second peak and the third peak by using a dry etching process.

[0046] For details, please refer to Figure 2-Figure 6 , Figure 2-Figure 6 It is a schematic diagram of the semiconductor structure in each process step of preparing an IGBT device according to an embodiment of the present invention.

[0047] First, if Figure 2 As shown, a substrate 10 is provided. A trench emitter structure 20 and a trench gate structure 30 located on either side of the trench emitter structure 20 are formed in the substrate 10. An interlayer insulating dielectric layer 40 is formed on the substrate. The trench emitter structure 20 includes an isolation oxide layer 21 and a polysilicon layer 31 covering the isolation oxide layer 21. Specifically, the trench gate structure 30 includes a gate oxide layer 22 and a gate polysilicon layer 32 covering the gate oxide layer 22. Multiple trenches are formed in the substrate 10. The gate oxide layer 22 and the isolation oxide layer 21 cover the bottom and sidewalls of each trench. The gate polysilicon layer 32 and the polysilicon layer 31 fill the remaining space in each corresponding trench. The substrate 10 may be single crystal silicon and may have a silicon-on-insulator (SOI) or epitaxial layer-on-silicon (EOS) structure. The interlayer insulating dielectric layer 40 may be made of silicon dioxide. The isolation oxide layer 21 may be made of silicon dioxide.

[0048] Then, if Figure 3 As shown, a patterned photoresist layer 50 is formed. Specifically, a photoresist layer is spin-coated on the surface of the substrate 10, and windows are opened on the photoresist layer through a photolithography process to obtain the patterned photoresist layer 50.

[0049] Better, such as Figure 3As shown, a portion of the thickness of the interlayer insulating dielectric layer 40 is removed to form an etching window 51 in the interlayer insulating dielectric layer 40. Specifically, in this embodiment, a wet etching process can be used to remove a portion of the thickness of the interlayer insulating dielectric layer 40 to form the etching window 51 in the interlayer insulating dielectric layer 40. The wet etching process of the present application removes a portion of the thickness of the interlayer insulating dielectric layer 40 in order to form two obtuse angles at the edge of the interlayer insulating dielectric layer 40 in the etching window 51, thereby avoiding right-angle peaks caused by directly dry etching the entire interlayer insulating dielectric layer 40.

[0050] It is worth noting that in another embodiment, the process step of "removing a portion of the thickness of the interlayer insulating dielectric layer 40 to form an etching window 51 in the interlayer insulating dielectric layer 40" may not be performed, and the interlayer insulating dielectric layer 40 may be directly etched using a dry etching process to expose the trench emitter structure.

[0051] Further, such as Figure 4 As shown, according to the etching window 51, the remaining thickness of the interlayer insulating dielectric layer 40 is removed, wherein, while removing the remaining thickness of the interlayer insulating dielectric layer 40, the process has over-etching, thereby etching away the first thickness of the isolation oxide layer 21. Specifically, this embodiment can use a dry etching process to remove the remaining thickness of the interlayer insulating dielectric layer 40 and over-etch the first thickness of the isolation oxide layer 21. Figure 4 It can be seen that in the trench forming the trench emitter structure 20, due to the influence of the dry etching to remove the remaining thickness of the interlayer insulating dielectric layer 40, a part of the thickness of the isolation oxide layer 21 is etched away at the same time, resulting in a portion of the top of the isolation oxide layer 21 being missing. In this embodiment, due to the influence of the dry etching to remove the remaining thickness of the interlayer insulating dielectric layer 40, the thickness of the part of the isolation oxide layer 21 etched away can be 0μm to 2μm.

[0052] Then, if Figure 5As shown, according to the etching window 51, a dry etching process is used to remove a certain thickness of the substrate 10 and a certain thickness of the polysilicon layer 31. At this time, in the etching window 51, the isolation oxide layer 21 and the substrate 10 remaining on the first side and the polysilicon layer 31 remaining on the second side form two first peaks 211, wherein the first side and the second side are opposite to each other. Specifically, due to the different materials of the substrate 10, the polysilicon layer 31, and the isolation oxide layer 21, as well as different etching gases, the selective etching ratios of the substrate 10, the polysilicon layer 31, and the isolation oxide layer 21 are different. In addition, in this embodiment, the dry etching process is anisotropic etching. Therefore, the dry etching process can remove more of the substrate 10 and the polysilicon layer 31, but has little effect on the isolation oxide layer 21, leaving more of the isolation oxide layer 21 unetched. After a certain thickness of the substrate 10 and a certain thickness of the polysilicon layer 31 are removed by dry etching, some residues of the substrate 10 material will be left on one side of the isolation oxide layer 21 and some residues of the polysilicon layer 31 material will be left on the other side of the isolation oxide layer 21, thereby forming two first peaks 211. In this embodiment, the lateral size of the first peak 211 can be

[0053] Further, such as Figure 6 As shown, the patterned photoresist layer 50 is removed.

[0054] Then, if Figure 6 As shown, a wet etching process is used to remove the second thickness of the isolation oxide layer 21 in the first peak 211. Due to reasons such as etching selectivity, after the second thickness of the isolation oxide layer 21 in the first peak 211 is removed, a second peak 212 is formed at the interface between the isolation oxide layer 21 and the substrate 10, and a third peak 213 is formed at the interface between the isolation oxide layer 21 and the polysilicon layer 31. Figure 6 As can be seen, the two symmetrical second peaks 212 are equivalent to two materials (the isolation oxide layer 21 and the substrate 10) + an interface; the two symmetrical third peaks 213 are equivalent to two materials (the isolation oxide layer 21 and the polysilicon layer 31) + an interface. In this embodiment, the wet etching process can effectively remove a large amount of the isolation oxide layer 21. In this embodiment, the lateral size of the second peak 212 is The transverse dimension of the third peak 213 is

[0055] It should be noted that the first thickness and the second thickness of the isolation oxide layer 21 are not necessarily equal to each other, and are only used to describe etching the isolation oxide layer 21 of a certain thickness in several steps.

[0056] Finally, if Figure 7 As shown, the second peak 212 and the third peak 213 are removed by a dry etching process.

[0057] In the present application, a portion of the substrate 10 and a portion of the polysilicon layer 31 are removed by etching. At this time, the substrate 10 and the polysilicon layer 31 remaining on the two opposite sides of the isolation oxide layer 21 respectively form two first peaks 211; then a wet etching process is used to remove the second thickness of the isolation oxide layer 21 in the first peak 211. At this time, a second peak 212 is formed at the junction of the isolation oxide layer 21 and the substrate 10, and a third peak 213 is formed at the junction of the isolation oxide layer 21 and the polysilicon layer 31; then the second peak 212 and the third peak 213 are removed by wet etching, By well processing the three substances of substrate-isolation oxide layer-polysilicon layer (Si-SiO2-Poly) and the two interfaces formed therein (two second peaks 212 and two third peaks 213) existing at the top of each side of the trench emitter structure, the top of the final trench emitter structure 20 tends to be flat without any peaks or burrs, that is, the upper surface of the substrate 10 under the etching window 51, the upper surface of the polysilicon layer 31 and the upper surface of the isolation oxide layer 21 tend to be flush, achieving a smooth transition of the surface of the trench emitter structure 20 (embedded emitter structure), thereby improving the yield of the IGBT device.

[0058] Based on the same inventive concept, the embodiment of the present application further provides an IGBT device, such as Figure 6 As shown, the IGBT device includes:

[0059] substrate 10;

[0060] A trench emitter structure 20 , wherein the trench emitter structure 20 is located in the substrate 10 , wherein the trench emitter structure 20 comprises: an isolation oxide layer 21 and a polysilicon layer 31 covering the isolation oxide layer 21 ;

[0061] A trench gate structure 30 is located in the substrate 10 on both sides of the trench emitter structure 20, wherein the trench gate structure 30 includes: a gate oxide layer 22 and a gate polysilicon 32 covering the gate oxide layer 22;

[0062] An interlayer insulating dielectric layer 40 is located on the substrate 10; wherein an etching window 51 is formed in the interlayer insulating layer 40, and the upper surface of the isolation oxide layer 21 and the upper surface of the polysilicon layer 31 under the etching window 51 are both lower than the upper surface of the trench gate structure 30 at the bottom of the interlayer insulating dielectric layer 40, that is, the flat upper surface of the trench emitter structure 20 is lower than the upper surface of the trench gate structure 30.

[0063] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of this application.

Claims

1. A method for preparing an IGBT device, characterized in that: include: A substrate is provided, wherein a trench emitter structure and trench gate structures located on both sides of the trench emitter structure are formed in the substrate, and an interlayer insulating dielectric layer is formed on the substrate, wherein the trench emitter structure includes: an isolation oxide layer and a polysilicon layer covering the isolation oxide layer; removing a portion of the thickness of the interlayer insulating dielectric layer to form an etching window in the interlayer insulating dielectric layer; Removing the remaining thickness of the interlayer insulating dielectric layer according to the etching window, wherein while removing the remaining thickness of the interlayer insulating dielectric layer, the isolation oxide layer of the first thickness is over-etched; According to the etching window, an etching process is used to remove a certain thickness of the substrate and a certain thickness of the polysilicon layer, wherein in the etching window, the isolation oxide layer and the substrate and the polysilicon layer remaining on two opposite sides of the isolation oxide layer respectively form two first peaks; Removing the isolation oxide layer of the second thickness in the first peak by a wet etching process, wherein a second peak is formed at the interface between the isolation oxide layer and the substrate; and a third peak is formed at the interface between the isolation oxide layer and the polysilicon layer; The second peak and the third peak are removed by a dry etching process.

2. The method for preparing an IGBT device according to claim 1, wherein: A wet etching process is adopted to remove a portion of the thickness of the interlayer insulating dielectric layer to form the etching window in the interlayer insulating dielectric layer.

3. The method for preparing an IGBT device according to claim 1, wherein: According to the etching window, a dry etching process is adopted to remove the remaining thickness of the interlayer insulating dielectric layer and to over-etch the isolation oxide layer to a certain thickness.

4. The method for preparing an IGBT device according to claim 1, wherein: In the process of over-etching the isolation oxide layer having a first thickness while removing the remaining thickness of the interlayer insulating dielectric layer according to the etching window, the first thickness of the over-etched isolation oxide layer is greater than 0 μm and ≤ 2 μm.

5. The method for preparing an IGBT device according to claim 1, wherein: According to the etching window, a dry etching process is adopted to remove a certain thickness of the substrate and a certain thickness of the polysilicon layer.

6. The method for preparing an IGBT device according to claim 1, wherein: The transverse dimension of the first peak is 7. The method for preparing an IGBT device according to claim 1, wherein: The transverse dimension of the second peak is The transverse dimension of the third peak is 8. The method for preparing an IGBT device according to claim 1, wherein: Before removing a portion of the thickness of the interlayer insulating dielectric layer to form the etching window in the interlayer insulating dielectric layer, the method for preparing the IGBT device further includes: A patterned photoresist layer is formed.

9. The method for preparing an IGBT device according to claim 8, wherein: After removing the substrate and the polysilicon layer of a certain thickness by an etching process according to the etching window and before removing the isolation oxide layer of a second thickness in the first peak by a wet etching process, the method for preparing the IGBT device further includes: The patterned photoresist layer is removed.

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