Method of manufacturing fin field effect transistor

Abstract

The application provides a manufacturing method of a fin field effect transistor. The width of each pseudo gate is less than the original width of the pseudo gate according to the original width of the to-be-formed pseudo gate, so that the overall width of the pseudo gate can be reduced, the width of the pseudo gate on the fin is reduced, and the etching rate of the pseudo gate on the fin is less than the etching rate of the pseudo gate in the middle area between the fins when the pseudo gate is etched to form a dielectric layer opening in the interlayer dielectric layer. The second width difference between the width of the dielectric layer opening on the fin and the width of the dielectric layer opening between the fins is less than the first width difference between the width of the pseudo gate on the fin and the width of the pseudo gate in the middle area between the fins, so that the width of the gate on the fin is less different from the width of the gate in the middle area between the fins.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for manufacturing a fin field-effect transistor. Background Technology

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are evolving towards higher component density and higher integration. Transistors, as the most basic semiconductor devices, are currently widely used. Therefore, as the component density and integration of semiconductor devices increase, the gate size of planar transistors is becoming shorter and shorter. Traditional planar transistors have weaker control over channel current, resulting in short-channel effects, leakage current, and ultimately affecting the electrical performance of semiconductor devices. To overcome the short-channel effect of transistors and suppress leakage current, the FinFET (Fin Field-Effect Transistor) has been proposed. The FinFET is a common multi-gate device. A FinFET typically includes a semiconductor substrate, fins located on the surface of the semiconductor substrate, and a gate spanning the fins.

[0003] like Figure 1 As shown, before forming the gate, a dummy gate 12 is typically formed to define the gate's position. The dummy gate 12 is formed by first forming a dummy gate material layer on the substrate 10 and the fin 11, and then etching the dummy gate material layer. However, during the etching process of the dummy gate material layer, due to the presence of the fin, a micro-loading effect is more likely to occur. The etching rate of the dummy gate material layer on the fin and the dummy gate material layer near the sidewall of the fin is lower than the etching rate of the dummy gate material layer on the substrate. Therefore, after forming the dummy gate 12, the width 'a' of the dummy gate 12a on the fin is different from the width 'b' of the dummy gate 12b in the middle region between the fin and the fin. This width difference affects the width of the subsequently formed gate, thus affecting the device's performance. Existing technologies reduce this width difference by increasing the cleaning time, but the effect is not significant. Summary of the Invention

[0004] The purpose of this invention is to provide a method for manufacturing a fin field-effect transistor to reduce the width difference between the gate located on the fin and the gate in the intermediate region between the fin and the fin.

[0005] To achieve the above objectives, the present invention provides a method for manufacturing a fin field-effect transistor, comprising:

[0006] A semiconductor substrate is provided, the surface of which has at least two discrete fins, and a dummy gate material layer is formed on the fins and the semiconductor substrate;

[0007] providing a dummy gate to be formed with an original width;

[0008] etching the dummy gate material layer to form at least two dummy gates across the fin, each of the dummy gates having a width less than the original width of the dummy gate, and each of the dummy gates having a width less than a target width of a gate to be formed, and having a dummy gate opening between adjacent dummy gates, the width of the dummy gate on the fin having a first width difference from the width of the dummy gate in the middle region between the fins;

[0009] filling an interlayer dielectric layer in the dummy gate opening, the top surface of the interlayer dielectric layer being flush with the top surface of the dummy gate;

[0010] etching the dummy gate until the dummy gate is removed to form a dielectric layer opening in the interlayer dielectric layer, wherein, when etching the dummy gate, the etching rate of the dummy gate on the fin is less than the etching rate of the dummy gate in the middle region between the fins;

[0011] increasing the width of the dielectric layer opening to the target width, the width of the dielectric layer opening on the fin having a second width difference from the width of the dielectric layer opening between the fins, the second width difference being less than the first width difference; and,

[0012] filling a gate having the target width in the dielectric layer opening after the width is increased, the top surface of the gate being flush with the top surface of the interlayer dielectric layer.

[0013] Optionally, in the method of manufacturing the fin field effect transistor, the method of etching the dummy gate material layer comprises:

[0014] forming a patterned photoresist layer on the dummy gate material layer, the patterned photoresist layer having at least two photoresist openings exposing the dummy gate, each of the photoresist openings having a width less than the target width of the gate to be formed;

[0015] etching the dummy gate material layer with the patterned photoresist layer as a mask to form at least two dummy gates across the fin; and,

[0016] removing the patterned photoresist layer.

[0017] Optionally, in the method of manufacturing the fin field effect transistor, the material of the dummy gate material layer is polysilicon.

[0018] Optionally, in the method of manufacturing the fin field effect transistor, before filling the interlayer dielectric layer in the dummy gate opening, the method further comprises forming a sidewall layer on the sidewall of the dummy gate opening, and the method of increasing the width of the dielectric layer opening to the target width comprises:

[0019] The sidewall layer is etched along the width direction of the dielectric layer opening by a dry etching process until the width of the dielectric layer opening is increased to the target width.

[0020] Optionally, in the method for manufacturing the fin field effect transistor, after the sidewall layer is etched along the width direction of the dielectric layer opening by the dry etching process, the method further comprises measuring the width of the dielectric layer opening and comparing the measured width of the dielectric layer opening with the target width, and if the measured width of the dielectric layer opening is less than the target width, the interlayer dielectric layer is continuously etched along the width direction of the dielectric layer opening by the dry etching process until the width of the dielectric layer opening is increased to the target width.

[0021] Optionally, in the method for manufacturing the fin field effect transistor, the width of the dielectric layer opening is measured by an optical line width measuring instrument.

[0022] Optionally, in the method for manufacturing the fin field effect transistor, the dummy gate is removed by the dry etching process and / or the wet etching process.

[0023] Optionally, in the method for manufacturing the fin field effect transistor, the material of the gate is metal.

[0024] Optionally, in the method for manufacturing the fin field effect transistor, the material of the interlayer dielectric layer comprises at least one of silicon oxide, silicon nitride and silicon oxynitride.

[0025] Optionally, in the method for manufacturing the fin field effect transistor, after the interlayer dielectric layer is filled in the dummy gate opening, the method further comprises performing chemical mechanical polishing on the top surface of the interlayer dielectric layer so that the top surface of the interlayer dielectric layer is flush with the top surface of the dummy gate.

[0026] In the method for manufacturing the fin field effect transistor provided by the application, before etching the dummy gate material layer to form a dummy gate, the width of each dummy gate formed is less than the original width of the dummy gate according to the original width of the dummy gate to be formed, so that the overall width of the dummy gate can be reduced, and the width of the dummy gate on the fin can be reduced. When the dummy gate is etched to form a dielectric layer opening in the interlayer dielectric layer, the etching rate of the dummy gate on the fin is less than the etching rate of the dummy gate in the middle region between the fins. Accordingly, the width difference between the dielectric layer opening on the fin and the dielectric layer opening between the fins can be small, that is, the second width difference between the width of the dielectric layer opening on the fin and the width of the dielectric layer opening between the fins is less than the first width difference between the width of the dummy gate on the fin and the width of the dummy gate in the middle region between the fins. Accordingly, the width difference between the gate on the fin and the gate in the middle region between the fins can be small. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 is a top view of a prior art fin field effect transistor;

[0028] Figure 2 is a flowchart of a method for manufacturing a fin field effect transistor according to an embodiment of the application;

[0029] Figures 3-10 is a schematic diagram of a structure formed in a method for manufacturing a fin field effect transistor according to an embodiment of the application;

[0030] In the drawings, the following reference signs are used:

[0031] 10 - substrate; 11 - fin; 12 - dummy gate; 12a - dummy gate on the fin; 12b - dummy gate in the middle region between the fins;

[0032] 100 - semiconductor substrate; 101 - fin; 102 - isolation structure; 110 - dummy gate; 110a - dummy gate on the fin; 110b - dummy gate in the middle region between the fins; 120 - interlayer dielectric layer; 120a, 120b - dielectric layer opening; 130 - gate. DETAILED DESCRIPTION

[0033] The method for manufacturing a fin field effect transistor provided by the application will be described in further detail below in combination with the drawings and specific embodiments. The advantages and features of the application will be more apparent from the following description. It should be noted that the drawings are very simplified and use non-precise proportions, and are only used to facilitate and clarify the purpose of assisting the description of the embodiments of the application.

[0034] Figure 2is a flowchart of a manufacturing method of a fin field effect transistor according to an embodiment of the present application. As shown in Figure 2 The present embodiment provides a manufacturing method of a fin field effect transistor, comprising:

[0035] Step S1: providing a semiconductor substrate, a surface of the semiconductor substrate having at least two separate fin portions, the fin portions and the semiconductor substrate being formed with a pseudo gate material layer;

[0036] Step S2: providing an original width of a pseudo gate to be formed;

[0037] Step S3: etching the pseudo gate material layer to form at least two pseudo gates across the fin portions, each of the pseudo gates having a width smaller than the original width of the pseudo gate, and each of the pseudo gates having a width smaller than a target width of a gate to be formed, and the pseudo gates having a pseudo gate opening between adjacent pseudo gates, the width of the pseudo gate on the fin portion and the width of the pseudo gate in the intermediate region between the fin portions having a first width difference;

[0038] Step S4: filling an interlayer dielectric layer in the pseudo gate opening, a top surface of the interlayer dielectric layer being flush with a top surface of the pseudo gate;

[0039] Step S5: etching until the pseudo gate is removed to form a dielectric layer opening in the interlayer dielectric layer, wherein, when etching the pseudo gate, an etching rate of the pseudo gate on the fin portion is smaller than an etching rate of the pseudo gate in the intermediate region between the fin portions;

[0040] Step S6: increasing the width of the dielectric layer opening to the target width, the width of the dielectric layer opening on the fin portion and the width of the dielectric layer opening between the fin portions having a second width difference, the second width difference being smaller than the first width difference; and,

[0041] Step S7: filling a gate having the target width in the dielectric layer opening with the increased width, a top surface of the gate being flush with a top surface of the interlayer dielectric layer.

[0042] Figures 3-10 is a structure diagram formed in a manufacturing method of a fin field effect transistor according to an embodiment of the present application. Hereinafter, the above steps will be described in more detail. Figures 3-10

[0043] Firstly, Step S1 is performed, as shown in Figure 2 A semiconductor substrate 100 is provided, a surface of the semiconductor substrate 100 having at least two separate fin portions 101, the fin portions 101 and the semiconductor substrate 100 being formed with a pseudo gate material layer (not shown).

[0044] ​In this embodiment, the semiconductor substrate 100 is made of silicon. In other embodiments of the present invention, the semiconductor substrate 100 may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, indium gallium dihydrogen phosphate, a silicon substrate on an insulator, or a germanium substrate on an insulator.

[0045] In this embodiment, the fin 101 is made of silicon. In other embodiments of the present invention, the fin 101 may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.

[0046] In this embodiment, an isolation structure 102 is formed between adjacent fins 101, and the isolation structure 102 is used for isolation between the fins 101. The top surface of the isolation structure 102 is lower than the top surface of the fin 101, and the dummy gate material layer covers the isolation structure 102 and the fin 101. The material of the isolation structure 102 can be silicon oxide.

[0047] In this embodiment, the dummy gate material layer is made of polycrystalline silicon and can be formed by chemical vapor deposition. The dummy gate material layer is used to form the dummy gate 110.

[0048] In step S2, the original width of the pseudo gate to be formed is provided, which may be, for example, 30nm to 60nm.

[0049] Next, proceed to step S3, refer to... Figures 4-6 As shown, the dummy gate material layer is etched to form at least two dummy gates 110 spanning the fin 101. The width of each dummy gate 110 is smaller than the original width of the dummy gate, and the width of each dummy gate 110 is smaller than the target width of the gate 130 to be formed. Adjacent dummy gates 110 have dummy gate openings. A first width difference exists between the width c of the dummy gate 110a on the fin 101 and the width d of the dummy gate 110b in the intermediate region between the fins 101. Figure 4 This is a schematic diagram of the cross-sectional structure along the extension direction of the fin 101. Figure 5 This is a top view. Figure 6 This is a schematic diagram of the cross-sectional structure along the direction perpendicular to the extension of the fin 101.

[0050] In this embodiment, the target width of the gate to be formed can be, for example, 20nm to 30nm. The width of the dummy gate 110 can be, for example, 10nm to 20nm.

[0051] Specifically, the method for etching the dummy gate material layer includes: first, forming a patterned photoresist layer (not shown) on the dummy gate material layer, the patterned photoresist layer has at least two photoresist openings exposing the dummy gates 110, and the width of each photoresist opening is less than the target width of the gate 130 to be formed; wherein the photoresist openings are used to define the openings formed between the dummy gates 110.

[0052] Then, the dummy gate material layer is etched with the patterned photoresist layer as a mask to form at least two dummy gates 110 across the fin 101. The dummy gates 110 are used to define the position of the gate 130 to be formed. As shown in Figure 5 During the etching of the dummy gate material layer, due to the presence of the fin 101, the etching rate of the dummy gate 110a located on the fin 101 is lower than that of the dummy gate 110b in the middle region between the fins 101. Therefore, after the formation of the dummy gates 110, the width c of the dummy gate 110a located on the fin 101 is greater than the width d of the dummy gate 110b in the middle region between the fins 101. In this embodiment, the width of each dummy gate 110 is less than the target width of the gate to be formed, that is, the width c of the dummy gate 110a located on the fin 101 and the width d of the dummy gate 110b in the middle region between the fins 101 are both less than the target width of the gate to be formed. Thus, the overall width of the dummy gate 110 can be reduced, thereby reducing the width c of the dummy gate 110a located on the fin 101 and the width d of the dummy gate 110b in the middle region between the fins 101.

[0053] Next, the patterned photoresist layer is removed. The patterned photoresist layer can be removed by a plasma ashing process.

[0054] After that, a sidewall layer 111 is formed on the sidewall of the dummy gate opening, and the material of the sidewall layer 111 can be silicon oxide and / or silicon nitride.

[0055] Next, step S4 is performed, as shown in Figure 7 The interlayer dielectric layer 120 is filled in the dummy gate opening, and the top surface of the interlayer dielectric layer 120 is flush with the top surface of the dummy gate 110. In this embodiment, the interlayer dielectric layer 120 covers the sidewall of the sidewall layer 111, and the material of the interlayer dielectric layer 120 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer 120 can be silicon nitride and / or silicon oxynitride. The interlayer dielectric layer 120 can be formed by a chemical vapor deposition process.

[0056] In this embodiment, the interlayer dielectric layer 120 can be planarized by chemical mechanical polishing, which can improve the flatness of the top surface of the interlayer dielectric layer 120, thereby making the top surface of the interlayer dielectric layer 120 flush with the top surface of the pseudo gate 110 and improving the quality of the interlayer dielectric layer 120.

[0057] Next, proceed to step S5, as follows: Figure 8 As shown, the dummy gate 110 is etched until it is removed to form a dielectric layer opening 120a in the interlayer dielectric layer 120. During the etching of the dummy gate 110, due to the presence of the fins 101, the etching rate of the dummy gate 111a on the fins is lower than the etching rate of the dummy gate 111b in the intermediate region between the fins 101, resulting in a width difference between the width of the dielectric layer opening on the fins 101 and the width of the dielectric layer opening between the fins 101. Since the width of the dummy gate 110 is smaller than the target width of the gate 130 to be formed, the width of the dielectric layer opening 120a will also be smaller than the target width of the gate to be formed after removing the dummy gate 110.

[0058] In this embodiment, the dummy gate 110 can be removed using a dry etching process and / or a wet etching process. Preferably, the dummy gate 110 is removed by combining a dry etching process and a wet etching process to avoid the residue of the dummy gate 110. After the dummy gate 110 is removed, a pit will be formed at the location of the dummy gate 110, which will then form the dielectric layer opening 120a. The dielectric layer opening 120a is used to define the position of the gate 130.

[0059] Next, proceed to step S5, as follows: Figure 9 As shown, the width e of the dielectric layer opening 120a is increased to the target width f. A second width difference exists between the width of the dielectric layer opening on the fin 101 and the width of the dielectric layer opening between the fins 101, and this second width difference is smaller than the first width difference. This reduces the width difference between the width of the gate subsequently formed on the fin 101 and the width of the dummy gate in the intermediate region between the fins 101. Here, increasing the width e of the dielectric layer opening 120a to the target width f means increasing the width of the dielectric layer opening between the fins 101 to the target width f.

[0060] In this embodiment, the sidewall layer 111 is etched along the width direction of the dielectric layer opening 120a by a dry etching process until the width e of the dielectric layer opening 120a is increased to the target width f. During the etching of the sidewall layer 111, the etching rate of the sidewall layer 111 on the fins is lower than that of the sidewall layer 111 in the middle region between the fins due to the presence of the fins. When the width of the dielectric layer opening between the fins 101 is increased to the target width, the second width difference between the width of the dielectric layer opening on the fins 101 and the width of the dielectric layer opening between the fins 101 is smaller than the first width difference, so as to reduce the width difference between the gate on the fins 101 and the gate in the middle region between the fins 101. The process gas of the dry etching process includes sulfur dioxide (SO2), oxygen and helium (He), the flow rate of the sulfur dioxide is 100-200 sccm, the flow rate of the oxygen is 10-50 sccm, and the flow rate of the helium is 20-100 sccm. The dry etching process can be performed in an etching machine with a reactive ion etching (RIE) mode or an inductively coupled plasma (ICP) mode, the pressure in the dry etching process is 10-15 mTorr, and the excitation power is 600-700 W. However, the specific parameters of the dry etching process can be adjusted according to the process requirements and the properties of the etched material.

[0061] Since the sidewall layer 111 is etched by the dry etching process, the etching rate is relatively constant and the etching precision is better because the dry etching process is usually anisotropic etching. In addition, the process gas used in the dry etching process has a very low etching rate on the isolation structure 102 and the fins 101 under the sidewall layer 111, so that the dry etching process can reduce or avoid damaging the isolation structure 102 and the fins 101 under the sidewall layer 111.

[0062] Furthermore, after etching the sidewall layer 111 along the width direction of the dielectric layer opening 120a using a dry etching process, the method further includes measuring the width of the dielectric layer opening 120a and comparing the measured width of the dielectric layer opening 120a with the target width. If the measured width of the dielectric layer opening 120a is less than the target width, the sidewall layer 111 is etched along the width direction of the dielectric layer opening 120a using a dry etching process until the width of the dielectric layer opening 120a increases to the target width. Here, it refers to increasing the dielectric layer opening located between the fins to the target width. When etching the sidewall layer 111, the etching rate of the sidewall layer 111 located on the fins 101 is less than the etching rate of the sidewall layer 111 located between the fins 101, thereby reducing the width difference between the dielectric layer openings located between the fins 101 and the dielectric layer openings located between the fins 101.

[0063] In this embodiment, the width of the opening 120a in the dielectric layer is measured by an optical linewidth measuring instrument. The information contained in the spectral curve reflected back from the surface of the interlayer dielectric layer 120 is analyzed to achieve the purpose of measuring the width of the opening 120a in the dielectric layer.

[0064] Next, proceed to step S7, as follows: Figure 10 As shown, a gate 130 with the target width is filled into the increased width opening 120b of the dielectric layer. The top surface of the gate 130 is flush with the top surface of the interlayer dielectric layer 120. There is a second width difference between the width of the gate 130 on the fin 101 and the width of the gate 130 in the intermediate region between the fins 101, and the second width difference is smaller than the first width difference. The gate 130 spans the fin 101. Because in the aforementioned steps, the width of each formed pseudo-gate is smaller than the original width of the pseudo-gate according to the original width of the pseudo-gate to be formed, the overall width of the pseudo-gate can be reduced, thereby reducing the width of the pseudo-gate on the fin. This also makes the difference between the width of the gate on the fin and the width of the gate in the intermediate region between the fins smaller, thus reducing the dimensional difference between the width of the gate on the fin and the width of the gate in the intermediate region between the fins compared to the prior art.

[0065] In the embodiment, the material of the gate 130 is metal, and specifically includes one or more of tungsten, titanium, tantalum, titanium nitride, tantalum nitride, aluminum titanate, aluminum titanium nitride, copper, aluminum, tungsten, silver, or gold. In the embodiment, atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD) can be used to form the gate 130. Since the width of each dummy gate 110 is less than the target width of the gate 130 to be formed in the foregoing step, after the dummy gate 110 is removed, the width of the dielectric layer opening 120a is not greater than the target width, and thus the width of the gate on the fin 101 and the width of the gate in the middle region between the fins 101 are not greater than the target width, and the size of the device is not increased. Moreover, since the width of the dielectric layer opening 120a is increased to the target width in the foregoing step, the gate 130 formed in the dielectric layer opening 120a has the target width f (the gate in the middle region between the fins has the target width), and the size of the gate 130 is ensured.

[0066] In summary, in the method for manufacturing the fin field effect transistor provided in the embodiment, the width of each dummy gate is less than the original width of the dummy gate to be formed according to the original width of the dummy gate, so that the overall width of the dummy gate can be reduced, and thus the width of the dummy gate on the fin can be reduced. When the dummy gate is etched to form the dielectric layer opening in the interlayer dielectric layer, the etching rate of the dummy gate on the fin is less than the etching rate of the dummy gate in the middle region between the fins, i.e., the second width difference between the width of the dielectric layer opening on the fin and the width of the dielectric layer opening between the fins is less than the first width difference between the width of the dummy gate on the fin and the width of the dummy gate in the middle region between the fins, so that the width of the gate on the fin and the width of the gate in the middle region between the fins are less different.

[0067] The above description is only a description of the preferred embodiments of the present application, and is not intended to limit the scope of the present application. Any modification or change made by a person of ordinary skill in the art based on the above disclosure is within the scope of protection of the claims.

Claims

1. A method for manufacturing a finned field-effect transistor, characterized in that, include: A semiconductor substrate is provided, the surface of which has at least two discrete fins, and a dummy gate material layer is formed on the fins and the semiconductor substrate; Provide the original width of the pseudo-gate to be formed; The dummy gate material layer is etched to form at least two dummy gates spanning the fin, each dummy gate having a width smaller than the original width of the dummy gate, and each dummy gate having a width smaller than the target width of the gate to be formed, and there is a dummy gate opening between adjacent dummy gates, and there is a first width difference between the width of the dummy gate on the fin and the width of the dummy gate in the middle region between the fins. An interlayer dielectric layer is filled into the pseudo-gate opening, and the top surface of the interlayer dielectric layer is flush with the top surface of the pseudo-gate. The dummy gate is etched until it is removed to form a dielectric layer opening in the interlayer dielectric layer, wherein, when the dummy gate is etched, the etching rate of the dummy gate located on the fin is less than the etching rate of the intermediate region located between the fins. The width of the medium layer opening located between the fins is increased to the target width, and there is a second width difference between the width of the medium layer opening on the fin and the width of the medium layer opening between the fins, the second width difference being smaller than the first width difference; as well as, A gate having the target width is filled into the opening of the dielectric layer after the width is increased, and the top surface of the gate is flush with the top surface of the interlayer dielectric layer.

2. The method for manufacturing a finned field-effect transistor as described in claim 1, characterized in that, The method for etching the pseudo-gate material layer includes: A patterned photoresist layer is formed on the dummy gate material layer. The patterned photoresist layer has at least two photoresist openings that expose the dummy gate. The width of each photoresist opening is smaller than the target width of the gate to be formed. The dummy gate material layer is etched using the patterned photoresist layer as a mask to form at least two dummy gates spanning the fin; and, Remove the patterned photoresist layer.

3. The method for manufacturing a finned field-effect transistor as described in claim 1, characterized in that, The pseudo-gate material layer is made of polycrystalline silicon.

4. The method for manufacturing a finned field-effect transistor as described in claim 1, characterized in that, Before filling the dummy gate opening with an interlayer dielectric layer, the method further includes forming a sidewall layer on the sidewall of the dummy gate opening, and increasing the width of the dielectric layer opening to the target width, comprising: The sidewall layer is etched along the width direction of the opening in the dielectric layer using a dry etching process until the width of the opening in the dielectric layer increases to the target width.

5. The method for manufacturing a finned field-effect transistor as described in claim 4, characterized in that, After etching the sidewall layer along the width direction of the dielectric layer opening using a dry etching process, the method further includes measuring the width of the dielectric layer opening and comparing the measured width of the dielectric layer opening with the target width. If the measured width of the dielectric layer opening is less than the target width, the interlayer dielectric layer is etched along the width direction of the dielectric layer opening using a dry etching process until the width of the dielectric layer opening increases to the target width.

6. The method for manufacturing a finned field-effect transistor as described in claim 5, characterized in that, The width of the opening in the dielectric layer is measured using an optical linewidth meter.

7. The method for manufacturing a finned field-effect transistor as described in claim 1, characterized in that, The dummy gate is removed by dry etching and / or wet etching processes.

8. The method for manufacturing a fin field-effect transistor as described in claim 1, characterized in that, The gate is made of metal.

9. The method for manufacturing a fin field-effect transistor as described in claim 1, characterized in that, The material of the interlayer dielectric layer includes at least one of silicon oxide, silicon nitride, and silicon oxynitride.

10. The method for manufacturing a fin field-effect transistor as described in claim 1, characterized in that, After filling the dummy gate opening with an interlayer dielectric layer, the top surface of the interlayer dielectric layer is further subjected to chemical mechanical polishing to make the top surface of the interlayer dielectric layer flush with the top surface of the dummy gate.

Images