A flash memory device and a method of fabricating the same

Abstract

The application provides a flash memory device and a preparation method thereof. The substrate has active regions distributed along a second direction. Each of the active regions comprises source regions and drain regions alternately arranged along a first direction. A plurality of gate structures are distributed on the substrate along the first direction and located between the source regions and the drain regions. A dielectric layer covers the gate structures and the substrate. A plurality of source region plugs extend along the second direction and are distributed along the first direction. Each of the source region plugs is located on a plurality of the source regions and electrically connected with the corresponding plurality of the source regions. A plurality of drain region plugs are electrically connected with the corresponding drain regions. The plurality of the source regions are electrically connected through the source region plugs to form a common source structure of the flash memory device, thereby reducing the size of the flash memory device. Meanwhile, the strip-shaped source region plugs reduce the difficulty in preparation of the source region plugs.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a flash memory device and a preparation method thereof. BACKGROUND

[0002] With the continuous development of semiconductor technology, the process node of semiconductor devices is also continuously reduced, and forming a flash memory device with small size and high density gradually becomes a research and development trend. However, for the flash memory device, reducing the size often causes short channel effect, hot carrier effect and leakage, which has a bad influence on the reliability and service life of the flash memory device. SUMMARY

[0003] The purpose of the present application is to provide a flash memory device and a preparation method thereof, so as to reduce the size of the flash memory device while avoiding problems such as leakage.

[0004] In order to achieve the above purpose, the present application provides a flash memory device and a preparation method thereof, comprising:

[0005] a substrate, the substrate having active regions extending along a first direction and distributed along a second direction, each of the active regions comprising source regions and drain regions arranged alternately along the first direction;

[0006] a plurality of gate structures located on the substrate, extending along the second direction and distributed along the first direction, each of the gate structures being located between the source regions and the drain regions;

[0007] a dielectric layer covering the gate structures and the substrate;

[0008] a plurality of source region plugs located in the dielectric layer, extending along the second direction and distributed along the first direction, each of the source region plugs being located on and electrically connected to a corresponding plurality of the source regions;

[0009] a plurality of drain region plugs located in the dielectric layer, each of the drain region plugs being located on and electrically connected to a corresponding drain region.

[0010] Optionally, adjacent active regions are isolated by a shallow trench isolation structure, and the flash memory device further comprises:

[0011] a conductive layer located in the shallow trench isolation structure and between adjacent source regions, the conductive layer electrically connecting adjacent source regions and corresponding source region plugs.

[0012] Optionally, the gate structure comprises:

[0013] a gate stack comprising a tunneling oxide layer, a floating gate layer, a gate dielectric layer and a control gate layer stacked in the substrate from bottom to top.

[0014] a sidewall on the substrate and covering sidewalls of the gate stack.

[0015] Optionally, the dielectric constant of the dielectric layer is less than the dielectric constant of the sidewall.

[0016] Optionally, the gate structure is a straight strip structure.

[0017] Optionally, the first direction is perpendicular to the second direction.

[0018] Based on the same inventive concept, the present application also provides a method for manufacturing a flash memory device, comprising:

[0019] providing a substrate, the substrate having active regions formed therein, the active regions extending along a first direction and being distributed along a second direction, and each of the active regions including source regions and drain regions arranged alternately along the first direction;

[0020] forming gate structures on the substrate, the gate structures extending along the second direction and being distributed along the first direction, and each of the gate structures being located between the source regions and the drain regions;

[0021] forming a dielectric layer covering the gate structures and the substrate;

[0022] forming source region plugs in the dielectric layer, the source region plugs extending along the second direction and being distributed along the first direction, and each of the source region plugs being located on and electrically connected to corresponding source regions;

[0023] forming drain region plugs in the dielectric layer, each of the drain region plugs being located on and electrically connected to corresponding drain regions.

[0024] Optionally, adjacent active regions are isolated by shallow trench isolation structures, and after the gate structures are formed, the dielectric layer is formed, and the method further comprises:

[0025] removing the shallow trench isolation structures between adjacent source regions to form recesses;

[0026] filling the recesses with conductive material to form a conductive layer.

[0027] Optionally, the step of forming the source region plugs comprises:

[0028] etching the dielectric layer to form trenches extending along the second direction and being distributed along the first direction, each of the trenches being located on corresponding source regions and exposing the source regions and the conductive layer;

[0029] filling a first metal material in the trench, the first metal material filling the trench to form the source region plug.

[0030] Optionally, the step of forming the drain region plug comprises:

[0031] etching the dielectric layer to form a plurality of openings, each of the openings being located on one of the drain regions and exposing the corresponding drain region;

[0032] filling a second metal material layer in the openings, the second metal material layer filling the openings to form the drain region plug.

[0033] In the flash memory device provided by the present application, the source region plug in strip shape is used to electrically connect the corresponding plurality of source regions, forming the common source structure of the flash memory device. The source region plug in strip shape can effectively reduce the difficulty in preparation of the source region plug, avoid the short circuit or leakage between the source region plug and the gate structure due to the reduction of the device size and the process window during the preparation of the source region plug, and further improve the reliability of the flash memory device.

[0034] When the source region plug is in straight line type strip shape, the corresponding plurality of gate structures can also be adjusted to be in straight line type strip shape, facilitating the control of the distance between the gate structure and the source region plug, avoiding the short circuit and leakage due to the too small distance between the gate structure and the source region plug. At the same time, the straight line type strip shape can improve the integration density of the semiconductor device, being conducive to the miniaturization of the semiconductor device. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1 is a structural schematic diagram of a flash memory device;

[0036] Figure 2 is Figure 1 is a sectional structural schematic diagram of the flash memory device along the line B-B';

[0037] Figure 3 is a flow chart of the preparation method of the flash memory device provided by the embodiment of the present application;

[0038] Figures 4 to 14 is a structural schematic diagram corresponding to the corresponding steps of the preparation method of the flash memory device provided by the embodiment of the present application, wherein, Figure 13 is a structural schematic diagram of a flash memory device provided by the embodiment of the present application, Figure 14 is Figure 13 is a sectional structural schematic diagram of the flash memory device along the line A-A';

[0039] wherein, the reference signs are:

[0040] y-first direction; x-second direction;

[0041] 30, 100 - substrate; 31, 101 - shallow trench isolation structure; 32, 102 - active region; 33, 103 - gate structure; 34, 104 - drain region; 35, 105 - source region; 106 - metal silicide layer; 36, 107 - dielectric layer; 108 - mask layer; 38, 109 - source region plug; 37, 110 - drain region plug; 39, 111 - conductive layer;

[0042] 11 - tunnel oxide layer; 12 - floating gate layer; 13 - gate dielectric layer; 14 - control gate layer; 15 - sidewall. DETAILED DESCRIPTION

[0043] Figure 1 Fig. 1 is a schematic diagram of a structure of a flash memory device, Figure 2 Fig. 2 is a schematic diagram of a structure of a flash memory device, Figure 1 Fig. 3 is a schematic diagram of a cross-sectional structure of the flash memory device along line B-B' shown in Fig. 2, and Fig. 4 is a schematic diagram of a cross-sectional structure of the flash memory device along line C-C' shown in Fig. 2. Figure 2 The flash memory device includes a substrate 30, a plurality of gate structures 33, and a dielectric layer 36.

[0044] Specifically, the substrate 30 has active regions 32 extending along a first direction y and distributed along a second direction x, and the active regions 32 are separated by shallow trench isolation structures 31. Each of the active regions 32 includes source regions 35 and drain regions 34 arranged alternately along the first direction y. The gate structures 33 extend along the second direction x and are distributed on the substrate 30 along the first direction y, and each of the gate structures 33 is located between the source regions 35 and the drain regions 34. The dielectric layer 36 covers the gate structures 33 and the substrate 30.

[0045] The flash memory device further includes a conductive layer 39, a plurality of source region plugs 38, and a plurality of drain region plugs 37.

[0046] The conductive layer 39 is located in the shallow trench isolation structure 31 and between every two adjacent active regions 32, and is used to electrically connect the adjacent source regions 35. The source region plugs 38 and the drain region plugs 37 are located in the dielectric layer 36. The source region plugs 38 are located on the most edge source region 35 in the most edge active region 32 and are electrically connected to the corresponding source regions 35 through the conductive layer 39 to form a common source structure of the flash memory device. The drain region plugs 37 are located on each of the drain regions 34 in the other active regions 32 and are electrically connected to the corresponding drain regions 34.

[0047] The adjacent gate structure 33 and the gate structure 33 and the source area plug 38 and the drain area plug 37 need to reserve a certain distance to avoid short circuit or leakage between the gate structure 33 and the source area plug 38 and the drain area plug 37; in order to reduce the size of the flash memory device, the part of the gate structure 33 close to the source area plug 38 is in arc shape, but the arc-shaped gate structure 33 will increase the difficulty of preparation of the flash memory device, increase the risk of short circuit between the gate structure 33 and the source area plug 38, and is not conducive to further reducing the size of the flash memory device. In addition, the performance stability of the arc-shaped gate structure 33 is poor, and it is generally not used as an effective structure, which reduces the integration density of the effective structure of the flash memory device.

[0048] The specific embodiments of the present application will be described in more detail below with reference to the accompanying drawings. The advantages and features of the present application will be more apparent from the following description. It should be noted that the drawings are very simplified and use non-precise proportions, only to facilitate, clarify the purpose of assisting the description of the embodiments of the present application.

[0049] In the following, the terms "first", "second", etc. are used to distinguish between similar elements, and are not necessarily used to describe a particular order or time sequence. It should be understood that these terms used in this way can be replaced under appropriate circumstances. Similarly, if the method described herein includes a series of steps, and the steps presented herein are not necessarily the only order in which the steps can be performed, and some of the steps described can be omitted and / or other steps not described in the text can be added to the method.

[0050] Figure 13 The structure schematic diagram of the flash memory device provided by the embodiments of the present application is shown in the figure, Figure 14 For Figure 13 The cross-sectional structure schematic diagram of the flash memory device along the A-A line is shown in the figure, Figures 13 to 14 As shown in the figure, the flash memory device comprises a substrate 100, a plurality of gate structures 103, a dielectric layer 107 and a plurality of source area plugs 109 and drain area plugs 110 located in the dielectric layer 107.

[0051] Specifically, the substrate 100 has an active area 102 extending along a first direction y and distributed along a second direction x, and the adjacent active areas 102 are isolated by a shallow trench isolation structure 101. Each of the active areas 102 comprises a source area 105 and a drain area 104 arranged alternately along the first direction y; the gate structure 103 is located on the substrate 100, and the gate structure 103 extends along the second direction x and is distributed along the first direction y, and each of the gate structures 103 is located between the source area 105 and the drain area 104.

[0052] The gate structure 103 comprises a gate stack and a side wall 15, the gate stack comprises a tunneling oxide layer 11, a floating gate layer 12, a gate dielectric layer 13 and a control gate layer 14 which are sequentially stacked on the substrate 100 from bottom to top, and the side wall 15 is located on the substrate 100 and covers the side wall of the gate stack.

[0053] Further, the source region 105, the drain region 104 and the top surface of the gate structure are all formed with a metal silicide layer 106, the dielectric layer 107 covers the gate structure 103, the metal silicide layer 106 and the substrate 100; the source region plug 109 and the drain region plug 110 are both located in the dielectric layer 107, the source region plug 109 extends along the second direction x and is distributed along the first direction y, each source region plug 109 is located on and electrically connected with a plurality of source regions 105, and a plurality of source regions 105 are simultaneously powered by one source region plug 109 to form a common source (CS) structure of the flash memory device; each drain region plug 110 is located on and electrically connected with a drain region 104.

[0054] In the embodiment, the first direction y is perpendicular to the second direction x, and the gate structure 103 is a linear strip structure, and correspondingly, the source region plug 109 located between the gate structures 103 is also a linear strip structure, the linear gate structure 103 and the source region plug 109 can reduce the difficulty of preparing the flash memory device, thereby avoiding the short circuit between the gate structure 103 and the source region plug 109 caused by process error in the preparation process, and improving the reliability of the flash memory device.

[0055] Meanwhile, compared with Figure 1 and Figure 13 It can be seen that when the source region plug 109 is a linear strip structure, a plurality of gate structures can also be adjusted to be linear strip structures, and all the gate structures can be used as effective structures, without discarding the arc-shaped gate structure 33, thereby effectively improving the integration density of the effective structures of the flash memory device.

[0056] In addition, the flash memory device also comprises a metal silicide layer 106 and a conductive layer 111. The metal silicide layer 106 is located on the top surface of the source region 105, the drain region 104 and the gate structure 103; the conductive layer 111 is located in the shallow trench isolation structure 101 and between adjacent source regions 105, and the conductive layer 111 is electrically connected with adjacent source regions 105 and corresponding source region plugs 109.

[0057] In this embodiment, the dielectric constant of the dielectric layer 107 is less than that of the sidewall 15, thereby enhancing the isolation effect between the source plug 109, the drain plug 110, and the gate structure 103.

[0058] Based on this, this embodiment also provides a method for fabricating a flash memory device. Figure 3 This is a flowchart of the method for fabricating the aforementioned flash memory device. Figure 3 As shown, the method for fabricating the flash memory device includes:

[0059] Step S1: Provide a substrate in which active regions extending along a first direction and distributed along a second direction are formed, and each active region includes source regions and drain regions alternately arranged along the first direction.

[0060] Step S2: A plurality of gate structures are formed on the substrate, extending along the second direction and distributed along the first direction, each gate structure being located between the source region and the drain region;

[0061] Step S3: Form a dielectric layer to cover the gate structure and the substrate;

[0062] Step S4: A plurality of source region plugs are formed in the dielectric layer. The source region plugs extend along the second direction and are distributed along the first direction. Each source region plug is located on a plurality of source regions and is electrically connected to the corresponding plurality of source regions.

[0063] Step S5: A plurality of drain plugs are formed in the dielectric layer, each drain plug being located on a drain area and electrically connected to the corresponding drain area.

[0064] Figures 4 to 14 This is a schematic diagram of the corresponding steps in the fabrication method of the flash memory device provided in this embodiment. Next, we will combine... Figures 4 to 14 The fabrication method of the aforementioned flash memory device is described in detail.

[0065] like Figure 4 As shown, a substrate 100 is provided, in which active regions 102 extending along a first direction y and distributed along a second direction x are formed, and adjacent active regions 102 are isolated by shallow trench isolation structures 101; then a plurality of gate structures 103 are formed on the substrate 100, the gate structures 103 extending along the second direction x and distributed along the first direction y on the substrate 100.

[0066] Wherein, the first direction y is perpendicular to the second direction x.

[0067] Figure 5 for Figure 4A cross-sectional view of the flash memory device along the line A-A is shown in FIG. 1. Figure 5 As shown, the step of forming the gate structure 103 specifically includes: forming a tunneling oxide layer 11, a floating gate layer 12, a gate dielectric layer 13 and a control gate layer 14 in sequence on the substrate 100, and etching the control gate layer 14, the gate dielectric layer 13, the floating gate layer 12 and the tunneling oxide layer 11 in sequence, and the remaining part constitutes a plurality of gate stacks; finally, forming a side wall 15 on the substrate 100, the side wall 15 covers the sidewall of the gate stacks, and the side wall 15 and the gate stacks constitute the gate structure 103. Generally, the material of the side wall 15 is silicon oxide.

[0068] Continuing to refer to Figure 4 , the gate structure 103 is a linear strip structure, the shape of the gate structure 103 is simple, and the preparation difficulty is low, which can effectively improve the reliability of the flash memory device, and in addition, the distance between the linear gate structures 103 is easy to control.

[0069] As shown in Figures 6 to 7 , the ion implantation process is performed on the active regions 102 on both sides of the gate structure 103 to form source regions 105 and drain regions 104 arranged alternately along the first direction y in each active region 102, and each gate structure 103 is located between the source region 105 and the drain region 104.

[0070] Further, part of the shallow trench isolation structure 101 between adjacent source regions 105 is removed to form a plurality of grooves; and a conductive material is filled in the grooves to form a conductive layer 111, and the conductive layer 111 electrically connects a plurality of source regions 105.

[0071] As shown in Figure 8 , a metal silicide layer 106 is formed on the top surface of the gate structure 103, the source region 105, the drain region 104 and the conductive layer 111.

[0072] As shown in Figure 9 , a dielectric layer 107 is formed, which covers the metal silicide layer 106 and the gate structure 103, a planarization process is performed on the dielectric layer 107 to make the upper surface of the dielectric layer 107 flat, and then a mask layer 108 is formed on the dielectric layer 107.

[0073] Among them, the dielectric constant of the dielectric layer 107 is less than the dielectric constant of the side wall, which enhances the isolation effect of the dielectric layer 107.

[0074] As shown in Figure 10 , the mask layer 108 is patterned.

[0075] As shown in Figure 11 The medium layer 107 is etched to form grooves extending along the second direction x and distributed along the first direction y, each of the grooves is located on a plurality of the source regions 105 and exposes the corresponding source regions 105 and the conductive layer 111. In this embodiment, only part of the width of the medium layer 107 is removed, and the remaining medium layer 107 covers the gate structure 103 to provide better isolation effect.

[0076] As shown in Figure 12 The first metal material is filled in the grooves to form the source region plug 109, each of the source region plugs 109 is located on a plurality of the source regions 105 and electrically connected with the corresponding plurality of the source regions 105 to form the common source structure of the flash memory device.

[0077] In this embodiment, the source region plug 109 is formed in a self-alignment manner, which reduces the difficulty of forming the source region plug 109 and is also beneficial to improve the density of the flash memory device.

[0078] As shown in Figures 13 to 14 The medium layer 107 is etched to form a plurality of openings, each of the openings is located on one of the drain regions 104 and exposes the corresponding drain region 104; then, the second metal material layer is filled in the openings to form the drain region plug 110, each of the drain region plugs 110 is located on one of the drain regions 104 and electrically connected with the corresponding drain region 104.

[0079] In summary, the present application provides a flash memory device and a preparation method thereof, which comprises: a substrate 100, the substrate 100 has active regions 102 extending along a first direction y and distributed along a second direction x, each of the active regions 102 comprises source regions 105 and drain regions 104 arranged alternately along the first direction y; a plurality of gate structures 103 located on the substrate 100, extending along the second direction x and distributed along the first direction y, each of the gate structures 103 is located between the source regions 105 and the drain regions 104; a medium layer 107 covering the gate structures 103 and the substrate 100; a plurality of source region plugs 109 located in the medium layer 107, extending along the second direction x and distributed along the first direction y, each of the source region plugs 109 is located on a plurality of the source regions 105 and electrically connected with the corresponding plurality of the source regions 105; a plurality of drain region plugs 110 located in the medium layer 107, each of the drain region plugs 110 is located on one of the drain regions 104 and electrically connected with the corresponding drain region 104.

[0080] In the flash memory device provided by the application, the source region plug 109 in strip shape is used to electrically connect the corresponding source regions 105, and the common source structure of the flash memory device is formed. The source region plug 109 in strip shape can effectively reduce the difficulty in preparation of the source region plug 109, avoid the short circuit or leakage problem between the source region plug 109 and the gate structure caused by the device size and the process window reduction in the preparation process of the source region plug 109, and further improve the reliability of the flash memory device.

[0081] When the source region plug 109 is in the linear strip structure, the corresponding gate structures can also be adjusted to the linear strip structure, so as to facilitate the control of the distance between the gate structure and the source region plug 109, avoid the short circuit and leakage caused by the too small distance between the gate structure and the source region plug 109, and at the same time, the linear strip structure can improve the integration density of the semiconductor device, and is beneficial to the miniaturization of the semiconductor device.

[0082] The above is only the preferred embodiment of the application, and does not limit the application. Any person skilled in the art can make any form of equivalent replacement, modification or change to the technical scheme and technical content disclosed by the application without departing from the scope of the technical scheme of the application, and still belongs to the protection scope of the application.

Claims

1. A flash memory device, characterized by, The application relates to a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate, a plurality of active regions formed in the substrate and extending along a first direction and distributed along a second direction, and a plurality of shallow trench isolation structures separating adjacent active regions, each of the active regions comprising source regions and drain regions arranged alternately along the first direction; A plurality of gate structures are formed on the substrate, extending along the second direction and distributed along the first direction, each of the gate structures being located between the source regions and the drain regions; A dielectric layer covers the gate structures and the substrate; A plurality of source region plugs are formed in the dielectric layer, extending along the second direction and distributed along the first direction, each of the source region plugs being located on and electrically connected to a plurality of the source regions; A plurality of drain region plugs are formed in the dielectric layer, each of the drain region plugs being located on and electrically connected to a drain region, and the conductive layer being electrically connected to adjacent source regions and corresponding source region plugs. The gate structure comprises:

2. The flash memory device of claim 1, wherein, A gate stack comprising a tunneling oxide layer, a floating gate layer, a gate dielectric layer and a control gate layer stacked on the substrate in sequence from bottom to top; Side walls formed on the substrate and covering the sidewalls of the gate stack. The dielectric constant of the dielectric layer is less than the dielectric constant of the side walls.

3. The flash memory device of claim 2, wherein, The gate structure is a linear strip structure.

4. The flash memory device of claim 1, wherein, The first direction is perpendicular to the second direction.

5. The flash memory device of claim 1, wherein, The application relates to a semiconductor device and a manufacturing method thereof.

6. A method of fabricating a flash memory device, comprising: The semiconductor device comprises a substrate, a plurality of active regions formed in the substrate and extending along a first direction and distributed along a second direction, and a plurality of shallow trench isolation structures separating adjacent active regions, each of the active regions comprising source regions and drain regions arranged alternately along the first direction; A plurality of gate structures are formed on the substrate, extending along the second direction and distributed along the first direction, each of the gate structures being located between the source regions and the drain regions; The shallow trench isolation structures between adjacent source regions are removed to form a plurality of recesses; A conductive layer is formed by filling the recesses with a conductive material; A dielectric layer covers the gate structures and the substrate; A plurality of source region plugs are formed in the dielectric layer, extending along the second direction and distributed along the first direction, each of the source region plugs being located on and electrically connected to a plurality of the source regions; A plurality of drain region plugs are formed in the dielectric layer, each of the drain region plugs being located on and electrically connected to a drain region, and the conductive layer being electrically connected to adjacent source regions and corresponding source region plugs. The step of forming the source region plugs comprises:

7. The method for fabricating a flash memory device as described in claim 6, characterized in that, Etching the dielectric layer to form a plurality of trenches extending along the second direction and distributed along the first direction, each of the trenches being located on a plurality of the source regions and exposing corresponding source regions and the conductive layer; Filling the trenches with a first metal material to form the source region plugs. The step of forming the drain region plugs comprises:

8. The method for fabricating a flash memory device as described in claim 6, characterized in that, Etching the dielectric layer to form a plurality of openings, each of the openings being located on a drain region and exposing the drain region; ​ filling a second metal material layer in the opening, the second metal material layer filling the opening to form the drain plug.

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