Semiconductor memory device

Abstract

A semiconductor storage device capable of improving heat dissipation efficiency is provided. The semiconductor storage device includes a body, a memory, a controller, and a plurality of terminals. The plurality of terminals include a plurality of signal terminals for transmitting signals, and are exposed on a first surface of the body. The plurality of terminals form at least a first column and a second column. The first column includes a plurality of terminals arranged in a first direction at positions closer to a first end edge than to a second end edge of the body. The second column includes a plurality of terminals arranged in the first direction at positions closer to the second end edge than to the first end edge of the body. An area between the first column and the second column on the first surface of the body includes a contact area that contacts a heat conduction member electrically connected to the semiconductor storage device and disposed on a substrate of a host machine.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor memory device. Background Technology

[0002] In recent years, with technological improvements in non-volatile memory such as NAND (Not-AND) flash memory, the storage capacity of non-volatile memory has increased. Along with this, the development of semiconductor memory devices, such as removable memory devices, has continued to advance.

[0003] However, in semiconductor memory devices such as removable memory devices, there is a need to implement structures to improve heat dissipation efficiency.

[0004] [Background Technical Documents]

[0005] [Patent Literature]

[0006] Patent Document 1: Japanese Patent Application Publication No. 2016-167167 Summary of the Invention

[0007] [The problem the invention aims to solve]

[0008] The problem that this invention aims to solve is to provide a semiconductor memory device that can improve heat dissipation efficiency.

[0009] [Technical Approaches to Problem Solving]

[0010] According to an embodiment, a semiconductor memory device includes a body, a memory, a controller, and a plurality of terminals. The body has: a first surface; a second surface located opposite to the first surface; a first edge extending in a first direction; a second edge located opposite to the first edge and extending in the first direction; a first side edge extending in a second direction intersecting the first direction; and a second side edge located opposite to the first side edge and extending in the second direction. The memory is disposed inside the body. The controller is disposed inside the body and controls the memory. The plurality of terminals includes a plurality of signal terminals for transmitting signals and is exposed on the first surface. The plurality of terminals form at least a first column and a second column. The first column includes a plurality of terminals spaced apart from each other in the first direction at positions closer to the first edge than the second edge. The second column includes a plurality of terminals spaced apart from each other in the first direction at positions closer to the second edge than the first edge. The region between the first column and the second column of the first surface includes a contact region that contacts a heat-conducting component electrically connected to the semiconductor memory device and disposed on the substrate of the host machine. Attached Figure Description

[0011] Figure 1 (A) to (C) are illustrative diagrams showing the external shape of the memory device according to the first embodiment.

[0012] Figure 2 This is a diagram illustrating a configuration example of a memory device with the same implementation.

[0013] Figure 3 This is a top view showing the external shape and a configuration example of multiple terminals of a memory device with the same implementation.

[0014] Figure 4 (A) to (B) are top views showing the external shape of the memory device of the same embodiment, the external shape of the connector for mounting the memory device, and the configuration of the area where the TIM is attached.

[0015] Figure 5 This is a side view showing the state in which a memory device of the same implementation is mounted on a connector.

[0016] Figure 6 (A) to (B) are diagrams used to illustrate the case where the terminals of memory devices using the same implementation are used as SCS terminals.

[0017] Figure 7 This diagram shows the host control unit and switches mounted on the substrate of a host machine using a memory device with the same implementation.

[0018] Figure 8 (A) to (B) are top views showing the external shape of memory devices with the same implementation, namely, a 2-power memory device and a 1-power memory device.

[0019] Figure 9 (A) to (B) are diagrams used to illustrate the case where the terminals of a memory device using the same implementation are used as PCD terminals.

[0020] Figure 10 (A) to (B) are diagrams showing the internal circuitry of memory devices with the same implementation, namely, a 2-power-source memory device and a 1-power-source memory device.

[0021] Figure 11 (A) to (B) are diagrams used to illustrate cases where a terminal of a memory device using the same implementation is used as an SCS terminal or as a PCD terminal.

[0022] Figure 12 This is a timing diagram illustrating an example of operation where a terminal of a memory device using the same implementation is used as an SCS terminal or a PCD terminal.

[0023] Figure 13(A) to (B) are top views showing the external shape of the memory device, the external shape of the connector for mounting the memory device, and the configuration example of the area where the TIM is attached, according to the first variation.

[0024] Figure 14 (A) to (B) are top views showing the external shape of the memory device, the external shape of the connector for mounting the memory device, and the configuration example of the area where the TIM is attached, in the second variation.

[0025] Figure 15 (A) to (B) are top views showing the external shape of the memory device, the external shape of the connector for mounting the memory device, and the configuration example of the area where the TIM is attached, in the third variation.

[0026] Figure 16 (A) to (B) are top views showing the external shape of the memory device, the external shape of the connector for mounting the memory device, and the configuration example of the area where the TIM is attached, in the fourth variation.

[0027] Figure 17 This is a diagram illustrating an example of the pin assignment of the memory device according to the second embodiment.

[0028] Figure 18 It means relative to Figure 17 A diagram showing the pin assignment of a comparative example of the configuration.

[0029] Figure 19 This is a diagram illustrating other examples of pin assignments for memory devices with the same implementation.

[0030] Figure 20 This is a diagram illustrating an example of the pin assignment of a memory device with the same implementation.

[0031] Figure 21 It means relative to Figure 20 A diagram showing the pin assignment of a comparative example of the configuration.

[0032] Figure 22 This is a perspective view showing the outer and inner layers of a memory device with the same implementation.

[0033] Figure 23 (A) to (C) are diagrams used to illustrate the terminals of the memory device according to the third embodiment, sharing the signal terminal, SCS terminal and PCD terminal used to transmit sideband signals.

[0034] Figure 24 This is a timing diagram illustrating an example of operation where the terminals of memory devices with the same implementation share signal terminals, SCS terminals, and PCD terminals used to transmit sideband signals. Detailed Implementation

[0035] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0036] A semiconductor memory device includes non-volatile memory and a controller for controlling the non-volatile memory. A semiconductor memory device is a storage device configured to write data to and read data from the non-volatile memory. A semiconductor memory device can also be implemented, for example, as a solid-state drive (SSD). In this case, the SSD is used as a storage device in various information processing devices that function as host machines, such as personal computers, mobile devices, video recorders, and automotive devices.

[0037] (First Embodiment)

[0038] The semiconductor memory device of the first embodiment has a card shape and can function as a removable SSD that can be installed in a host machine. The connector for mounting the semiconductor memory device of this embodiment can be a push-type connector, a push-pull connector, or a hinge-type connector. In this embodiment, it is envisioned that the connector for mounting the semiconductor memory device is a hinge-type connector.

[0039] Due to the removable nature of semiconductor memory devices, capacity can be upgraded and maintenance is easy. Hereinafter, semiconductor memory devices are referred to as memory devices (or removable memory devices).

[0040] Figure 1 This is an example diagram showing the external shape of the memory device 10 according to the first embodiment. Figure 1 (A) is a top view showing one surface of the memory device 10. Figure 1 (B) is a side view showing the side of the memory device 10. Figure 1 (C) is a top view showing one surface of the memory device 10, that is, a view showing the surface located at... Figure 1 (A) is a top view of the other surface on the opposite side of one surface.

[0041] like Figure 1 (A)~ Figure 1 As shown in (C), the X-axis, Y-axis, and Z-axis are defined in this specification. The X-axis, Y-axis, and Z-axis are orthogonal to each other. The X-axis is along the width of the memory device 10. The Y-axis is along the length (height) of the memory device 10. The Z-axis is along the thickness of the memory device 10. In this specification, the view of the memory device 10 and the connector for mounting the memory device 10 from the negative direction of the Z-axis is referred to as the top view.

[0042] The memory device 10 is a semiconductor memory device configured to operate on a power supply voltage supplied from an external source.

[0043] like Figure 1 As shown, the memory device 10 includes a body (frame) 11 having a thin plate-like semiconductor package shape. The memory device 10 and the body 11 are formed into a generally rectangular plate shape, for example, extending in the Y-axis direction. The Y-axis direction is the direction of the long side of the memory device 10 and the body 11.

[0044] like Figure 1 As shown, the body 11 is plate-shaped and has a first surface 21, a second surface 22, and an outer edge 23. The first surface 21 and the second surface 22 are formed into a roughly quadrilateral (rectangular) shape extending in the Y-axis direction. That is, the Y-axis direction is also the direction of the long side of the first surface 21 and the second surface 22.

[0045] Surface 21 is a generally flat surface facing the positive direction of the Z-axis. Surface 22 is a generally flat surface located on the opposite side of surface 21 and facing the negative direction of the Z-axis.

[0046] The outer edge 23 is disposed between the first surface 21 and the second surface 22, and connects the edge of the first surface 21 and the edge of the second surface 22. For example... Figure 1 As shown, the outer edge 23 has a first edge 31, a second edge 32, a third edge 33, a fourth edge 34, a first corner 35, a second corner 36, a third corner 37, and a fourth corner 38.

[0047] The first edge 31 extends in the X-axis direction and faces the positive Y-axis direction. The X-axis direction is the direction of the short sides of the body 11, the first surface 21 and the second surface 22, including the positive and negative X-axis directions.

[0048] The second edge 32 extends in the Y-axis direction, towards the negative X-axis direction. The third edge 33 is located on the opposite side of the second edge 32, extending in the Y-axis direction, towards the positive X-axis direction. The fourth edge 34 is located on the opposite side of the first edge 31, extending in the X-axis direction, towards the negative Y-axis direction.

[0049] The lengths of the second edge 32 and the third edge 33 are each longer than the lengths of the first edge 31 and the fourth edge 34. The first edge 31 and the fourth edge 34 form the short side of the generally rectangular memory device 10, and the second edge 32 and the third edge 33 form the long side (side) of the generally rectangular memory device 10.

[0050] The first corner 35 is the corner between the first edge 31 and the second edge 32, connecting the negative X-axis end of the first edge 31 to the positive Y-axis end of the second edge 32.

[0051] The first corner portion 35 extends linearly between the negative X-axis end of the first edge 31 and the positive Y-axis end of the second edge 32. The angle between the first edge 31 and the second edge 32 is set as a chamfer called C1.1 (also known as a C chamfer), thereby defining the first corner portion 35. In other words, the first corner portion 35 is a chamfered portion C formed between the first edge 31 and the second edge 32.

[0052] The second corner portion 36 is the corner between the first edge 31 and the third edge 33, connecting the positive X-axis end of the first edge 31 to the positive Y-axis end of the third edge 33. The second corner portion 36 extends in an arc shape between the positive X-axis end of the first edge 31 and the positive Y-axis end of the third edge 33. The angle between the first edge 31 and the third edge 33 is set as a rounded chamfer of R0.2 (also called an R-chamfer), thus defining the second corner portion 36. Therefore, the shapes of the first corner portion 35 and the second corner portion 36 are different.

[0053] The third corner portion 37 connects the negative Y-axis end of the second edge 32 to the negative X-axis end of the fourth edge 34. The fourth corner portion 38 connects the negative Y-axis end of the third edge 33 to the positive X-axis end of the fourth edge 34. The third corner portion 37 and the fourth corner portion 38 extend in an arc shape, similar to the second corner portion 36.

[0054] The lengths of the body 11, the first surface 21, and the second surface 22 in the Y-axis direction are set to approximately 18 ± 0.10 mm, and the lengths in the X-axis direction are set to approximately 14 ± 0.10 mm. That is, the distance between the first edge 31 and the fourth edge 34 in the Y-axis direction is set to approximately 18 ± 0.1 mm, and the distance between the second edge 32 and the third edge 33 in the X-axis direction is set to approximately 14 ± 0.10 mm. Furthermore, the lengths of the body 11, the first surface 21, and the second surface 22 in the X-axis and Y-axis directions are not limited to the examples described above.

[0055] The thickness of the body 11 and the outer edge 23 in the Z-axis direction is set to approximately 1.4 ± 0.10 mm. That is, the distance between the first surface 21 and the second surface 22 in the Z-axis direction is set to approximately 1.4 ± 0.10 mm. Furthermore, since there may be cases where an inclined portion 39 is formed or a chamfer is applied, the length of the outer edge 23 in the Z-axis direction is not limited to the example described. For a secure fit with the connector, the Z-axis direction needs to be specified with planar tolerances, and the thickness of the entire surface must be within the tolerance.

[0056] like Figure 1 As shown in (B), the body 11 also has an inclined portion 39. The inclined portion 39 is the corner portion between the first surface 21 and the first edge 31, and extends in a straight line between the end of the first surface 21 in the positive direction of the Y axis and the end of the first edge 31 in the positive direction of the Z axis.

[0057] like Figure 1As shown in (A), multiple terminals can also be configured in three columns, R1, R2, and R3, on the first surface 21 of the memory device 10. Column R1 contains signal terminals for a two-channel high-speed serial interface, such as PCIe (registered trademark). Each channel's signal terminals include a receive differential signal pair 2 terminal and a transmit differential signal pair 2 terminal. Furthermore, the differential signal pair 2 terminals are surrounded by a ground terminal. Although not shown, a PCIe channel can also be added between columns R1 and R2.

[0058] Column R2 can be configured with signal terminals for various optional signals for different products. Examples of optional signal terminals include, for example, signal terminals for PCIe-compliant sideband signals (SMBus signal, WAKE# signal, and PRSNT# signal) or ground terminals. Column R3 is configured with control signals and power terminals shared by the products. Examples of PCIe-compliant sideband signals include, for example, CLKREF signal pairs, CLKREQ# signal, and PERST# signal. Column R3 is also configured with multiple power terminals and ground terminals supplying power voltage from the host machine.

[0059] Additionally, there are cases where column R1 is called column 1. Furthermore, there are cases where column R3 is called column 2. And there are also cases where column R2 is called column 3.

[0060] Figure 2 This is an example of the configuration of memory device 10.

[0061] like Figure 2 As shown, a printed circuit board substrate 12, a NAND flash memory 13, and a controller 14 are disposed inside the body 11 of the memory device 10. The printed circuit board substrate 12, the NAND flash memory 13, and the controller 14 can be housed in the box-shaped body 11 or embedded in the body 11. The NAND flash memory 13 and the controller 14 are mounted on the surface of the printed circuit board substrate 12.

[0062] Alternatively, the printed circuit substrate 12 can be made to form part of the body 11 by exposing its back side. In this case, the back side of the printed circuit substrate 12 can function as the first surface 21.

[0063] The NAND flash memory 13 may also comprise multiple stacked NAND flash memory chips. Typically, these multiple NAND flash memory chips operate in an interleaved manner. The controller 14 is an LSI. The controller 14 controls the NAND flash memory 13 and the entire memory device 10 containing the NAND flash memory 13. For example, the controller 14 can perform read / write control of the NAND flash memory 13 and communication control with external devices. Furthermore, the memory device 10 has a PCIe interface as a system interface, enabling communication control within the memory device 10 according to PCIe protocol specifications.

[0064] The memory device 10 is implemented in a card-shaped package (memory package), and the NAND flash memory 13 and the controller 14 are covered and sealed by a molding resin 40 formed in such a way as to form the body (body 11) of the memory device 10.

[0065] Figure 3 This is a top view showing the external shape of the memory device 10 and an example of the configuration of the multiple terminals P.

[0066] like Figure 3 As shown, memory device 10 has multiple terminals P. Terminals P may also be referred to as pins or pads. Figure 3 The example shown illustrates a memory device 10 with 32 terminals P, but the number of terminals P is merely an example and is not limited to this example. That is, the number of terminals P may be less than 32 or more than 32. Multiple terminals P are disposed, for example, on the back side of a printed circuit substrate 12. Multiple terminals P are formed on the printed circuit substrate 12 and exposed on the first surface 21. In this embodiment, no terminals P are disposed on the second surface 22, allowing for use on, for example, the printed surface.

[0067] Multiple terminals P are arranged in three columns, forming columns R1, R2, and R3. The terminal group belonging to column R1 is used as a signal terminal for transmitting differential signal pairs according to the PCIe specification's two-channel capability. The terminal group belonging to column R2 can be configured with signal terminals for various optional signals for each product. Since these signal terminals are not essential for the memory device 10 (in other words, they are optional for the memory device 10), the number of terminals belonging to column R2 can be less than the number of terminals belonging to the other columns. The terminal group belonging to column R3 is configured with control signals and power terminals shared by all products. These terminals are primarily used as differential clock signal terminals, shared PCIe sideband signal terminals, power terminals, and other terminals.

[0068] like Figure 3As shown, column R1 includes 13 terminals P101 to P113, which are spaced apart from each other in the X-axis direction at a position closer to the first edge 31 than the fourth edge 34. Terminals P101 to P113 are arranged side by side in the X-axis direction along the first edge 31 near the first edge 31.

[0069] Column R2 includes: six terminals P114 to P119, spaced apart along the X-axis, located closer to the fourth edge 34 than the first edge 31. Terminals P114 to P116 are arranged side-by-side along the fourth edge 34 in the X-axis direction, located closer to the second edge 32 than the third edge 33. Terminals P117 to P119 are arranged side-by-side along the fourth edge 34 in the X-axis direction, located closer to the third edge 33 than the second edge 32. In other words, terminals P114 to P116 are positioned between the center line (shown as a dashed line) of the memory device 10 and body 11 in the X-axis direction and the second edge 32, while terminals P117 to P119 are positioned between the center line of the memory device 10 and body 11 in the X-axis direction and the third edge 33. The spacing between terminals P116 and P117, which belong to column R2, is wider than the spacing between other adjacent terminals in column R2 in the X-axis direction (specifically, the spacing between terminals P114 and P115, P115 and P116, P117 and P118, and P118 and P119).

[0070] Column R3 contains 13 terminals P120 to P132, which are spaced apart in the X-axis direction and located closer to the fourth edge 34 than the first edge 31. Terminals P120 to P132 belonging to column R3 are arranged side by side closer to the fourth edge 34 than terminals P114 to P119 belonging to column R2.

[0071] When the length between the second edge 32 and the third edge 33 is specific, the distance between adjacent terminals P in the X-axis direction is determined, for example, by the number of terminals P. Furthermore, the maximum number of terminals P arranged side-by-side in the X-axis direction is determined based on the width of adjacent terminals P in the X-axis direction and the minimum distance between adjacent terminals P. Taking into account the deviation of the contact portion with the connector contact, the pad width and the distance between adjacent pads that ensure reliable contact are determined. The distances between multiple terminals P in the X-axis direction can be equal or different. In this embodiment, since the number of terminals P belonging to columns R1 and R3 is the same, and the number of terminals P belonging to column R2 is less than that of other columns, the terminal spacing of column R2 can also be different from the terminal spacing of columns R1 and R3.

[0072] like Figure 3 As shown, the distance D1 between column R1 and column R3 in the Y-axis direction is longer than the distance D2 between column R1 and the first edge 31 in the Y-axis direction, and the distance D3 between column R3 and the fourth edge 34 in the Y-axis direction.

[0073] Figure 3 In the example, the lengths of the terminals P in the Y-axis direction of columns R1, R2, and R3 are set to be the same. That is, the terminals P of columns R1, R2, and R3 are arranged side by side with their ends aligned in both the negative and positive Y-axis directions.

[0074] Figure 4 This is a top view showing the external shape of the memory device 10, the external shape of the connector 100 inside the host machine for mounting the memory device 10, and an example of the configuration of the area where the thermal interface material (TIM) 107 is attached. Figure 4 (A) is a top view showing the external shape of the memory device 10 and the area in contact with the area where the TIM 107 is attached (hereinafter referred to as the contact area) A1. Figure 4 (B) is a top view showing the external shape of connector 100 and the area (hereinafter referred to as attachment area) A2 where TIM 107 is attached. Memory device 10 will... Figure 4 (A) is shown with the terminal face facing down, from... Figure 4 (B) is mounted on top of connector 100. Figure 5 This is a side view showing the state in which the memory device 10 is mounted on the connector 100.

[0075] exist Figure 4 (A) shows the connector 100 for mounting the memory device 10, as shown in Figure 10. Figure 4 As shown in (B), multiple lead frames are arranged in three columns r1, r2, and r3, corresponding to columns R1, R2, and R3 of the memory device 10. The lead frames are also sometimes referred to as spring leads. In column r1, 13 lead frames 101 are arranged corresponding to the 13 terminals P101 to P113 of column R1 of the memory device 10. Similarly, in column r2, 6 lead frames 102 are arranged corresponding to the 6 terminals P114 to P119 of column R2 of the memory device 10, and in column r3, 13 lead frames 103 are arranged corresponding to the 13 terminals P120 to P132 of column R3 of the memory device 10.

[0076] Figure 4 In (B), the Y-axis lengths of the lead frames 101 to 103 forming columns r1, r2, and r3 are the same. However, the Y-axis lengths of the lead frames 101 to 103 are not limited to the example described above. For example, the Y-axis lengths of the lead frames 101 to 103 may also be different from each other.

[0077] like Figure 4 As shown in (B), leadframes 101 to 103 each have leadframe terminals 104 and mounting portions 105. Leadframe terminals 104 are portions that make contact (point contact) with each of the plurality of terminals P of columns R1, R2, and R3 forming the memory device 10. Mounting portions 105 are portions that connect to the printed circuit board substrate when leadframes 101 to 103 are mounted on the printed circuit board substrate within the host machine. In other words, mounting portions 105 are portions that fix leadframes 101 to 103 to the printed circuit board substrate within the host machine.

[0078] If the memory device 10 is mounted on the connector 100, then the lead frame terminals 104 of the lead frames 101 to 103 of the connector 100 contact each of the plurality of terminals P forming columns R1, R2 and R3.

[0079] If the lead frame terminals 104 of lead frames 101 to 103 contact terminal P, then the host control unit disposed on the system substrate of the host machine is electrically connected to the controller 14 of the memory device 10.

[0080] in addition, Figure 4 In (B), the lead frame terminals 104 of the lead frame 101 forming column r1 face the negative direction of the Y-axis. The lead frame terminals 104 of the lead frame 102 forming column r2 face the negative direction of the Y-axis. The lead frame terminals 104 of the lead frame 103 forming column r3 face the positive direction of the Y-axis. Alternatively, the lead frame terminals 104 of columns r1, r2, and r3 may also face the opposite direction.

[0081] like Figure 4 As shown in (B), the connector 100 includes a connector frame 106 that supports the memory device 10 when it is mounted. In other words, the connector 100 includes a connector frame 106 that accommodates the memory device 10 when it is mounted. Figure 4 As shown in (B), the connector frame 106 has a first edge 111, a second edge 112, a third edge 113, a fourth edge 114, a connecting portion 115, and a notch 116.

[0082] The first edge 111 extends in the X-axis direction and faces the negative direction of the Y-axis. When the memory device 10 is mounted, the first edge 111 is connected to the first edge 31 of the memory device 10. When viewed from above, the first edge 111 overlaps with the mounting portion 105 of the lead frame 101 forming column r1 and is connected to the mounting portion 105 (next).

[0083] The second edge 112 extends in the Y-axis direction and faces the negative X-axis direction. When the memory device 10 is mounted, the second edge 112 is connected to the third edge 33 of the memory device 10. The third edge 113 extends in the Y-axis direction and faces the positive X-axis direction. When the memory device 10 is mounted, the third edge 113 is connected to the second edge 32 of the memory device 10.

[0084] The fourth edge 114 extends in the X-axis direction and faces the positive direction of the Y-axis. When the memory device 10 is mounted, the fourth edge 114 is connected to the fourth edge 34 of the memory device 10. When viewed from above, the fourth edge 114 overlaps with the mounting portion 105 of the lead frame 103 forming column r3 and is connected to the mounting portion 105 (next).

[0085] The connecting portion 115 extends in the X-axis direction and is located between the first edge 111 and the fourth edge 114, connecting the second edge 112 and the third edge 113. When viewed from above, the connecting portion 115 overlaps with the mounting portion 105 of the lead frame 102 forming column r2 and is connected to the mounting portion 105 (then).

[0086] The gaps 116 are formed at the second edge 112 and the third edge 113, respectively. For example... Figure 5 As shown, when the memory device 10 is mounted on the connector 100, the claws of the cover 120 used to secure the memory device 10 are fastened to the notch 116.

[0087] exist Figure 4 (B) The area A2, indicated by the diagonal line, is where TIM107 is attached. More specifically, as shown... Figure 4 As shown in (B), in connector 100, TIM 107 is attached to the area between columns r1 and r2, and to the area between the lead frame 102 forming column r2, the lead frame 102 corresponding to terminal P116 of memory device 10, and the lead frame 102 corresponding to terminal P117 of memory device 10. TIM 107 is attached to a printed circuit substrate inside the host machine.

[0088] Figure 4 (A) The contact area A1, and... Figure 4 (B) The attachment area A2, indicated by the diagonal line, where the TIM107 is attached, overlaps when the memory device 10 is mounted on the connector 100 in a top view. In other words, when the memory device 10 is mounted on the connector 100, the memory device 10 is facing and in contact with the TIM107 attached to the attachment area A2 of the connector 100 in the contact area A1.

[0089] By connecting the terminal P of memory device 10 as Figure 4As shown in (A), the connector 100 for mounting the memory device 10, such as Figure 4 (B) shows the mounting area A2 for attaching the TIM107. Generally, in removable memory devices, heat dissipation is achieved by using configured terminals as heat dissipation terminals to ensure a heat dissipation path to the printed circuit board substrate inside the host machine. However, since the terminals configured on the memory device only make point contact with the lead frame terminals of the lead frame, the heat dissipation area is small, resulting in poor heat dissipation efficiency. Furthermore, since the lead frame terminals of the lead frame are not soldered to the printed circuit board substrate inside the host machine, they are affected by the thermal resistance along the length from the lead frame terminals to the mounting portion of the lead frame, leading to poor heat dissipation efficiency.

[0090] In contrast, the memory device 10 of this embodiment achieves this by reducing the number of terminals P forming column R2 to less than the number of terminals P forming columns R1 or R3. Figure 4 As shown in (A), the terminal configuration of contact area A1 allows for the provision of attachment area A2 for attaching TIM107 on connector 100. Thus, as... Figure 5 As shown, when the memory device 10 is mounted on the connector 100, the memory device 10 is in contact with the TIM107 surface in the contact area A1. Therefore, compared with the point contact case, the heat dissipation area can be expanded, thereby improving the heat dissipation efficiency.

[0091] Here, for reference Figure 6 The following description addresses the case where at least one of the terminals P of the formation column R3 of the memory device 10 in this embodiment is used as an SCS (Sideband signal Configuration Select) terminal.

[0092] Figure 6 This diagram illustrates the use of terminal P of memory device 10 as the SCS terminal. Figure 6 In (A), we envision using the terminal P132 of column R3 of memory device 10 as the SCS terminal. Additionally, Figure 6 In (A), it is envisioned that terminal P132 of the memory device 10 belonging to column R3 is used as the SCS terminal. However, it is not limited to the above example. Terminals P (terminals P120 to P131) that are different from terminal P132 of the memory device 10 belonging to column R3 may also be used as the SCS terminal. Furthermore, Figure 6 In (A), we envision a case where there is one SCS terminal, but it is not limited to the example described above; multiple SCS terminals may also be provided.

[0093] also, Figure 6In (A), it is envisioned that four of the six terminals P114 to P119 of the memory device 10 belonging to column R2, namely terminals P115 to P118, are used as signal terminals for PCIe sideband signals, and two terminals P114 and P119 are used as signal terminals for GND (Ground). However, the allocation of the six terminals P114 to P119 of the memory device 10 belonging to column R2 is not limited to the above example. Any terminal P of the six terminals P114 to P119 of the memory device 10 belonging to column R2 may be used as a signal terminal for sideband signals, and any terminal P may be used as a signal terminal for GND.

[0094] The SCS terminal is a signal terminal used to transmit signals (hereinafter referred to as selection signals) used to modify (select) sideband signals from the host machine. The host machine inputs a High level selection signal or a Low level selection signal to the SCS terminal.

[0095] like Figure 6 As shown in (B), when a High level selection signal is input to the SCS terminal, terminal P115 of the memory device 10 belonging to column R2 is used as the signal terminal for transmitting the first sideband signal SB1, terminal P116 is used as the signal terminal for transmitting the second sideband signal SB2, terminal P117 is used as the signal terminal for transmitting the third sideband signal SB3, and terminal P118 is used as the signal terminal for transmitting the fourth sideband signal SB4. In other words, when a High level selection signal is input to the SCS terminal, terminals P115 to P118 of the memory device 10 belonging to column R2 are used as signal terminals for transmitting the first sideband signals SB1 to SB4.

[0096] On the other hand, such as Figure 6 As shown in (B), when a low-level selection signal is input to the SCS terminal, terminal P115 of the memory device 10 belonging to column R2 is used as the signal terminal for transmitting the 5th sideband signal SB5, terminal P116 is used as the signal terminal for transmitting the 6th sideband signal SB6, terminal P117 is used as the signal terminal for transmitting the 7th sideband signal SB7, and terminal P118 is used as the signal terminal for transmitting the 8th sideband signal SB8. In other words, when a low-level selection signal is input to the SCS terminal, terminals P115 to P118 of the memory device 10 belonging to column R2 are used as the signal terminals for transmitting the second set of sideband signals SB5 to SB8.

[0097] in addition, Figure 6The example illustrates the transmission of sideband signals that are different from each other in the first and second configurations, but is not limited to this example. A portion of the common sideband signals in the first and second configurations can also be transmitted. For example, terminals P115 and P116 can be used to transmit the first sideband signal SB1 and the second sideband signal SB2 regardless of whether a high-level selection signal or a low-level selection signal is input to the SCS terminal. Terminals P117 and P118 can be used to transmit the third sideband signal SB3 and the fourth sideband signal SB4 when a high-level selection signal is input to the SCS terminal, and the fifth sideband signal SB5 and the sixth sideband signal SB6 when a low-level selection signal is input to the SCS terminal.

[0098] Figure 7 This refers to the host control unit 201 and switch 202 configured on the substrate of the host machine.

[0099] The switch 202 on the substrate of the host machine is connected to terminal 103 in connector 100 via pull-up resistor 202A, and further connected to SCS terminal P132 of memory device 10. The level of SCS terminal can be selected by fixing the switch 202 on or off.

[0100] As a method not shown, the host control unit 201 can also select the level of the SCS terminal by directly connecting the GPIO (General-purpose input / output) output of the host control unit 201 to terminal 103 in the connector 100. Furthermore, if the level of the SCS terminal is not selected, a pull-up resistor or a pull-down resistor can be used to fix the level.

[0101] like Figure 7 As shown, one end of switch 202 is grounded, and the other end is connected to pull-up resistor 202A and lead frame 103, which contacts the SCS terminal. If switch 202 is opened, a High level selection signal is input to the SCS terminal of memory device 10 via lead frame 103. If a High level selection signal is input to the SCS terminal, then... Figure 6 As shown in (B), terminals P115 to P118 belonging to column R2 function as signal terminals for transmitting the first sideband signal SB1 to the fourth sideband signal SB4 of the first configuration. On the other hand, if switch 202 is turned on, a low-level selection signal is input to the SCS terminal of the memory device 10 via lead frame 103. If a low-level selection signal is input to the SCS terminal, then... Figure 6As shown in (B), terminals P115 to P118 belonging to column R2 function as signal terminals for transmitting the 5th sideband signal SB5 to the 8th sideband signal SB8.

[0102] Next, refer to Figure 8 The power supply voltage supplied to the memory device 10 of this embodiment will be described.

[0103] Figure 8 This is a top view showing the external shapes of the first-generation memory device 10a and the second-generation memory device 10b. The first-generation memory device 10a is configured to operate with n different (where n ≥ 2) power supply voltages supplied from the outside. On the other hand, the second-generation memory device 10b is configured to operate with m different (where n > m ≥ 1, and n and m are natural numbers) power supply voltages supplied from the outside. Therefore, there is a possibility that the first-generation memory device 10a and the second-generation memory device 10b may coexist in the market. Hereinafter, we will assume that the first-generation memory device 10a is a storage device configured to operate with two power supply voltages, and refer to the memory device 10a as a 2-power supply memory device. On the other hand, we will refer to the memory device 10b as a 1-power supply memory device.

[0104] After a period of time has passed since the manufacture and shipment of first-generation memory devices, such as 10a, have begun, the manufacture and shipment of second-generation memory devices, such as 10b, have begun. As described above, an environment has arisen where first-generation memory devices and second-generation memory devices with different specifications are mixed together.

[0105] Therefore, in product manufacturing lines that manufacture host machines such as information processing devices, sometimes the manufacturing and operation testing of a Type 1 host machine configured to be supplied with two power supply voltages is carried out, and the manufacturing and operation testing of a Type 2 host machine configured to be supplied with one power supply voltage is carried out.

[0106] Type 1 host is an information processing device configured to supply two power storage devices 10a with a connector installed inside the host machine with two different power supply voltages. On the other hand, Type 2 host is an information processing device configured to supply one power storage device 10b with a connector installed inside the host machine with one different power supply voltage.

[0107] When two power storage devices 10a and one power storage device 10b have the same storage device shape, in the product manufacturing line, there may be instances where the power storage device 10b is incorrectly installed in the connector of the first type host and an operation test of the first type host is performed, or where the two power storage devices 10a are incorrectly installed in the connector of the second type host and an operation test of the second type host is performed.

[0108] During host machine operation testing, the host machine is powered on, and thus, the host machine supplies several power voltages corresponding to the type of host machine to the memory device. If the host machine operation test is performed with a power voltage supplied from the host machine that is incompatible with the power supply configuration of the memory device, there is a concern that a large current may flow and damage the memory device due to applying a voltage outside the operation guarantee, potentially causing a fire.

[0109] Therefore, in order to suppress the occurrence of this defect, it is considered to set the memory device shapes of the two-power-supply memory device 10a and the one-power-supply memory device 10b to be different, thereby distinguishing the two-power-supply memory device 10a from the one-power-supply memory device 10b. For example, consider the following... Figure 8 As shown in (A), in the 2-power memory device 10a, a first corner 35 is formed as a chamfered portion C. In contrast, in the 1-power memory device 10b, as shown in (A), a first corner 35 is formed as a chamfered portion C. Figure 8 As shown in (B), the second corner 36 is formed as in the chamfered portion C. Therefore, since it is impossible to install one power storage device 10b in the connector of the first type host and impossible to install two power storage devices 10a in the connector of the second type host, the occurrence of the aforementioned defect can be suppressed.

[0110] Figure 8 In this paper, the case of preventing the incorrect installation of power memory device 10b in the connector of a Type 1 host and the incorrect installation of power memory device 10a in the connector of a Type 2 host by setting the memory device shapes of the two power memory devices 10a and the one power memory device 10b to be different from each other will be described. On the other hand, it is considered to use at least one of the terminals P of the forming column R3 of the memory device 10 as a PCD (Power Configuration Detect) terminal, thereby suppressing the occurrence of the above problem. Hereinafter, refer to Figure 9 The case in which at least one of the terminals P of the forming column R3 of the memory device 10 of this embodiment is used as a PCD terminal will be described.

[0111] Figure 9 This diagram illustrates the use of terminal P of memory device 10 as the PCD terminal. Figure 9 In (A), we envision using the terminal P131 of the memory device 10 belonging to column R3 as the PCD terminal. Furthermore, Figure 9 In (A), the assumption is... Figure 6 Similarly, in case (A), the terminal P132 belonging to column R3 of memory device 10 is used as the SCS terminal. Additionally, Figure 9In (A), it is envisioned that terminal P131 of the memory device 10 belonging to column R3 is used as the PCD terminal. However, it is not limited to the above example. Terminals P120 to P130 of the memory device 10 that are different from terminals P131 and P132 belonging to column R3 can also be used as PCD terminals. Furthermore, Figure 9 In (A), we envision a case where there is one PCD terminal, but it is not limited to the example described above; multiple PCD terminals may also be provided.

[0112] The PCD terminal is a signal terminal used to transmit signals (hereinafter referred to as detection signals) for detecting the power configuration of the memory device 10. A High-level detection signal or a Low-level detection signal is output to the host machine from the PCD terminal.

[0113] like Figure 9 As shown in (B), when a high-level detection signal is output from the PCD terminal, the host machine identifies the power supply configuration of the memory device 10 as a dual-power supply. In other words, when a high-level detection signal is output from the PCD terminal, the host machine identifies the memory device mounted on the connector 100 as a dual-power supply memory device 10a. On the other hand, when a low-level detection signal is output from the PCD terminal, the host machine identifies the power supply configuration of the memory device 10 as a single-power supply. In other words, when a low-level detection signal is output from the PCD terminal, the host machine identifies the memory device mounted on the connector 100 as a single-power supply memory device 10b.

[0114] Figure 10 This refers to the internal circuitry connected to the PCD terminal of power storage device 10b and the internal circuitry connected to power storage device 20a.

[0115] like Figure 10 As shown in (A), the PCD terminal of the power storage device 10b is connected to GND within the device 10b. Therefore, under the control of the host control unit 201, if the first power supply voltage is supplied to the power storage device 10b, then GND becomes grounded, and a low-level detection signal is output from the PCD terminal of the power storage device 10b.

[0116] On the other hand, such as Figure 10 As shown in (B), the PCD terminal of the 2-power memory device 10a is turned on. Therefore, a High input is supplied to the host machine via a pull-up resistor on the substrate of the host machine.

[0117] according to Figure 10As shown, the host machine (host control unit 201) can identify the power supply configuration of the memory device 10 based on the level of the detection signal that can be output at the time when the first power supply voltage is supplied, and can determine whether the second power supply voltage is supplied, thereby suppressing the occurrence of the aforementioned malfunction.

[0118] Here, for reference Figure 11 The case where a terminal P of the memory device 10 of this embodiment is used as an SCS terminal or as a PCD terminal will be described. Figure 11 This diagram illustrates the use of a terminal P of memory device 10 as an SCS terminal or as a PCD terminal.

[0119] As described above, the SCS terminal is used to input selection signals, and the PCD terminal is used to output detection signals. Therefore, as long as the timing of the input selection signal and the timing of the output detection signal do not overlap, a single terminal P can perform the functions of both an SCS terminal and a PCD terminal.

[0120] To enable a single terminal P to function as both an SCS terminal and a PCD terminal, such as... Figure 11 As shown in (A), for example, a tri-state buffer 203 is provided between the host control unit 201 of the host machine and the lead frame 103 that contacts a terminal P that functions as both an SCS terminal and a PCD terminal. The tri-state buffer 203 may also be enclosed within the host control unit 201.

[0121] like Figure 11 As shown in (B), when one terminal P functions as an SCS terminal, a low-level switching signal is input from the host control unit 201 to the tri-state buffer 203. In this case, the tri-state buffer 203 directly outputs the selection signal output from the host control unit 201 to the memory device 10, thus enabling one terminal P to function as an SCS terminal.

[0122] Furthermore, under the control of the host control unit 201, if the second power supply voltage is supplied to the dual power memory device 10a, then switch 15 is opened, and the connection between the wiring used to supply the first power supply voltage and the pull-up resistor can also be disconnected. Alternatively, if a disconnection circuit (not shown) is provided, and the second power supply voltage is supplied to the dual power memory device 10a to execute the initialization sequence, then the connection between the wiring used to supply the first power supply voltage and the pull-up resistor can be disconnected through the disconnection circuit. This suppresses unnecessary power consumption caused by the pull-up resistor after the detection signal is output from the PCD terminal.

[0123] On the other hand, when one terminal P functions as a PCD terminal, such as Figure 11As shown in (B), a High level switching signal is input to the tri-state buffer 203 from the host control unit 201. If a High level switching signal is input from the host control unit 201, the tri-state buffer 203 becomes a high impedance state and an electrically disconnected state, so no signal is output from the tri-state buffer 203 to the memory device 10, and one terminal P can function as a PCD terminal.

[0124] Figure 12 This is a timing diagram illustrating an example of operation when a terminal P of the memory device 10 of this embodiment is used as an SCS terminal or as a PCD terminal.

[0125] like Figure 12 As shown, at time point T1, the host control unit 201 begins outputting a High level switching signal to the tri-state buffer 203. As a result, a specific terminal P of the memory device 10 functions as a PCD terminal. Next, at time point T2, under the control of the host control unit 201, the first power supply voltage is supplied to the memory device 10. If the first power supply voltage is supplied to the memory device 10, then at time point T3, a detection signal output from the PCD terminal of the memory device 10 is input to the host control unit 201. Thus, the host control unit 201 can identify the power supply configuration of the memory device 10 and determine whether a second power supply voltage is supplied.

[0126] At time T4, after identifying the power supply configuration of memory device 10, host control unit 201 switches the level of the switching signal output to tri-state buffer 203 from High level to Low level. As a result, the specific terminal P of memory device 10 functions as an SCS terminal. Hereafter, a selection signal of High or Low level is output from host control unit 201 to memory device 10, and the sideband signal terminal configured on memory device 10 is used as a signal terminal for transmitting a sideband signal of the first configuration corresponding to the High level selection signal, or a signal terminal for transmitting a sideband signal of the second configuration corresponding to the Low level selection signal.

[0127] The following describes a variation of the configuration of the multiple terminals P provided in the memory device 10. Furthermore, the following will primarily refer only to... Figure 4 The terminals shown have different configurations; details are omitted. Figure 4 Explanation of the same parts. In addition, the distance between column R1 and column R3 in the Y-axis direction of any terminal configuration is longer than the distance between column R1 and the first edge 31 in the Y-axis direction, and the distance between column R3 and the fourth edge 34 in the Y-axis direction.

[0128] (Example 1 of the variations)

[0129] Figure 13 This is a top view showing the external shape of the memory device 10A in the first variation example, the external shape of the connector 100A in the host machine for mounting the memory device 10A, and the configuration example of the area where the TIM 107 is attached. Figure 13 (A) is a top view showing the external shape of memory device 10A and the contact area A11 that contacts TIM107. Figure 13 (B) is a top view showing the external shape of connector 100A and the attachment area A21 of TIM107.

[0130] Figure 13 The terminal shown in (A) is positioned at a point closer to the first edge 31 than the fourth edge 34 at the location of the six terminals P114 to P119 forming column R2. Figure 4 (A) shows a different terminal configuration.

[0131] therefore, Figure 13 (A) shows the connector 100A for mounting the memory device 10A, such as Figure 13 As shown in (B), the lead frame terminals 104 of the lead frame 101 forming column r1 face the negative direction of the Y-axis, the lead frame terminals 104 of the lead frame 102 forming column r2 face the positive direction of the Y-axis, and the lead frame terminals 104 of the lead frame 103 forming column r3 face the positive direction of the Y-axis.

[0132] like Figure 13 As shown in (B), in connector 100A, TIM 107 is attached to the region between columns r1 and r2, and to the region between the lead frame 102 corresponding to terminal P116 of memory device 10A and the lead frame 102 corresponding to terminal P117 of memory device 10A in the lead frame 102 forming column r2. Figure 13 (B) The attached area A21, indicated by the diagonal line, is where TIM107 is attached.

[0133] Figure 13 (A) The contact area A11, and... Figure 13 (B) The mounting area A21 of the TIM107, shown by the diagonal line, overlaps when viewed from above when the memory device 10A is mounted on the connector 100A. In other words, when the memory device 10A is mounted on the connector 100A, the contact area A11 of the memory device 10A faces and contacts the TIM107 attached to the mounting area A21 of the connector 100A.

[0134] As explained above, by connecting terminal P of memory device 10A as... Figure 13As shown in (A), the connector 100A, which can be used to mount the memory device 10A, is configured as follows: Figure 13 As shown in (B), the mounting area A21 for attaching TIM107 is set. In other words, since the number of terminals P in the forming column R2 of the memory device 10A is less than the number of terminals P in the forming columns R1 or R3, the following is achieved: Figure 13 As shown in (A), the terminal configuration with contact area A11 allows for the provision of an attachment area A21 for attaching the TIM 107 to the connector 100A. Therefore, when the memory device 10A is mounted on the connector 100A, the memory device 10A contacts the TIM 107 surface in contact area A11, thus enabling... Figure 4 The terminal configuration shown also improves heat dissipation efficiency.

[0135] (Second variation example)

[0136] Figure 14 This is a top view showing the external shape of the memory device 10B in the second variation, the external shape of the connector 100B in the host machine for mounting the memory device 10B, and the configuration example of the area where the TIM 107 is attached. Figure 14 (A) is a top view showing the external shape of memory device 10B and the contact area A12 that contacts TIM107. Figure 14 (B) is a top view showing the external shape of connector 100B and the attachment area A22 of TIM107.

[0137] Figure 14 The terminal configuration shown in (A) reduces the number of terminals P forming column R2 from 6 to 3, which is consistent with... Figure 4 The terminal configuration shown in (A) is different. Specifically, Figure 14 The terminal shown in (A) is configured in Figure 4 The terminals P114 to P116 shown are not configured as terminals P forming column R2, which is consistent with... Figure 4 (A) shows a different terminal configuration.

[0138] Figure 14 (A) Of the three terminals P117 to P119 forming column R2 shown, two terminals P117 and P118 are used as signal terminals for PCIe sideband signals, and one terminal P119 is used as a signal terminal for GND. However, the allocation of the three terminals P117 to P119 of column R2 in memory device 10B is not limited to the example described above. Any terminal P of the three terminals P117 to P119 of column R2 in memory device 10B can also be used as a signal terminal for sideband signals and as a signal terminal for GND.

[0139] like Figure 14 As shown in (B), in connector 100B, TIM 107 is attached in the region between column r1 and column r2, and in the region between the lead frame 102 corresponding to terminal P117 of memory device 10B and the third edge 113 of connector frame 106. Figure 14 In (B), the attached area A22, indicated by the diagonal line, is where TIM107 is attached.

[0140] Figure 14 (A) The contact area A12, and... Figure 14 (B) The mounting area A22 of the TIM107, indicated by the diagonal line, overlaps when viewed from above when the memory device 10B is mounted on the connector 100B. In other words, when the memory device 10B is mounted on the connector 100B, the memory device 10B is facing and in contact with the TIM107 attached to the mounting area A22 of the connector 100B in the contact area A12.

[0141] As explained above, by connecting terminal P of memory device 10B as... Figure 14 As shown in (A), the connector 100B, which is used for mounting the memory device 10B, is configured as follows: Figure 14 As shown in (B), the mounting area A22 for attaching TIM107 is set. In other words, since the number of terminals P forming column R2 of memory device 10B is less than the number of terminals P forming column R1 or R3, and the implementation... Figure 14 (A) shows the terminal configuration with contact area A12, so an attachment area A22 for attaching TIM107 can be provided on connector 100B. Furthermore, according to... Figure 14 The contact area A12 provided for the terminal configuration shown is compared to that provided according to Figure 4 and Figure 13 The increased size of contact areas A1 and A11, as shown in the terminal configuration, effectively reduces the number of terminals forming column R2 from 6 to 3. Therefore, Figure 14 The terminal configuration shown is consistent with Figure 4 and Figure 13 Compared to the terminal configuration shown, the area in contact with the TIM107 surface can be expanded, which can further improve heat dissipation efficiency.

[0142] in addition, Figure 14 The text shows that it will not be included. Figure 4 Terminals P114 to P116 are configured as terminals P forming column R2, while terminals P117 to P119 are configured as terminals P forming column R2. However, the terminal configuration is not limited to this. For example, it is also possible not to configure terminals P. Figure 4Terminals P117 to P119 are configured as terminals P forming column R2, while terminals P114 to P116 are configured as terminals P forming column R2. This terminal configuration can also achieve the same... Figure 14 The terminal configuration shown has the same effect.

[0143] also, Figure 14 The diagram illustrates a configuration where terminals P117 to P119 forming column R2 are positioned closer to the fourth edge 34 than the first edge 31 of the memory device 10B. However, this configuration is not limited to this; for example, terminals P117 to P119 forming column R2 can be positioned closer to the first edge 31 than the fourth edge 34 of the memory device 10B. This terminal configuration can also achieve... Figure 14 The terminal configuration shown has the same effect.

[0144] Moreover, it is also possible to Figure 4 (A) The memory device 10 is installed Figure 14 (B) Connector 100B. In this case, terminals P114 to P116 of column R2 are in contact with TIM 107, but an insulating TIM is used to avoid short circuit, or the unconnected terminals P114 to P116 are set to be connected in a preset state, so that they will not become output mode, and the input is also a through current prevention type I / O unit.

[0145] (Example 3)

[0146] Figure 15 This is a top view showing the external shape of the memory device 10C in the third variation, the external shape of the connector 100C in the host machine for mounting the memory device 10C, and the configuration example of the area where the TIM 107 is attached. Figure 15 (A) is a top view showing the external shape of memory device 10C and the contact area A13 that contacts TIM107. Figure 15 (B) is a top view showing the external shape of connector 100C and the attachment area A23 of TIM107.

[0147] Figure 15 The terminal configuration shown in (A) is located at point P where the forming column R2 is not provided. Figure 4 The terminal configuration shown in (A) is different. That is to say, Figure 15 (A) shows the terminal configuration for sideband signal terminals without PCIe specification.

[0148] In the aforementioned cases, such as Figure 15 As shown in (B), in connector 100C, TIM107 is attached in the area between column r1 and column r3. In other words, in Figure 14(B) The attached area A23, indicated by the diagonal line, is where TIM107 is attached.

[0149] Figure 15 (A) The contact area A13, and... Figure 15 (B) The mounting area A23 of TIM107, indicated by the diagonal line, overlaps when viewed from above when the memory device 10C is mounted on the connector 100C. In other words, when the memory device 10C is mounted on the connector 100C, the memory device 10C is facing and in contact with the TIM107 attached to the mounting area A23 of the connector 100C in the contact area A13.

[0150] As explained above, by connecting terminal P of memory device 10C as... Figure 15 As shown in (A), the connector 100C, which can be mounted on the memory device 10C, is as follows: Figure 15 As shown in (B), the mounting area A23 for attaching TIM107 is provided. In other words, the memory device 10C achieves [the following] by not providing the terminal P that forms column R2. Figure 15 (A) shows the terminal configuration with contact area A13, thus allowing the connector 100C to have an attachment area A23 for attaching the TIM 107. Additionally, utilizing... Figure 15 The contact area A13 provided for the terminal configuration shown is compared to the one in the terminal configuration shown. Figure 4 and Figure 13 The contact area A1 and contact area A11 shown are... Figure 14 The contact area A12 shown is enlarged, corresponding to the portion of terminal P where column R2 is not formed. Therefore, Figure 15 The terminal configuration shown is consistent with Figure 4 , Figure 13 and Figure 14 Compared to the terminal configuration shown, it can expand the contact area with the TIM107 surface and further improve heat dissipation efficiency.

[0151] Moreover, it is also possible to Figure 4 (A) or Figure 13 (A) memory device 10 and memory device 10A, installed in Figure 15 (B) Connector 100C. In this case, although terminals P114 to P116 and terminals P117 to P119 of column R2 will contact TIM107, an insulating TIM is used to avoid short circuit, or the unconnected terminals P114 to P116 and terminals P117 to P119 are made to be connected in a preset state instead of being in output mode, and the input is also made to be a current-protected I / O unit.

[0152] (Example 4)

[0153] Figure 16 This is a top view showing the external shape of the memory device 10D in the fourth variation, the external shape of the connector 100D in the host machine for mounting the memory device 10D, and the configuration example of the area where the TIM 107 is attached. Figure 16 (A) is a top view showing the external shape of the memory device 10D and the contact area A14 that contacts the TIM107. Figure 16 (B) is a top view showing the external shape of connector 100D and the attachment area A24 of TIM107.

[0154] Figure 16 The terminal configuration shown in (A) relates to the following points: Figure 4 (A) shows a different terminal configuration, namely: due to Figure 16 (B) The length of the lead frame 103 of the connector 100 in the Y-axis direction is longer than [the length of the lead frame 103 in the Y-axis direction]. Figure 4 (B) shows the length of the lead frame 103 in the Y-axis direction, so the position of column R3 in the Y-axis direction becomes closer to the first edge 31. Specifically, Figure 16 In the terminal configuration shown in (A), the position of column R3 in the Y-axis direction is... Figure 4 Compared to the terminal configuration shown in (A), it is approximately one row closer to the first edge 31 (equivalent to the length of terminal P in the Y-axis direction).

[0155] In the aforementioned cases, such as Figure 16 As shown in (B), in connector 100D, TIM107 is attached in the area between column r1 and column r3. Figure 16 (B) The attached area A24, indicated by the diagonal line, is where TIM107 is attached.

[0156] Figure 16 (A) The contact area A14, and... Figure 16 (B) The mounting area A24, where the TIM107 is attached, is shown by a diagonal line. When the memory device 10D is mounted on the connector 100D, it overlaps with the TIM107 attached to the mounting area A24 of the connector 100D in a top view. In other words, when the memory device 10D is mounted on the connector 100D, the memory device 10D is facing and in contact with the TIM107 attached to the mounting area A24 of the connector 100D in the contact area A14.

[0157] As explained above, even if the length of the lead frame 103 in the Y-axis direction is greater than... Figure 4 The case shown in (B) is longer, but if... Figure 16 By configuring the terminals P of the memory device 10D as shown in (A), the connector 100D for mounting the memory device 10D can be connected as follows: Figure 16(B) shows the attachment area A24 for attaching TIM107. Figure 16 The terminal configuration shown can also improve heat dissipation efficiency compared to the point contact case.

[0158] As shown in one of the variations in the fourth example, the memory device 10 of this embodiment arranges multiple terminals P regardless of the length of the lead frame 103 of the connector 100 in the Y-axis direction, thereby enabling the provision of a contact area A1 that contacts the TIM 107 and improving the heat dissipation efficiency of the memory device 10.

[0159] Furthermore, in this embodiment, terminal P is not disposed in the contact area A1 of the memory device 10, but this is not limited to the above example; terminal P may also be disposed in the contact area A1 of the memory device 10. However, since terminal P disposed in the contact area A1 contacts the TIM 107 attached to the attachment area A2 when the memory device 10 is mounted on the connector 100, terminal P cannot be used as a signal terminal for sideband signals or a signal terminal for GND. However, in this case, the memory device 10 can still make contact with the TIM 107 surface, thereby improving the heat dissipation efficiency of the memory device 10.

[0160] Furthermore, the sideband signal in this embodiment can also be referred to as a selectable signal.

[0161] According to the first embodiment described above, the memory device 10 (10C) includes a plurality of signal terminals for transmitting signals and has a plurality of terminals P exposed on the first surface 21 of the body 11. The plurality of terminals P form at least columns R1 and R3. Column R1 includes a plurality of signal terminals P, spaced apart from each other in the X-axis direction at a position closer to the first edge 31 than the fourth edge 34 of the body 11. Column R3 includes a plurality of signal terminals P, spaced apart from each other in the X-axis direction at a position closer to the fourth edge 34 than the first edge 31 of the body 11. The area between columns R1 and R3 on the first surface 21 of the body 11 includes a contact area A1 (A13) that contacts a TIM 107 disposed on a printed circuit substrate of an electrically connected host machine. Therefore, when the memory device 10 (10C) is mounted on the connector 100 (100C), it can contact the TIM 107 surface in the contact area A1 (A13), thus improving the heat dissipation efficiency of the memory device 10 (10C).

[0162] (Second Implementation)

[0163] Next, the second embodiment will be described. Furthermore, detailed descriptions of matters already described in the first embodiment will be omitted; the following description will primarily focus on matters that differ from the first embodiment.

[0164] Figure 17 This diagram shows an example of the pin assignment of terminal groups P101 to P113 belonging to column R1 of memory device 10. Terminal groups P101 to P113 belonging to column R1 are used as signal terminals for transmitting differential signal pairs of 2 channels according to the PCIe specification, and as ground terminals for noise protection.

[0165] like Figure 17 As shown, terminals P101, P104, P107, P110, and P113 belonging to column R1 are used as noise protection grounding terminals (GND terminals) and are assigned grounding potential. Terminals P102 and P103, P105 and P106, P108 and P109, P111 and P112 belonging to column R1 are used as signal terminals for transmitting differential signal pairs according to the PCIe specification.

[0166] For terminals P102 and P103, a receive differential signal Rx0 output from the host machine is assigned. More specifically, terminal P102 is assigned the positive receive differential signal Rx0+, and terminal P103 is assigned the negative receive differential signal Rx0-. For terminals P105 and P106, a receive differential signal Rx1 output from the host machine is assigned. More specifically, terminal P105 is assigned the positive receive differential signal Rx1+, and terminal P106 is assigned the negative receive differential signal Rx1-.

[0167] As described above, differential signal pairs on the receiving side are assigned to the terminals P102, P103, P105, and P106, which are used as signal terminals for transmitting differential signal pairs according to the PCIe specification, that is, the terminals P102, P103, P105, and P106 arranged between the center line of the memory device 10 and the body 11 in the X-axis direction and the second edge 32.

[0168] For terminals P108 and P109, a transmit differential signal Tx0 output from memory device 10 is assigned. More specifically, a positive transmit differential signal Tx0+ is assigned to terminal P108, and a negative transmit differential signal Tx0- is assigned to terminal P109. For terminals P111 and P112, a transmit differential signal Tx1 output from memory device 10 is assigned. More specifically, a positive transmit differential signal Tx1+ is assigned to terminal P111, and a negative transmit differential signal Tx1- is assigned to terminal P112.

[0169] As described above, differential signal pairs on the transmitting side are assigned to the terminals P108, P109, P111, and P112, which are used as signal terminals for transmitting differential signal pairs according to the PCIe specification, that is, the terminals P108, P109, P111, and P112 arranged between the center line of the memory device 10 and the body 11 and the third edge 33 in the X-axis direction.

[0170] In the PCIe specification, a channel is formed by differential signal pairs on the receiving side and differential signal pairs on the transmitting side. Figure 17 In this configuration, a channel is formed by the received differential signal pairs Rx0+ and Rx0- and the transmitted differential signal pairs Tx0+ and Tx0-, and a channel is also formed by the received differential signal pairs Rx1+ and Rx1- and the transmitted differential signal pairs Tx1+ and Tx1-. Thus, as described above, differential signal pairs with two channel capacity according to the PCIe specification can be transmitted.

[0171] like Figure 17 As shown, terminals P102 and P103, which are used to receive differential signal pairs Rx0+ and Rx0-, are located between terminals P101 and P104, which are used as ground terminals. Furthermore, as... Figure 17 As shown, terminals P105 and P106, which are used to receive differential signal pairs Rx1+ and Rx1-, are located between terminals P104 and P107, which are used as ground terminals. Furthermore, as... Figure 17 As shown, terminals P108 and P109, which are used to transmit differential signals Tx0+ and Tx0-, are located between terminals P107 and P110, which are used as ground terminals. Furthermore, as... Figure 17 As shown, terminals P111 and P112, which are assigned to transmit differential signal pairs Tx1+ and Tx1-, are located between terminals P110 and P113, which are used as ground terminals.

[0172] according to Figure 17 The pin assignments shown reduce the impact of crosstalk. Crosstalk refers to the phenomenon where an interference from or influencing of adjacent signal traces leads to a deterioration in the signal quality of those traces. In this embodiment, the impact of a stronger transmitted differential signal pair affecting a weaker received differential signal pair, thus degrading the signal quality of the received differential signal pair, is considered.

[0173] The following will Figure 18 The pin assignment shown is used as a comparative example to explain the effect of the pin assignment in this embodiment in more detail. Furthermore, the comparative example is used to illustrate some of the effects that the pin assignment in this embodiment can achieve, and does not exclude the effects common to both the comparative example and this embodiment.

[0174] Figure 18 This is a diagram illustrating an example of pin assignment for a comparison example. For example... Figure 18 As shown, the pin assignment of the comparative example differs from that of this embodiment in that terminals P105 and P106 are assigned to transmit differential signal pairs Tx0+ and Tx0-, and terminals P108 and P109 are assigned to receive differential signal pairs Rx1+ and Rx1-.

[0175] according to Figure 18The pin assignments shown include cases where the received differential signal pairs Rx0+ and Rx0- assigned to terminals P102 and P103 are affected by the transmitted differential signal pairs Tx0+ and Tx0- assigned to terminals P105 and P106, resulting in signal quality degradation. Furthermore, there are cases where the received differential signal pairs Rx1+ and Rx1- assigned to terminals P108 and P109 are affected by the transmitted differential signal pairs Tx0+ and Tx0- assigned to terminals P105 and P106, and the transmitted differential signal pairs Tx1+ and Tx1- assigned to terminals P111 and P112, resulting in signal quality degradation.

[0176] In contrast, according to the pin assignment of this embodiment, such as Figure 17 As shown, since there are no terminals for transmitting differential signal pairs near terminals P102 and P103 that allocate the receiving differential signal pairs Rx0+ and Rx0-, the receiving differential signal pairs Rx0+ and Rx0- are almost unaffected by crosstalk, thus suppressing signal quality degradation. Furthermore, as... Figure 17 As shown, near terminals P105 and P106 that allocate the received differential signal pairs Rx1+ and Rx1-, there are terminals P108 and P109 that allocate the transmitted differential signal pairs Tx0+ and Tx0-. As terminals for allocating the transmitted differential signal pairs, as shown in the comparative example, since the received differential signal pairs Rx1+ and Rx1- are not affected by the transmitted differential signal pairs Tx0+ and Tx0- and the transmitted differential signal pairs Tx1+ and Tx1-, the degradation of signal quality can be further suppressed compared to the case of the comparative example.

[0177] in addition, Figure 17 The pin assignments for receiving differential signal pairs Rx0+ and Rx0- at terminals P102 and P103, receiving differential signal pairs Rx1+ and Rx1- at terminals P105 and P106, transmitting differential signal pairs Tx0+ and Tx0- at terminals P108 and P109, and transmitting differential signal pairs Tx1+ and Tx1- at terminals P111 and P112 have been described. However, the pin assignments that can suppress signal quality degradation caused by crosstalk are not limited to these. For example, differential signal pairs Tx1+ and Tx1- can be assigned to terminals P102 and P103 for transmission, Tx0+ and Tx0- for transmission to terminals P105 and P106, differential signal pairs Rx1+ and Rx1- for reception to terminals P108 and P109, and differential signal pairs Rx0+ and Rx0- for reception to terminals P111 and P112. In this case, it is also related to... Figure 17 Similarly, it can suppress signal quality degradation caused by crosstalk.

[0178] In other words, if the differential signal pairs on the receiving side are assigned to the terminals on the left and right sides, and the differential signal pairs on the transmitting side are assigned to the terminals on the other side, then... Figure 17 Similarly, it can suppress signal quality degradation caused by crosstalk.

[0179] also, Figure 17 The previous section explained the case where the number of terminals belonging to column R1 is 13, but the number of terminals belonging to column R1 is not limited to this; more than 13 terminals can also be configured for column R1. If the number of terminals belonging to column R1 is 14 or more, such as... Figure 19 As shown, by configuring two or more grounding terminals P107 and P108 between terminals P105 and P106 that allocate the receiving differential signal pairs Rx1+ and Rx1- and terminals P109 and P110 that allocate the transmitting differential signal pairs Tx0+ and Tx0- (in other words, between the terminals closest in distance between the terminals allocating the receiving differential signal pairs and the terminals allocating the transmitting differential signal pairs), the influence of the transmitting differential signal pairs Tx0+ and Tx0- on the receiving differential signal pairs Rx1+ and Rx1- can be reduced, and the degradation of signal quality can be suppressed.

[0180] Figure 20 This diagram illustrates an example of the pin assignment between terminal groups P114-P119 (belonging to column R2) and terminal groups P120-P132 (belonging to column R3) of memory device 10. Terminal groups P114-P119 (belonging to column R2) are used as signal terminals for various optional signals for different products. Terminal groups P120-P132 (belonging to column R3) are used as common control signal terminals and power supply terminals for all products.

[0181] like Figure 20 As shown, terminals P114, P115, P118, and P119 belonging to column R2 are used as grounding terminals (GND terminals) for return current. In other words, among the terminal groups P114 to P119 belonging to column R2, multiple terminals P114 and P115 arranged between the center line of the memory device 10 and the body 11 in the X-axis direction and the second edge 32 are used as grounding terminals for return current, and multiple terminals P118 and P119 arranged between the center line of the memory device 10 and the body 11 in the X-axis direction and the third edge 33 are used as grounding terminals for return current.

[0182] Terminals P116 and P117 belonging to column R2 are used as spare terminals (RSVD terminals), for example, to distribute sideband signals.

[0183] In addition, such as Figure 20As shown, terminals P121, P122, P125, and P129 belonging to column R3 are assigned signals, for example, those conforming to PCIe specifications. More specifically, differential signal pairs REFCLK+ and REFCLK- are assigned to terminals P121 and P122. The PERST# signal (reset signal) is assigned to terminal P125. The CLKREQ# signal is assigned to terminal P129.

[0184] Moreover, such as Figure 20 As shown, terminals P120 and P123, belonging to column R3, are used as grounding terminals for noise protection. Terminals P121 and P122, which distribute differential signal pairs REFCLK+ and REFCLK-, are located between terminals P120 and P123, which are used as grounding terminals for noise protection.

[0185] In addition, such as Figure 20 As shown, terminal P124, belonging to column R3, is used as a grounding terminal for returning current. Terminals P126 to P128, belonging to column R3, are used as power supply terminals for supplying a second power supply voltage (e.g., 1.2 V). Terminals P130 to P132, belonging to column R3, are used as power supply terminals for supplying a first power supply voltage (e.g., 2.5 V).

[0186] according to Figure 20 The pin assignment shown can accommodate the increase in current consumption as the performance of the memory device 10 improves. For example, when comparing a PCIe 3.0-based device with a PCIe 4.0-based device, the PCIe 4.0-based device performs approximately twice as well as the PCIe 3.0-based device, but consumes more current. The pin assignment according to this embodiment can accommodate this increase in current consumption.

[0187] The following will Figure 21 The pin assignment shown is used as a comparative example to explain the effect of the pin assignment in this embodiment in more detail. Furthermore, the comparative example is used to illustrate some of the effects that the pin assignment in this embodiment can achieve, and does not exclude the effects common to both the comparative example and this embodiment.

[0188] Figure 21 This is a diagram illustrating an example of pin assignment for a comparison example. For example... Figure 21As shown, the pin assignment of the comparative example differs from that of the present embodiment in that terminals P115 and P118 in column R2 are used as spare terminals instead of ground terminals for return current. Furthermore, the pin assignment of the comparative example differs from that of the present embodiment in that terminal P132 in column R3 is used as an NC terminal, and a ground terminal for return current is not located in column R3. Moreover, the pin assignment of the comparative example differs from that of the present embodiment in that terminal P124 in column R3, adjacent to terminal P123 which is used as a ground terminal for noise protection, is used as a power supply terminal.

[0189] according to Figure 21 As the pin assignments shown increase with the improved performance of memory device 10, there are no grounding terminals for return current except for terminals P114 and P119. Therefore, the increased return current needs to flow through terminals P120 and P123, which serve as noise-protection grounding terminals, to cope with the increased current consumption. If return current flows through terminals P120 and P123, which serve as noise-protection grounding terminals, there is a concern that the differential signals assigned to terminals P121 and P122 located between these terminals may degrade the signal quality of REFCLK+ and REFCLK-.

[0190] In contrast, according to the pin assignment of this embodiment, such as Figure 20 As shown, since terminals P115 and P118 belonging to column R2 and terminal P124 belonging to column R3 are used as ground terminals for return current, the increased return current can flow through these terminals P115, P118, and P124, which can cope with the increase in current consumption as the performance of memory device 10 improves. Furthermore, according to the pin allocation of this embodiment, as described above, since the path for the increased return current is ensured, signal quality degradation of differential signals for REFCLK+ and REFCLK- can be suppressed. Moreover, according to the pin allocation of this embodiment, as shown in the comparative example, since the ground terminal and power terminal are not arranged adjacently, it is possible to suppress the lead frame corresponding to the ground terminal of connector 100 from erroneously contacting the power terminal due to factors such as vibration.

[0191] Figure 22 This is a three-dimensional view showing the outer and inner layers of memory device 10. For example... Figure 22As shown, on the outer layer of the memory device 10, there are: terminal groups P101 to P113 belonging to column R1; terminal groups P114 to P119 belonging to column R2; terminal groups P120 to P132 belonging to column R3; and through holes VA1 to VA12, which are used to connect terminals P101, P104, P107, P110, P113, P114, P115, P118, P119, P120, P123, and P124, which are used as grounding terminals, to the inner layer.

[0192] like Figure 22 As shown, in the inner layer of the memory device 10, a ground plane GP1 is provided, which is electrically and thermally connected to terminals P101, P104, P107, P110, and P113 in column R1, which are used as grounding terminals for noise protection. In the inner layer of the memory device 10, a ground plane GP2 is provided, which is electrically and thermally connected to terminals P114, P115, P118, and P119 in column R2, which are used as grounding terminals for return current, and terminal P124 in column R3, which is also used as a grounding terminal for return current. In the inner layer of the memory device 10, a ground plane GP3 is provided, which is electrically and thermally connected to terminals P120 and P123 in column R3, which are used as grounding terminals for noise protection. Ground planes GP1 to GP3 are formed, for example, of copper foil. Ground planes GP1 to GP3 are not electrically connected to each other. Furthermore, in the inner layer of the memory device 10, through holes VB1 to VB12 are provided, corresponding to the through holes VA1 to VA12 provided in the outer layer.

[0193] Terminals P101, P104, P107, P110, and P113, located on the outer layer of the memory device 10 and used as grounding terminals, are electrically and thermally connected to ground plane GP1 via through-holes VA1-VA5 and VB1-VB5. Terminals P114, P115, P118, P119, and P124, located on the outer layer of the memory device 10 and used as grounding terminals for return current, are electrically and thermally connected to ground plane GP2 via through-holes VA6-VA9 and VA12 and through-holes VB6-VB9 and VB12. Terminals P120 and P123, located on the outer layer of the memory device 10 and used as grounding terminals for noise protection, are electrically and thermally connected to ground plane GP3 via through-holes VA10 and VA11 and through-holes VB10 and VB11.

[0194] in addition, Figure 22 The example shown illustrates the case where ground planes GP1 to GP3 are formed in the same layer, but this is not a limitation; each of ground planes GP1 to GP3 may also be formed in different layers.

[0195] according to Figure 22 The structure shown (in other words, Figure 20 (Pin assignment shown), with Figure 21Compared to the comparative example shown, this configuration improves heat dissipation. More specifically, Figure 22 The structure shown is Figure 21 Compared to the configuration of the comparative example shown, the number of terminals used as grounding terminals is greater, and more terminals can be electrically and thermally connected to the ground plane GP2, thus further improving the heat dissipation effect compared to the configuration of the comparative example.

[0196] According to the second embodiment described above, the memory device 10 includes multiple pairs of terminals for allocating and receiving differential signal pairs (e.g., terminals P102 and P103, P105 and P106) and multiple pairs of terminals for allocating and transmitting differential signal pairs (e.g., terminals P108 and P109, P111 and P112). The multiple pairs of terminals for allocating and receiving differential signal pairs are positioned between the centerline of the body 11 in the X-axis direction and one side edge (second edge 32), and the multiple pairs of terminals for allocating and transmitting differential signal pairs are positioned between the centerline of the body 11 in the X-axis direction and another side edge (third edge 33). This suppresses crosstalk and signal quality degradation.

[0197] Furthermore, according to the second embodiment described above, the memory device 10 includes a plurality of grounding terminals (e.g., terminals P114 and P115) for returning current disposed between the center line of the body 11 and the second edge 32 in the X-axis direction, and a plurality of grounding terminals (e.g., terminals P118 and P119) for returning current disposed between the center line of the body 11 and the third edge 33 in the X-axis direction. Therefore, more of the terminals belonging to column R2 can be electrically and thermally connected to the ground plane GP2, thus improving heat dissipation.

[0198] (Third Implementation)

[0199] Next, the third embodiment will be described. Furthermore, detailed descriptions of matters already described in the first and second embodiments will be omitted; the following description will primarily focus on matters that differ from the first and second embodiments.

[0200] Figure 23 This diagram illustrates the case where terminals P116 and P117 of column R2 belonging to memory device 10 are used as signal terminals for transmitting sideband signals, and terminals P116 and P117 are also used as SCS terminals and PCD terminals (that is, the signal terminals, SCS terminals, and PCD terminals for transmitting sideband signals are shared).

[0201] As described above, the SCS terminal is the signal terminal used to input the selection signal before the memory device 10 is started, and the PCD terminal is the signal terminal used to output the detection signal before the memory device 10 is started. In contrast, since the sideband signal is the signal input after the memory device 10 is started, the signal terminal, SCS terminal, and PCD terminal used to transmit the sideband signal can be shared. Furthermore, the situation before the memory device 10 is started is equivalent to the case where a reset signal is applied, and the situation after the memory device 10 is started is equivalent to the case where the reset signal has been released.

[0202] exist Figure 23 In (A), it is envisioned that terminal P116 belonging to column R2 of memory device 10 is shared by a signal terminal used to transmit sideband signals and an SCS terminal. More specifically, it is envisioned that terminal P116 is used as an SCS terminal before memory device 10 is powered on, and as a signal terminal used to transmit sideband signals after memory device 10 is powered on. Furthermore, in Figure 23 In (A), it is envisioned that terminal P117 belonging to column R2 of memory device 10 is shared by a signal terminal used to transmit sideband signals and a PCD terminal. More specifically, it is envisioned that terminal P117 is used as a PCD terminal before memory device 10 is powered on, and is used as a signal terminal used to transmit sideband signals after memory device 10 is powered on.

[0203] like Figure 23 As shown in (B), if a high-level selection signal is input to terminal P116 (used as an SCS terminal) before device startup, after device startup, terminal P116 is used as a signal terminal to transmit the first sideband signal SB1, and terminal P117 is used as a signal terminal to transmit the second sideband signal SB2. In other words, if a high-level selection signal is input to terminal P116 (used as an SCS terminal) before device startup, after device startup, terminals P116 and P117 are used as signal terminals to transmit the first sideband signals SB1 and SB2.

[0204] On the other hand, such as Figure 23 As shown in (B), if a low-level selection signal is input to terminal P116 (used as an SCS terminal) before device startup, after device startup, terminal P116 is used as a signal terminal to transmit the third sideband signal SB3, and terminal P117 is used as a signal terminal to transmit the fourth sideband signal SB4. In other words, if a low-level selection signal is input to terminal P116 (used as an SCS terminal) before device startup, after device startup, terminals P116 and P117 are used as signal terminals to transmit the second sideband signals SB3 and SB4.

[0205] like Figure 23 As shown in (C), when a high-level detection signal is output from terminal P117 (used as a PCD terminal) before the device is powered on, the host machine identifies the power supply configuration of the memory device 10 as a dual power supply. On the other hand, as... Figure 23 As shown in (C), when a low-level detection signal is output from terminal P117, which is used as a PCD terminal, before the device is started, the host machine recognizes that the power supply configuration of the memory device 10 is 1 power supply.

[0206] Here, for reference Figure 24 The timing diagram illustrates... Figure 23 The operation of the memory device 10 shown is an example of the operation when the signal terminals, SCS terminals and PCD terminals used to transmit sideband signals are shared.

[0207] like Figure 24 As shown, at time 1 T1, under the control of the host machine (host control unit 201), the first power supply voltage is supplied to the memory device 10. If the first power supply voltage is supplied to the memory device 10, then at time 2 T2, a detection signal is output from the PCD terminal of the memory device 10 (that is, terminal P117 before device startup) to the host machine. At time 3 T3, the host machine reads the detection signal output by the memory device 10, identifies the power supply configuration of the memory device 10, and determines whether the second power supply voltage is supplied. Furthermore, at time 3 T3, the host machine establishes terminal P116 as the SCS terminal, and subsequently outputs a selection signal to the memory device 10.

[0208] At time 4 (T4) after identifying the power supply configuration of memory device 10, a low-level reset signal is de-established. Consequently, terminal P117, which is used as a PCD terminal, is subsequently used as a signal terminal to transmit a sideband signal corresponding to the level of the selection signal input to the SCS terminal. Then, at time 5 (T5), the host machine de-establishes terminal P116, which is used as an SCS terminal, and terminal P116 is subsequently used as a signal terminal to transmit a sideband signal corresponding to the level of the selection signal input to the SCS terminal.

[0209] according to Figure 23 and Figure 24 The configuration shown allows for the sharing of the signal terminals, SCS terminals, and PCD terminals used to transmit sideband signals, thus increasing the design freedom of pin assignment for the memory device 10. For example, as Figure 20 and Figure 22 As shown, the number of terminals used as grounding terminals for return current can be increased, etc.

[0210] According to the third embodiment described above, the memory device 10 includes at least two signal terminals (e.g., terminals P116 and P117) for allocating sideband signals. Before the memory device 10 is started, a selection signal is input to one signal terminal (e.g., terminal P116), and a detection signal is output from the other signal terminal (e.g., terminal P117). After the memory device 10 is started, sideband signals are input to these two signal terminals. This allows the signal terminals, SCS terminals, and PCD terminals used to transmit sideband signals to be shared, increasing the design freedom of the pin assignment of the memory device 10.

[0211] According to at least one embodiment described above, a memory device 10 capable of improving heat dissipation efficiency can be provided.

[0212] Furthermore, in this embodiment, NAND flash memory is exemplified as a non-volatile memory. However, the functionality of this embodiment can also be applied to various other non-volatile memories such as MRAM (Magnetoresistive Random Access Memory), PRAM (Phase Change Random Access Memory), ReRAM (Resistive Random Access Memory), or FeRAM (Ferroelectric Random Access Memory).

[0213] While several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included within the scope or spirit of the invention, and are included within the scope of the invention described in the claims and their equivalents.

[0214] [Symbol Explanation]

[0215] 10 memory devices

[0216] 11 body

[0217] 100 connector

[0218] 101-103 lead frame

[0219] 104 lead frame terminal

[0220] 105 Installation Department

[0221] 106 connector frame

[0222] 107TIM

[0223] P101~P132 terminals

[0224] A1 Contact Area

[0225] A2 Attachment Area.

Claims

1. A semiconductor memory device, comprising: The body has: a first surface; a second surface located on the opposite side of the first surface; a first end edge extending in a first direction; a second end edge located on the opposite side of the first end edge and extending in the first direction; a first side edge extending in a second direction intersecting the first direction; and a second side edge located on the opposite side of the first side edge and extending in the second direction. The memory is located inside the main body; A controller, located inside the main body, controls the memory; and Multiple terminals, including multiple signal terminals for transmitting signals, are exposed on the first surface; and The plurality of terminals form at least a first column and a second column; The first column includes a plurality of terminals, which are spaced apart from each other in the first direction at a position closer to the first end edge than the second end edge; The second column includes a plurality of terminals, which are spaced apart from each other in the first direction at a position closer to the second end edge than the first end edge; The region between the first column and the second column of the first surface includes a contact region that contacts a heat-conducting component disposed on a printed circuit board in a host machine capable of being electrically connected to the semiconductor memory device. The plurality of terminals further form a third column. The third column includes a plurality of terminals, spaced apart from each other in the first direction, located between the first and second columns, wherein the number of terminals forming the third column is less than the number of terminals forming the first or second column. The third column is located closer to the second end edge than the first end edge, and farther away from the second end edge than the second column.

2. The semiconductor memory device according to claim 1, wherein The distance between the first column and the second column in the second direction is longer than the distance between the first column and the first end edge in the second direction, and is also longer than the distance between the second column and the second end edge in the second direction.

3. The semiconductor memory device according to claim 1 or 2, wherein The plurality of terminals forming the first column include at least one pair of differential data signal terminals assigned to differential data signals; The plurality of terminals forming the second column include power terminals assigned for supplying power voltage from the host machine.

4. The semiconductor memory device according to claim 3, wherein The differential data signal is based on the PCIe specification; The plurality of terminals forming the first column include multiple pairs of differential data signal terminals assigned to multiple channels of the differential data signal.

5. The semiconductor memory device according to claim 1 or 2, wherein The contact area includes: an area that is empty, corresponding to the portion where the number of terminals forming the third column is less than the number of terminals forming the first column.

6. The semiconductor memory device according to claim 5, wherein The plurality of terminals forming the third column include at least one ground terminal assigned to the ground wire and at least one sideband signal terminal assigned to a PCIe specification sideband signal.

7. The semiconductor memory device according to claim 1, wherein The third column includes the same number of terminals between the center line of the body and the first side edge in the first direction, and between the center line and the second side edge.

8. The semiconductor memory device according to claim 7, wherein The third column includes the plurality of terminals between the center line and the first side edge, and between the center line and the second side edge.

9. The semiconductor memory device according to claim 1, wherein The third column contains a different number of terminals between the center line of the body and the first side edge in the first direction, and between the center line and the second side edge.

10. The semiconductor memory device according to claim 1, wherein The plurality of terminals forming the first column include a plurality of pairs of receiving differential data signal terminals assigned to receiving differential data signals, and a pair of transmitting differential data signal terminals assigned to transmitting differential data signals. Multiple sets of the pair of receiving differential data signal terminals are located between the center line and one side edge of the body in the first direction, and multiple sets of the pair of transmitting differential data signal terminals are located between the center line and the other side edge.

11. The semiconductor memory device of claim 10, wherein... The pair of receiving differential data signal terminals and the pair of transmitting differential data signal terminals are disposed between grounding terminals for noise protection.

12. A semiconductor memory device, comprising: The body has: a first surface; a second surface located on the opposite side of the first surface; a first end edge extending in a first direction; a second end edge located on the opposite side of the first end edge and extending in the first direction; a first side edge extending in a second direction intersecting the first direction; and a second side edge located on the opposite side of the first side edge and extending in the second direction. The memory is located inside the main body; A controller, located inside the main body, controls the memory; and Multiple terminals, including multiple signal terminals for transmitting signals, are exposed on the first surface; and The plurality of terminals form at least a first column and a second column; The first column includes a plurality of terminals, which are spaced apart from each other in the first direction at a position closer to the first end edge than the second end edge; The second column includes a plurality of terminals, which are spaced apart from each other in the first direction at a position closer to the second end edge than the first end edge; The region between the first column and the second column of the first surface includes: a contact region that contacts a heat-conducting component disposed on a printed circuit board in a host machine capable of being electrically connected to the semiconductor memory device; The plurality of terminals further form a third column. The third column includes a plurality of terminals, spaced apart from each other in the first direction, located between the first and second columns, wherein the number of terminals forming the third column is less than the number of terminals forming the first or second column. The third column is located closer to the first end edge than the second end edge, and farther away from the first end edge than the first column.

13. A semiconductor memory device, comprising: The body has: a first surface; a second surface located on the opposite side of the first surface; a first end edge extending in a first direction; a second end edge located on the opposite side of the first end edge and extending in the first direction; a first side edge extending in a second direction intersecting the first direction; and a second side edge located on the opposite side of the first side edge and extending in the second direction. The memory is located inside the main body; A controller, located inside the main body, controls the memory; and Multiple terminals, including multiple signal terminals for transmitting signals, are exposed on the first surface; and The plurality of terminals form at least a first column and a second column; The first column includes a plurality of terminals, which are spaced apart from each other in the first direction at a position closer to the first end edge than the second end edge; The second column includes a plurality of terminals, which are spaced apart from each other in the first direction at a position closer to the second end edge than the first end edge; The region between the first column and the second column of the first surface includes: a contact region that contacts a heat-conducting component disposed on a printed circuit board in a host machine capable of being electrically connected to the semiconductor memory device; The plurality of terminals further form a third column. The third column includes a plurality of terminals, spaced apart from each other in the first direction, located between the first and second columns, wherein the number of terminals forming the third column is less than the number of terminals forming the first or second column. The contact area includes: an area that is empty, corresponding to the portion where the number of terminals forming the third column is less than the number of terminals forming the first column. The plurality of terminals forming the third column include at least one ground terminal assigned to ground and at least one sideband signal terminal assigned to a PCIe specification sideband signal. The plurality of terminals forming the second column include a first terminal, which is assigned to a selection signal for selecting the configuration of the sideband signal; When the first terminal is input with a high-level selection signal, a first sideband signal is assigned to the at least one sideband signal terminal; when the first terminal is input with a low-level selection signal, a second sideband signal different from the first sideband signal is assigned to the at least one sideband signal terminal.

14. A semiconductor memory device, comprising: The body has: a first surface; a second surface located on the opposite side of the first surface; a first end edge extending in a first direction; a second end edge located on the opposite side of the first end edge and extending in the first direction; a first side edge extending in a second direction intersecting the first direction; and a second side edge located on the opposite side of the first side edge and extending in the second direction. The memory is located inside the main body; A controller, located inside the main body, controls the memory; and Multiple terminals, including multiple signal terminals for transmitting signals, are exposed on the first surface; and The plurality of terminals form at least a first column and a second column; The first column includes a plurality of terminals, which are spaced apart from each other in the first direction at a position closer to the first end edge than the second end edge; The second column includes a plurality of terminals, which are spaced apart from each other in the first direction at a position closer to the second end edge than the first end edge; The region between the first column and the second column of the first surface includes: a contact region that contacts a heat-conducting component disposed on a printed circuit board in a host machine capable of being electrically connected to the semiconductor memory device; The plurality of terminals further form a third column. The third column includes a plurality of terminals, spaced apart from each other in the first direction, located between the first and second columns, wherein the number of terminals forming the third column is less than the number of terminals forming the first or second column. The contact area includes: an area that is empty, corresponding to the portion where the number of terminals forming the third column is less than the number of terminals forming the first column; The plurality of terminals forming the third column include at least one ground terminal assigned to the ground wire and at least one sideband signal terminal assigned to a sideband signal of the PCIe specification. The plurality of terminals forming the second column include a second terminal assigned to a detection signal, which is used by the host machine to detect the power configuration of the semiconductor memory device; When the power supply configuration of the semiconductor memory device is configured to operate with multiple power supply voltages, the controller outputs a high-level detection signal to the host machine via the second terminal; when the power supply configuration of the semiconductor memory device is configured to operate with one power supply voltage, the controller outputs a low-level detection signal to the host machine via the second terminal.

15. A semiconductor memory device, comprising: The body has: a first surface; a second surface located on the opposite side of the first surface; a first end edge extending in a first direction; a second end edge located on the opposite side of the first end edge and extending in the first direction; a first side edge extending in a second direction intersecting the first direction; and a second side edge located on the opposite side of the first side edge and extending in the second direction. The memory is located inside the main body; A controller, located inside the main body, controls the memory; and Multiple terminals, including multiple signal terminals for transmitting signals, are exposed on the first surface; and The plurality of terminals form at least a first column and a second column; The first column includes a plurality of terminals, which are spaced apart from each other in the first direction at a position closer to the first end edge than the second end edge; The second column includes a plurality of terminals, which are spaced apart from each other in the first direction at a position closer to the second end edge than the first end edge; The region between the first column and the second column of the first surface includes: a contact region that contacts a heat-conducting component disposed on a printed circuit board in a host machine capable of being electrically connected to the semiconductor memory device; The plurality of terminals forming the first column include a plurality of pairs of receiving differential data signal terminals assigned to receiving differential data signals, and a pair of transmitting differential data signal terminals assigned to transmitting differential data signals. Multiple sets of the pair of receiving differential data signal terminals are located between the center line and one side edge of the body in the first direction, and multiple sets of the pair of transmitting differential data signal terminals are located between the center line and the other side edge; The plurality of terminals further form a third column; The third column includes a plurality of terminals, which are spaced apart from each other in the first direction at a position between the first column and the second column; The plurality of terminals forming the third column include a plurality of grounding terminals for return current disposed between the center line and the first side edge, and also include a plurality of grounding terminals for return current disposed between the center line and the second side edge.

16. The semiconductor memory device of claim 15, wherein The plurality of terminals forming the second column include at least one grounding terminal for the return current.

17. The semiconductor memory device of claim 16, wherein... The body also includes: a first ground plane, connected to a grounding terminal for noise protection; and a second ground plane, connected to a grounding terminal for return current; and The first ground plane and the second ground plane are not electrically connected.

18. The semiconductor memory device according to claim 15, wherein The plurality of terminals forming the third column include at least two signal terminals assigned to sideband signals; Before the semiconductor memory device is started, a selection signal is input to one of the at least two signal terminals to select the configuration of the sideband signal, and a detection signal is output from the other of the at least two signal terminals to the host machine for detecting the power configuration of the semiconductor memory device; After the semiconductor memory device is started, the sideband signal is input to the two signal terminals.

19. The semiconductor memory device of claim 18, wherein The plurality of terminals forming the second column include signal terminals assigned to reset signals; When the reset signal is applied, the selection signal is input to one of the at least two signal terminals, and the detection signal is output from the other of the at least two signal terminals; When the reset signal is released, the sideband signal is input to the two signal terminals.

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